Array substrate and display device
By designing deep vias and optimizing the metal line layout in the array substrate, the problems of high cost of Micro OLED display devices and insufficient channel length in high-resolution display panels have been solved, achieving high-resolution and low-cost display effects.
Patent Information
- Application Number
- CN202411044794.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2026-02-03
AI Technical Summary
Existing Micro OLED display devices are expensive and difficult to manufacture, making them difficult to popularize. Furthermore, the shortened transistor channel length in the pixel area of high-resolution display panels leads to device failure, and the deformation of metal lines causes light leakage problems.
By designing a first via in the array substrate that penetrates the second sub-insulator layer and extends into the interior of the first sub-insulator layer, the channel length is increased. The projection of the via on the substrate is covered by a second metal line, which improves the channel length, reduces the number of vias, optimizes the metal line layout, and uses a highly conductive active pattern portion as an electrode, simplifying the fabrication process.
Without increasing the linewidth of the grid, the resolution and contrast of the display panel were improved, the problems of component failure and light leakage were solved, and the manufacturing cost was reduced.
Smart Images
Figure CN121463656A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate and a display device. Background Technology
[0002] With the rise of the metaverse concept, virtual reality (VR) headsets have received much attention as port devices. Currently, the display products with good performance on the market are usually micro organic light-emitting diode (Micro OLED) products with 3000+ PPI. However, Micro OLED products are expensive and difficult to manufacture, making them difficult to popularize. Summary of the Invention
[0003] This disclosure provides an array substrate and a display device. The array substrate has a display area and a peripheral area located around the display area; the array substrate includes:
[0004] Substrate;
[0005] A first metal layer is located on one side of the substrate, and the first metal layer includes: a plurality of first metal lines located in the display area;
[0006] A first active layer is located on the side of the first metal layer facing away from the substrate, and the first active layer includes a plurality of first active patterns located in the display area;
[0007] A first insulating layer is located on the side of the first active layer facing the substrate; the first insulating layer includes: a first sub-insulating layer located between the first metal layer and the substrate, and a second sub-insulating layer located between the first metal layer and the first active layer; the first insulating layer has a plurality of first vias located in the display area, the first vias penetrating the second sub-insulating layer, exposing a portion of the first metal line, and a portion of the first sub-insulating layer exposing at least one side of the first metal line; the first active pattern passes through the first vias, partially covering the first metal line, and partially covering the first insulating layer on the side of the first metal line;
[0008] The second metal layer is located on the side of the first active layer away from the first insulating layer. The second metal layer includes: a plurality of second metal lines located in the display area and extending along a first direction; the orthogonal projection of the second metal lines on the substrate covers the orthogonal projection of the first via on the substrate.
[0009] In one possible implementation, the first sub-insulating layer has a first surface facing away from the substrate, and the first via exposes a portion of the first surface; the first active pattern covers a portion of the first surface.
[0010] In one possible implementation, the first sub-insulating layer has a first surface facing away from the substrate; the first via passes through the first surface and extends through the first surface into the interior of the first sub-insulating layer.
[0011] In one possible implementation, the array substrate further includes a light-shielding layer located on the side of the first insulating layer facing the substrate;
[0012] The light-shielding layer has a cutout portion; the orthographic projection of the cutout portion onto the substrate covers the orthographic projection of the first active pattern onto the substrate.
[0013] In one possible implementation, the array substrate further includes: a plurality of pixel electrodes located in the display area; the pixel electrodes include: a first sub-electrode; the first active pattern further covers a portion of the first sub-electrode.
[0014] In one possible implementation, the first sub-electrode includes: a first sub-part, and a second sub-part connected to the first sub-part;
[0015] The orthographic projection of the first sub-part onto the substrate is located in the region between the orthographic projections of two adjacent first metal lines onto the substrate; the orthographic projection of the second sub-part onto the substrate overlaps with the orthographic projection of the first metal line onto the substrate.
[0016] In one possible implementation, the second metal line includes a first outer edge and a second outer edge; the first outer edge, in its orthographic projection onto the substrate, is located on the side of the second outer edge in its orthographic projection onto the substrate that faces the first sub-electrode.
[0017] The second sub-part has a third outer edge on the side away from the first sub-part, the third outer edge extending along the first direction; the orthographic projection of the third outer edge onto the substrate coincides with the orthographic projection of the first outer edge onto the substrate.
[0018] In one possible implementation, the orthographic projection of the first sub-electrode onto the substrate does not overlap with the orthographic projection of the first via onto the substrate.
[0019] In one possible implementation, the first sub-electrode is located between the first active layer and the second sub-insulating layer.
[0020] In one possible implementation, the first active pattern includes: a first pattern portion and a second pattern portion; the orthographic projection of the first pattern portion on the substrate overlaps with the orthographic projection of the second metal line on the substrate; the orthographic projection of the second pattern portion on the substrate and the orthographic projection of the second metal line on the substrate do not overlap.
[0021] The first sub-electrode reuses the second patterned portion, and the conductivity of the second patterned portion is higher than that of the first patterned portion.
[0022] In one possible implementation, the pixel electrode further includes: a second sub-electrode located on the side of the second metal layer opposite to the substrate, and a third sub-electrode located on the side of the second sub-electrode opposite to the substrate and partially stacked with the second sub-electrode;
[0023] The array substrate further includes: a second insulating layer located between the second metal layer and the second sub-electrode; the second insulating layer has a second via, the second via exposing a portion of the first sub-part, and the second sub-electrode overlapping the first sub-part of the first sub-electrode via the second via.
[0024] In one possible implementation, the second metal wire includes: a second metal wire main portion and a second metal wire protrusion; the second metal wire main portion extends along the first direction; the second metal wire protrusion protrudes from the second metal wire main portion along a direction perpendicular to the first direction;
[0025] The orthographic projection of the second metal wire protrusion on the substrate overlaps with the orthographic projection of a portion of the first metal wire on the substrate.
[0026] In one possible implementation, the first active pattern extends along a second direction, and the orthographic projection of the first active pattern onto the substrate overlaps with the orthographic projection of the first metal line onto the substrate, and also overlaps with the orthographic projection of the second metal line onto the substrate.
[0027] In one possible implementation, the maximum width of the first active pattern in the first direction is greater than the maximum width of the first metal line in the first direction.
[0028] In one possible implementation, the maximum width of the first via in the first direction is greater than the maximum width of the first metal line in the first direction.
[0029] In one possible implementation, the first metal line includes: a first sub-data section, a second sub-data section, and a third sub-data section;
[0030] The first sub-data section and the second sub-data section both extend along the second direction, and the outer edge extension line of the first sub-data section extending along the second direction does not overlap with the second sub-data section; the third sub-data section extends along the first direction, and one end of the third sub-data section is connected to the first sub-data section, and the other end is connected to the second sub-data section.
[0031] In one possible implementation, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the third sub-data section on the substrate; the orthographic projection of the first active pattern on the substrate overlaps with the orthographic projection of the third sub-data section on the substrate.
[0032] In one possible implementation, the array substrate further includes: a plurality of driving transistors located in the peripheral region; the driving transistors include: a driving source, a driving drain, a driving gate, and a driving active layer;
[0033] The driving source and the driving drain are in the same layer and made of the same material as the first metal line.
[0034] In one possible implementation, the array substrate further includes: a plurality of light-shielding portions located in the display area; the orthographic projection of the light-shielding portions on the substrate overlaps with a portion of the orthographic projection of the first active pattern on the substrate;
[0035] The light-shielding portion is in the same layer and made of the same material as the driving gate; or, the light-shielding portion is in the same layer and made of the same material as the driving active layer.
[0036] This disclosure also provides a display device, which includes the array substrate as provided in this disclosure. Attached Figure Description
[0037] Figure 1A This is one of the top views of the array substrate provided in the embodiments of this disclosure;
[0038] Figure 1B It can be Figure 1A A schematic diagram of a single film layer of the first metal layer in the middle;
[0039] Figure 1C It can be Figure 1A A schematic diagram of the first metal line and the first via.
[0040] Figure 1D It can be Figure 1A Schematic diagram of a single film layer of the first sub-electrode layer;
[0041] Figure 1E It can be Figure 1A Schematic diagram of the single-film layer of the first active layer in the middle;
[0042] Figure 1F It can be Figure 1A Schematic diagram of a single film layer of the second metal layer in the middle;
[0043] Figure 1G It can be Figure 1A A schematic diagram of a single-film layer of the second insulating layer;
[0044] Figure 1H It can be Figure 1A Schematic diagram of the film layers of the second and third sub-electrodes;
[0045] Figure 2 It can be Figure 1A A schematic diagram of the cross-section along the dashed line e;
[0046] Figure 3 for Figure 1A A schematic diagram of removing the second insulating layer;
[0047] Figure 4A This is a second top view of the array substrate provided in the embodiments of this disclosure;
[0048] Figure 4B for Figure 4A Schematic diagram of a single film layer with a common electrode layer in the middle;
[0049] Figure 5 This is one of the schematic cross-sectional views of the array substrate provided in the embodiments of this disclosure;
[0050] Figure 6 This is a second schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;
[0051] Figure 7 This is the third schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;
[0052] Figure 8 This is the fourth schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;
[0053] Figure 9 This is the fifth schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;
[0054] Figure 10 This is the sixth schematic cross-sectional view of the array substrate provided in the embodiments of this disclosure;
[0055] Figure 11 This is the third top view schematic diagram of the array substrate provided in the embodiments of this disclosure;
[0056] Figure 12A A cross-sectional view of the array substrate structure used to form the driving active layer;
[0057] Figure 12B A cross-sectional view of the array substrate structure forming the first sub-insulating layer;
[0058] Figure 12C A cross-sectional view of the array substrate structure for forming the second sub-insulating layer;
[0059] Figure 12D A cross-sectional schematic diagram of the array substrate structure forming the first sub-electrode;
[0060] Figure 12E A top view of the array substrate structure for forming the first sub-electrode;
[0061] Figure 12F A cross-sectional schematic diagram of the array substrate structure for forming the first active pattern;
[0062] Figure 12G Top view of the array substrate structure for forming the first active pattern;
[0063] Figure 12H A top view of the array substrate structure for forming the second metal line;
[0064] Figure 12I A cross-sectional view of the array substrate structure for forming the second sub-electrode;
[0065] Figure 12J A top view of the array substrate structure for forming the second sub-electrode;
[0066] Figure 12K A cross-sectional view of the array substrate structure forming the spacers;
[0067] Figure 12L A cross-sectional schematic diagram of the array substrate structure forming the common electrode. Detailed Implementation
[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0069] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0070] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.
[0071] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.
[0072] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0073] The optimal solution for ultra-high PPI is currently Liquid Crystal Display (LCD) technology. This is because the pixel area circuit in an LCD display only has one switching transistor (Thin Film Transistor, TFT), which is highly conducive to achieving high PPI. However, LCDs have relatively low transmittance, necessitating the development of backplane processes with high aperture ratios. Especially when the PPI reaches above 2000, various linewidths, line spacings, and via sizes reach the limits of display manufacturing equipment. As the PPI increases to above 2500, the size of metal traces needs further compression (e.g., from the current 1.5µm level to 1.0µm or lower). Data lines can be reduced, but the gate line size determines the channel length of the TFT device, typically requiring a length of 2.0µm or more. Oxide TFT devices are inherently unstable; when the channel length decreases to 1.5µm or less, the device is prone to conductor formation problems, leading to device failure.
[0074] In view of this, the present disclosure provides an array substrate, see [link to relevant documentation]. Figures 1A-1H , Figure 2 , Figure 3 As shown, where, Figure 1B It can be Figure 1AA schematic diagram of the single-film layer of the first metal layer in the middle. Figure 1C It can be Figure 1A A schematic diagram of the first metal line and the first via. Figure 1D It can be Figure 1A A schematic diagram of the single film layer of the first sub-electrode layer. Figure 1E It can be Figure 1A A schematic diagram of the first active layer in the middle. Figure 1F It can be Figure 1A A schematic diagram of a single film layer of the second metal layer in the middle. Figure 1G It can be Figure 1A A schematic diagram of the single-film layer of the second insulating layer. Figure 1H It can be Figure 1A Schematic diagram of the film layers of the second and third sub-electrodes. Figure 2 It can be Figure 1A A schematic diagram of the cross-section along the dashed line e. Figure 3 To clearly illustrate the film layer below the second insulating layer, the [material name] was removed. Figure 1A The second insulating layer in; combined Figure 2 As shown, the array substrate has a display area AA and a peripheral area BB located around the display area AA; including:
[0075] Substrate 1;
[0076] The first metal layer 2 is located on one side of the substrate 1. The first metal layer 2 includes: a plurality of first metal lines 21 located in the display area AA; optionally, the first metal lines 21 can be data lines; optionally, the first metal lines 21 can be straight lines extending along the second direction Y; optionally, the first metal lines 21 can also be zigzag lines, with the main body extending along the second direction Y, and bends existing in some areas.
[0077] The first active layer 3 is located on the side of the first metal layer 2 away from the substrate 1, and the first active layer 3 includes a plurality of first active patterns 31 located in the display area AA;
[0078] The first insulating layer F1 is located on the side of the first active layer 3 facing the substrate 1. The first insulating layer F1 includes: a first sub-insulating layer F11 located between the first metal layer 2 and the substrate 1, and a second sub-insulating layer F12 located between the first metal layer 2 and the first active layer 3. The first insulating layer F1 has a plurality of first vias K1 located in the display area AA. The first vias K1 penetrate the second sub-insulating layer F12, exposing a portion of the first metal line 21, and a portion of the first sub-insulating layer F11 exposing at least one side of the first metal line 21. The first active pattern 31 passes through the first vias K1, partially covering the first metal line 21, and partially covering the first insulating layer F11 on the side of the first metal line 21.
[0079] The second metal layer 4 is located on the side of the first active layer 3 opposite to the first insulating layer F1. The second metal layer 4 includes: a plurality of second metal lines 41 located in the display area AA and extending along the first direction X; the orthographic projection of the second metal lines 41 onto the substrate 1 covers the orthographic projection of the first via K1 onto the substrate 1. Optionally, the second metal lines 41 may be located on a gate line.
[0080] In this embodiment, the region in the first active pattern 31 that overlaps with the orthographic projection of the second metal line 41 can form a channel region. The first active pattern 31 covers the portion of the first metal line 21 exposed by the first via K1 and a portion of the first insulating layer F11. The orthographic projection of the second metal line 41 onto the substrate 1 covers the orthographic projection of the first via K1 onto the substrate 1. That is, the channel region of the first active pattern 31 includes at least: a portion covering the surface of the first metal line 21 facing away from the substrate 1, a portion covering the surface of the second sub-insulating layer F12 facing away from the substrate 1, and a portion covering the sidewall of the first via K1. In addition to the portion parallel to the surface of the substrate 1, the channel region also includes a portion perpendicular to the surface of the substrate 1. That is, the channel length is increased by utilizing the sidewall of the first via K1. The composition of the channel region is L. 总 =L 垂直 +L 水平 L 垂直 The depth of the first via K1 is determined by the thickness of the second sub-insulating layer F12. This allows for an increase in the channel length of the device without increasing the gate linewidth, mitigating the problem of device failure caused by conductor formation due to shortened channel length in high-resolution display panels. The pixel transistor can be smaller, and the second metal line 41 (gate line) is no longer constrained by the channel size, allowing for further reduction and improving resolution. Furthermore, in related technologies, the top-gate structure used in pixel transistors suffers from problems where the first metal line 21 (data line) is thinner than the first via K1, leading to deformation at the via K1 location and metal diffraction depolarization, resulting in light leakage. In this embodiment, the first metal line 21 (data line) is located at the bottom of the first via K1, ensuring its shape remains undistorted, thus improving light leakage and enhancing the display panel's contrast.
[0081] In one possible implementation, see Figure 2 As shown, the first sub-insulating layer F11 has a first surface S1 on the side opposite to the substrate 1, and a first via K1 exposes a portion of the first surface S1; a first active pattern 51 covers a portion of the first surface S1. In this embodiment of the disclosure, as... Figure 2As shown, the first via K1 only penetrates the second sub-insulating layer F12 and does not extend downwards into the interior of the first sub-insulating layer F11. The depth of the first via K1 is the same as the thickness of the second sub-insulating layer F12, and the L of the channel region... 垂直 Part of the length is determined by the thickness of the second sub-insulating layer F12. Increasing the thickness of the second sub-insulating layer F12 can increase the length of the channel region. This allows the channel length of the device to be increased without increasing the gate linewidth.
[0082] Optional, combined Figure 2 and Figure 3 As shown, the first via K1 exposes a portion of the first metal line 21 and a portion of the first sub-insulating layer F11 on both sides of the first metal line 21; the first active pattern 31 covers the surface of the first metal line 21 exposed by the first via K1 on the side away from the substrate 1, covers a portion of the surface of the first sub-insulating layer F11 on both sides of the first metal line 21, covers the sidewall of the second sub-insulating layer F12 exposed by the first via K1, and covers a portion of the surface of the second sub-insulating layer F12. That is, the first active pattern 31 covers the surface of the first sub-metal line 21, and covers the area at the bottom of the first via K1 other than the first metal line 21, and extends along the sidewall of the first via K1 to the surface of the second sub-insulating layer F12.
[0083] In one possible implementation, see Figure 6 As shown, the first sub-insulating layer F11 has a first surface S1 facing away from the substrate 1; the first via K1 passes through the first surface S1 and extends through the first surface S1 into the interior of the first sub-insulating layer F11. In this embodiment, the first via K1 not only penetrates the second sub-insulating layer F12, but also extends downward into the interior of the first sub-insulating layer F11 below the first metal line 21. This allows for deep hole etching beyond the thickness limit of the second sub-insulating layer F12, further extending the channel length and allowing for further reduction in transistor size, which is beneficial for achieving higher resolution.
[0084] Optional, see Figure 6 As shown, the first via K1 can be a second sub-insulating layer F12 that exposes only one side of the first metal line, and a first sub-insulating layer F11. That is, the first via K1 and the first metal line 21 can be designed to be staggered, thereby achieving a greater depth of the first via K1. Optionally, the center of the first via K1 in the orthographic projection of the substrate 1 can be staggered from the center of the first metal line 21 in the orthographic projection of the substrate 1.
[0085] Optional, see Figure 6As shown, the first active pattern 21 can cover part of the surface of the first metal line 21, extend along the sidewall of the first via K1 to the bottom of the first via K1, and extend along the sidewall of the first via K1 to part of the surface of the second sub-insulating layer F12.
[0086] Optional, combined Figure 2 or Figure 6 As shown, the first sub-insulating layer F11 may include: a first buffer layer F113, a first gate insulating layer F112 located on the side of the first buffer layer F113 facing away from the substrate 1, and a first interlayer dielectric layer F111 located on the side of the first gate insulating layer F112 facing away from the substrate 1; optionally, see Figure 6 As shown, the first via K1 can penetrate the second sub-insulating layer F12 and extend into the interior of the first interlayer dielectric layer F111.
[0087] Optional, see Figure 6 As shown, the depth of the first via K1 can be greater than the thickness of the second sub-insulating layer F12, but less than the sum of the thicknesses of the second sub-insulating layer F12 and the first interlayer dielectric layer F111.
[0088] In one possible implementation, see Figure 6 As shown, the array substrate further includes a light-shielding layer G located on the side of the first insulating layer F1 facing the substrate 1; the light-shielding layer G has a cutout portion G0; the orthographic projection of the cutout portion G0 onto the substrate 1 covers the orthographic projection of the first active pattern 31 onto the substrate 1. In this embodiment of the present disclosure, the light-shielding layer G has a cutout portion G0; the orthographic projection of the cutout portion G0 onto the substrate 1 covers the orthographic projection of the first active pattern 31 onto the substrate 1, that is, in the vertical region between the first active pattern 31 and the substrate 1, a light-shielding portion may not be provided, to prevent the first via K1 from extending downward and penetrating to the light-shielding portion, causing the first active pattern to connect with the light-shielding portion.
[0089] In one possible implementation, combining Figures 1A-1H , Figure 2 , Figure 3 As shown, the array substrate also includes: a plurality of pixel electrodes 5 located in the display area; the pixel electrode 5 includes: a first sub-electrode 51; and a first active pattern 31 also covers a portion of the first sub-electrode 51.
[0090] In one possible implementation, combining Figure 1A , Figure 1D , Figure 2 , Figure 3As shown, the first sub-electrode 51 includes: a first sub-part 511, and a second sub-part 512 connected to the first sub-part 511; the orthographic projection of the first sub-part 511 onto the substrate 1 is located in the region between the orthographic projections of two adjacent first metal lines 21 onto the substrate 1; the orthographic projection of the second sub-part 512 onto the substrate 1 overlaps with the orthographic projection of the first metal lines 21 onto the substrate 1.
[0091] Optional, combined Figure 1D , Figure 3 As shown, the orthographic projection of the first sub-part 511 onto the substrate 1 can be block-shaped; the orthographic projection of the second sub-part 512 onto the substrate 1 can be strip-shaped. The second sub-part 512 can extend along the third direction Z. Optionally, the angle formed by the third direction Z and the second direction Y is in the range of 0° to 90°. Optionally, the angle formed by the third direction Z and the second direction Y is in the range of 30° to 60°.
[0092] In one possible implementation, combining Figure 1A , Figure 1D , Figure 2 , Figure 3 As shown, the pixel electrode 5 further includes: a second sub-electrode 52 located on the side of the second metal layer 4 facing away from the substrate 1, and a third sub-electrode 53 located on the side of the second sub-electrode 52 facing away from the substrate 1 and partially stacked with the second sub-electrode 52; optionally, combined with Figure 3 , Figure 2 As shown, the first sub-electrode 51 can be connected to the first active pattern 31 through the second sub-part 512, and the first sub-electrode 51 can be connected to the second sub-electrode 52 through the first sub-part 511.
[0093] In one possible implementation, combining Figure 1A , Figure 1F , Figure 2 , Figure 3 As shown, the second metal line 41 includes a first outer edge w1 and a second outer edge w2; the orthographic projection of the first outer edge w1 onto the substrate 1 is located on the side of the orthographic projection of the second outer edge w2 onto the substrate 1 facing the first sub-electrode 51, that is, combined with Figure 3 As shown, the first outer edge w1 can be the lower edge of the second metal line 41, and the second outer edge w2 can be the upper edge of the second metal line 41; the second sub-part 512 has a third outer edge w3 on the side away from the first sub-part 511, and the third outer edge w3 extends along the first direction X; the orthographic projection of the third outer edge w3 onto the substrate 1 coincides with the orthographic projection of the first outer edge w1 onto the substrate 1. In this embodiment of the present disclosure, the third outer edge w3 of the second sub-part 512 coincides with the first outer edge w1 of the second metal line 41, which can avoid the pixel electrode 5 and the second metal line 41 forming overlapping capacitance, thereby affecting the normal display of the display panel.
[0094] It is understood that the first outer edge w1 of the second metal line 41 is projected onto the substrate 1 in the orthogonal projection of the second outer edge w2 onto the substrate 1 on the side facing the first sub-electrode 51. The second metal line 41 and the first sub-electrode 51 may be electrically connected to the same transistor.
[0095] In one possible implementation, combining Figure 1A , Figure 1F , Figure 2 , Figure 3 As shown, the orthographic projection of the first sub-electrode 51 onto the substrate 1 does not overlap with the orthographic projection of the first via K1 onto the substrate 1.
[0096] In one possible implementation, the first sub-electrode 51 can be a single film layer, for example, combined with Figure 1A , Figure 1F , Figure 2 , Figure 3 As shown, the first sub-electrode 51 is located between the first active layer 31 and the second sub-insulating layer F12. Optionally, the first sub-electrode 51 can be a transparent conductive layer, and the material can be indium tin oxide.
[0097] In one possible implementation, the first sub-electrode 51 may also reuse a portion of the first active pattern 31, for example, in combination with... Figure 7 , Figure 8 As shown, the first active pattern 31 includes a first pattern portion 311 and a second pattern portion 312; the orthographic projection of the first pattern portion 311 onto the substrate 1 overlaps with the orthographic projection of the second metal line 41 onto the substrate 1; the orthographic projection of the second pattern portion 312 onto the substrate 1 and the orthographic projection of the second metal line 41 onto the substrate 1 do not overlap; the first sub-electrode 51 reuses the second pattern portion 312, and the conductivity of the second pattern portion 312 is higher than that of the first pattern portion 311. In this embodiment, the first sub-electrode 51 reuses a portion of the first active pattern 31, which can eliminate the need for separate fabrication of the first sub-electrode 51, reduce one masking process, and lower the fabrication cost of the array substrate.
[0098] In one possible implementation, see Figure 7 As shown, in actual fabrication, an ion implantation process can be used to partially conductor the first active pattern 31, serving as the first sub-electrode 51. In another possible implementation, see... Figure 8 As shown, in actual fabrication, after etching the second metal line 41, a portion of the surface of the first active pattern 31 can be treated with plasma gas to form a conductive electrode, compared to... Figure 7 The illustrated embodiment can reduce the number of ion implantation steps.
[0099] Optional, combined Figure 2 , Figures 5-8As shown, a second gate insulating layer F23 is also present between the first active pattern 31 and the second metal line 41; optionally, combined with Figure 8 As shown, the pattern of the second gate insulating layer F23 can be the same as the pattern of the second metal line 41. Optionally, the orthographic projection of the second gate insulating layer F23 onto the substrate 1 can coincide with the orthographic projection of the second metal line 41 onto the substrate 1.
[0100] In one possible implementation, combining Figure 1A , Figure 1G , Figure 2 , Figure 3 As shown, the array substrate further includes a second insulating layer F2 located between the first sub-electrode 511 and the second sub-electrode 512; the second insulating layer F2 has a second via K2, the second via K2 exposing a portion of the first sub-electrode 511, and the second sub-electrode 512 overlapping with the first sub-electrode 511 via the second via K2. In this embodiment, the pixel area may only have two vias, the first via K1 and the second via K2. Compared to related technologies, where the pixel area requires three vias, this embodiment reduces the number of vias, which is beneficial for improving light leakage and increasing high resolution.
[0101] Optional, combined Figure 1A , Figure 1G As shown, the second via K2 of multiple sub-pixels can be an integrally connected structure, which is beneficial to make the array substrate flatter in the second via K2 and the surrounding area.
[0102] Optional, combined Figure 2 As shown, the second insulating layer F2 may include: a second gate insulating layer F23, a second interlayer dielectric layer F22 located on the side of the second gate insulating layer F23 facing away from the substrate 1, and a first planarization layer F21 located on the side of the second interlayer dielectric layer F22 facing away from the substrate 1; the second via K2 may penetrate the first planarization layer F21, the second interlayer dielectric layer F22, and the second gate insulating layer F23.
[0103] Optional, see Figure 2 As shown, the array substrate may further include a third insulating layer F3 filled in the second via K2, thereby achieving planarization at the location of the second via K2. Optionally, the third insulating layer F3 may be a second planarization layer.
[0104] Optional, combined Figure 2 , Figure 3 As shown, the orthogonal projection of the third sub-electrode 53 onto the substrate 1 can cover the orthogonal projection of the third insulating layer F3 onto the substrate 1; optionally, combined with Figure 2 , Figure 3As shown, the combination of the second sub-electrode 52 and the third sub-electrode 53 can be strip-shaped and located in the area formed by the intersection of two adjacent first metal lines 21 and two adjacent second metal lines 41.
[0105] In one possible implementation, combining Figure 1A , Figure 1F , Figure 2 , Figure 3 As shown, the second metal line 41 includes: a second metal line main portion 411 and a second metal line protrusion 412; the second metal line main portion 411 extends along a first direction X; the second metal line protrusion 412 protrudes from the second metal line main portion 411 along a direction perpendicular to the first direction; the orthographic projection of the second metal line protrusion 412 onto the substrate 1 overlaps with the orthographic projection of a portion of the first metal line 21 onto the substrate 1. In this embodiment, the second metal line 41 has a second metal line protrusion 412 at a position corresponding to the first metal line 21, that is, the second metal line 41 adds an edge along the direction of the first metal line 21 at a position corresponding to the first via K1, thereby extending the length of the transistor device channel along the direction of the first metal line 21 and ensuring the stability of the transistor device characteristics.
[0106] Optionally, the width of the second metal wire protrusion 412 along the first direction X can be the same as the width of the first metal wire 21 in the first direction;
[0107] In one possible implementation, combining Figure 1A , Figure 1E , Figure 3 As shown, the first active pattern 31 extends along the second direction Y, and the orthographic projection of the first active pattern 31 onto the substrate 1 overlaps with the orthographic projection of the first metal line 21 onto the substrate 1, and also overlaps with the orthographic projection of the second metal line 41 onto the substrate 1. That is, the first active pattern 31 is located at the intersection of the first metal line 21 and the second metal line 41; that is, in this embodiment of the present disclosure, the transistor is located at the intersection of the first metal line 21 and the second metal line 41.
[0108] Optional, combined Figure 1A , Figure 1E , Figure 3 As shown, the orthographic projection of the first active pattern 31 onto the substrate 1 can be rectangular; optionally, the orthographic projection of the first active pattern 31 onto the substrate 1 can cover the orthographic projection of the first via K1 onto the substrate 1; optionally, the width of the first active pattern 31 along the first direction X can be the same as the width of the first via K1 along the first direction X; optionally, the length of the first active pattern 31 along the second direction Y can be greater than the length of the first via K1 along the second direction Y.
[0109] In one possible implementation, combining Figure 1A , Figure 1E , Figure 3 As shown, the maximum width a1 of the first active pattern 31 in the first direction X is greater than the maximum width a2 of the first metal line 21 in the first direction X.
[0110] In one possible implementation, combining Figure 1A , Figure 3 As shown, the maximum width a3 of the first via K1 in the first direction X is greater than the maximum width a2 of the first metal line 21 in the first direction X. That is, the first via K1 exposes not only a portion of the first metal line 21, but also the portion surrounding the first metal line 21.
[0111] In one possible implementation, see Figure 1A As shown, the first metal line 21 is a straight line, and the pixels can be arranged in Real RGB.
[0112] In one possible implementation, see Figure 11 As shown, the first metal line 21 includes: a first sub-data section 211, a second sub-data section 212, and a third sub-data section 213; the first sub-data section 211 and the second sub-data section 212 both extend along the second direction Y, and the outer edge extension line f of the first sub-data section 211 extending along the second direction Y does not overlap with the second sub-data section 212; the third sub-data section 213 extends along the first direction X, and one end of the third sub-data section 213 is connected to the first sub-data section 211, and the other end is connected to the second sub-data section 212. Optionally, see [reference needed]. Figure 11 As shown, in the second direction Y, the second sub-electrode 52 and the third sub-electrode 53 can be located between two adjacent segments of the first sub-data line 211; in the first direction X, the second sub-electrode 52 and the third sub-electrode 53 can be located between two adjacent segments of the second sub-data line 212. In this embodiment, the pixel arrangement can adopt a Delta RGB arrangement, which can increase the pixel space.
[0113] In one possible implementation, see Figure 11 As shown, the orthographic projection of the first via K1 onto the substrate 1 overlaps with the orthographic projection of the third sub-data section 213 onto the substrate 1; the orthographic projection of the first active pattern 31 onto the substrate 1 overlaps with the orthographic projection of the third sub-data section 213 onto the substrate 1.
[0114] Optional, see Figure 11 As shown, the first active pattern 31 extends along the second direction Y; optionally, see [reference needed]. Figure 11 As shown, in two adjacent rows of sub-pixels, the orientation of the second sub-part 512 of the first sub-electrode 51 can be opposite.
[0115] In one possible implementation, see Figures 5-10As shown, the array substrate also includes: a plurality of driving transistors QT located in the peripheral region BB; the driving transistors QT include: driving source QTA, driving drain QTB, driving gate QTC, and driving active layer QTD; the driving source QTA and driving drain QTB are in the same layer and made of the same material as the first metal line 21.
[0116] In one possible implementation, see Figure 5 , Figures 7-9 As shown, the array substrate further includes a plurality of light-shielding portions G1 located in the display area AA; the orthographic projection of the light-shielding portion G1 onto the substrate 1 overlaps with the portion of the orthographic projection of the first active pattern 31 onto the substrate 1. In this embodiment of the present disclosure, the array substrate further includes a plurality of light-shielding portions G1, because the transistor is located in the area where the first metal line 21 and the second metal line 41 overlap, the increase of the light-shielding portion G1 will not cause a loss of aperture ratio, and at the same time can improve the illumination stability of the transistor.
[0117] In one possible implementation, see Figure 5 , Figure 7 , Figure 8 As shown, the light-shielding portion G1 and the driving gate QTC are on the same layer and made of the same material. In this way, the light-shielding portion G1 can be formed at the same time as the driving gate QTC, thereby simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.
[0118] In one possible implementation, see Figure 9 As shown, the light-shielding portion G1 is in the same layer and made of the same material as the driving active layer QTD. In this embodiment of the present disclosure, the light-shielding portion G1 can be in the same layer and made of the same material as the driving active layer QTD. Since the driving active layer QTD is made of Poly-Si, it can be thinner and can absorb ultraviolet light, and can also act as a shielding layer, which is beneficial to improving the aperture ratio and reducing the step difference. In this way, the light-shielding portion G1 can be formed at the same time as the driving active layer QTD, thereby simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.
[0119] In one possible implementation, see Figure 6 or Figure 9 As shown, the array substrate may also be without a light-shielding part. The first active pattern 31 is made of a metal oxide material with high light stability, so the light-shielding part can be removed.
[0120] In one possible implementation, the material of the driving active layer QTD in the peripheral area BB includes polysilicon. The material of the first active layer 3 in the display area AA may include an oxide active layer. That is, in this embodiment of the present disclosure, the transistors in the non-display area BB can be made of polysilicon active layer, which has advantages such as high mobility and fast charging. Oxide thin film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a single display panel forms a low-temperature polysilicon oxide display panel. By utilizing the advantages of both, high resolution (Pixel Per Inch, PPI) and low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.
[0121] In one possible implementation, see Figures 4A-4B ,as well as Figure 5 As shown, the array substrate may further include a common electrode 7 located on the side of the pixel electrode 5 facing away from the substrate 1; the common electrode 7 includes a plurality of cutouts 70. In one possible embodiment, the orthogonal projection of the pixel electrode 5 onto the substrate 1 partially coincides with the orthogonal projection of the cutouts 70 onto the substrate 1. Optionally, the cutouts 70 may extend obliquely, intersecting the extension direction of the second direction Y.
[0122] In one possible implementation, see Figure 5 As shown, the array substrate may further include: a second light-shielding layer 81 located on the side of the common electrode 7 away from the pixel electrode 5 and in direct contact with the common electrode 7, and a spacer 82 located on the side of the second light-shielding layer 81 away from the pixel electrode 5; the orthographic projection of the common electrode 7 on the substrate 1 covers the orthographic projection of the second light-shielding layer 81 on the substrate 1, and the linewidth of the second light-shielding layer 81 is smaller than the linewidth of the common electrode 7; the orthographic projection of the second light-shielding layer 81 on the substrate 1 covers the orthographic projection of the spacer 82 on the substrate 1, and the linewidth of the spacer 82 is smaller than the linewidth of the second light-shielding layer 82.
[0123] Optionally, the second light-shielding layer 81 can be made of a blackened metal material, and the spacer 82 can be made of molybdenum or aluminum (i.e., a material that can be wet-etched). The second light-shielding layer 81 and the spacer 82 can be formed by a single mask process, using wet etching and dry etching. By utilizing the difference in etching bias between the spacer 82 and the second light-shielding layer 81, the second light-shielding layer 81 and the spacer 82 can form a stepped shape.
[0124] Specifically, the thickness of the second light-shielding layer 81 can be 30nm to 80nm, and the thickness of the spacer 82 can be 0.4μm to 1μm. The second light-shielding layer 81 can be used to shield the second metal line 41 and the first metal line 21, and can also reduce the resistance of the common electrode 7.
[0125] In one possible implementation, the orthogonal projection of the second light-shielding layer 81 onto the substrate 1 covers the orthogonal projection of the first metal line 21 onto the substrate 1, and also covers the orthogonal projection of the second metal line 21 onto the substrate 1; the orthogonal projection of the spacer 82 onto the substrate 1 covers the orthogonal projection of the first metal line 21 onto the substrate 1, and also covers the orthogonal projection of the second metal line 41 onto the substrate 1.
[0126] Specifically, the shapes of the second light-shielding layer 81 and the spacer 82 can be similar to the pattern shape of the common electrode 7. The second light-shielding layer 81 may include a first light-shielding portion extending along the first direction X and a second light-shielding portion extending along the second direction Y. The first light-shielding portion and the second light-shielding portion intersect to form a mesh structure. The spacer 82 may include a first spacer portion extending along the first direction X and a second spacer portion extending along the second direction Y. The first spacer portion and the second spacer portion intersect to form a mesh structure. The spacer 82 with the mesh structure can be designed with a narrower line width, which is beneficial to improving the aperture ratio of the display panel.
[0127] In one possible implementation, see Figure 5 As shown, the array substrate may further include a fourth insulating layer F4 located between the pixel electrode 5 and the common electrode 7. Optionally, the fourth insulating layer F4 may be a passivation layer.
[0128] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, which includes an array substrate as provided in embodiments of this disclosure.
[0129] Based on the same inventive concept, this disclosure also provides a display device, which includes a display panel as provided in the embodiments of this disclosure. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.
[0130] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0131] Based on the same inventive concept, see [link to inventive concept] Figures 12A-12L As shown in the embodiments of this disclosure, a method for manufacturing a display panel as provided in the embodiments of this disclosure is also provided, comprising:
[0132] Step 1: Fabricate a first buffer layer F113 and an aSi layer on substrate 1 (substrate 1 can be, for example, a glass substrate), then perform common processes such as laser annealing, and finally form a Poly-Si layer (as the driving active layer QTD) through patterning and etching, such as... Figure 12A As shown;
[0133] Step 2: First, complete the first gate insulating layer F112, the driving gate QTC of the peripheral region BB, and simultaneously fabricate the light-shielding part G1 of the oxide TFT in the display area AA. Complete the first dielectric layer F111, and then perform patterning and etching processes, such as... Figure 12B As shown;
[0134] Step 3: Continue to complete the first metal line 21 of the display area AA, and the driving source QTA and driving drain QTB of the peripheral area BB. These three can share the first metal layer 2. Then, perform the deposition of the second buffer layer F12. The second buffer layer F12 is made of SiO2 or SiN / SiO2 stack, or it can be made of organosiloxane materials, etc., with a thickness of 200nm to 800nm. Because the thickness of the second buffer layer F12 determines the channel length of the oxide transistor, it can be increased according to the actual device characteristics requirements. Then, perform via etching of the second buffer layer F12, such as... Figure 12C As shown;
[0135] Step 4: Complete the first sub-electrode 51, extending it to the pixel opening area, with its starting point flush with the lower edge of the subsequent second metal line 41 (gate line), as shown below. Figure 12D and Figure 12E As shown;
[0136] Step 5: Deposition of the first active layer. The material can be indium gallium zinc oxide (IGZO), IGTO (In-Ga-Sn oxide), or other doped indium zinc oxide (IZO) or indium tin zinc oxide (ITZO) materials, patterned as the first active pattern 31. The first active pattern 31 overlaps the first metal line 21 and the first sub-electrode 51, and then the second gate insulating layer F23 is deposited. The material is SiO2, with a thickness of 80nm to 150nm. Then, the second metal line 41 (gate line) is deposited. The material is Mo, Al, Cu, or other alloy materials. The second metal line 41 (gate line) intersects the first metal line 21 (data line) perpendicularly. At the same time, the second metal line 41 (gate line) is specially compensated by adding a rim along the direction of the first metal line 21 (data line) at the first via K1 position, thereby extending the channel length of the transistor device to ensure device characteristics, as follows. Figure 12F , 12G , Figure 12H As shown;
[0137] Step Six: Deposit the second dielectric layer F22 and the first planarization layer F21. The second dielectric layer F22 is selected as SiO2 / SiN, with a thickness ranging from 300nm to 600nm. The first planarization layer F21 can be made of acrylic or organic resin, requiring good planarization performance and high transmittance. The first planarization layer F21 adopts a trench design, with a thickness ranging from 1.0μm to 2.0μm. Using the first planarization layer F21 as a mask, etch the second dielectric layer F22, and then perform the deposition and patterning of the second sub-electrode 52, as follows... Figure 12I and Figure 12J As shown;
[0138] Step 7: Complete the subsequent leveling process for the third insulating layer F3 (second planarization layer) and the subsequent third sub-pixel electrode 53, common electrode 7, and second light-shielding layer 81 (Common metal, CM layer). Form the metal stack structure (pillow) using a single mask etching process, such as... Figure 12K , Figure 12L As shown.
[0139] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0140] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, It has a display area and a peripheral area located around the display area; The array substrate includes: Substrate; A first metal layer is located on one side of the substrate, and the first metal layer includes: a plurality of first metal lines located in the display area; A first active layer is located on the side of the first metal layer facing away from the substrate, and the first active layer includes a plurality of first active patterns located in the display area; A first insulating layer is located on the side of the first active layer facing the substrate; the first insulating layer includes: a first sub-insulating layer located between the first metal layer and the substrate, and a second sub-insulating layer located between the first metal layer and the first active layer; the first insulating layer has a plurality of first vias located in the display area, the first vias penetrating the second sub-insulating layer, exposing a portion of the first metal line, and a portion of the first sub-insulating layer exposing at least one side of the first metal line; the first active pattern passes through the first vias, partially covering the first metal line, and partially covering the first insulating layer on the side of the first metal line; The second metal layer is located on the side of the first active layer away from the first insulating layer. The second metal layer includes: a plurality of second metal lines located in the display area and extending along a first direction; the orthogonal projection of the second metal lines on the substrate covers the orthogonal projection of the first via on the substrate.
2. The array substrate as claimed in claim 1, wherein, The first sub-insulating layer has a first surface facing away from the substrate, and the first via exposes a portion of the first surface; the first active pattern covers a portion of the first surface.
3. The array substrate as claimed in claim 1, wherein, The first sub-insulating layer has a first surface facing away from the substrate; the first via passes through the first surface and extends through the first surface into the interior of the first sub-insulating layer.
4. The array substrate as claimed in claim 3, wherein, The array substrate further includes a light-shielding layer located on the side of the first insulating layer facing the substrate; The light-shielding layer has a cutout portion; the orthographic projection of the cutout portion onto the substrate covers the orthographic projection of the first active pattern onto the substrate.
5. The array substrate according to any one of claims 2-4, wherein, The array substrate further includes: a plurality of pixel electrodes located in the display area; the pixel electrodes include: a first sub-electrode; the first active pattern also covers a portion of the first sub-electrode.
6. The array substrate as claimed in claim 5, wherein, The first sub-electrode includes: a first sub-part, and a second sub-part connected to the first sub-part; The orthographic projection of the first sub-part onto the substrate is located in the region between the orthographic projections of two adjacent first metal lines onto the substrate; the orthographic projection of the second sub-part onto the substrate overlaps with the orthographic projection of the first metal line onto the substrate.
7. The array substrate as claimed in claim 5, wherein, The second metal line includes a first outer edge and a second outer edge; the first outer edge, in its orthographic projection onto the substrate, is located on the side of the second outer edge in its orthographic projection onto the substrate that faces the first sub-electrode. The second sub-part has a third outer edge on the side away from the first sub-part, the third outer edge extending along the first direction; the orthographic projection of the third outer edge onto the substrate coincides with the orthographic projection of the first outer edge onto the substrate.
8. The array substrate according to any one of claims 5-7, wherein, The orthographic projection of the first sub-electrode onto the substrate does not overlap with the orthographic projection of the first via onto the substrate.
9. The array substrate according to any one of claims 5-8, wherein, The first sub-electrode is located between the first active layer and the second sub-insulating layer.
10. The array substrate according to any one of claims 5-8, wherein, The first active pattern includes: a first pattern portion and a second pattern portion; the orthographic projection of the first pattern portion on the substrate overlaps with the orthographic projection of the second metal line on the substrate; the orthographic projection of the second pattern portion on the substrate and the orthographic projection of the second metal line on the substrate do not overlap. The first sub-electrode reuses the second patterned portion, and the conductivity of the second patterned portion is higher than that of the first patterned portion.
11. The array substrate according to any one of claims 6-10, wherein, The pixel electrode further includes: a second sub-electrode located on the side of the second metal layer away from the substrate, and a third sub-electrode located on the side of the second sub-electrode away from the substrate and partially stacked with the second sub-electrode; The array substrate further includes: a second insulating layer located between the second metal layer and the second sub-electrode; the second insulating layer has a second via, the second via exposing a portion of the first sub-part, and the second sub-electrode overlapping the first sub-part of the first sub-electrode via the second via.
12. The array substrate according to any one of claims 1-11, wherein, The second metal wire includes: a main portion of the second metal wire and a protruding portion of the second metal wire; the main portion of the second metal wire extends along the first direction; the protruding portion of the second metal wire protrudes from the main portion of the second metal wire in a direction perpendicular to the first direction; The orthographic projection of the second metal wire protrusion on the substrate overlaps with the orthographic projection of a portion of the first metal wire on the substrate.
13. The array substrate as claimed in claim 12, wherein, The first active pattern extends along the second direction, and the orthographic projection of the first active pattern on the substrate overlaps with the orthographic projection of the first metal line on the substrate, and also overlaps with the orthographic projection of the second metal line on the substrate.
14. The array substrate as claimed in claim 13, wherein, The maximum width of the first active pattern in the first direction is greater than the maximum width of the first metal line in the first direction.
15. The array substrate according to any one of claims 1-14, wherein, The maximum width of the first via in the first direction is greater than the maximum width of the first metal line in the first direction.
16. The array substrate according to any one of claims 1-15, wherein, The first metal line includes: a first sub-data section, a second sub-data section, and a third sub-data section; The first sub-data section and the second sub-data section both extend along the second direction, and the outer edge extension line of the first sub-data section extending along the second direction does not overlap with the second sub-data section; the third sub-data section extends along the first direction, and one end of the third sub-data section is connected to the first sub-data section, and the other end is connected to the second sub-data section.
17. The array substrate as claimed in claim 16, wherein, The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the third sub-data section on the substrate; The orthographic projection of the first active pattern onto the substrate overlaps with the orthographic projection of the third sub-data section onto the substrate.
18. The array substrate according to any one of claims 1-3 and 5-17, wherein, The array substrate further includes: a plurality of driving transistors located in the peripheral region; the driving transistors include: a driving source, a driving drain, a driving gate, and a driving active layer; The driving source and the driving drain are in the same layer and made of the same material as the first metal line.
19. The array substrate as claimed in claim 18, wherein, The array substrate further includes: a plurality of light-shielding portions located in the display area; the orthographic projection of the light-shielding portions on the substrate overlaps with the portion of the orthographic projection of the first active pattern on the substrate; The light-shielding portion is in the same layer and made of the same material as the driving gate; or, the light-shielding portion is in the same layer and made of the same material as the driving active layer.
20. A display device, wherein, Includes the array substrate as described in any one of claims 1-19.