Display device

Abstract

According to one embodiment, a display device includes: a substrate having a display region on which an image is displayed; a plurality of pixels disposed in the display area, each of the plurality of pixels including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light according to an applied voltage; a dummy pixel region surrounding the display region and including a plurality of dummy pixels that do not display an image; and a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall being provided in the display region, the dummy pixel region, and an outer peripheral region surrounding the dummy pixel region. Furthermore, the partition wall has a plurality of slits provided in the display region and the dummy pixel region, and the slits are not provided at the boundary between the dummy pixel region and the outer peripheral region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-124584 filed on July 31, 2024, and incorporates the entire contents of the Japanese Patent Application by reference. TECHNICAL FIELD

[0003] The present application relates to a display device. BACKGROUND

[0004] In recent years, a display device in which an organic light emitting diode (OLED) is applied as a display element has been put into practical use. In such a display device, a technique for improving yield is required. SUMMARY

[0005] According to an embodiment, a display device has a substrate having a display region in which an image is displayed, a plurality of pixels arranged in the display region, each of the plurality of pixels including a lower electrode, an upper electrode positioned above the lower electrode, and an organic layer positioned between the lower electrode and the upper electrode and emitting light according to an applied voltage, a dummy pixel region surrounding the display region, the dummy pixel region including a plurality of dummy pixels that do not display an image, and a barrier including a lower portion that is electrically conductive, and an upper portion having an end portion protruding from a side surface of the lower portion, the barrier being provided in the display region, the dummy pixel region, and a peripheral region surrounding the dummy pixel region. The barrier has a plurality of slits provided in the display region and the dummy pixel region, and the slits are not provided at a boundary between the dummy pixel region and the peripheral region.

[0006] According to an embodiment, a display device has a substrate having a display region in which an image is displayed, a plurality of pixels arranged in the display region, each of the plurality of pixels including a lower electrode, an upper electrode positioned above the lower electrode, and an organic layer positioned between the lower electrode and the upper electrode and emitting light according to an applied voltage, a dummy pixel region surrounding the display region, the dummy pixel region including a plurality of dummy pixels that do not display an image, a barrier including a lower portion that is electrically conductive, and an upper portion having an end portion protruding from a side surface of the lower portion, the barrier being provided in the display region, the dummy pixel region, and a peripheral region surrounding the dummy pixel region, a first sealing layer formed of an inorganic insulating material and covering the plurality of pixels and the plurality of dummy pixels, and a second sealing layer formed of an inorganic insulating material and covering the peripheral region. The barrier has a plurality of slits provided at least in the display region and the dummy pixel region, at least one of the plurality of slits is positioned at a boundary between the dummy pixel region and the peripheral region, and the second sealing layer covers the slit positioned at the boundary.

[0007] According to these configurations, it is possible to improve the yield of the display device. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a diagram showing a configuration example of the display device of the first embodiment.

[0009] Figure 2 is a schematic plan view showing an example of the layout of the sub-pixel of the first embodiment.

[0010] Figure 3 is a schematic cross-sectional view of the display device along the III-III line in Figure 2

[0011] Figure 4 is a schematic plan view of the display device of the first embodiment.

[0012] Figure 5 is a schematic cross-sectional view of the peripheral region of the display device of the first embodiment.

[0013] Figure 6 is a schematic plan view enlarging the region surrounded by the frame VI in Figure 4

[0014] Figure 7 is a schematic plan view enlarging the vicinity of the boundary between the dummy pixel region and the outer peripheral region of the first embodiment.

[0015] Figure 8 is a schematic cross-sectional view of the dummy pixel region and the outer peripheral region along the VIII-VIII line in Figure 7

[0016] Figure 9 is a schematic plan view of the mother substrate of the first embodiment.

[0017] Figure 10 is a schematic plan view of the panel portion of the first embodiment.

[0018] Figure 11 is a flowchart showing an example of the manufacturing method of the first embodiment.

[0019] Figure 12A is a schematic cross-sectional view showing a manufacturing step of the display device.

[0020] Figure 12B is a schematic cross-sectional view showing a subsequent step of Figure 12A

[0021] Figure 12C is a schematic cross-sectional view showing a subsequent step of Figure 12B

[0022] ​​​​​Figure 12D is a schematic cross-sectional view of a subsequent step. Figure 12C

[0023] Figure 12E is a schematic cross-sectional view of a subsequent step. Figure 12D

[0024] Figure 12F is a schematic cross-sectional view of a subsequent step. Figure 12E

[0025] Figure 12G is a schematic cross-sectional view of a subsequent step. Figure 12F

[0026] Figure 13 is a schematic plan view showing the configuration of a comparative example.

[0027] Figure 14 is a schematic cross-sectional view of a dummy pixel region and a peripheral region along the line XIV-XIV in Figure 7

[0028] is a schematic plan view showing the configuration of a second embodiment. Figure 15

[0029] Figure 16 is a schematic cross-sectional view of a dummy pixel region and a peripheral region along the line XVI-XVI in Figure 15

[0030] Figure 17 is a schematic plan view showing the configuration of a third embodiment.

[0031] Figure 18 is a schematic cross-sectional view of a dummy pixel region and a peripheral region along the line XVIII-XVIII in Figure 17

[0032] Figure 19 is a schematic plan view showing the configuration of a fourth embodiment.

[0033] Figure 20 is a schematic plan view showing the configuration of a fifth embodiment.

[0034] Figure 21 is a schematic plan view showing the configuration of a sixth embodiment. DETAILED DESCRIPTION

[0035] Several embodiments will be described with reference to the accompanying drawings, wherein:

[0036] ​​​​​​​The disclosure is only one example, and appropriate modifications that can be easily conceived by those skilled in the art while maintaining the gist of the application are of course included within the scope of the application. In addition, with regard to the drawings, in order to make the description clearer, the width, thickness, shape, and the like of each portion are sometimes schematically represented compared to the actual manner, but this is only one example and is not intended to limit the explanation of the application. In addition, in the present specification and the drawings, there are cases where the same reference numerals are attached to constituent elements that exhibit the same or similar functions to those of the constituent elements described with regard to the drawing explanation that has been made, and detailed description is appropriately omitted.

[0037] Note that the X-axis, Y-axis, and Z-axis that are orthogonal to one another are described in the drawings as needed for ease of understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the case where various constituent elements are observed in parallel with the Z-direction is referred to as plan view observation.

[0038] The display device of each embodiment is an organic electroluminescent display device provided with an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, wearable terminals, and the like.

[0039] [First Embodiment]

[0040] Figure 1 is a view that shows a configuration example of the display device DSP of the present embodiment. The display device DSP has a substrate 10 that is insulating. The substrate 10 has a display region DA that displays an image, and a surrounding region SA around the display region DA. The substrate 10 can be glass, or can be a resin film that has flexibility.

[0041] In the present embodiment, the shape of the substrate 10 and the display region DA in plan view observation is circular. However, the shape of the substrate 10 and the display region DA in plan view observation is not limited to circular, and can be other shapes such as rectangular, square, or elliptical.

[0042] The display region DA has a plurality of pixels PX arranged in a matrix shape in the X-direction and the Y-direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, a case is assumed in which the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. The pixel PX can include a sub-pixel SP of another color such as white, together with the sub-pixels SP1, SP2, SP3, or instead of any one of the sub-pixels SP1, SP2, SP3.

[0043] The display device DSP also has a terminal portion T disposed in the peripheral area SA. On the terminal portion T, a flexible circuit board that supplies, for example, a voltage and a signal for driving the display device DSP is connected.

[0044] The sub-pixel SP has a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 has a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are, for example, switching elements constituted by thin film transistors.

[0045] In the display area DA, a plurality of scan lines G that supply a scan signal to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines S that supply an image signal to the pixel circuit 1 of each sub-pixel SP, and a plurality of power lines PL are disposed. Figure 1 In the example, the scan lines G and the power lines PL extend in the X direction, and the signal lines S extend in the Y direction, but are not limited to this example.

[0046] The gate electrode of the pixel switch 2 is connected to the scan line G. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0047] Further, the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 can have more thin film transistors and capacitors.

[0048] Figure 2 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, SP3 that constitute one pixel PX. Figure 2 In the example of, the sub-pixels SP1, SP3 are arranged in the Y direction. In addition, the sub-pixels SP1, SP3 are arranged in the X direction with the sub-pixel SP2 therebetween.

[0049] In the case where the sub-pixels SP1, SP2, SP3 are arranged in this manner, in the display area DA, a column in which the sub-pixels SP1, SP3 are alternately arranged in the Y direction, and a column in which a plurality of sub-pixels SP2 are repeatedly arranged in the Y direction are formed. These columns are alternately arranged in the X direction. Further, the layout of the sub-pixels SP1, SP2, SP3 is not limited to the example of. Figure 2

[0050] In the display area DA, a rib portion layer 5 is disposed. The rib portion layer 5 has pixel openings AP1, AP2, AP3 in the sub-pixels SP1, SP2, SP3, respectively. Figure 2 ​In the example, the pixel openings AP1, AP2, AP3 are each a rectangular column. The area of the pixel opening AP1 is larger than the area of the pixel opening AP3. In addition, the area of the pixel opening AP2 is larger than the area of the pixel opening AP1. However, the shape of the pixel openings AP1, AP2, AP3 is not limited to the example.

[0051] The sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel opening AP1, respectively. The sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel opening AP2, respectively. The sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel opening AP3, respectively.

[0052] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute a display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute a display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute a display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, DE3 can also include a cover layer described later. The rib layer 5 surrounds each of the display elements DE1, DE2, DE3.

[0053] A partition wall 6 of an electrically conductive material is disposed above the rib layer 5. The partition wall 6 has a function as a wiring that supplies a common voltage to the upper electrodes UE1, UE2, UE3. The partition wall 6 overlaps the rib layer 5 as a whole and has the same planar shape as the rib layer 5. The partition wall 6 surrounds the sub-pixels SP1, SP2, SP3.

[0054] The partition wall 6 has a plurality of slits SLa extending in the Y direction. Figure 2 In the example, the sub-pixels SP1, SP2, SP3 that constitute one pixel PX are disposed between two slits SLa in the X direction. Also, the partition wall 6 has a connection portion CT that connects portions broken by the slits SLa. In addition, the configuration pattern of the slits SLa and the connection portion CT is not limited to the example. Figure 2 For example, a slit SLa that is continuous between both ends in the Y direction of the display region DA can also exist.

[0055] In the sub-pixels SP1, SP2, SP3, sealing layers SE11, SE12, SE13 (first sealing layers) are respectively disposed. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around the display element DE1. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around the display element DE2. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around the display element DE3.

[0056] Figure 2In the example, the sealing layers SE11, SE12, and SE13 do not overlap the slit Sla. As another example, at least one of the sealing layers SE11, SE12, and SE13 can also overlap the slit Sla.

[0057] Figure 3 is along the III-III line of Figure 2 A schematic cross-sectional view of a display device DSP along the III-III line of Figure 1 The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, the scan line G, the signal line S, and the power line PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film that planarizes irregularities generated by the circuit layer 11.

[0058] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The peripheral edge portions of the lower electrodes LE1, LE2, and LE3 are covered with the rib layer 5. Although not shown in the cross section of Figure 3 The lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12, although not shown in the cross section of

[0059] The partition wall 6 includes a lower portion 61 having conductivity disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. That is, the partition wall 6 has a cantilever shape in which both end portions of the upper portion 62 protrude from side surfaces of the lower portion 61.

[0060] Figure 3 In the example, the lower portion 61 has a base layer 63 disposed on the rib layer 5, and a shaft portion layer 64 disposed on the base layer 63. For example, the base layer 63 is formed thinner than the shaft portion layer 64. Figure 3 In the example, both end portions of the base layer 63 protrude from side surfaces of the shaft portion layer 64.

[0061] In addition, Figure 3 In the example, the upper portion 62 has a first top layer 65, and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. Not limited thereto, the first top layer 65 and the second top layer 66 can have the same width.

[0062] The organic layer OR1 covers the lower electrode LE1 from the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and opposes the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 from the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and opposes the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 from the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and opposes the lower electrode LE3. The upper electrodes UE1, UE2, UE3 contact the lower portion 61 of the partition wall 6.

[0063] The display element DE1 includes a cover layer CP1 that covers the upper electrode UE1. The display element DE2 includes a cover layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cover layer CP3 that covers the upper electrode UE3. The cover layers CP1, CP2, CP3 respectively function as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, OR3.

[0064] In the following description, a multilayer body including the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is referred to as a laminated film FL1, a multilayer body including the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is referred to as a laminated film FL2, and a multilayer body including the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is referred to as a laminated film FL3.

[0065] In the subpixels SP1, SP2, SP3, sealing layers SE11, SE12, SE13 are respectively provided. Specifically, the sealing layer SE11 continuously covers the laminated film FL1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the laminated film FL2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the laminated film FL3 and the partition wall 6 around it.

[0066] The sealing layers SE11, SE12, SE13 are covered by a resin layer RS1. The resin layer RS1 is covered by a sealing layer SE2. The sealing layer SE2 is covered by a resin layer RS2. The resin layers RS1, RS2 and the sealing layer SE2 are continuously provided at least on the entire display region DA, and a part thereof reaches the surrounding region SA.

[0067] Figure 3 In the example of FIG. 9, a touch panel electrode TP for detecting a touch operation by a user is provided on the sealing layer SE2. The touch panel electrode TP is formed of, for example, a metal material and has the same shape as the partition wall 6 when viewed in plan.

[0068] A cover member such as a polarizing plate, a protective film, or a cover glass can be further provided above the resin layer RS2. Such a cover member can be adhered to the resin layer RS2 via an adhesive layer such as an optical clear adhesive (OCA).

[0069] Figure 3 In the example, the end portions of the sealing layers SE11, SE12 overlap each other in the Z direction at the upper portion of the partition wall 6 between the sub-pixels SP1, SP2. In addition, the end portions of the sealing layers SE11, SE13 overlap each other in the Z direction at the partition wall 6 between the sub-pixels SP1, SP3.

[0070] For example, a gap is formed between the sealing layer SE11 and the upper portion 62 of the partition wall 6. In addition, a gap is also formed between the sealing layer SE12 and the upper portion 62, and between the end portion of the sealing layer SE11 and the end portion of the sealing layer SE12. These gaps are generated due to the disappearance of the laminated films FL1, FL2 during the manufacturing process. At least a part of these gaps can be filled with the resin layer RS1.

[0071] On the other hand, the laminated film FL3a is disposed between the sealing layer SE13 and the partition wall 6, and between the end portion of the sealing layer SE11 and the end portion of the sealing layer SE13. The laminated film FL3a is, for example, obtained by modifying the laminated film FL3 during the manufacturing process. Further, the laminated film FL3a can also be made to disappear during the manufacturing process. In this case, a gap is generated between the sealing layer SE13 and the partition wall 6, and between the end portions of the sealing layers SE11, SE13.

[0072] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of, for example, a resin material (organic insulating material) such as an epoxy resin and a polypropylene resin.

[0073] The lower electrodes LE1, LE2, LE3 have, for example, a reflective layer formed of silver, and a pair of conductive oxide layers that cover the upper surface and the lower surface of the reflective layer, respectively. Each conductive oxide layer can be formed of, for example, a transparent conductive oxide of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0074] The upper electrodes UE1, UE2, UE3 are formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0075] The organic layers OR1, OR2, OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, OR3 have a configuration in which a hole-injection layer, a hole-transport layer, an electron-blocking layer, a light-emitting layer, a hole-blocking layer, an electron-transport layer, and an electron-injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, OR3 can also have other configurations such as a so-called stacked configuration including a plurality of light-emitting layers.

[0076] The cover layers CP1, CP2, CP3 have, for example, a stacked configuration in which a plurality of transparent layers are stacked. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, UE3 and the refractive indices of the sealing layers SE11, SE12, SE13. Furthermore, at least one of the cover layers CP1, CP2, CP3 can also be omitted.

[0077] The bottom layer 63 and the shaft portion layer 64 of the partition wall 6 are formed of a metal material. As the metal material of the bottom layer 63, for example, molybdenum, titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft portion layer 64, for example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi) can be used. Furthermore, the shaft portion layer 64 can also be formed of an insulating material.

[0078] The first top layer 65 of the partition wall 6 is formed of, for example, a metal material, and the second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. As the metal material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. Furthermore, the upper portion 62 can have three or more layers or can be formed of a single layer. Also, the upper portion 62 can include a layer formed of an insulating material.

[0079] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the lower portion 61, respectively. To the lower electrodes LE1, LE2, LE3, a pixel voltage corresponding to an image signal of the signal line S is supplied by the pixel circuit 1 of the sub-pixel SP1, SP2, SP3, respectively.

[0080] The organic layers OR1, OR2, OR3 emit light according to the applied voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0081] As another example, the light-emitting layers of the organic layers OR1, OR2, OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can have a color filter that converts the light emitted by the light-emitting layers into light of colors corresponding to the sub-pixels SP1, SP2, SP3. Alternatively, the display device DSP can have a layer including quantum dots that are excited by the light emitted by the light-emitting layers and generate light of colors corresponding to the sub-pixels SP1, SP2, SP3.

[0082] Figure 4 is a schematic plan view of the display device DSP. In the example of this figure, in the peripheral area SA, there is provided a dummy pixel area DMY that surrounds the display area DA. In the dummy pixel area DMY, there is also provided the partition wall 6.

[0083] Also, in an outer peripheral area OP that surrounds the dummy pixel area DMY, there is also provided the partition wall 6. In the outer peripheral area OP, the partition wall 6 is covered by a sealing layer SE1x (2nd sealing layer). The sealing layer SE1x is formed of the same inorganic insulating material as the sealing layers SE11, SE12, SE13.

[0084] Outside the sealing layer SE1x, there is provided a dam structure DS1. The terminal portion T is located outside the dam structure DS1. For example, the dummy pixel area DMY, the outer peripheral area OP, the sealing layer SE1x, and the dam structure DS1 are all circular in a concentric circular shape with the display area DA.

[0085] In the outer peripheral area OP, the partition wall 6 is connected to the underlying relay layer RL and the feed line PW (see Figure 5 ) via a plurality of contact portions CN1. The feed line PW is connected to the terminal portion T and receives supply of the common voltage from the terminal portion T. The common voltage of the partition wall 6 is supplied to the upper electrodes UE1, UE2, UE3 that are in contact with the partition wall 6. Figure 4 In the example of FIG. 8, the plurality of contact portions CN1 are arranged in a circular arc shape on the terminal portion T side.

[0086] Figure 5 is a schematic sectional view of the peripheral area SA of the display device DSP. The configuration of the partition wall 6 in the outer peripheral area OP is the same as that of Figure 3The configuration of the partition wall 6 in the display region DA shown is the same.

[0087] Figure 3 The circuit layer 11 shown includes inorganic insulating layers 31, 32, 33 formed of inorganic insulating materials, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed on the organic insulating layer 34, covered by the organic insulating layer 12.

[0088] For example, the dam structure DS1 has a dam portion DM1, a dam portion DM2 that surrounds the dam portion DM1, and a dam portion DM3 that surrounds the dam portion DM2. For example, the dam portions DM1, DM2, DM3 are circular shapes that surround the display region DA. Further, the number of dam portions that the dam structure DS1 has is not limited to three.

[0089] The dam portions DM1, DM2, DM3 each protrude upward of the substrate 10. Figure 5 In the example, the dam portion DM1 is formed of the organic insulating layers 12, 34. The dam portions DM2, DM3 are also similarly formed of the organic insulating layers 12, 34. That is, in the present embodiment, the dam portions DM1, DM2, DM3 are formed of the same material as the organic insulating layers 12, 34 as the same layers as the organic insulating layers 12, 34.

[0090] Below the dam portions DM1, DM2, a feeding line PW that applies a common voltage is disposed. The feeding line PW has a first wiring W1 formed of the metal layer 42, and a second wiring W2 formed of the metal layer 43.

[0091] Figure 5 In the example, the first wiring W1 and the second wiring W2 are in contact through a contact portion CN0 located between the dam portions DM1, DM2. In each of the dam portions DM1, DM2, a portion of the second wiring W2 is located between the organic insulating layers 12, 34.

[0092] In the peripheral region SA, a conductive relay layer RL that connects the partition wall 6 and the feeding line PW, and a rib layer 5 are also disposed. The relay layer RL is formed of the same material as the above-described lower electrodes LE1, LE2, LE3, for example, through the same process.

[0093] The relay layer RL is located on the display region DA side (left side in the figure) compared to the dam portion DM1, covering the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the dam portions DM1, DM2, DM3.

[0094] In the outer peripheral region OP, partition 6 is positioned above rib layer 5. Partition 6 is also... Figure 4 The contact portion CN1 shown is in contact with the relay layer RL. Specifically, the rib layer 5 has an opening in the contact portion CN1, through which the lower part 61 (specifically the bottom layer 63) of the partition wall 6 contacts the relay layer RL. The contact portion CN1 is located above the organic insulating layer 12.

[0095] The relay layer RL contacts the second wiring W2 of the feeder line PW in the contact part CN2. When viewed from above, the contact part CN2 is located between the end E0 of the organic insulation layer 12 and the dam part DM1.

[0096] In the outer peripheral region OP, a laminated membrane FLx is disposed above the partition wall 6. The partition wall 6 and the laminated membrane FLx are covered by a sealing layer SE1x. The laminated membrane FLx is connected to... Figure 3 The laminated films FL1, FL2, and FL3 shown are formed using the same process and the same materials. The sealing layer SE1x is formed by... Figure 3 The sealing layers SE11, SE12, and SE13 shown are formed using the same process and the same materials. In this embodiment, it is envisioned that the laminated film FLx and the sealing layer SE1x are formed using the same process and the same materials as the laminated film FL3 and the sealing layer SE13. That is, the laminated film FLx includes the upper electrode UE3, the organic layer OR3, and the capping layer CP3.

[0097] Above the sealing layer SE1x, there is configured Figure 3 The resin layer RS1, sealing layer SE2, and resin layer RS2 are shown. Additionally, a layer is disposed on top of the sealing layer SE2 that... Figure 3 The touch panel electrode TP shown is connected to the touch panel wiring TPL. For example, the touch panel wiring TPL is formed of the same material as the touch panel electrode TP.

[0098] Resin layer RS1 covers sealing layer SE1x and rib layer 5. Dams DM1, DM2, and DM3 serve to block the resin layer RS1 before it cures during the manufacturing of the display device DSP. Figure 5 In this example, the end Er1 of the resin layer RS1 is located above the dam DM2. That is, the resin layer RS1 covers a portion of both the dam DM1 and the dam DM2. However, the location of the end Er1 is not limited to this example.

[0099] The sealing layer SE2 covers the end Er1 of the resin layer RS1. The sealing layer SE2 contacts the rib layer 5 in the area located on the outer side (right side in the figure) compared to the end Er1. Figure 5In the example, the seal layer SE2 is removed near the dam portion DM3. The resin layer RS1 is surrounded by the seal layer SE1x, the rib layer 5, and the seal layer SE2. Thereby, the moisture is suppressed from being infiltrated into the resin layer RS1.

[0100] As shown in Figure 5 , the organic insulating layer 12 can also have a first portion PN1 and a second portion PN2 that is thinner than the first portion PN1. The second portion PN2 is formed on the periphery of the first portion PN1. That is, the second portion PN2 surrounds the first portion PN1 when viewed from above. The partition wall 6, the laminated film FLx, and the seal layer SE1x in the outer peripheral region OP are all located above the first portion PN1.

[0101] Figure 5 In the example, the organic insulating layer 34 is disposed below the first portion PN1, and the organic insulating layer 34 is not disposed below the second portion PN2. Near the end portion of the organic insulating layer 34, a step portion 12a is generated in the organic insulating layer 12. For example, the portion of the organic insulating layer 12 that is located on the dam portion DM1 side compared to the step portion 12a corresponds to the second portion PN2.

[0102] The relay layer RL covers the first portion PN1, the second portion PN2, and the step portion 12a. In the case where the organic insulating layer 12 is assumed not to have the second portion PN2, the step portion 12a would be steeper. If the relay layer RL is formed in a manner of covering such a steep step portion 12a, there is a possibility that the relay layer RL generates a shape abnormality. In contrast, in the case where the second portion PN2 is provided, the step portion 12a is made gentle, and the relay layer RL can be formed favorably.

[0103] Further, Figure 5 , the cross-sectional configuration shown in Figure 5 is applicable to any position of the surrounding region SA except for the vicinity of the terminal portion T. However, the configuration of the surrounding region SA is not necessarily limited to the configuration shown in Figure 5 . For example, the organic insulating layer 12 can also not have the second portion PN2. In addition, the configuration for connecting the partition wall 6 and the feed line PW can also be appropriately deformed based on the position of the feed line PW and the layer configuration of the circuit layer 11, and the like.

[0104] Figure 6 is an enlarged schematic plan view of the region surrounded by the frame VI in Figure 4 . A plurality of dummy pixels DPX are disposed in the dummy pixel region DMY. For example, the dummy pixel DPX includes dummy sub-pixels DP1, DP2, DP3. The dummy sub-pixels DP1, DP2, DP3 each have a configuration similar to the sub-pixels SP1, SP2, SP3 shown in Figure 2 .

[0105] That is, the dummy sub-pixel DP1 has the lower electrode LE1, the organic layer OR1, the upper electrode UE1, and the sealing layer SE11. Further, the dummy sub-pixel DP2 has the lower electrode LE2, the organic layer OR2, the upper electrode UE2, and the sealing layer SE12. Further, the dummy sub-pixel DP3 has the lower electrode LE3, the organic layer OR3, the upper electrode UE3, and the sealing layer SE13.

[0106] However, the dummy sub-pixels DP1, DP2, DP3 are configured in such a manner that they do not emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy sub-pixels DP1, DP2, DP3. Further, the pixel openings AP1, AP2, AP3 can also be omitted in each of the dummy sub-pixels DP1, DP2, DP3. Thereby, the rib layer 5 is interposed between the organic layers OR1, OR2, OR3 and the lower electrodes LE1, LE2, LE3, and does not apply a voltage for causing the organic layers to emit light to the organic layers OR1, OR2, OR3.

[0107] A part of the partition wall 6 is located in the dummy pixel region DMY, and surrounds each of the plurality of dummy pixels DPX. More specifically, the partition wall 6 surrounds each of the dummy sub-pixels DP1, DP2, DP3.

[0108] The outer peripheral region OP is formed continuously with the partition wall 6 in the dummy pixel region DMY. For example, the outer peripheral region OP corresponds to a part of the partition wall 6 that overlaps with the sealing layer SE1x. The lower electrodes LE1, LE2, LE3 and the pixel circuit PC are not disposed in the outer peripheral region OP, although they are disposed in the display region DA and the dummy pixel region DMY.

[0109] For example, the opening pattern of the partition wall 6 in the display region DA and the dummy pixel region DMY is the same. That is, the partition wall 6 has openings 71, 72, 73 (first openings) in the sub-pixels SP1, SP2, SP3, respectively, and has openings 81, 82, 83 (second openings) in the dummy sub-pixels DP1, DP2, DP3, respectively. The openings 71, 72, 73 have the same shape as the openings 81, 82, 83, respectively. Further, the arrangement of the openings 71, 72, 73 is the same as the arrangement of the openings 81, 82, 83.

[0110] The partition wall 6 has a plurality of openings 91 (third openings) provided in the outer peripheral region OP. These openings 91 are arranged at a fixed interval in the X direction and the Y direction. Each of the openings 91 is, for example, a rectangle in which the length in the Y direction is larger than the length in the X direction, but can be other shapes.

[0111] The slit SLa and the connection portion CT are provided in the display region DA. The slit SLa and the connection portion CT are also provided in the dummy pixel region DMY. On the other hand, in the present embodiment, the slit SLa and the connection portion CT are not provided in the outer peripheral region OP.

[0112] In the present embodiment, the display region DA, the dummy pixel region DMY, and the outer peripheral region OP each have a circular shape. Such a shape can be realized by, for example, making the boundary between the display region DA and the dummy pixel region DMY, and the boundary between the dummy pixel region DMY and the outer peripheral region OP, as shown in FIG. 8, stepwise. Figure 6

[0113] In this way, if the boundary between the dummy pixel region DMY and the outer peripheral region OP is stepwise, as surrounded by the frame A, a portion where the openings 82 of the dummy pixel region DMY and the openings 91 of the outer peripheral region OP are arranged in the X direction is generated. In the present embodiment, in this portion, that is, between the openings 82, 91 arranged in the X direction, the slit SLa is not provided.

[0114] Figure 7 is an enlarged schematic plan view of the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP. As with the sub-pixels SP1, SP2, SP3, the sealing layers SE11, SE12, SE13 are respectively provided on the dummy sub-pixels DP1, DP2, DP3. The sealing layer SE13, for example, is continuous in the range of the plurality of openings 82 arranged in the Y direction.

[0115] Figure 7 In the example of FIG. 9, the sealing layers SE11, SE12, SE13 do not overlap the slit SLa. As another example, at least one of the sealing layers SE11, SE12, SE13 can overlap the slit SLa.

[0116] Each of the openings 91 of the outer peripheral region OP overlaps the sealing layer SE1x. The sealing layer SE1x is separate from each of the sealing layers SE11, SE12, SE13 at the boundary between the dummy pixel region DMY and the outer peripheral region OP. However, at this boundary, the sealing layer SE1x can overlap at least one of the sealing layers SE11, SE12, SE13.

[0117] Figure 8 is a plan view of the vicinity of the boundary between the display region DA and the outer peripheral region OP. As with the sub-pixels SP1, SP2, SP3, the sealing layers SE11, SE12, SE13 are respectively provided on the dummy sub-pixels DP1, DP2, DP3. The sealing layer SE13, for example, is continuous in the range of the plurality of openings 82 arranged in the Y direction. Figure 7 ​FIG. 8 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP of FIG. 7. In this figure, the illustration of the substrate 10, the circuit layer 11, the organic insulating layer 12, the sealing layer SE2, and the resin layer RS2 is omitted. In the following description, the partition wall 6 disposed in the dummy pixel region DMY is referred to as the partition wall 6A, the partition wall 6 disposed in the outer peripheral region OP is referred to as the partition wall 6B, and the partition wall 6 disposed at the boundary between the dummy pixel region DMY and the outer peripheral region OP is referred to as the partition wall 6C.

[0118] The lower electrode LE1, the laminated film FL1, and the sealing layer SE11 are disposed in the dummy sub-pixel DP1. The lower electrode LE2, the laminated film FL2, and the sealing layer SE12 are disposed in the dummy sub-pixel DP2. Figure 8 In the example of FIG. 7, the pixel opening is not provided in the rib layer 5 in the dummy sub-pixels DP1, DP2. Therefore, the lower electrode LE1 and the laminated film FL1 face each other with the rib layer 5 interposed therebetween. In addition, the lower electrode LE2 and the laminated film FL2 face each other with the rib layer 5 interposed therebetween.

[0119] The sealing layer SE11 continuously covers the laminated film FL1 and the partition wall 6A around the laminated film FL1. The sealing layer SE12 continuously covers the laminated film FL2 and the partition walls 6A, 6C around the laminated film FL2. Figure 8 In the example of FIG. 7, the end portions of the sealing layers SE11, SE12 overlap each other in the Z direction above the partition wall 6A. For example, a gap is formed between the sealing layer SE11 and the upper portion 62 of the partition wall 6A. In addition, a gap is also formed between the sealing layer SE12 and the upper portion 62 of the partition wall 6A, 6C, and between the end portion of the sealing layer SE11 and the end portion of the sealing layer SE12. At least a part of these gaps can be filled with the resin layer RS1.

[0120] In the outer peripheral region OP, the laminated film FLx is disposed above the upper portion 62 of the partition wall 6B and the opening 91. The sealing layer SE1x continuously covers these laminated films FLx, the partition wall 6B, and a part of the partition wall 6C.

[0121] The laminated film FLxa is disposed between the sealing layer SE1x and the upper portion 62 of the partition wall 6C. The laminated film FLxa is, for example, obtained by modifying the laminated film FLx during the manufacturing process. Alternatively, the laminated film FLxa can be made to disappear during the manufacturing process. In this case, a gap is generated between the sealing layer SE1x and the partition wall 6C.

[0122] In the example of FIG. 7, the end portion Es of the sealing layer SE12 and the end portion Ex of the sealing layer SE1x are separated above the partition wall 6C. The resin layer RS1 covers the sealing layers SE11, SE12, SE1x. In addition, the resin layer RS1 covers the upper portion 62 of the partition wall 6C exposed from the sealing layer SE12, SE1x in the region between the end portions Es, Ex.

[0123] Next, an example of a manufacturing method of the display device DSP will be described. When the display device DSP is manufactured, a large-sized mother substrate in which a plurality of regions (panel portions) are formed is prepared, and the plurality of regions include portions each corresponding to the display device DSP.

[0124] Figure 9 is a schematic plan view of a mother substrate MB (mother substrate for display device) of the present embodiment. The mother substrate MB is, for example, rectangular as illustrated, but can be circular or another shape.

[0125] The mother substrate MB has a plurality of panel portions PP arranged in a matrix shape, and a blank region BA around the panel portions PP. Figure 9 In the example, the panel portions PP are arranged with the blank region BA sandwiched in the X direction and the Y direction. However, the arrangement pattern of the plurality of panel portions PP in the mother substrate MB is not limited to the example. As another example, several panel portions PP can be arranged without the blank region BA sandwiched therebetween.

[0126] Figure 10 is a schematic plan view of a panel portion PP. The outer shape of the panel portion PP corresponds to a cutting line CL1 for cutting out each panel portion PP from the mother substrate MB.

[0127] The panel portion PP has the display region DA and the surrounding region SA described above. The surrounding region SA in the panel portion PP corresponds to a region between the display region DA and the cutting line CL1.

[0128] The surrounding region SA further has a cutting line CL2 that becomes the outer shape of the substrate 10 of the display device DSP. When the display device DSP is manufactured, the panel portion PP is cut out from the mother substrate MB along the cutting line CL1. Also, the display device DSP is cut out from the panel portion PP along the cutting line CL2.

[0129] The panel portion PP further has a dam structure DS2 on the basis of the dam structure DS1 described above. The dam structure DS2 functions to block the resin layer RS2 before curing. For example, the dam structure DS2 has a plurality of dam portions formed of the organic insulating layers 12, 34 similarly to the dam portions DM1, DM2, DM3.

[0130] The dam structure DS1 is located between the cutting line CL2 and the display region DA, and surrounds the display region DA. The dam structure DS2 is located between the cutting lines CL1, CL2, and surrounds the cutting line CL2. Figure 10 In the example, the dam structures DS1, DS2 converge near the terminal portion T, and the converged portion passes between the terminal portion T and the display region DA.

[0131] Most of the cutting line CL2 is located between the dam structures DS1, DS2. However, Figure 10In the example, the cutting line CL2 is located outside the dam structures DS1 and DS2 near the terminal T. That is, the cutting line CL2 crosses the dam structure DS2 near the terminal T.

[0132] Figure 11 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figure 12A to Figure 12G This is a schematic cross-sectional view showing the manufacturing process of the display device DSP. Figure 12A to Figure 12G In this paper, the focus is on the display area DA, and elements located below the organic insulating layer 12 are omitted.

[0133] When the panel portion PP is formed, firstly, a circuit layer 11 is formed above the substrate 10 of the mother substrate MB, including the aforementioned inorganic insulating layers 31, 32, 33, organic insulating layer 34, and metal layers 41, 42, 43, etc. Figure 11 Process PR1). Furthermore, an organic insulating layer 12 is formed to cover the circuit layer 11. Figure 11 (Process PR2). At this time, the dam structures DS1 and DS2 are also formed.

[0134] After process PR2, such as Figure 12A As shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Figure 11 The process PR3). Moreover, such as Figure 12A As shown, a rib layer 5 is formed on the entire mother substrate MB to cover the lower electrodes LE1, LE2, and LE3. Figure 11 (Process PR4). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0135] After the formation of rib layer 5, as Figure 12B As shown, a partition wall 6 is formed above the rib layer 5. Figure 11 (Process PR5). For example, when the partition 6 is formed, layers of material, including a bottom layer 63, a shaft layer 64, a first top layer 65, and a second top layer 66, are formed on the entire mother substrate MB. Furthermore, a photoresist in the shape of the partition 6 is disposed on these layers. Each layer is etched using this photoresist as a mask, thereby forming the partition 6.

[0136] Next, as Figure 12C As shown, pixel openings AP1, AP2, and AP3 are formed in rib layer 5. Figure 11 (Process PR6). In addition, pixel openings AP1, AP2, and AP3 can also be formed before the partition 6.

[0137] After process PR6, the process for forming display element DE1 is performed.Figure 11 Process PR7). When forming the display element DE1, firstly, as... Figure 12D As shown, a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 that passes through the pixel opening AP1 and contacts the lower electrode LE1, an upper electrode UE1 that covers the organic layer OR1, and a capping layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. In addition, the sealing layer SE11 can be formed, for example, by CVD.

[0138] The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA of each panel portion PP, but also on the entire mother substrate MB, including the peripheral area SA and the blank area BA. The laminated film FL1 is separated by a cantilevered partition 6. The sealing layer SE11 continuously covers the separated portions of the laminated film FL1 and the partition 6.

[0139] Next, the laminated film FL1 and the sealing layer SE11 are patterned. This patterning, as shown... Figure 12D As shown, resist RT is disposed on top of the sealing layer SE11. Resist RT covers a portion of the sub-pixel SP1 and its surrounding partition 6.

[0140] Then, an etching process is performed using the resist RT as a mask. Thus, as... Figure 12E As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist RT are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are retained, while the remaining portions are removed. Thus, the display element DE1 is formed on the sub-pixel SP1. For example, in the peripheral region SA and the blank region BA, the laminated film FL1 and the sealing layer SE11 are removed by this etching process. This etching process can include wet etching and dry etching performed sequentially relative to the sealing layer SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist RT is removed (stripped off).

[0141] After process PR7, the process for forming display element DE2 is performed. Figure 11 (Process PR8). Display element DE2 can be formed in the same sequence as display element DE1. That is, when display element DE2 is formed, a laminated film FL2 and a sealing layer SE12 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 that passes through the pixel opening AP2 and contacts the lower electrode LE2, an upper electrode UE2 that covers the organic layer OR2, and a capping layer CP2 that covers the upper electrode UE2.

[0142] The organic layer OR2, the upper electrode UE2, and the cover layer CP2 are formed, for example, by evaporation. In addition, the sealing layer SE12 is formed, for example, by CVD. By patterning such a laminated film FL2 and the sealing layer SE2, as shown in FIG. 2B, a display element DE2 is formed on the sub-pixel SP2. For example, in the peripheral region SA and the blank region BA, the laminated film FL2 and the sealing layer SE12 are removed by etching at the time of the patterning. Figure 12F

[0143] After the process PR8, a process (process PR9 of FIG. 3) for forming a display element DE3 is performed. The display element DE3 can be formed by the same sequence as the display elements DE1 and DE2. That is, when the display element DE3 is formed, a laminated film FL3 and a sealing layer SE13 are formed on the entire mother substrate MB. As shown in FIG. 4B, the laminated film FL3 includes an organic layer OR3 which contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 which covers the organic layer OR3, and a cover layer CP3 which covers the upper electrode UE3. Figure 11 Figure 3

[0144] The organic layer OR3, the upper electrode UE3, and the cover layer CP3 can be formed, for example, by evaporation. In addition, the sealing layer SE13 can be formed, for example, by CVD. By patterning such a laminated film FL3 and the sealing layer SE13, as shown in FIG. 5B, a display element DE3 is formed on the sub-pixel SP3. Figure 12G Figure 12G In the embodiment, a gap is formed under the sealing layer SE13 on the partition wall 6 between the sub-pixels SP1 and SP3. In the gap, the laminated film FL3a shown in FIG. 6B can remain. Figure 3

[0145] For example, in most of the peripheral region SA and the blank region BA, the laminated film FL3 and the sealing layer SE13 are removed by etching at the time of the patterning. However, a portion of the laminated film FL3 and the sealing layer SE13 which covers the outer peripheral region OP is left. The portion left as such corresponds to the laminated film FLx and the sealing layer SE1x described above.

[0146] Further, in this embodiment, the case where the display elements DE1, DE2, and DE3 are formed in this order is assumed, but the display elements DE1, DE2, and DE3 can be formed in other orders.

[0147] After the process PR9, a resin layer RS1 is formed (process PR10 of FIG. 7). The resin layer RS1 can be formed, for example, by injection molding on the inner side of the dam structure DS1. After the process PR10, a sealing layer SE2 is formed, for example, by CVD (process PR11 of FIG. 8). Figure 11 Figure 11 ​​​​​​Process PR11).

[0148] After the process PR11, an etching process for removing the rib layer 5 and the sealing layer SE2 covering the terminal portion T is performed (process PR12). The etching is, for example, dry etching. Figure 11

[0149] After the process PR12, a touch panel electrode TP and a touch panel wiring TPL are formed on the sealing layer SE2 (process PR13). Also, a resin layer RS2 is formed (process PR14). The resin layer RS2 can be formed on the inner side of the dam structure DS2 by, for example, injection molding. The dam structure DS2 functions to block the resin layer RS2 before curing. Figure 11 Figure 11

[0150] After the process PR14, the mother substrate MB is cut along the cutting line CL1 (process PR15). Also, the panel portion PP is cut along the cutting line CL2 (process PR16). Thus, the display device DSP is completed. For the cutting in the processes PR15 and PR16, for example, laser cutting by irradiating infrared laser light along the cutting lines CL1 and CL2 can be used. However, the cutting in the processes PR15 and PR16 can be performed by other methods such as scribe cutting. Figure 11 Figure 11

[0151] According to the above embodiment, the yield of the display device DSP can be improved. That is, the laminated film FL1, FL2, FL3 formed by evaporation has a disadvantage of poor close contact with the substrate. Therefore, there is a possibility that the laminated film FL1, FL2, FL3 and the sealing layer SE11, SE12, SE13 covering them are peeled from the substrate when the display device DSP is manufactured.

[0152] The above peeling is likely to occur when the laminated film FL1, FL2, FL3 is continuously formed in a wide range. In the display area DA, the laminated film FL1, FL2, FL3 is finely broken by the partition wall 6. Therefore, the above peeling is suppressed.

[0153] In addition, in the present embodiment, the partition wall 6 having a plurality of openings 91 is also arranged in the outer peripheral area OP. Thus, in the outer peripheral area OP, the laminated film FL1, FL2, FL3 is also finely broken, and the above peeling is suppressed.

[0154] Also, according to the configuration of the display device DSP of the present embodiment, for example, the effects as described below can be obtained.

[0155] Figure 13 is a schematic plan view showing the configuration of a comparative example of the present embodiment. In this figure, the same components as those in the above figures are denoted by the same reference numerals, and the description thereof will be omitted.​​​​​Figure 7 Similarly, the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP is focused on.

[0156] In this comparative example, a slit SLa is also provided at the boundary between the dummy pixel region DMY and the outer peripheral region OP. That is, a portion where the slit SLa is located between the openings 82, 91 arranged in the X direction is generated.

[0157] Figure 14 is a cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP along the XIV-XIV line in Figure 7 In this comparative example, the portion corresponding to the partition wall 6C in Figure 7 is broken by the slit SLa into partition walls 6C1, 6C2. Also, the end portion Es of the sealing layer SE12 is located above the partition wall 6C1, and the end portion Ex of the sealing layer SE1x is located above the partition wall 6C2.

[0158] In the case where the resin layer RS1 is formed by injection molding, droplets of the resin material are ejected toward the display region DA, the dummy pixel region DMY, and the outer peripheral region OP. Normally, the droplets spread and diffuse over the sealing layers SE11, SE12, SE13, SE1x, covering the entire inside of the dam structure DS1.

[0159] However, the opening pattern of the partition wall 6 is different in the dummy pixel region DMY and the outer peripheral region OP. Due to this, the concavities and convexities exhibited on the upper surfaces of the sealing layers SE11, SE12, SE13 in the dummy pixel region DMY and the concavities and convexities exhibited on the upper surface of the sealing layer SE1x in the outer peripheral region OP become different shapes. If the shape of the base material of the resin layer RS1 is thus different, the diffusion manner of the droplets is affected at the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP.

[0160] Also, in the comparative example shown in Figure 14 In the comparative example shown in Figure 14 the steep layer differences formed by the partition wall 6C1 and the end portion Es of the sealing layer SE12 and the steep layer differences formed by the partition wall 6C2 and the end portion Ex of the sealing layer SE1x are generated on both sides of the slit SLa. If such layer differences are formed at the boundary between the dummy pixel region DMY and the outer peripheral region OP where the diffusion manner of the droplets changes, there is a possibility that the droplets will not spread over the slit SLa. In this case, as shown in

[0161] The coating omission portion where the resin layer RS1 is locally missing is generated in the vicinity of the slit SLa.

[0162] In the present embodiment, in contrast, no slits SLa are provided at the boundary between the dummy pixel region DMY and the outer peripheral region OP. Therefore, no steep layer difference as shown in the comparative example is generated. As a result, liquid droplets at the time of coating of the resin layer RS1 easily spread over the boundary, and occurrence of coating defects is suppressed.

[0163] Further, by suppressing occurrence of coating defects, coating defects of liquid resin of various resists coated after formation of the resin layer RS1 are also suppressed. As such liquid resin, for example, resists used for processing of the rib layer 5 and the sealing layer SE2 in the process PR12, and resists used for processing of the touch panel electrode TP and the touch panel wiring TPL in the process PR13 can be cited.

[0164] The display device DSP can also have a plurality of color filters corresponding to the colors of the sub-pixels SP1, SP2, SP3, and a black matrix located at the boundaries between the sub-pixels SP1, SP2, SP3. For example, these color filters and the black matrix can be disposed above the sealing layer SE2. By suppressing occurrence of coating defects of the resin layer RS1, coating defects of resin as a material of these color filters and the black matrix are also suppressed.

[0165] [2nd Embodiment]

[0166] Figure 15 is a schematic plan view showing the configuration of the 2nd embodiment. Figure 16 is a schematic sectional view of the dummy pixel region DMY and the outer peripheral region OP along the line XVI-XVI in Figure 15 These drawings focus on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP as in Figure 7 and Figure 8

[0167] In the present embodiment, as in the above-described comparative example, a slit SLa is also provided at the boundary between the dummy pixel region DMY and the outer peripheral region OP. That is, a portion through which the slit SLa passes between the openings 82, 91 arranged in the X direction and extending in the Y direction is generated. However, in the present embodiment, this slit SLa is covered by the sealing layer SE1x.

[0168] As shown in Figure 16 , in the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, the partition walls 6C1, 6C2 broken by the slit SLa are disposed. The laminated film FLx is disposed at the slit SLa. The sealing layer SE1x fills the slit SLa.

[0169] The end portion Ex of the sealing layer SE1x is located above the partition wall 6C1. Figure 16 ​In this example, the end Ex overlaps with the end Es of the sealing layer SE12 along the Z direction. A laminated film FLxa is disposed between the sealing layer SE1x and the upper portion 62 of the partition wall 6C1. As another example, a gap may also be formed between the sealing layer SE1x and the upper portion 62 of the partition wall 6C1. In addition, at least a portion of this gap may be filled by the resin layer RS1.

[0170] Figure 15 as well as Figure 16 The configuration shown can be applied to various positions where openings 82 and 91 are arranged along the X direction at the boundary between the dummy pixel region DMY and the peripheral region OP (e.g., Figure 6 (The part enclosed by frame A).

[0171] In this embodiment, even if a slit Sla is provided at the boundary between the dummy pixel region DMY and the peripheral region OP, by covering the slit Sla with the sealing layer SE1x, it is possible to suppress [the slit]. Figure 14 The comparative example shows a steep layer difference. Therefore, it is possible to suppress the occurrence of coating defects in the resin layer RS1.

[0172] [Third Implementation]

[0173] Figure 17 This is a schematic top view showing the configuration of the third embodiment. Figure 18 It is along Figure 17 A schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP of the XVIII-XVIII lines. In these figures, [the text abruptly ends here, likely due to an incomplete sentence or missing information]. Figure 7 as well as Figure 8 Similarly, pay attention to the area near the boundary between the dummy pixel region DMY and the peripheral region OP.

[0174] In this embodiment, similar to the first embodiment, no slit SLa is provided between the dummy pixel region DMY and the outer peripheral region OP. On the other hand, similar to the second embodiment, the end Ex of the sealing layer SE1x and the end Es of the sealing layer SE12 overlap along the Z direction. Even with this configuration, as in the embodiments described above, it is possible to suppress the occurrence of coating defects in the resin layer RS1.

[0175] [Fourth Implementation]

[0176] Figure 19 This is a schematic top view showing the configuration of the fourth embodiment. In this figure, [the following text is incomplete and likely refers to a different image or diagram]. Figure 7 Similarly, pay attention to the area near the boundary between the dummy pixel region DMY and the peripheral region OP.

[0177] In this embodiment, the slits Sla extend in the range of the dummy pixel region DMY and the outer peripheral region OP. Each slit Sla passes between the openings 91 adjacent in the X direction in the outer peripheral region OP. At least one of the plurality of slits Sla can also reach the end of the outer peripheral region OP.

[0178] Each slit Sla of the outer peripheral region OP is covered by the sealing layer SE1x. Also, as in the third embodiment, the slit Sla at the boundary between the dummy pixel region DMY and the outer peripheral region OP (the slit Sla between the openings 82, 91 in the X direction) is also covered by the sealing layer SE1x. Even with this configuration, as in each of the above embodiments, occurrence of a coating omission of the resin layer RS1 can be suppressed.

[0179] [5th Embodiment]

[0180] Figure 20 is a schematic plan view showing the configuration of the 5th embodiment. In this figure, as in the Figure 7 As in the 4th embodiment, attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP.

[0181] In this embodiment, as in the 4th embodiment, the slits Sla extend in the range of the dummy pixel region DMY and the outer peripheral region OP. Also, in this embodiment, the openings 91 and the slits Sla are connected by the slit SLx extending in the X direction.

[0182] Figure 20 In the example of Fig. 10, the slit SLx crosses the slit Sla and connects the two openings 91. However, Figure 20 The slit SLx near the center of Fig. 10 and the slit Sla are connected in a T shape.

[0183] In the outer peripheral region OP, the slit Sla, the slit SLx, and the openings 91 are covered by the sealing layer SE1x. Thereby, a recess corresponding to the shapes of the slit Sla, the slit SLx, and the openings 91 is formed on the upper surface of the sealing layer SE1x. When the droplets ejected at the time of formation of the resin layer RS1 pass within this recess, they easily spread over the entirety of the outer peripheral region OP.

[0184] [6th Embodiment]

[0185] Figure 21 is a schematic plan view showing the configuration of the 6th embodiment. In this figure, as in the Figure 7 As in the 5th embodiment, attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP.

[0186] In this embodiment, as in the fifth embodiment, the slits Sla extend in the range of the dummy pixel region DMY and the outer peripheral region OP, and the openings 91 and the slits Sla are connected by the slits SLx extending in the X direction.

[0187] Further, in this embodiment, the connecting portions CT connecting the portions of the partition wall 6 broken by the slits SLa are provided in the outer peripheral region OP as well. For example, the arrangement intervals of the connecting portions CT in the Y direction are the same in each of the display region DA, the dummy pixel region DMY, and the outer peripheral region OP. At least one opening 91 is connected to the slits Sla divided by the connecting portions CT. However, in the outer peripheral region OP, there can be slits SLa not connected to the openings 91.

[0188] The configurations disclosed in the first to sixth embodiments can be appropriately combined. For example, it is also possible that the configuration of any one of the embodiments is applied to a part of the outer peripheral region OP and the configuration of another embodiment is applied to another part.

[0189] In each of the embodiments, the term "partition wall" includes various configurations in a cantilevered shape. Even if a configuration in a cantilevered shape different from the partition walls disclosed in the embodiments is provided, the portion extending to the side corresponds to the "upper portion" and the portion retreating below the portion corresponds to the "lower portion".

[0190] All display devices that can be appropriately designed, changed, and implemented by those skilled in the art based on the display devices disclosed in the embodiments belong to the scope of the present application as long as they include the gist of the present application.

[0191] It should be noted that various modifications that can be conceived by those skilled in the art within the scope of the idea of the present application also belong to the scope of the present application. For example, a technical solution obtained by appropriately adding, deleting, or changing the configuration elements of the above-described embodiments or a technical solution obtained by adding, omitting, or changing conditions belong to the scope of the present application as long as they include the gist of the present application.

[0192] In addition, as for other effects brought about by the modes described in the above-described embodiments, effects that can be explicitly understood from the description of the present specification or that can be appropriately conceived by those skilled in the art are of course to be regarded as effects brought about by the present application.

Claims

1. A display device, wherein, have: A substrate having a display area for displaying images; Multiple pixels are configured in the display area, each of the multiple pixels including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light according to the applied voltage; A dummy pixel region surrounding the display area, which includes a plurality of dummy pixels that do not display an image; and The partition includes a conductive lower portion and an upper portion having an end protruding from the side of the lower portion, and is disposed in the display area, the dummy pixel area, and the peripheral area surrounding the dummy pixel area. The partition has multiple slits located in the display area and the dummy pixel area. The slit is not provided at the boundary between the dummy pixel region and the outer peripheral region.

2. The display device as claimed in claim 1, wherein, The partition wall has: A plurality of first openings are provided in each of the plurality of pixels in the display area; A plurality of second openings are provided in each of the plurality of dummy pixels in the dummy pixel region; and A plurality of third openings are provided in the outer peripheral region.

3. The display device as claimed in claim 2, wherein, The boundary between the dummy pixel region and the outer peripheral region is stepped. In a portion of the boundary, the second opening and the third opening are arranged along the first direction. The plurality of slits extend in a second direction intersecting the first direction, and are not located between the second opening and the third opening arranged along the first direction.

4. The display device as claimed in claim 1, wherein, Further features: The first sealing layer is formed of an inorganic insulating material and covers the plurality of pixels and the plurality of dummy pixels; The second sealing layer is formed of an inorganic insulating material and covers the outer peripheral area; and A resin layer that covers the first sealing layer and the second sealing layer.

5. The display device as claimed in claim 4, wherein, At the boundary between the dummy pixel region and the outer peripheral region, the first sealing layer and the second sealing layer are separated.

6. The display device as claimed in claim 5, wherein, The resin layer covers the partition wall exposed from the first sealing layer and the second sealing layer at the boundary between the dummy pixel area and the outer peripheral area.

7. The display device as claimed in claim 4, wherein, At the boundary between the dummy pixel region and the outer peripheral region, the first sealing layer and the second sealing layer overlap.

8. The display device as claimed in claim 1, wherein, The partition has a connecting portion in the display area and the dummy pixel area that connects the portion that is broken by the slit.

9. The display device according to any one of claims 1 to 8, wherein, The display area, the dummy pixel area, and the outer perimeter area are circular.

10. A display device, wherein, have: A substrate having a display area for displaying images; Multiple pixels are configured in the display area, each of the multiple pixels including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light according to the applied voltage; A dummy pixel region surrounding the display area, which includes a plurality of dummy pixels that do not display an image; The partition includes a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion, and is disposed in the display area, the dummy pixel area, and the peripheral area surrounding the dummy pixel area; The first sealing layer is formed of an inorganic insulating material and covers the plurality of pixels and the plurality of dummy pixels; and The second sealing layer, formed of an inorganic insulating material, covers the outer peripheral area. The partition has at least a plurality of slits located in the display area and the dummy pixel area. At least one of the plurality of slits is located at the boundary between the dummy pixel region and the outer peripheral region. The second sealing layer will cover the slit located at the boundary.

11. The display device as claimed in claim 10, wherein, At the boundary between the dummy pixel region and the outer peripheral region, the first sealing layer and the second sealing layer overlap.

12. The display device as claimed in claim 10, wherein, At least one of the plurality of slits extends into the peripheral region.

13. The display device as claimed in claim 12, wherein, The second sealing layer covers the slit located in the outer peripheral region.

14. The display device as claimed in claim 12, wherein, The partition wall has: A plurality of first openings are provided in each of the plurality of pixels in the display area; A plurality of second openings are provided in each of the plurality of dummy pixels in the dummy pixel region; and A plurality of third openings are provided in the outer peripheral region.

15. The display device as claimed in claim 14, wherein, The boundary between the dummy pixel region and the outer peripheral region is stepped. In a portion of the boundary, the second opening and the third opening are arranged along the first direction. At least one of the plurality of slits passes between the second opening and the third opening arranged along the first direction, and extends in a second direction intersecting the first direction.

16. The display device as claimed in claim 15, wherein, At least one of the plurality of slits extends through the third opening adjacent to each other in the outer peripheral region along the first direction.

17. The display device as claimed in claim 16, wherein, At least one of the plurality of third openings is connected to the slit located in the peripheral region.

18. The display device as claimed in claim 16, wherein, The partition has a connecting portion that connects to the portion that is disconnected by the slit located in the outer peripheral region.

19. The display device as claimed in claim 10, wherein, It further includes a resin layer that covers the first sealing layer and the second sealing layer.

20. The display device according to any one of claims 10 to 19, wherein, The display area, the dummy pixel area, and the outer perimeter area are circular.

Images