Display device

Abstract

The present application provides a display device, according to one embodiment, comprising: a display element disposed in a display area in which an image is displayed; an inorganic insulating layer disposed within the display region and a peripheral region located outside the display region; a partition wall disposed on the inorganic insulating layer, having conductivity, and surrounding the display element in the display region; and a power supply line covered by the inorganic insulating layer, an outer edge of the display region including a rounded portion, the power supply line being disposed along the rounded portion in the peripheral region and electrically connected to the partition wall via a plurality of contact holes penetrating the inorganic insulating layer, the plurality of contact holes being arranged in a stepped shape along the rounded portion.

Description

[0001] Cross reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-127826 filed on August 2, 2024, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a display device. BACKGROUND

[0004] In recent years, a display device using an organic light emitting diode (OLED) as a display element has been put into practical use. In such a display device, a technique for improving yield is required. SUMMARY

[0005] An object of embodiments is to provide a display device capable of improving yield.

[0006] According to an embodiment, a display device includes:

[0007] a display element disposed in a display region in which an image is displayed; an inorganic insulating layer disposed in a range of the display region and a peripheral region located outside the display region; a barrier wall disposed on the inorganic insulating layer and having conductivity, the barrier wall surrounding the display element in the display region; and a power supply line covered by the inorganic insulating layer, an outer edge of the display region including a rounded corner portion, the power supply line being disposed along the rounded corner portion in the peripheral region, the power supply line being electrically connected to the barrier wall via a plurality of contact holes that penetrate the inorganic insulating layer, the plurality of contact holes being arranged in a stepped manner along the rounded corner portion.

[0008] According to an embodiment, a display device includes:

[0009] a display element disposed in a display region in which an image is displayed; an inorganic insulating layer disposed in a range of the display region and a peripheral region located outside the display region; a barrier wall disposed on the inorganic insulating layer and having conductivity, the barrier wall surrounding the display element in the display region; and a power supply line covered by the inorganic insulating layer, the power supply line being electrically connected to the barrier wall via a contact hole that penetrates the inorganic insulating layer in the peripheral region, the barrier wall being formed in a lattice shape having a plurality of first extension portions and a plurality of second extension portions in the peripheral region, the plurality of first extension portions each extending in a first direction, the plurality of first extension portions being arranged at a first pitch in a second direction intersecting the first direction, the plurality of second extension portions each extending in the second direction, the plurality of second extension portions being arranged at a second pitch in the first direction, the contact hole being located at an intersection of one of the plurality of first extension portions and one of the plurality of second extension portions.

[0010] According to an embodiment, a display device includes:

[0011] A display element configured in a display region in which an image is displayed; an inorganic insulating layer configured in a range of the display region and a peripheral region located outside the display region; a barrier wall configured on the inorganic insulating layer and having conductivity, the barrier wall surrounding the display element in the display region; and a power supply line covered by the inorganic insulating layer, the power supply line being electrically connected to the barrier wall via a contact hole that penetrates the inorganic insulating layer in the peripheral region, the barrier wall being formed in a lattice shape having a plurality of openings in the peripheral region, the plurality of openings having a first opening, a second opening, and a third opening arranged at equal intervals in one direction in order, the contact hole being located between the second opening and the third opening, and a width between the first opening and the second opening and a width between the second opening and the third opening being equal in the barrier wall.

[0012] According to an embodiment, a display device capable of improving yield can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 FIG. 1 is a diagram showing one configuration example of a display device DSP.

[0014] Figure 2 FIG. 2 is a diagram showing one example of a layout of sub-pixels SP1, SP2, and SP3 configuring one pixel PX.

[0015] Figure 3 FIG. 3 is a diagram showing a schematic cross-sectional view of the display device DSP along A-B line in FIG. 1. Figure 2

[0016] Figure 4 FIG. 4 is a diagram showing a schematic plan view of a part of the display device DSP.

[0017] Figure 5 FIG. 5 is a diagram showing one example of a layout of sealing layers SE11, SE12, and SE13 and a slit ST.

[0018] Figure 6 FIG. 6 is a diagram showing a schematic cross-sectional view of the display device DSP along C-D line in FIG. 1. Figure 5

[0019] Figure 7 FIG. 7 is a plan view showing one shape example of the barrier wall 6 in the vicinity of the rounded corner portion RD.

[0020] Figure 8 FIG. 8 is a plan view showing one shape example of the barrier wall 6 in the vicinity of the contact hole CH1 shown in FIG. 1. Figure 7 ​​

[0021] Figure 9 is a cross-sectional view of the display device DSP along the line E-F in Figure 8

[0022] Figure 10 is a cross-sectional view of the display device DSP along the line G-H in Figure 8

[0023] Figure 11A is a cross-sectional view of the display device DSP along the line G-H in

[0024] Figure 11B Figure 11A

[0025] Figure 11C Figure 11B

[0026] Figure 11D Figure 11C

[0027] Figure 11E Figure 11D

[0028] Figure 11F Figure 11E

[0029] Figure 12

[0030] Figure 13

[0031] Figure 14 Figure 13

[0032] Figure 15 Figure 13 DETAILED DESCRIPTION

[0033] Embodiments will be described with reference to the drawings.

[0034] ​​​​​​​​​​​​​​​​​​The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the application are naturally included in the scope of the application. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each portion of the drawings are sometimes schematically shown compared to the actual shape, but are merely examples and not intended to limit the explanation of the application. In addition, in the present specification and the drawings, sometimes the same reference numerals are attached to the constituent elements that perform the same or similar functions to the constituent elements described with respect to the already-described drawings and the repeated detailed description is appropriately omitted.

[0035] Note that, as necessary, the X axis, Y axis, and Z axis orthogonal to one another are shown in the drawings for ease of understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Observing various elements in parallel with the third direction Z is referred to as plan view observation. Note that, the terms "upper" or "above", "between", "opposite", and the like indicating the positional relationship of two or more constituent elements to one another include not only the case where the two or more constituent elements are in direct contact with one another, but also the case where they are separated from one another with a gap or other constituent elements interposed therebetween. In addition, the positive direction of the Z axis is referred to as upper or above.

[0036] The display device of the embodiment is an organic electroluminescent display device provided with an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0037] Figure 1 is a view showing one configuration example of a display device DSP.

[0038] The display device DSP is provided with a display panel 100. The display panel 100 has a display region DA for displaying an image and a peripheral region SA around the display region DA on an insulating substrate 10. The substrate 10 can be a glass substrate or a resin substrate having flexibility.

[0039] The outer edge of at least a portion of the display region DA includes a rounded corner portion RD. In the illustrated example, the shape of the display region DA is circular in plan view observation. However, the shape of the display region DA in plan view observation is not limited to the illustrated example. For example, the outer edge of the display region DA can be a combination of a rounded corner portion RD and a straight line portion.

[0040] The display region DA has a plurality of pixels PX arranged in a matrix shape in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP that display mutually different colors. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are mutually different colors. Note that the pixel PX can include a sub-pixel SP of another color such as white, in addition to or instead of any of the sub-pixels SP1, SP2, SP3.

[0041] Note that the rounded portion RD of the display region DA is a shape that is visually confirmed macroscopically, and is a shape formed by the plurality of pixels PX arranged in a stepped manner microscopically.

[0042] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driver transistor 3, and a capacitor 4. The pixel switch 2 and the driver transistor 3 are, for example, switching elements each composed of a thin film transistor.

[0043] The gate electrode of the pixel switch 2 is connected to a scan line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to a signal line SL, and the other is connected to the gate electrode of the driver transistor 3 and the capacitor 4. In the driver transistor 3, one of the source electrode and the drain electrode is connected to a power supply line PL and the capacitor 4, and the other is connected to the display element DE. In the example illustrated, the scan line GL and the power supply line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0044] Note that the configuration of the pixel circuit 1 is not limited to the example illustrated. For example, the pixel circuit 1 can have more thin film transistors and capacitors.

[0045] The display element DE is, for example, an organic light emitting diode (OLED) which is a light emitting element, and is sometimes referred to as an organic EL element.

[0046] The display device DSP further has a terminal portion T arranged in the surrounding region SA. The terminal portion T has a plurality of terminals, for example, electrically connected to an IC chip for driving the display device DSP, a flexible circuit substrate.

[0047] Figure 2 FIG. 1 is a diagram illustrating an example of a layout of the sub-pixels SP1, SP2, SP3 that constitute one pixel PX.

[0048] In the example illustrated, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0049] In the case where the subpixels SP1, SP2, SP3 are of this layout, columns in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y and columns in which the subpixels SP1 are arranged in the second direction Y are formed in the display region DA. These columns are alternately arranged in the first direction X. Note that the layout of the subpixels SP1, SP2, SP3 is not limited to the above-described example. Figure 2

[0050] The inorganic insulating layer 5 and the barrier 6 are arranged in the display region DA. The inorganic insulating layer 5 has openings AP1, AP2, AP3 in the subpixels SP1, SP2, SP3, respectively. The inorganic insulating layer 5 having the openings AP1, AP2, AP3 is sometimes referred to as a rib portion.

[0051] The barrier 6 overlaps with the inorganic insulating layer 5 when viewed in plan view. The barrier 6 is formed in a lattice shape so as to surround the openings AP1, AP2, AP3. The barrier 6 can also have openings OP1, OP2, OP3 in the subpixels SP1, SP2, SP3, respectively, like the inorganic insulating layer 5. The opening OP1 overlaps with the opening AP1, the opening OP2 overlaps with the opening AP2, and the opening OP3 overlaps with the opening AP3. The barrier 6 has conductivity and is electrically connected to the terminal for the common voltage in the terminal portion T illustrated in FIG. 8B. Figure 1

[0052] The subpixels SP1, SP2, SP3 each include a display element DE1, DE2, DE3 as the display element DE.

[0053] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 which overlap with the opening AP1, respectively. The peripheral portion of the lower electrode LE1 is covered with the inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 which form the display element DE1 are surrounded with the barrier 6 when viewed in plan view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 each overlap with the inorganic insulating layer 5 when viewed in plan view. The organic layer OR1 includes a light-emitting layer which emits light in a blue wavelength range, for example.

[0054] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 which overlap with the opening AP2, respectively. The peripheral portion of the lower electrode LE2 is covered with the inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 which form the display element DE2 are surrounded with the barrier 6 when viewed in plan view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 each overlap with the inorganic insulating layer 5 when viewed in plan view. The organic layer OR2 includes a light-emitting layer which emits light in a green wavelength range, for example.

[0055] ​​The display element DE3 of the sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 which overlap the opening AP3, respectively. The peripheral portion of the lower electrode LE3 is covered with the inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 which constitute the display element DE3 are surrounded by the partition wall 6 when viewed from the top. The peripheral portions of the organic layer OR3 and the upper electrode UE3 each overlap the inorganic insulating layer 5 when viewed from the top. The organic layer OR3 includes, for example, a light-emitting layer which emits light in the red wavelength range.

[0056] In the illustrated example, the outer shape of the lower electrodes LE1, LE2, LE3 is indicated by a broken line, and the outer shape of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 is indicated by a single-dot chain line. Note that the outer shape of each of the illustrated lower electrodes, organic layers, and upper electrodes is not limited to the case of reflecting the exact shape.

[0057] The lower electrodes LE1, LE2, LE3 correspond to, for example, anodes of the display elements. The upper electrodes UE1, UE2, UE3 correspond to cathodes or common electrodes of the display elements, and are in contact with the partition wall 6.

[0058] The lower electrode LE1 is electrically connected to the pixel circuit 1 (see Figure 1 ) of the sub-pixel SP1. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0059] In the illustrated example, the area of the opening AP1, the area of the opening AP2, and the area of the opening AP3 are different from each other. The area of the opening AP1 is larger than the area of the opening AP2, and the area of the opening AP2 is larger than the area of the opening AP3.

[0060] The partition wall 6 has a plurality of slits ST. In the illustrated example, the slits ST each extend in the second direction Y. For example, the sub-pixels SP1, SP2, SP3 which constitute one pixel PX are arranged in the first direction X between two slits ST which are adjacent to each other.

[0061] Figure 3 is a schematic cross-sectional view of the display device DSP along the A-B line in Figure 2 .

[0062] The circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1 , various wirings such as scan lines GL, signal lines SL, and power supply lines PL, and various insulating layers.

[0063] The insulating layer 12 is arranged on the circuit layer 11. The insulating layer 12 is, for example, an organic insulating layer which flattens the concavo-convexities generated by the circuit layer 11.

[0064] The lower electrode LE1 of the sub-pixel SP1, the LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are disposed on the insulating layer 12 and separated from each other.

[0065] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening API of the inorganic insulating layer 5 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through the contact holes provided in the insulating layer 12. Note that the contact holes of the insulating layer 12 are omitted in Figure 3

[0066] The barrier wall 6 has a lower portion 61 disposed on the inorganic insulating layer 5 and having conductivity, and an upper portion 62 disposed on the lower portion 61.

[0067] In the illustrated example, the lower portion 61 has a base layer 63 disposed on the inorganic insulating layer 5, and a shaft layer 64 disposed between the base layer 63 and the upper portion 62. The base layer 63 is thinner than the shaft layer 64. The base layer 63 has a larger width than the shaft layer 64. The both end portions of the base layer 63 protrude from the side surface of the shaft layer 64.

[0068] The upper portion 62 is disposed on the shaft layer 64. The upper portion 62 has a larger width than the shaft layer 64. The both end portions of the upper portion 62 protrude from the side surface of the shaft layer 64. In this specification, the side surface of the shaft layer 64 refers to a surface of the shaft layer 64 extending between the base layer 63 and the upper portion 62. In the illustrated example, the upper portion 62 has a larger width than the base layer 63. Note that the base layer 63 can have a larger width than the upper portion 62.

[0069] In the display element DE1, the organic layer OR1 contacts the lower electrode LE1 through the opening API, covers the lower electrode LE1 exposed from the opening API, and has its peripheral portion on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0070] In the display element DE2, the organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral portion on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0071] In the display element DE3, the organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral portion on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61.​

[0072] Note that the contact of each of the upper electrodes UE1, UE2, and UE3 with the lower portion 61 includes a case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and a case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and in direct contact with the side surface of the shaft layer 64. In this specification, the upper surface of the bottom layer 63 refers to a surface of the bottom layer 63 including a surface in direct contact with the shaft layer 64 and a surface opposite to the upper portion 62 and protruding from the shaft layer 64.

[0073] In the illustrated example, the sub-pixel SP1 has the cap layer CP1 and the sealing layer SE11, the sub-pixel SP2 has the cap layer CP2 and the sealing layer SE12, and the sub-pixel SP3 has the cap layer CP3 and the sealing layer SE13. The cap layers CP1, CP2, and CP3 each function as an optical adjustment layer for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. Note that the cap layers CP1, CP2, and CP3 can be omitted.

[0074] The cap layer CP1 is provided over the upper electrode UE1. The cap layer CP2 is provided over the upper electrode UE2. The cap layer CP3 is provided over the upper electrode UE3.

[0075] The sealing layer SE11 is provided over the cap layer CP1 and in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP1. The sealing layer SE11 is in contact with the shaft layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE1.

[0076] The sealing layer SE12 is provided over the cap layer CP2 and in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP2. The sealing layer SE12 is in contact with the shaft layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE2.

[0077] The sealing layer SE13 is provided over the cap layer CP3 and in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP3. The sealing layer SE13 is in contact with the shaft layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE3.

[0078] In the following description, a multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is referred to as a layered film FL1, a multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is referred to as a layered film FL2, and a multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is referred to as a layered film FL3.

[0079] The end portions of the sealing layers SE11, SE12, and SE13 are positioned on the partition wall 6. In the illustrated example, the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the partition wall 6.

[0080] The laminated films FL1, FL2, and FL3 are not formed on the partition wall 6. The cavities are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6, respectively.

[0081] The transparent resin layer RS1 covers the partition wall 6 and the sealing layers SE11, SE12, and SE13. In addition, the resin layer RS1 is filled into the cavities formed on the partition wall 6.

[0082] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 covers the sealing layer SE2.

[0083] The inorganic insulating layers 5, the sealing layers SE11, SE12, and SE13, and the sealing layer SE2 are formed of, for example, inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like.

[0084] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of, for example, an aluminum-based material such as aluminum or an aluminum compound.

[0085] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but can be formed of an insulating material. The upper portion 62 is formed of a material different from the lower portion 61. For example, the upper portion 62 is formed of a titanium-based material such as titanium or a titanium compound, an oxide conductive material such as indium tin oxide (ITO), or the like.

[0086] The lower electrodes LE1, LE2, and LE3 are, for example, multilayer bodies including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer bodies including a reflective layer between a pair of transparent layers.

[0087] The organic layer OR1 includes an emission layer EM1. The organic layer OR2 includes an emission layer EM2. The organic layer OR3 includes an emission layer EM3. The emission layer EM1, the emission layer EM2, and the emission layer EM3 are formed of mutually different materials. In one example, the emission layer EM1 is formed of a material that emits light in a blue wavelength range, the emission layer EM2 is formed of a material that emits light in a green wavelength range, and the emission layer EM3 is formed of a material that emits light in a red wavelength range.

[0088] In addition, the organic layers OR1, OR2, OR3 each include a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like.

[0089] The upper electrodes UE1, UE2, UE3 are formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg).

[0090] The cover layers CP1, CP2, CP3 are multilayer bodies of a plurality of thin films. The plurality of thin films are each transparent and have mutually different refractive indexes.

[0091] The illustrated circuit layer 11, the insulating layer 12, and the inorganic insulating layer 5 are disposed within the range of the display region DA and the surrounding region SA.

[0092] Figure 4 is a schematic plan view showing part of the elements of the display device DSP.

[0093] The partition walls 6 and the upper electrodes UE1, UE2, UE3 constitute a common electrode CE that applies a common voltage to the display elements DE1, DE2, DE3. The common electrode CE is, for example, circular and overlaps the circular display region DA as a whole.

[0094] The common electrode CE has a plurality of slits ST. The slits ST each cross the display region DA, and both ends thereof reach the outer edge of the common electrode CE. Thus, the common electrode CE is constituted of a plurality of segments SG separated by the respective slits ST.

[0095] In the illustrated example, the slits ST and the segments SG extend in the second direction Y. As another example, the slits ST and the segments SG can extend in the first direction X. The number of the slits ST provided in the common electrode CE is not particularly limited.

[0096] The plurality of segments SG each have a first end portion Ea and a second end portion Eb in the extension direction of the slits ST (the second direction Y in the illustrated example). The first end portion Ea is located between the display region DA and the terminal portion T in the second direction Y. The second end portion Eb is located on the opposite side of the first end portion Ea.

[0097] The power supply line PW is arranged along the rounded portion RD in the peripheral area SA between the display area DA and the terminal portion T in the second direction Y. In addition, the power supply line PW is electrically connected to the terminal portion T.

[0098] Each of the segments SG is electrically connected to the power supply line PW on the first end portion Ea side. Each of the segments SG is not connected to a member having such electrical conductivity as the power supply line PW on the second end portion Eb side. A common voltage is applied to each of the segments SG from the terminal portion T via the power supply line PW.

[0099] Figure 5 is a view showing an example of the layout of the sealing layers SE11, SE12, SE13 and the slit ST.

[0100] The sealing layers SE11, SE12, SE13 are formed in island shapes in the sub-pixels SP1, SP2, SP3, respectively, as indicated by dotted lines. Note that the sealing layer SE11 can also be formed continuously across a plurality of the sub-pixels SP1 arranged in the second direction Y.

[0101] The end portions of each of the sealing layers SE11, SE12, SE13 overlap the barrier 6 as a whole. In the example shown, none of the sealing layers SE11, SE12, SE13 overlaps the slit ST. However, at least a part of the sealing layers SE11, SE12, SE13 can also overlap the slit ST.

[0102] The slit ST extends in the second direction Y between the sealing layer SE11 and the sealing layer SE12 and between the sealing layer SE11 and the sealing layer SE13. The barrier 6 of the region shown is divided by the slit ST into two barriers 6A, 6B which are adjacent in the first direction X.

[0103] Figure 6 is a schematic cross-sectional view of the display device DSP along the C-D line in Figure 5 In the example shown in Figure 6 In the example shown in

[0104] The slit ST corresponds to a portion in which the bottom layer 63 and the shaft layer 64 of the lower portion 61 and the upper portion 62 are penetrated in the barrier 6.

[0105] In the barriers 6A, 6B, both end portions of the upper portion 62 protrude beyond the lower portion 61 (or the side surface of the shaft layer 64). In addition, both end portions of the bottom layer 63 protrude beyond the side surface of the shaft layer 64.

[0106] The end portion of the sealing layer SE11 is located above the barrier 6A. The sealing layer SE11 continuously covers the display element DE1 of the sub-pixel SP1 and a part of the barrier 6A.

[0107] In addition, the end portion of the sealing layer SE12 is positioned above the barrier rib 6B. The sealing layer SE12 continuously covers the display element DE2 of the sub-pixel SP2 and a portion of the barrier rib 6B.

[0108] The inorganic insulating layer 5 covers the insulating layer 12 in the slit ST and does not have a through-hole overlapping the slit ST. The resin layer RS1 is filled in the slit ST, covers the bottom layer 63, the shaft layer 64, and the upper portion 62, and is in contact with the inorganic insulating layer 5.

[0109] The lower electrodes LE1, LE2, and LE3 do not overlap the slit ST. Thus, a transmissive region through which the light Li can transmit can be formed between the adjacent lower electrodes.

[0110] Figure 7 is a plan view showing one shape example of the barrier rib 6 in the vicinity of the rounded portion RD.

[0111] In the display region DA, as described above, the barrier rib 6 is formed in a lattice shape having the openings OP1, OP2, and OP3. In the peripheral region SA, the barrier rib 6 is formed in a lattice shape different in shape from the display region DA.

[0112] That is, the barrier rib 6 has a plurality of openings OP arranged in a matrix shape in the first direction X and the second direction Y in the peripheral region SA. The openings OP each have the same shape, and in the illustrated example, are formed in an oblong shape or a rectangular shape extending in the second direction Y. The shapes of these openings OP are different from those of the openings OP1, OP2, and OP3 in the display region DA.

[0113] The plurality of openings OP are arranged at a fixed pitch Px in the first direction X. In addition, the plurality of openings OP are arranged at a fixed pitch Py in the second direction Y. The pitch Py is different from the pitch Px. In the illustrated example, the pitch Py is larger than the pitch Px (Py > Px).

[0114] In the peripheral region SA, the barrier rib 6 is electrically connected to the power supply line PW shown in Fig. 1 via a plurality of contact holes CH. The plurality of contact holes CH are arranged in a stepped shape along the rounded portion RD. The contact holes CH are each positioned between two openings OP adjacent to each other in the second direction Y. Figure 4

[0115] ​Here, attention is directed to the first opening OP21, the second opening OP22, and the third opening OP23, which are arranged in the second direction Y at equal intervals Py in that order. One of the plurality of contact holes CH is located between the second opening OP22 and the third opening OP23, and there is no contact hole between the first opening OP21 and the second opening OP22. In the barrier rib 6, the width Wy21 in the second direction Y between the first opening OP21 and the second opening OP22 and the width Wy22 in the second direction Y between the second opening OP22 and the third opening OP23 are equal.

[0116] The contact hole CH does not overlap the second opening OP22 and the third opening OP23 when viewed in plan view.

[0117] The first opening OP21, the second opening OP22, and the third opening OP23 have the same shape when viewed in plan view.

[0118] Next, attention is directed to one of the plurality of contact holes CH1, which will be described in detail below.

[0119] Figure 8 is a plan view showing one shape example of the barrier rib 6 in the vicinity of the contact hole CH1. Figure 7

[0120] The barrier rib 6 is formed in a lattice shape in the peripheral region SA and has the openings OP11, OP12, OP13, OP14, OP15, and OP16 as a plurality of openings OP.

[0121] The openings OP11 and OP12 are adjacent to each other in the first direction X.

[0122] The openings OP12 and OP15 are adjacent to each other in the first direction X.

[0123] The openings OP13 and OP14 are adjacent to each other in the first direction X.

[0124] The openings OP14 and OP16 are adjacent to each other in the first direction X.

[0125] The openings OP11 and OP13 are adjacent to each other in the second direction Y.

[0126] The openings OP12 and OP14 are adjacent to each other in the second direction Y.

[0127] The openings OP15 and OP16 are adjacent to each other in the second direction Y.

[0128] ​The openings OP11, OP12, OP13, OP14, OP15, OP16 have the same shape. In each of the openings OP11, OP12, OP13, OP14, OP15, OP16, the width Wyo along the second direction Y is larger than the width Wxo along the first direction X (Wyo > Wxo).

[0129] In the first direction X, the partition wall 6 has a width Wxl l between the opening OP11 and the opening OP12, and further has a width Wx12 equivalent to the width Wxl l between the opening OP14 and the opening OP16. Further, in the second direction Y, the partition wall 6 has a width Wyl l between the opening OP11 and the opening OP13, and further has a width Wy12 equivalent to the width Wyl l between the opening OP12 and the opening OP14. The widths Wxl l, Wx12 are different from the widths Wyl l, Wy12, respectively. In the illustrated example, the widths Wxl l, Wx12 are smaller than the widths Wyl l, Wy12 (Wxl l, Wx12 < Wyl l, Wy12), respectively. Each of the widths Wxl l, Wx12, Wyl l, Wy12 is 40 μm or less.

[0130] The contact hole CH1 has a width Wxl in the first direction X and a width Wy1 in the second direction Y. The width Wxl can be equivalent to or different from the width Wy1. The width Wxl of the contact hole CH1 is larger than the widths Wxl l, Wx12 of the partition wall 6 (Wxl > Wxl l, Wx12). The width Wy1 of the contact hole CH1 is smaller than the widths Wyl l, Wy12 of the partition wall 6 (Wy1 < Wyl l, Wy12).

[0131] The contact hole CH1 is surrounded by the four openings OP12, OP14, OP15, OP16. Further, the contact hole CH1 is located between the opening OP12 and the opening OP14 adjacent in the second direction Y, and further is located between the opening OP15 and the opening OP16.

[0132] On the other hand, there is no contact hole between the opening OP11 and the opening OP13.

[0133] From another viewpoint, the partition wall 6 is formed in the peripheral region SA in a lattice shape having a plurality of extension portions 6X and a plurality of extension portions 6Y. The plurality of extension portions 6X extend along the first direction X and are arranged at a fixed pitch Py in the second direction Y, respectively. The plurality of extension portions 6Y extend along the second direction Y and are arranged at a fixed pitch Px in the first direction X, respectively. The contact hole CH1 is located at an intersection portion where one of the extension portions 6X and one of the extension portions 6Y intersect.

[0134] The pitch Py is different from the pitch Px. In the illustrated example, the pitch Py is larger than the pitch Px (Py > Px).

[0135] The width of the extension 6X in the second direction Y is equivalent to the width Wy11 or the width Wy12 described above, and is larger than the width Wy1 of the contact hole CH1 in the second direction Y (Wy1 < Wy11, Wy12).

[0136] The width of the extension 6Y in the first direction X is equivalent to the width Wx11 or the width Wx12 described above, and is smaller than the width Wx1 of the contact hole CH1 in the first direction X (Wx1 > Wx11, Wx12).

[0137] The width Wy11 of the extension 6X in the second direction Y is different from the width Wx11 of the extension 6Y in the first direction X. In the example illustrated, the width Wy11 is larger than the width Wx11 (Wy11 > Wx11).

[0138] Figure 9 is a cross-sectional view of the display device DSP along the line E-F in Figure 8 is a cross-sectional view of the display device DSP along the line E-F in Figure 9 In the cross-sectional view in FIG. 6, elements below the insulating layer 12 and elements above the sealing layer SE13 are omitted.

[0139] The power supply line PW is disposed above the insulating layer 12 and is covered by the inorganic insulating layer 5. This power supply line PW is formed of the same material as the lower electrode LE1 or the like, and can be formed in the same process as the lower electrode LE1.

[0140] The contact hole CH1 penetrates the inorganic insulating layer 5.

[0141] The bottom layer 63 in the partition wall 6 is disposed above the inorganic insulating layer 5 and contacts the power supply line PW in the contact hole CH1. The shaft layer 64 is disposed above the bottom layer 63, and the upper portion 62 is disposed above the shaft layer 64.

[0142] In the peripheral region SA, one of the laminated films FL1, FL2, FL3 disposed in the display region DA is disposed above the partition wall 6. In the example illustrated, the laminated film FL3 including the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is disposed above the partition wall 6. The laminated film FL3 is covered by the sealing layer SE13.

[0143] Here, the cross-sectional shape at the contact hole CH1 of the plurality of contact holes CH in which the power supply line PW is electrically connected to the partition wall 6 is described, but the other contact holes CH of the peripheral region SA also have the same cross-sectional shape as the contact hole CH1.

[0144] Figure 10 is a cross-sectional view of the display device DSP along the line E-F in Figure 8 is a cross-sectional view of the display device DSP along the line E-F inFigure 10 In the text, elements below the insulating layer 12 and elements above the sealing layer SE13 are omitted.

[0145] The inorganic insulating layer 5 does not have through holes that overlap with openings OP11, OP12, OP13, and OP14. Therefore, in the area except for the contact hole CH, the power supply line PW is covered by the inorganic insulating layer 5.

[0146] The partition 6 also has the same cross-sectional shape as the display area DA in the peripheral area SA. That is, the lower part 61 of the partition 6 has a bottom layer 63 and a shaft layer 64 located above the inorganic insulating layer 5, and the upper part 62 is located above the lower part 61, with both ends of the upper part 62 protruding from the side of the lower part 61 or the side of the shaft layer 64.

[0147] The laminated film FL3 comprises a first portion located above the upper part 62 of the partition 6 and a second portion located above the inorganic insulating layer 5 in the openings OP11, OP12, OP13, and OP14. The first and second portions are separated from each other. As described above, this laminated film FL3 comprises an organic layer OR3, an upper electrode UE3, and a capping layer CP3.

[0148] The sealing layer SE13 continuously covers the first and second portions of the laminated film FL3, and also covers the septum 6 exposed from the laminated film FL3.

[0149] It should be noted that the laminated film and sealing layer overlapping the adjacent wall 6 in the surrounding area SA are not limited to the example shown in the figure. They can also be laminated film FL1 and sealing layer SE11 or laminated film FL2 and sealing layer SE12.

[0150] Next, the manufacturing method of the display device DSP will be explained. It should be noted that... Figures 11A to 11F In the text, elements below the insulating layer 12 are omitted.

[0151] First, such as Figure 11A As shown, a processing substrate SUB is prepared. The process for preparing the processing substrate SUB includes: forming a lower electrode LE1 of sub-pixel SP1, a lower electrode LE2 of sub-pixel SP2, and a lower electrode LE3 of sub-pixel SP3 on an insulating layer 12; forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3 respectively; and forming a partition 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. It should be noted that the partition 6 may be formed after the inorganic insulating layer 5 with openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed on the inorganic insulating layer 5 after the partition 6 is formed.

[0152] Next, the display element DE1 is formed.

[0153] First, such as Figure 11B As shown, vapor deposition is performed using partition 6 as a mask to form a multilayer film FL1 on the processed substrate SUB. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 contained in the multilayer film FL1 are continuously formed in a vacuum environment in a vapor deposition apparatus. The multilayer film FL1 is separated by the suspended partition 6.

[0154] Then, a sealing layer SE11 is formed that continuously covers the laminated film FL1 and the partition 6. In a CVD (Chemical Vapor Deposition) apparatus, the sealing layer SE11 is formed by depositing an inorganic insulating material (e.g., silicon nitride) on the processing substrate SUB.

[0155] The laminated film FL1 and the sealing layer SE11 are formed over approximately the entire processing substrate SUB, and are disposed not only in sub-pixel SP1, but also in sub-pixels SP2 and SP3 in the display area DA.

[0156] Next, as Figure 11C As shown, a resist RS patterned into a prescribed shape is formed on the sealing layer SE11. The resist RS overlaps with a portion of the sub-pixel SP1 and its surrounding partition 6.

[0157] Next, as Figure 11D As shown, the sealing layer SE11 and the laminated film FL1 are patterned using the resist RS as a mask. By performing various etching operations using the resist RS as a mask, the sealing layer SE11 exposed from the resist RS is removed, and the capping layer CP1, the upper electrode UE1, and the organic layer OR1 contained in the laminated film FL1 are sequentially removed.

[0158] This patterning exposes the lower electrode LE2 of sub-pixel SP2 and the lower electrode LE3 of sub-pixel SP3.

[0159] The resist RS is then removed. As a result, the display element DE1 is formed in the sub-pixel SP1. Furthermore, in the illustrated example, the laminated film FL1 stacked on the partition 6 is removed during the patterning of the laminated film FL1 and the removal of the resist RS. Therefore, a void GP is formed between the sealing layer SE11 and the partition 6.

[0160] Next, as Figure 11EThe display element DE2 is shown. The steps for forming the display element DE2 are the same as those for forming the display element DE1. That is, a laminated film FL2 is formed on the lower electrode LE2. The laminated film FL2 has an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a capping layer CP2. Furthermore, an encapsulating layer SE12 is formed on the laminated film FL2. Then, a photoresist is formed on the encapsulating layer SE12. Then, patterning is performed using the photoresist as a mask. As a result, the encapsulating layer SE12 and the laminated film FL2 exposed from the photoresist are sequentially removed. Then, the photoresist is removed.

[0161] Thus, a display element DE2 is formed in sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 is exposed. Furthermore, in the illustrated example, the laminated film FL2 above partition 6 is removed during patterning, thus forming a void GP between the sealing layer SE12 and partition 6.

[0162] Next, as Figure 11F As shown, display element DE3 is formed. The steps for forming display element DE3 are the same as those for forming display element DE1. That is, a multilayer film FL3 is formed on the lower electrode LE3. The multilayer film FL3 has an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a capping layer CP3. Then, an encapsulating layer SE13 is formed on the multilayer film FL3. Then, a photoresist is formed on the encapsulating layer SE13. Then, patterning is performed using the photoresist as a mask. As a result, the encapsulating layer SE13 and the multilayer film FL3 exposed from the photoresist are sequentially removed. Then, the photoresist is removed.

[0163] Thus, a display element DE3 is formed in the sub-pixel SP3. Furthermore, in the illustrated example, the laminated film FL3 above the partition 6 is removed during patterning, thereby forming a void GP between the sealing layer SE13 and the partition 6.

[0164] It should be noted that in the above manufacturing process, the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0165] Then, a resin layer RS1 is formed by applying a resin material. Then, a sealing layer SE2 is formed by depositing an inorganic insulating material. Then, a resin layer RS2 is formed by applying a resin material.

[0166] After the above processes, the display device DSP is completed.

[0167] In the manufacturing process described above, the laminated film FL1, the sealing layer SE11, the laminated film FL2, the sealing layer SE12, the laminated film FL3, and the sealing layer SE13 are also formed in the peripheral area SA. For example, in the case where the laminated film FL1 and the sealing layer SE11 are peeled off from the processing substrate SUB during the period until the patterning process described above, it can become a source of contamination of the manufacturing equipment. In addition, the area in the processing substrate SUB where the laminated film FL1 and the sealing layer SE11 are peeled off can be damaged at the time of patterning. Therefore, in the peripheral area SA, it is important to suppress the undesired peeling of the laminated film FL1 and the sealing layer SE11. Similarly, for the laminated film FL2 and the sealing layer SE12, the laminated film FL3 and the sealing layer SE13, it is also required to suppress the undesired peeling. Figure 11D In the case where the laminated film FL1 and the sealing layer SE11 are peeled off from the processing substrate SUB during the period until the patterning process described above, it can become a source of contamination of the manufacturing equipment. In addition, the area in the processing substrate SUB where the laminated film FL1 and the sealing layer SE11 are peeled off can be damaged at the time of patterning. Therefore, in the peripheral area SA, it is important to suppress the undesired peeling of the laminated film FL1 and the sealing layer SE11. Similarly, for the laminated film FL2 and the sealing layer SE12, the laminated film FL3 and the sealing layer SE13, it is also required to suppress the undesired peeling.

[0168] According to the present embodiment, in the peripheral area SA, the partition wall 6 is formed in a lattice shape having a plurality of openings OP. In addition, the area of the partition wall 6 overlapping with the contact hole CH is also the same as the area not overlapping with the contact hole CH. That is, the partition wall 6 does not have a large area portion in a local area, particularly in the area overlapping with the contact hole CH.

[0169] Therefore, for example, when the laminated film FL1 is formed in the peripheral area SA, the laminated film FL1 is subdivided by the partition wall 6, and in addition, the laminated film FL1 in which the sealing layer SE11 is subdivided is wrapped together with the partition wall 6. Thereby, it is possible to suppress the undesired peeling of the laminated film FL1 and the sealing layer SE11.

[0170] Similarly, when the laminated film FL2 is formed in the peripheral area SA, the laminated film FL2 is also subdivided and wrapped by the sealing layer SE12. When the laminated film FL3 is formed in the peripheral area SA, the laminated film FL3 is also subdivided and wrapped by the sealing layer SE13. Thereby, it is possible to suppress the undesired peeling of the laminated film FL2 and the sealing layer SE12 and the undesired peeling of the laminated film FL3 and the sealing layer SE13.

[0171] Therefore, when manufacturing the display device DSP, it is possible to improve the yield.

[0172] The inventors have conducted various studies and found that in the case where the width Wx11 along the first direction X and the width Wx12 along the second direction Y of the partition wall 6 are each 40 μm or less, the laminated film is not peeled off. On the other hand, the partition wall 6 of the peripheral area SA has a function of supplying the common voltage supplied from the power supply line PW to the partition wall 6 of the display area DA. Therefore, it is not possible to make the width of the partition wall 6 of the peripheral area SA extremely small, and it is preferably 10 μm or more.

[0173] Next, several other configuration examples will be described.

[0174] Figure 12is a plan view showing another shape example of the partition wall 6 in the vicinity of the contact hole CH1.

[0175] Figure 12 The example shown in Figure 8 The example shown in

[0176] In addition, Figure 12 The example shown in Figure 8 The example shown in

[0177] The contact hole CH1 is located at an intersection of one extension 6X and one extension 6Y. The width Wx1 of the contact hole CH1 along the first direction X is larger than the width Wy1 of the contact hole CH1 along the second direction Y (Wy1 < Wx1). In addition, the width Wy11 of the extension 6X is larger than the width Wy1 of the contact hole CH1 (Wy1 < Wy11). The width Wx11 of the extension 6Y is smaller than the width Wx1 of the contact hole CH1 (Wx1 > Wx11).

[0178] In this configuration example, the same effects as described above can be obtained. In addition, in the peripheral region SA, since the extension 6X of the partition wall 6 has the same width as the extension 6Y, when the laminated film is formed on the extension 6X and the extension 6Y, respectively, the stress of the laminated film acting on the extension 6X and the stress of the laminated film acting on the extension 6Y are uniformized, and peeling of the laminated film in a local portion can be suppressed.

[0179] In addition, the contact hole CH is expanded in the first direction X in a region overlapping the partition wall 6. Therefore, an increase in connection resistance accompanying a decrease in the area of the contact hole CH can be suppressed.

[0180] Note that, in the example shown in Figure 12 In the example shown in

[0181] Figure 13 is a plan view showing another shape example of the partition wall 6 in the vicinity of the contact hole CH1.

[0182] Figure 13 The example shown in Figure 7 The example shown in

[0183] As described above, in the display region DA, the partition wall 6 is formed in a lattice shape having the openings OP1, OP2, OP3. In the peripheral region SA, the partition wall 6 is formed in a lattice shape having the openings OP11, OP12, OP13. The opening OP11 has the same shape as the opening OP1, the opening OP12 has the same shape as the opening OP2, and the opening OP13 has the same shape as the opening OP3.

[0184] In the peripheral region SA, the partition wall 6 is electrically connected to the power supply line PW via a plurality of contact holes CH. The plurality of contact holes CH are arranged in a stepped manner along the rounded portion RD. The contact holes CH are respectively located between two openings OP adjacent to each other in the second direction Y. One of the plurality of contact holes CH1 is focused on, and will be described in detail below. Figure 4

[0185] Figure 14 is a plan view showing one example of a shape of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG. 6. Figure 13

[0186] The partition wall 6 is formed in a lattice shape in the peripheral region SA, and has the opening OP11, the opening OP12, and the opening OP13 as a plurality of openings OP.

[0187] The opening OP11 and the opening OP12 are adjacent to each other in the first direction X.

[0188] The opening OP11 and the opening OP13 are adjacent to each other in the first direction X.

[0189] The opening OP12 and the opening OP13 are adjacent to each other in the second direction Y.

[0190] These openings OP11, OP12, OP13 have mutually different shapes. For example, the opening OP11 extends in the second direction Y, and the opening OP13 extends in the first direction X. The opening OP12 extends in the second direction Y, but is shorter than the opening OP11. In terms of a width in the first direction X, the width Wxo1 of the opening OP11 is smaller than the width Wxo2 of the opening OP12 (Wxo1 < Wxo2). The width in the first direction X of the opening OP13 is equal to the width Wxo2.

[0191] In the first direction X, the partition wall 6 has a width Wx11 between the opening OP11 and the opening OP12. In addition, in the second direction Y, the partition wall 6 has a width Wy11 between the opening OP12 and the opening OP13. Each of the widths Wx11 and Wy11 is 40 μm or less.

[0192] ​​In the second direction Y, the contact hole CH1 is located between the opening OP12 and the opening OP13. The contact hole CH1 has a width Wx1 in the first direction X and a width Wy1 in the second direction Y. In the illustrated example, the width Wx1 is equal to the width Wy1 (Wx1 = Wy1).

[0193] The width Wx1 of the contact hole CH1 is smaller than the width Wxo2 of the opening OP12 (Wx1 < Wxo2). The width Wy1 of the contact hole CH1 is smaller than the width Wy11 of the barrier 6 (Wy1 < Wy11).

[0194] Note that the cross-sectional configuration of the contact hole CH1 is the same as that shown in Figure 9 the configuration shown in Figure 10 the configuration shown in

[0195] In this configuration example as well, the same effects as described above can be obtained.

[0196] Figure 15 is a plan view showing another shape example of the barrier 6 in the vicinity of the contact hole CH1 shown in Figure 13

[0197] Figure 15 the example shown in Figure 14 the example shown in

[0198] In this configuration example as well, the same effects as described above can be obtained.

[0199] In addition, the contact hole CH expands in the first direction X in a region overlapping the barrier 6. Therefore, an increase in connection resistance accompanying a decrease in the area of the contact hole CH can be suppressed.

[0200] Note that in the example shown in Figure 15 the contact hole CH expands in the second direction Y.

[0201] In the above-described embodiment, for example, the contact hole CH1 corresponds to a first contact hole. The opening OP11 corresponds to a first opening, the opening OP12 corresponds to a second opening, the opening OP13 corresponds to a third opening, and the opening OP14 corresponds to a fourth opening.

[0202] ​In the next room 6, the width Wyll is equivalent to the first width, the width Wyl2 is equivalent to the second width, the extension 6X is equivalent to the first extension, and the extension 6Y is equivalent to the second extension. The pitch Py is equivalent to the first pitch, and the pitch Px is equivalent to the second pitch.

[0203] As explained above, according to the present embodiment, a display device capable of improving the yield can be provided.

[0204] All display devices that can be appropriately designed, changed, and implemented by those skilled in the art based on the display device explained above as an embodiment of the present application, as long as including the gist of the present application, also belong to the scope of the present application.

[0205] Various modifications can be conceived by those skilled in the art within the scope of the idea of the present application, and these modifications should also be considered to belong to the scope of the present application. For example, as long as including the gist of the present application, embodiments obtained by those skilled in the art appropriately adding, deleting, or changing the design of the constituent elements or adding, omitting, or changing the conditions of the processes with respect to the above-described embodiments also belong to the scope of the present application.

[0206] In addition, other effects brought about by the modes explained in the above-described embodiments are of course considered to be brought about by the present application, as long as known from the description of the present specification or appropriately conceived by those skilled in the art.

Claims

1. A display device, characterized in that, include: Display elements are arranged in the display area where the image is displayed; An inorganic insulating layer is disposed within the display area and the peripheral area located outside the display area; A partition wall, disposed on the inorganic insulating layer and having conductivity, surrounds the display element in the display area; as well as The power supply line is covered by the inorganic insulation layer. The outer edge of the display area includes rounded corners. The power supply line is arranged along the rounded corner in the peripheral area and is electrically connected to the partition wall via a plurality of contact holes penetrating the inorganic insulating layer. The plurality of contact holes are arranged in a stepped manner along the rounded corner.

2. The display device according to claim 1, characterized in that, The partition wall is formed in the peripheral region as a grid with a first opening and a second opening adjacent to each other in a first direction, and a third opening and a fourth opening adjacent to each other in the first direction. The first opening and the third opening are adjacent to each other in a second direction that intersects the first direction. The second opening and the fourth opening are adjacent to each other in the second direction. In the second direction, the partition wall has a first width between the first opening and the third opening, and a second width equal to the first width between the second opening and the fourth opening. The plurality of contact holes includes a first contact hole located between the second opening and the fourth opening. Neither of the contact holes is located between the first opening and the third opening.

3. The display device according to claim 2, characterized in that, The second width is less than 40 μm.

4. The display device according to claim 2, characterized in that, The first opening, the second opening, the third opening, and the fourth opening have the same shape.

5. The display device according to claim 4, characterized in that, In each of the first opening, the second opening, the third opening, and the fourth opening, the width along the second direction is greater than the width along the first direction.

6. The display device according to claim 1, characterized in that, In the peripheral region, the partition wall has a first extension extending in a first direction and a second extension extending in a second direction intersecting the first direction. The plurality of contact holes includes a first contact hole located at the intersection between the first extension and the second extension. The width of the first extension along the second direction is greater than the width of the first contact hole along the second direction. The width of the second extension along the first direction is smaller than the width of the first contact hole along the first direction.

7. The display device according to claim 6, characterized in that, The width of the first extension along the second direction is different from the width of the second extension along the first direction.

8. The display device according to claim 1, characterized in that, In the peripheral region, the partition wall has a first extension extending in a first direction and a second extension extending in a second direction intersecting the first direction. The plurality of contact holes includes a first contact hole located at the intersection between the first extension and the second extension. The width of the first extension along the second direction is the same as the width of the second extension along the first direction.

9. The display device according to claim 8, characterized in that, The width of the first contact hole along the first direction is greater than the width of the first contact hole along the second direction.

10. The display device according to claim 1, characterized in that, In the surrounding area, the partition wall is formed as a grid with a first opening, a second opening, and a third opening. The first opening and the second opening are adjacent to each other in the first direction. The first opening and the third opening are adjacent to each other in the first direction. The second opening and the third opening are adjacent to each other in a second direction that intersects with the first direction. The plurality of contact holes includes a first contact hole located between the second opening and the third opening in the second direction.

11. The display device according to claim 10, characterized in that, The first opening, the second opening, and the third opening have different shapes from each other.

12. The display device according to claim 10, characterized in that, In the second direction, the partition wall has a width of less than 40 μm between the second opening and the third opening.

13. The display device according to claim 10, characterized in that, The width of the first contact hole along the first direction is the same as the width of the first contact hole along the second direction.

14. The display device according to claim 10, characterized in that, The width of the first contact hole along the first direction is greater than the width of the first contact hole along the second direction.

15. The display device according to claim 10, characterized in that, The partition is formed in the same grid pattern in the display area and the surrounding area.

16. A display device, characterized in that, include: Display elements are arranged in the display area where the image is displayed; An inorganic insulating layer is disposed within the display area and the peripheral area located outside the display area; A partition wall, disposed on the inorganic insulating layer and having conductivity, surrounds the display element in the display area; as well as The power supply line is covered by the inorganic insulation layer. In the surrounding area, the power supply line is electrically connected to the partition wall via a contact hole penetrating the inorganic insulation layer. In the surrounding area, the partition wall is formed in a lattice shape having a plurality of first extensions and a plurality of second extensions. The plurality of first extension portions extend in a first direction and are arranged at a first spacing in a second direction intersecting the first direction. The plurality of second extension portions extend in the second direction and are arranged at a second spacing in the first direction. The contact hole is located at the intersection between one of the plurality of first extensions and one of the plurality of second extensions.

17. The display device according to claim 16, characterized in that, The first spacing is different from the second spacing.

18. The display device according to claim 16, characterized in that, The first spacing is greater than the second spacing.

19. The display device according to claim 16, characterized in that, The width of each of the plurality of first extensions along the second direction is different from the width of each of the plurality of second extensions along the first direction.

20. The display device according to claim 16, characterized in that, The width of each of the plurality of first extensions along the second direction is greater than the width of each of the plurality of second extensions along the first direction.

21. The display device according to claim 16, characterized in that, The width of each of the plurality of first extensions along the second direction is greater than the width of the contact hole along the second direction. The width of each of the plurality of second extensions along the first direction is smaller than the width of the contact hole along the first direction.

22. A display device, characterized in that, include: Display elements are arranged in the display area where the image is displayed; An inorganic insulating layer is disposed within the display area and the peripheral area located outside the display area; A partition wall, disposed on the inorganic insulating layer and having conductivity, surrounds the display element in the display area; as well as The power supply line is covered by the inorganic insulation layer. In the surrounding area, the power supply line is electrically connected to the partition wall via a contact hole penetrating the inorganic insulation layer. In the surrounding area, the partition wall is formed as a grid with multiple openings. The plurality of openings have a first opening, a second opening, and a third opening arranged sequentially at equal intervals in one direction. The contact hole is located between the second opening and the third opening. In the partition, the width between the first opening and the second opening is equal to the width between the second opening and the third opening.

23. The display device according to claim 22, characterized in that, When viewed from above, the contact hole does not overlap with either the second or third opening.

24. The display device according to claim 22, characterized in that, The first opening, the second opening, and the third opening have the same shape.

25. The display device according to any one of claims 2, 10, and 22, characterized in that, The inorganic insulating layer does not contain through holes that overlap with the first opening, the second opening, and the third opening.

26. The display device according to any one of claims 1, 16, and 22, characterized in that, The partition wall comprises: The lower part, which is formed of conductive material, is located above the inorganic insulating layer in the display area and the surrounding area, and is in contact with the power supply line in the surrounding area; as well as The upper part, which is located above the lower part, has an end that protrudes from the side of the lower part.

27. The display device according to claim 26, characterized in that, The display element includes: The lower electrode has a peripheral portion covered by the inorganic insulating layer; An organic layer, situated above the lower electrode, comprising a light-emitting layer; and The upper electrode is located above the organic layer and is in contact with the lower part of the partition wall.

28. The display device according to claim 26, characterized in that, The surrounding area also includes: A laminated film comprising a first portion and a second portion, the first portion being located above the upper portion of the partition wall, and the second portion being located above the inorganic insulating layer and separated from the first portion; and A sealing layer, formed of an inorganic insulating material, continuously covers the first and second portions of the laminated film.

29. The display device according to claim 28, characterized in that, The laminated film comprises: An organic layer, situated above the inorganic insulating layer, includes a light-emitting layer; The upper electrode, located above the organic layer, is in contact with the lower portion of the partition wall; and A capping layer, which is located above the upper electrode.

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