Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a base layer; a circuit element layer; and a display element layer including a light emitting element and a light receiving element, in which the circuit element layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a readout line connected to the plurality of sensor driving circuits, and extending in a first direction; a first data line connected to the plurality of pixel driving circuits, and extending in a first direction; a first vertical connection line between the first data line and the readout line in the second direction and extending in the first direction, and to which the first DC signal is transmitted; and an insulating layer covering the first vertical connection line and the first data line, and the first DC signal is a signal transmitted to the plurality of pixel driving circuits.

Description

TECHNICAL FIELD

[0001] Aspects of some embodiments of the disclosure described herein relate to display apparatuses and electronic apparatuses including the same. BACKGROUND

[0002] Electronic apparatuses such as smartphones, digital cameras, laptop computers, navigation systems, and smart TVs that provide images to users include display apparatuses for displaying images. The display apparatuses include display panels for generating images, input apparatuses such as input sensors, cameras for capturing external images, and various sensors.

[0003] The input sensor can be positioned on the display panel and sense a touch of a user. The sensor can include a fingerprint sensor, a proximity sensor, and an illumination sensor, etc. Among these sensors, the fingerprint sensor can sense a fingerprint of a user provided on the display panel.

[0004] The above information disclosed in this Background section is only for enhancing the understanding of the background and therefore the information discussed in the Background section can not necessarily constitute prior art. SUMMARY

[0005] Aspects of some embodiments of the disclosure described herein relate to display apparatuses and electronic apparatuses including the same, and for example, to display apparatuses including vertical connection lines and electronic apparatuses including the same.

[0006] Aspects of some embodiments of the disclosure include display apparatuses in which an optical sensor can be completely disposed on a display surface.

[0007] According to some embodiments of the disclosure, a display apparatus includes a base layer including a display area and a non-display area, a circuit element layer on the base layer, and a display element layer on the circuit element layer, and the display element layer includes a light emitting element and a light receiving element overlapping the display area, wherein the circuit element layer includes a pixel driving circuit connected to the light emitting element, a sensor driving circuit connected to the light receiving element, a readout line connected to a plurality of the sensor driving circuits and extending in a first direction, a first data line connected to a plurality of the pixel driving circuits and extending in the first direction, a first vertical connection line between the first data line and the readout line in a second direction intersecting the first direction and extending in the first direction, and a first direct current (DC) signal is transmitted to the first vertical connection line, and an insulating layer covering the first vertical connection line and the first data line, and the first DC signal is a signal transmitted to the plurality of the pixel driving circuits.

[0008] According to some embodiments, the circuit element layer can further include: a first horizontal connection line electrically connected to the plurality of pixel driving circuits, the first horizontal connection line extending in the second direction, and the first horizontal connection line connected to the first vertical connection line through a first via hole passing through the insulating layer, and the first DC signal being transmitted to the first horizontal connection line.

[0009] According to some embodiments, the first vertical connection line and the first horizontal connection line can be arranged on different layers.

[0010] According to some embodiments, the first vertical connection line can be provided as a plurality of first vertical connection lines, the first horizontal connection line can be provided as a plurality of first horizontal connection lines, and the plurality of first vertical connection lines and the plurality of first horizontal connection lines can have a mesh shape.

[0011] According to some embodiments, the readout line can be between first vertical connection lines closest to each other among the plurality of first vertical connection lines.

[0012] According to some embodiments, the circuit element layer can further include: a second data line connected to the plurality of pixel driving circuits, the second data line spaced apart from the first data line, and the second data line extending in the first direction; and a second vertical connection line between the second data line and the readout line in the second direction, and the second vertical connection line extending in the first direction, and the second DC signal being transmitted to the second vertical connection line.

[0013] According to some embodiments, the second DC signal can be transmitted to the plurality of sensor driving circuits.

[0014] According to some embodiments, the circuit element layer can further include: a second horizontal connection line extending in the second direction, and the second horizontal connection line connected to the second vertical connection line through a second via hole passing through the insulating layer, and the second DC signal being transmitted to the second horizontal connection line.

[0015] According to some embodiments, the second vertical connection line and the second horizontal connection line can be arranged on different layers.

[0016] According to some embodiments, the second vertical connection line can be provided as a plurality of second vertical connection lines, the second horizontal connection line can be provided as a plurality of second horizontal connection lines, and the plurality of second vertical connection lines and the plurality of second horizontal connection lines can have a mesh shape.

[0017] According to some embodiments, the readout line can be between the first vertical connection line and the second vertical connection line.

[0018] According to some embodiments, each of the plurality of sensor driving circuits can be between corresponding two adjacent pixel driving circuits among the plurality of pixel driving circuits.

[0019] According to some embodiments, the first vertical connecting line may overlap with a corresponding one of the multiple sensor driving circuits.

[0020] According to some embodiments, the second vertical connecting line may overlap with a corresponding one of the multiple sensor driving circuits.

[0021] According to some embodiments, the first vertical connecting line may be closer to the center of a corresponding one of the plurality of sensor driving circuits than the first data line.

[0022] According to some embodiments, the first vertical connecting line can be electrically connected to multiple pixel driving circuits.

[0023] According to some embodiments of this disclosure, an electronic device includes a display panel and a window on the display panel, wherein the display panel includes: a substrate layer including a display area and a non-display area; a circuit element layer on the substrate layer; and a display element layer on the circuit element layer, wherein the display element layer includes a light-emitting element and a light-receiving element overlapping the display area, wherein the circuit element layer includes: a pixel driving circuit connected to the light-emitting element; a sensor driving circuit connected to the light-receiving element; a readout line connected to a plurality of sensor driving circuits and extending in a first direction; a first data line and a second data line, each connected to a plurality of pixel driving circuits, the first data line and the second data line extending in the first direction, and the first data line and the second data line being spaced apart from each other in a second direction intersecting the first direction. The system comprises: a first vertical connecting line and a second vertical connecting line, each electrically connected to a plurality of pixel driving circuits or a plurality of sensor driving circuits, transmitting direct current (DC) signals, and being spaced apart from each other in a second direction, with a corresponding sensor driving circuit located between the first vertical connecting line and the second vertical connecting line; and an insulating layer covering the first data line, the second data line, and the first vertical connecting line and the second vertical connecting line, wherein the first vertical connecting line is closer to the readout line than the first data line, and the second vertical connecting line is closer to the readout line than the second data line.

[0024] According to some embodiments, the circuit element layer may further include: a first horizontal connection line electrically connected to a plurality of pixel driving circuits, the first horizontal connection line extending in a second direction and connected to a first vertical connection line through a first through-hole passing through an insulating layer; and a second horizontal connection line electrically connected to a plurality of pixel driving circuits, the second horizontal connection line extending in a second direction and connected to a second vertical connection line through a second through-hole passing through an insulating layer.

[0025] According to some embodiments, the first vertical connecting line can transmit a first DC signal, and the second vertical connecting line can transmit a second DC signal that is different from the first DC signal.

[0026] According to some embodiments, the first DC signal may be a signal transmitted to multiple pixel driving circuits, and the second DC signal may be a signal transmitted to multiple sensor driving circuits. Attached Figure Description

[0027] The above and other aspects and features of embodiments of the present disclosure will become more apparent from the description of various aspects of some embodiments of the present disclosure with reference to the accompanying drawings.

[0028] FIG. 1 This is a perspective view of a display device according to some embodiments of the present disclosure.

[0029] FIG. 2 It is an illustrative representation FIG. 1 The image shows a cross-sectional view of the display device.

[0030] FIG. 3 It is an illustrative representation FIG. 2 The image shows a cross-sectional view of the display panel.

[0031] FIG. 4 This is a block diagram of a display device according to some embodiments of the present disclosure.

[0032] FIG. 5 It is shown FIG. 4 The diagram shows a view of any one of the plurality of pixels, and the equivalent circuitry of the optical sensor adjacent to said any one pixel.

[0033] FIG. 6 It is an illustrative representation FIG. 5 The image shows a cross-sectional view of the light-emitting element, the first transistor, the fourth transistor, and the sixth transistor of the pixel.

[0034] FIG. 7A and FIG. 7B It is an illustrative representation FIG. 5 The image shows a cross-sectional view of the light-sensing element, the first sensing transistor, and the second sensing transistor of the optical sensor.

[0035] FIG. 8 It shows the arrangement in FIG. 4 The image shows a view of the arrangement of light-emitting elements and light-sensing elements in a portion of the display area on a plane (or in a plan view).

[0036] FIG. 9 It shows through FIG. 4 ,FIG. 7A and FIG. 7B The diagram shows an optical sensor securing fingerprint information as a biometric feature.

[0037] FIG. 10 This is a plan view illustrating data lines, vertical connecting lines, and horizontal connecting lines according to some embodiments of the present disclosure.

[0038] FIG. 11 yes FIG. 10 A magnified plan view of region AA'.

[0039] FIG. 12 to FIG. 15 This is a plan view illustrating the stacked structure of data lines, vertical connecting lines, and horizontal connecting lines according to some embodiments of the present disclosure.

[0040] FIG. 16 This is a plan view illustrating data lines, vertical connecting lines, and horizontal connecting lines according to some embodiments of the present disclosure. Detailed Implementation

[0041] In this specification, the descriptions of a first component (or region, layer, part, section, etc.) being "located on" a second component, "connected to" a second component, or "coupled to" a second component mean that the first component is directly located on / directly connected to / directly coupled to the second component, or that a third component is located between the first component and the second component.

[0042] The same reference numerals refer to the same components. Furthermore, in the drawings, the thickness, proportions, and size of the components are exaggerated for the sake of effective description of the technical content. The expression "and / or" includes one or more combinations that the associated components can define.

[0043] Although the terms “first,” “second,” etc., may be used to describe various components, the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless otherwise expressly indicated in the context, singular expressions include plural expressions.

[0044] Additionally, terms such as "below," "under," "on," and "above" are used to describe the relevance of components shown in the accompanying drawings. Conceptually relative terms are described based on the orientation shown in the drawings.

[0045] It will be understood that the terms “comprising,” “including,” “having,” etc., indicate the presence of the features, quantities, steps, operations, elements or components described in this specification, or combinations thereof, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components, or combinations thereof.

[0046] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an overly idealized or formalized sense.

[0047] In the following, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Electronic devices can be activated and display images based on electrical signals. Electronic devices can include various embodiments, and for example, can include large devices such as televisions and billboards, as well as small and medium-sized devices such as monitors, mobile phones, tablet computers, navigation systems, and game consoles. Embodiments of electronic devices are exemplary, and the embodiments according to this disclosure are not limited to any one embodiment, as long as they do not depart from the spirit and scope of the embodiments according to this disclosure. Electronic devices include display devices (see [link to display device]). FIG. 1 The electronic device also includes providing a housing for the display device DD (see...). FIG. 1 The shell of the internal space of ).

[0049] FIG. 1 This is a perspective view of a display device DD according to some embodiments of the present disclosure.

[0050] Reference FIG. 1 According to some embodiments of the present disclosure, the display device DD may have a rectangular shape in a plan view, the rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, embodiments of the present disclosure are not limited thereto, and the display device DD may have various shapes in a plan view, such as a circular shape, an elliptical shape, other polygonal shapes, or irregular shapes. Hereinafter, the direction perpendicular to (or substantially perpendicular to) the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. In this specification, the phrase "when viewed in a plane" or "in a plan view" is defined as the state viewed from the third direction DR3.

[0051] The front surface of the display device DD can be defined as the display surface DS and can have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD can be provided to the user through the display surface DS.

[0052] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA (e.g., in the periphery of the display area DA or outside the occupied area of ​​the display area DA). The display area DA displays an image, and the non-display area NDA does not display an image. The non-display area NDA may surround the display area DA (e.g., in the periphery of the display area DA or outside the occupied area of ​​the display area DA), but embodiments according to this disclosure are not limited thereto, and the non-display area NDA may not be positioned on one side of the display area DA.

[0053] FIG. 2 Illustratively shown FIG. 1 The image shows a cross-section of the display device DD.

[0054] Reference FIG. 2 The display device DD may include a display panel DP, an input sensor ISP, an anti-reflection layer RPL, a window WIN, a panel protective film PPF, a first adhesive layer AL1, and a second adhesive layer AL2. According to some embodiments of this disclosure, the input sensor ISP may be omitted.

[0055] The display panel DP according to some embodiments of the present disclosure may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include inorganic light-emitting materials. However, the embodiments according to the present disclosure are not particularly limited thereto. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0056] An input sensor ISP can be positioned on the display panel DP. The input sensor ISP may include multiple sensors for capacitively sensing external input. The input sensor ISP can be formed directly on the display panel DP during the manufacture of the display device DD. However, embodiments according to this disclosure are not limited thereto, and the input sensor ISP can be manufactured as a separate panel from the display panel DP and attached to the display panel DP using an adhesive layer.

[0057] The anti-reflection layer RPL can be positioned on the input sensor ISP. The anti-reflection layer RPL can be formed directly on the input sensor ISP during the manufacturing of the display device DD. The anti-reflection layer RPL may include a color filter and may also include a black matrix.

[0058] However, embodiments according to this disclosure are not limited thereto, and the anti-reflection layer RPL can be manufactured as a separate panel and attached to the input sensor ISP via an adhesive layer. The anti-reflection layer RPL may include an optical film such as a polarizing film. The anti-reflection layer RPL can reduce the reflectivity of external light incident from the top side of the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, external light may not be visually perceptible to the user.

[0059] The WIN window can be positioned on the anti-reflective layer RPL. The WIN window can protect the display panel DP, input sensor ISP, and anti-reflective layer RPL from external scratches and impacts.

[0060] The panel protective film (PPF) can be positioned below the display panel (DP). The PPF protects the lower portion of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0061] FIG. 3 It is an illustrative representation FIG. 2 The image shows a cross-sectional view of the display panel DP.

[0062] Reference FIG. 3 The display panel DP may include a substrate layer SUB, a circuit element layer DP-CL positioned on the substrate layer SUB, a display element layer DP-OLED positioned on the circuit element layer DP-CL, and a thin film encapsulation layer TFE positioned on the display element layer DP-OLED.

[0063] The substrate layer SUB may include a display area DA and a non-display area NDA surrounding the display area DA, which is consistent with... FIG. 1 The display device is similar to DD. The substrate layer SUB can include glass or a flexible plastic material such as polyimide (PI).

[0064] The circuit element layer DP-CL may include driving circuitry for the light-emitting elements and driving circuitry for the light-sensing elements. The display element layer DP-OLED may include both light-emitting elements and light-sensing elements. The thin-film encapsulation layer TFE may be positioned on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin-film encapsulation layer TFE can protect the pixels from moisture, oxygen, and external foreign matter.

[0065] FIG. 4 This is a block diagram of a display device DD according to some embodiments of the present disclosure.

[0066] Reference FIG. 4The display device DD includes a display panel DP, a drive controller 100, and a drive circuit for the display device DD. According to some embodiments of this disclosure, the drive circuit for the display device DD includes a data driver 200, a scan driver 300, a light-emitting driver 350, a voltage generator 400, and a readout circuit 500. According to some embodiments of this disclosure, the voltage generator 400 and the readout circuit 500, together with the drive controller 100, can be implemented as a single drive chip.

[0067] The display panel DP may include a plurality of pixels PX arranged in a display area DA and a plurality of optical sensors SN arranged in the display area DA. According to some embodiments of the present disclosure, each of the plurality of optical sensors SN may be positioned between two adjacent pixels PX. However, the arrangement relationship between the optical sensors SN and the pixels PX is not limited thereto.

[0068] The display panel DP may include initialization scan lines GI1 to GIn, compensation scan lines GC1 to GCn, bias scan lines GB1 to GBn, write scan lines GW1 to GWn, light emission control lines EML1 to EMLn, reset scan lines GR1 to GRn, data lines DL1 to DLm, and readout lines RX1, RX2, ..., RXh. The initialization scan lines GI1 to GIn, compensation scan lines GC1 to GCn, bias scan lines GB1 to GBn, write scan lines GW1 to GWn, light emission control lines EML1 to EMLn, and reset scan lines GR1 to GRn extend in the second direction DR2. The data lines DL1 to DLm and the readout lines RX1 to RXh extend in the first direction DR1. "n", "m", and "h" are each a natural number greater than zero.

[0069] Multiple pixels PX are electrically connected to initialization scan lines GI1 to GIn, compensation scan lines GC1 to GCn, write scan lines GW1 to GWn, bias scan lines GB1 to GBn, light emission control lines EML1 to EMLn, and data lines DL1 to DLm. However, the number of signal lines connected to each of the pixels PX is not limited to this and can be changed.

[0070] Multiple optical sensors SN are electrically connected to write scan lines GW1 to GWn, reset scan lines GR1 to GRn, and readout lines RX1 to RXh. The number of signal lines connected to the multiple optical sensors SN is not limited to this and can be varied.

[0071] The drive controller 100 receives an image signal RGB and a control signal CTRL. The drive controller 100 generates an image data signal DATA by converting the data format of the image signal RGB, ensuring that the image data signal DATA meets the interface specifications with the data driver 200. The drive controller 100 outputs a first control signal DCS, a second control signal SCS, a third control signal ECS, and a fourth control signal RCS.

[0072] The data driver 200 receives a first control signal DCS and an image data signal DATA from the drive controller 100. The data driver 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm, which will be described below. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0073] The scan driver 300 receives a second control signal SCS from the drive controller 100. In response to the second control signal SCS, the scan driver 300 outputs an initialization scan signal to the initialization scan lines GI1 to GIn and a compensation scan signal to the compensation scan lines GC1 to GCn. Furthermore, in response to the second control signal SCS, the scan driver 300 may output a write scan signal to the write scan lines GW1 to GWn and a bias scan signal to the bias scan lines GB1 to GBn. Additionally, in response to the second control signal SCS, the scan driver 300 may output a reset scan signal to the reset scan lines GR1 to GRn.

[0074] The LED driver 350 receives a third control signal ECS from the drive controller 100. In response to the third control signal ECS, the LED driver 350 can output an LED control signal to the LED control lines EML1 to EMLn. Alternatively, the scan driver 300 can be connected to the LED control lines EML1 to EMLn. In this case, the LED driver 350 can be omitted, and the scan driver 300 can output the LED control signal to the LED control lines EML1 to EMLn.

[0075] The readout circuit 500 can receive a fourth control signal RCS from the drive controller 100. In response to the fourth control signal RCS, the readout circuit 500 can receive sensing signals from readout lines RX1 to RXh. The readout circuit 500 can process the sensing signals received from readout lines RX1 to RXh and provide the processed sensing signal S_FS to the drive controller 100. The drive controller 100 can identify biometric information based on the sensing signal S_FS.

[0076] Voltage generator 400 generates the voltages required to operate the display panel DP. According to some embodiments, voltage generator 400 may generate a first drive voltage ELVDD, a second drive voltage ELVSS having a lower level than the first drive voltage ELVDD, a first initialization voltage VINT, a second initialization voltage AINT, a reset voltage VRST, and a bias voltage VBIAS.

[0077] FIG. 5 It is shown FIG. 4 The diagram shows a view of the equivalent circuitry of any one pixel PXij among a plurality of pixels PX, and the optical sensor SNij adjacent to said pixel PXij. Although FIG. 5 Various components in the pixel PXij and optical sensor SNij according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and the pixel PXij and / or optical sensor SNij may include additional components or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0078] Illustratively, FIG. 5 Pixel PXij is shown, connected to the i-th scan line SLi, the i-th emission control line EMLi, and the j-th data line DLj. Furthermore, FIG. 5 An optical sensor SNij connected to the i-th reset scan line GRi and the j-th readout line RXj is illustrated. “i” is a natural number greater than zero and less than or equal to “n”, and “j” is a natural number greater than zero and less than or equal to “m”. The i-th scan line SNij may include the i-th initialization scan line GIi, the i-th compensation scan line GCI, the i-th bias scan line GBi, and the i-th write scan line GWi.

[0079] Reference FIG. 5 Pixel PXij may include a pixel driving circuit PC and a light-emitting element OLED electrically connected to the pixel driving circuit PC. The light-emitting element OLED can be turned on or off under the control of the pixel driving circuit PC.

[0080] The pixel driving circuit PC may include multiple transistors T1 to T8 and a capacitor CST. Transistors T1 to T8 and capacitor CST control the amount of current flowing through the light-emitting element OLED. The light-emitting element OLED can produce light with brightness depending on the amount of current supplied.

[0081] The i-th write scan line GWi can receive the i-th write scan signal GWSi, and the i-th compensation scan line GCI can receive the i-th compensation scan signal GCSi. The i-th initialization scan line GIi can receive the i-th initialization scan signal GISi, and the i-th bias scan line GBi can receive the i-th bias scan signal GBSi. The i-th reset scan line GRi can receive the i-th reset scan signal GRSi. The i-th emission control line EMLi can receive the i-th emission signal ESi.

[0082] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage AINT. The bias line VBL can receive the bias voltage VBIAS. The first power line PL1 can receive the first drive voltage ELVDD, and the second power line PL2 can receive the second drive voltage ELVSS. The light-emitting element OLED can be connected to the second power line PL2. The reset line VRL can receive the reset voltage VRST.

[0083] Each of transistors T1 through T8 may include a source (or source terminal), a drain (or drain terminal), and a gate (or gate terminal). In the following text, in FIG. 5 For convenience, one of the source and drain is defined as the first electrode, and the other of the source and drain is defined as the second electrode. Furthermore, the gate is defined as the gate electrode or control electrode.

[0084] Transistors T1 to T8 may include first transistor T1 to eighth transistor T8. First transistor T1, second transistor T2, and fifth transistor T5 to eighth transistor T8 may be P-type metal-oxide-semiconductor (PMOS) transistors. Third transistor T3 and fourth transistor T4 may be N-type metal-oxide-semiconductor (NMOS) transistors.

[0085] The first transistor T1 can be defined as a driving transistor, and the second transistor T2 can be defined as a switching transistor. The third transistor T3 can be called a compensation transistor. The fourth transistor T4 and the seventh transistor T7 can be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 can be defined as light-emitting control transistors. The eighth transistor T8 can be defined as a bias transistor.

[0086] An OLED (Organic Light-Emitting Diode) can include an organic light-emitting diode. The OLED can include a first electrode, a second electrode, and a light-emitting layer positioned between the first and second electrodes. According to some embodiments, for ease of description, the first electrode is described as an anode AE, and the second electrode as a cathode CE. The anode AE ​​can be electrically connected to a first power line PL1 via a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The cathode CE can be electrically connected to a second power line PL2.

[0087] The first transistor T1 can be positioned between the fifth transistor T5 and the sixth transistor T6, and connected to both transistors T5 and T6. The first transistor T1 can be connected to the first power line PL1 via the fifth transistor T5 and to the anode AE ​​via the sixth transistor T6.

[0088] The first transistor T1 may include a first electrode connected to the first power line PL1 via a fifth transistor T5, a second electrode connected to the anode AE ​​via a sixth transistor T6, and a gate electrode connected to the first node N1.

[0089] The first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current flowing through the light-emitting element OLED according to the voltage applied to the first node N1 of the gate electrode of the first transistor T1.

[0090] The second transistor T2 can be positioned between the first transistor T1 and the j-th data line DLj, and connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th write scan line GWi.

[0091] The second transistor T2 can be turned on by the i-th write scan signal GWSi applied through the i-th write scan line GWi, and electrically connect the j-th data line DLj to the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the data voltage VD applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0092] The third transistor T3 can be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a gate electrode connected to the i-th compensation scan line GCI.

[0093] The third transistor T3 can be turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCI, and electrically connect the second electrode and the gate electrode of the first transistor T1. When the third transistor T3 is turned on, it can connect the first transistor T1 in a diode manner.

[0094] A fourth transistor T4 may be connected to a first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to a first initialization line VIL1, and a gate electrode connected to the i-th initialization scan line GIi. The fourth transistor T4 may be turned on by an i-th initialization scan signal GISi applied through the i-th initialization scan line GIi and provide a first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0095] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th light-emitting control line EMLi. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a gate electrode connected to the i-th light-emitting control line EMLi.

[0096] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th emission signal ESi applied through the i-th emission control line EMLi. The first driving voltage ELVDD is provided to the light-emitting element OLED through the turned-on fifth transistor T5 and the turned-on sixth transistor T6, allowing driving current to flow into the light-emitting element OLED. Therefore, the light-emitting element OLED can emit light.

[0097] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a gate electrode connected to the i-th bias scan line GBi. The seventh transistor T7 may be turned on by the i-th bias scan signal GBSi applied through the i-th bias scan line GBi and provide the second initialization voltage AINT received through the second initialization line VIL2 to the anode AE ​​of the light-emitting element OLED.

[0098] According to some embodiments of this disclosure, the seventh transistor T7 may be omitted. According to some embodiments of this disclosure, the second initialization voltage AINT may have a different level than the first initialization voltage VINT, but the embodiments of this disclosure are not limited thereto, and the second initialization voltage AINT may have the same level as the first initialization voltage VINT.

[0099] The seventh transistor T7 can relatively improve the black performance of pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor of the OLED light-emitting element can be discharged. Therefore, when achieving black brightness, the OLED light-emitting element does not emit light due to the leakage current of the first transistor T1, and thus, the black performance can be relatively improved.

[0100] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage stored in the capacitor CST.

[0101] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th bias scan line GBi. According to some embodiments of this disclosure, the eighth transistor T8 may be omitted.

[0102] The eighth transistor T8 can be turned on by the i-th bias scan signal GBSi, and can provide a bias voltage VBIAS to the first electrode of the first transistor T1. Since the bias voltage VBIAS is applied to the first transistor T1, the shift of the hysteresis curve of the first transistor T1 can be suppressed.

[0103] The optical sensor SNij may include a sensor driving circuit SNC and a light sensing element LRE electrically connected to the sensor driving circuit SNC. The sensor driving circuit SNC can sense the operation of the light sensing element LRE.

[0104] The sensor driving circuit SNC may include a first sensing transistor T1', a second sensing transistor T2', and a third sensing transistor T3'. The first sensing transistor T1' and the third sensing transistor T3' may be PMOS transistors, and the second sensing transistor T2' may be an NMOS transistor.

[0105] A photosensitive element (LRE) can be defined as a photodiode. The LRE converts light energy incident from the outside into electrical energy. The LRE may include a first electrode, a second electrode, and a photoelectric conversion layer positioned between the first and second electrodes. According to some embodiments, for ease of description, the first electrode is described as an anode AE', and the second electrode is described as a cathode CE'. The anode AE' may be connected to a second node N2, and the cathode CE' may be connected to a second power line PL2. To distinguish the anode AE ​​and cathode CE of the light-emitting element (OLED) from the anode AE' and cathode CE' of the photosensitive element (LRE), the anode AE ​​and cathode CE of the OLED may be defined as the first electrode and the second electrode, and the anode AE' and cathode CE' of the photosensitive element (LRE) may be defined as electrode (1-1) and electrode (2-1).

[0106] A first sensing transistor T1' can be connected to a light sensing element LRE, a second sensing transistor T2', and a third sensing transistor T3'. The first sensing transistor T1' may include a first electrode receiving a second initialization voltage AINT, a gate electrode connected to a second node N2, and a second electrode connected to the third sensing transistor T3'. The first electrode of the first sensing transistor T1' can be connected to a second initialization line VIL2 to receive the second initialization voltage AINT. The second sensing transistor T2' may include a first electrode connected to the second node N2, a gate electrode connected to the i-th reset scan line GRi, and a second electrode connected to the reset line VRL. The third sensing transistor T3' may include a first electrode connected to the second electrode of the first sensing transistor T1', a gate electrode connected to the i-th write scan line GWi, and a second electrode connected to the j-th readout line RXj. The third sensing transistor T3' can be turned on by the i-th write scan signal GWSi received through the i-th write scan line GWi.

[0107] The second sensing transistor T2' can be turned on by the i-th reset scan signal GRSi received through the i-th reset scan line GRi. The turned-on second sensing transistor T2' can receive the reset voltage VRST and provide the reset voltage VRST to the second node N2. The second node N2 can be reset by the reset voltage VRST.

[0108] The i-th write scan signal GWSi can be applied to the gate electrode of the third sensing transistor T3', causing the third sensing transistor T3' to conduct. The first sensing transistor T1' can be connected to the j-th readout line RXj through the conducted third sensing transistor T3'.

[0109] The photosensitive element LRE can receive light and convert it into an electrical signal, and in this case, the voltage of the second node N2 can be changed. When the first sensing transistor T1' is turned on, the second initialization voltage AINT supplied to the first sensing transistor T1' can be controlled according to the change in the voltage of the second node N2, and can be supplied to the j-th readout line RXj through the third sensing transistor T3'. Therefore, the signal sensed by the photosensitive element LRE can be output as a sensing signal RS through the j-th readout line RXj.

[0110] FIG. 6 It is an illustrative representation FIG. 5 The image shows a cross-sectional view of the light-emitting element OLED, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 of pixel PXij.

[0111] FIG. 6 The first transistor T1, the fourth transistor T4, and the sixth transistor T6 in the pixel driving circuit PC are shown. (Refer to...) FIG. 6 The shielding layer BML can be positioned on the substrate layer SUB. The shielding layer BML can overlap with the first transistor T1. The shielding layer BML can include metal and receive a constant voltage. When a constant voltage is applied to the shielding layer BML, the threshold voltage (Vth) of the first transistor T1 positioned on the shielding layer BML can be maintained without change. Furthermore, the shielding layer BML can block light incident on the first transistor T1 from the underside of the shielding layer BML. For example, the shielding layer BML can include a reflective material. According to some embodiments of this disclosure, the shielding layer BML can be omitted.

[0112] A buffer layer BFL may be positioned on the substrate layer SUB, and the buffer layer BFL may include an inorganic layer. The buffer layer BFL may cover the shielding layer BML. The semiconductor layer SCP1 (or semiconductor patterned region, and hereinafter described as the first semiconductor layer SCP1) of the first transistor T1 and the semiconductor layer SCP6 (or semiconductor patterned region, and hereinafter described as the sixth semiconductor layer SCP6) of the sixth transistor T6 may be disposed on the buffer layer BFL. Hereinafter, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include polycrystalline silicon. However, embodiments according to this disclosure are not limited thereto, and the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include amorphous silicon.

[0113] The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 can be formed using the same process, and certain regions of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 can be doped with N-type or P-type dopant. The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 can include highly doped regions and lightly doped regions. The conductivity of the highly doped regions is greater than that of the lightly doped regions. The highly doped regions can correspond to the source and drain regions of the first transistor T1 and the sixth transistor T6. The lightly doped regions can correspond to the active regions (or channels) of the first transistor T1 and the sixth transistor T6.

[0114] The highly doped region of the first semiconductor layer SCP1 may include a first source region S1 and a first drain region D1. The lightly doped region of the first semiconductor layer SCP1 is defined as a first channel region A1 and is located between the first source region S1 and the first drain region D1. Similar to the first semiconductor layer SCP1, the sixth semiconductor layer SCP6 may include a sixth source region S6, a sixth channel region A6, and a sixth drain region D6.

[0115] exist FIG. 6 In cross-section, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be spaced apart from each other. However, in a planar view (or in a planar diagram), the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may have a single, integral shape. In other words, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be different parts or different regions of a single semiconductor pattern.

[0116] A first insulating layer INS1 covering the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 can be positioned on the buffer layer BFL. The gate electrode of the first transistor T1 and the gate electrode of the sixth transistor T6 are disposed on the first insulating layer INS1. The gate electrodes of the first transistor T1 and the sixth transistor T6 can be formed using the same process. Hereinafter, the gate electrode of the first transistor T1 is defined as the first gate electrode G1, and the gate electrode of the sixth transistor T6 is defined as the sixth gate electrode G6. The metal layer containing the first gate electrode G1 formed on the first insulating layer INS1 can be defined as the first gate layer. The first gate layer may also include multiple patterns in addition to the first gate electrode G1 and the sixth gate electrode G6.

[0117] A second insulating layer INS2 can be positioned on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. A dummy electrode DME can be positioned on the second insulating layer INS2. The dummy electrode DME can be positioned on the first gate electrode G1 and can overlap with the first gate electrode G1 when viewed in a plane (or in a plan view). The dummy electrode DME, together with the first gate electrode G1, can form a capacitor CST (see [reference]). FIG. 5 In other words, the first gate electrode G1 corresponds to the capacitor CST (see...). FIG. 5 One electrode of the capacitor, and the dummy electrode DME corresponds to the capacitor CST (see [reference]). FIG. 5 The other electrode. The metal layer containing the dummy electrode DME formed on the second insulating layer INS2 can be defined as the second gate layer. In addition to the dummy electrode DME, the second gate layer may also include multiple patterns.

[0118] The third insulating layer INS3 may be positioned on the second insulating layer INS2 to cover the dummy electrode DME. The semiconductor layer SCP4 (or semiconductor patterned region, and hereinafter described as the fourth semiconductor layer SCP4) of the fourth transistor T4 may be positioned on the third insulating layer INS3. The fourth semiconductor layer SCP4 may include an oxide semiconductor comprising a metal oxide. The oxide semiconductor may include crystalline oxide semiconductors or amorphous oxide semiconductors.

[0119] The fourth semiconductor layer SCP4 may include multiple regions classified according to whether the metal oxide is reduced. Regions where the metal oxide is reduced (hereinafter referred to as reduced regions) have a higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as non-reduced regions). Reduced regions may correspond to the source and drain regions of the fourth transistor T4. Non-reduced regions may correspond to the active region (or channel) of the fourth transistor T4.

[0120] The reduction region of the fourth semiconductor layer SCP4 may include a fourth source region S4 and a fourth drain region D4. The fourth channel region A4 may be located between the fourth source region S4 and the fourth drain region D4.

[0121] A fourth insulating layer INS4 can be positioned on the third insulating layer INS3 to cover the fourth semiconductor layer SCP4. The fourth gate electrode G4 of the fourth transistor T4 can be positioned on the fourth insulating layer INS4. The metal layer containing the fourth gate electrode G4 formed on the fourth insulating layer INS4 can be defined as the third gate layer. The third gate layer may also include multiple patterns in addition to the fourth gate electrode G4.

[0122] The fifth insulating layer INS5 can be positioned on the fourth insulating layer INS4 to cover the fourth gate electrode G4. The buffer layer BFL and the first insulating layers INS1 to the fifth insulating layer INS5 may include inorganic layers.

[0123] The connecting electrode CNE can be positioned between the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE can electrically connect the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1, a second connecting electrode CNE2 positioned on the first connecting electrode CNE1, and a third connecting electrode CNE3 positioned on the second connecting electrode CNE2.

[0124] The first connecting electrode CNE1 can be positioned on the fifth insulating layer INS5 and can be connected to the sixth drain region D6 through the first contact hole CH1 defined by the first insulating layer INS1 to the fifth insulating layer INS5. The metal layer containing the first connecting electrode CNE1 formed on the fifth insulating layer INS5 can be defined as the first source / drain layer. The first source / drain layer may include multiple patterns in addition to the first connecting electrode CNE1.

[0125] A sixth insulating layer INS6 can be positioned on the fifth insulating layer INS5 to cover the first connection electrode CNE1. A second connection electrode CNE2 can be positioned on the sixth insulating layer INS6. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a second contact hole CH2 defined by the sixth insulating layer INS6. The metal layer containing the second connection electrode CNE2 formed on the sixth insulating layer INS6 can be defined as a second source / drain layer. The second source / drain layer may include multiple patterns in addition to the second connection electrode CNE2.

[0126] A seventh insulating layer INS7 can be positioned on the sixth insulating layer INS6 to cover the second connection electrode CNE2. A third connection electrode CNE3 can be positioned on the seventh insulating layer INS7. The third connection electrode CNE3 can be connected to the second connection electrode CNE2 through a third contact hole CH3 defined by the seventh insulating layer INS7. The metal layer containing the third connection electrode CNE3 formed on the seventh insulating layer INS7 can be defined as a third source / drain layer. The third source / drain layer may include multiple patterns in addition to the third connection electrode CNE3.

[0127] The eighth insulating layer INS8 may be positioned on the seventh insulating layer INS7 to cover the third connection electrode CNE3. The light-emitting element OLED is positioned on the eighth insulating layer INS8. The sixth insulating layer INS6, the seventh insulating layer INS7, and the eighth insulating layer INS8 may include inorganic or organic layers. According to some embodiments, each of the sixth insulating layer INS6, the seventh insulating layer INS7, and the eighth insulating layer INS8 may include an organic layer.

[0128] An OLED (Optical Display Cell) element may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a light-emitting layer EML. The first electrode AE ​​can be... FIG. 5 The anode AE ​​is shown in the figure, and the second electrode CE can be FIG. 5 The cathode CE is shown in the diagram. The second electrode CE can be positioned on the first electrode AE. A hole control layer HCL and an electron control layer ECL can be disposed between the first electrode AE ​​and the second electrode CE, and a light-emitting layer EML can be positioned between the hole control layer HCL and the electron control layer ECL. The first electrode AE ​​can be positioned on the eighth insulating layer INS8. The first electrode AE ​​can be electrically connected to the third connecting electrode CNE3 through a fourth contact hole CH4 defined in the eighth insulating layer INS8.

[0129] A pixel-defining film (PDL) can be positioned on a first electrode AE ​​and an eighth insulating layer INS8, with a portion of the first electrode AE ​​exposed through the PDL. This portion of the first electrode AE ​​is exposed through a first opening PDL-OP1, which can be defined within the PDL. The first opening PDL-OP1 corresponds to a light-emitting region LEA. The display region DA can include the light-emitting region LEA corresponding to the first opening PDL-OP1 and a non-light-emitting region NLEA adjacent to the light-emitting region LEA.

[0130] The hole control layer (HCL) can be positioned on the first electrode (AE) and the pixel defining film (PDL). The HCL can also be commonly positioned within the light-emitting region (LEA) and the non-light-emitting region (NLEA). The HCL may include a hole transport layer and a hole injection layer.

[0131] The luminescent layer EML can be positioned on the hole control layer HCL. The luminescent layer EML can be positioned in the region corresponding to the first opening PDL-OP1. The luminescent layer EML can include organic and / or inorganic materials. The luminescent layer EML can produce light of any color selected from red, green, and blue.

[0132] The electronic control layer (ECL) can be located on the light-emitting layer (EML) and the hole control layer (HCL). The ECL can also be commonly located within the light-emitting region (LEA) and the non-light-emitting region (NLEA). The ECL may include an electron transport layer and an electron injection layer.

[0133] The second electrode CE can be positioned on the electronic control layer ECL. The second electrode CE can be arranged in a common configuration. FIG. 4 In the pixel PX shown, the second electrode CE can be commonly arranged on the light-emitting layer EML of pixel PX.

[0134] The layer from the buffer layer BFL to the eighth insulating layer INS8 can be defined as the circuit element layer DP-CL. The layer including the light-emitting element OLED can be defined as the display element layer DP-OLED.

[0135] A thin-film encapsulation layer (TFE) can be positioned on the OLED light-emitting element. The TFE can comprise sequentially stacked inorganic, organic, and inorganic layers. The inorganic layer can comprise inorganic materials and can protect the pixel from moisture / oxygen. The organic layer can comprise organic materials and protect the OLED light-emitting element from foreign matter such as dust particles.

[0136] FIG. 7A It is an illustrative representation FIG. 5 The image shows a cross-sectional view of the light-sensing element LRE, the first sensing transistor T1', and the second sensing transistor T2' of the optical sensor SNij. In the following text, for the sake of brevity, the terms "photosensing element LRE," "first sensing transistor T1'," and "second sensing transistor T2'" will be used interchangeably with "photosensing element LRE." FIG. 6 For a detailed description of the same configuration as described in [the previous section], please refer to [the relevant documentation]. FIG. 6 The description.

[0137] Reference FIG. 7A The semiconductor layer SCP1' of the first sensing transistor T1' (hereinafter referred to as the first sensing semiconductor layer SCP1') can be coupled with... FIG. 6 The first semiconductor layer SCP1 is formed using the same process, and the semiconductor layer SCP2' of the second sensing transistor T2' (hereinafter referred to as the second sensing semiconductor layer SCP2') can be... FIG. 6 The fourth semiconductor layer SCP4 is formed using the same process. The first sensing semiconductor layer SCP1' may include a first source region S1', a first drain region D1', and a first channel region A1'. The second sensing semiconductor layer SCP2' may include a second source region S2', a second drain region D2', and a second channel region A2'.

[0138] The first sensing transistor T1' may include a first gate electrode G1'. The first gate electrode G1' may overlap with the first channel region A1'. FIG. 6 The first gate electrode G1 is formed using the same process. In the following text, the first gate electrode G1' is defined as the first sensing gate electrode G1' to distinguish the first gate electrode G1' from the first gate electrode G1.

[0139] The second sensing transistor T2' may include a second gate electrode G2'. The second gate electrode G2' may overlap with the second channel region A2'. FIG. 6 The fourth gate electrode G4 is formed using the same process. In the following text, the second gate electrode G2' is defined as the second sensing gate electrode G2'.

[0140] The stacked structure of the first sensing transistor T1' can be with FIG. 6 The stacked structure of the first transistor T1 shown is the same (or substantially the same). The stacked structure of the second sensing transistor T2' can be the same as... FIG. 6 The stacked structure of the fourth transistor T4 shown is the same (or substantially the same). According to some embodiments, the stacked structure of the third sensing transistor T3' may be the same (or substantially the same) as the stacked structure of the first sensing transistor T1'.

[0141] The connection electrode CNE' may include a first connection electrode CNE1' (or a first sensing connection electrode), a second connection electrode CNE2' (or a second sensing connection electrode), and a third connection electrode CNE3' (or a third sensing connection electrode). The first connection electrode CNE1' may be positioned in conjunction with... FIG. 6 The first connecting electrode CNE1 shown is located on the same layer as the first connecting electrode CNE1, and can be connected to the first sensing gate electrode G1' of the first sensing transistor T1' through the first contact hole CH1'.

[0142] The second connecting electrode CNE2' can be positioned at... FIG. 6 The second connecting electrode CNE2 shown is located on the same layer as the first connecting electrode CNE1', and can be connected to the first connecting electrode CNE1' through the second contact hole CH2' defined in the sixth insulating layer INS6. The third connecting electrode CNE3' can be positioned at the same layer as the first connecting electrode CNE1'. FIG. 7A The third connecting electrode CNE3 shown is located on the same layer as the second connecting electrode CNE2' and can be connected to the second connecting electrode CNE2' through the third contact hole CH3'. The first electrode AE' can be connected to the third connecting electrode CNE3' through the fourth contact hole CH4' defined in the eighth insulating layer INS8.

[0143] The first vertical connection line VL1 can be positioned on the sixth insulating layer INS6. The first vertical connection line VL1 can be positioned on the same layer as the second connection electrode CNE2' and can be formed using the same process. The first horizontal connection line HL1 can be positioned on the fifth insulating layer INS5. The first horizontal connection line HL1 can be positioned on the same layer as the first connection electrode CNE1' and can be formed using the same process. The first vertical connection line VL1 can be connected to the first horizontal connection line HL1 through a first through-hole CNT1 passing through the sixth insulating layer INS6.

[0144] The first vertical connecting line VL1 and the first horizontal connecting line HL1 can be arranged on different layers. However, the layers on which the first vertical connecting line VL1 and the first horizontal connecting line HL1 are arranged are not limited to... FIG. 5 The diagram is shown and can be changed as needed.

[0145] For example, the first vertical connection line VL1 can be positioned on the seventh insulating layer INS7 and formed in the same process as the third connection electrode CNE3'. The first horizontal connection line HL1 can be positioned on the fourth insulating layer INS4 and formed in the same process as the second sensing gate electrode G2'. The first vertical connection line VL1 can be connected to the first horizontal connection line HL1 through vias passing through the fifth insulating layer INS5, the sixth insulating layer INS6, and the seventh insulating layer INS7.

[0146] Here, the first vertical connection line VL1 and the first horizontal connection line HL1 can be transmitted to the pixel driving circuit PC (see...). FIG. 5 The first vertical connection line VL1 and the first horizontal connection line HL1 can be used to transmit the first initialization voltage VINT (see [reference]). FIG. 5 The first initialization line VIL1 (see) FIG. 10 to FIG. 15 (This will be referred to later.) FIG. 7A This will be described.

[0147] The first vertical connecting line VL1 and the first horizontal connecting line HL1 are in FIG. 10 The image shows a similar shape, but the connecting lines can extend in different directions. See below for reference. FIG. 7A This will be described.

[0148] The readout line RX may include a first readout portion RX-1 and a second readout portion RX-2. The readout line RX may extend in the same direction as the first vertical connection line VL1. The first readout portion RX-1 may be positioned on the sixth insulating layer INS6 and may be formed using the same process as the second connection electrode CNE2'. The second readout portion RX-2 may be positioned on the seventh insulating layer INS7 and may be formed using the same process as the third connection electrode CNE3'.

[0149] The first readout section RX-1 can be connected to the second readout section RX-2 via a through-hole CNT-RX passing through the seventh insulating layer INS7. FIG. 7A The diagram shows a cross-section of the readout line RX comprising two layers connected to each other. However, the shape of the readout line RX is not limited to this. For example, the readout line RX can have a single-layer shape positioned on a sixth insulating layer INS6.

[0150] The second vertical connection line VL2 can be positioned on the seventh insulating layer INS7. The second vertical connection line VL2 can be positioned on the same layer as the third connecting electrode CNE3' and can be formed using the same process. The second horizontal connection line HL2 can be positioned on the fifth insulating layer INS5. The second horizontal connection line HL2 can be positioned on the same layer as the first connecting electrode CNE1' and can be formed using the same process. The second vertical connection line VL2 can be connected to the second horizontal connection line HL2 through a second through-hole CNT2 passing through the sixth insulating layer INS6 and the seventh insulating layer INS7.

[0151] The second vertical connecting line VL2 and the second horizontal connecting line HL2 can be positioned on different layers. However, the layers on which the second vertical connecting line VL2 and the second horizontal connecting line HL2 are arranged are not limited to... FIG. 5 The diagram is shown and can be changed as needed.

[0152] For example, the second vertical connection line VL2 can be positioned on the sixth insulating layer INS6 and formed in the same process as the second connection electrode CNE2'. The second horizontal connection line HL2 can be positioned on the fourth insulating layer INS4 and formed in the same process as the second sensing gate electrode G2'. The second vertical connection line VL2 can be connected to the second horizontal connection line HL2 through vias passing through the fifth insulating layer INS5 and the sixth insulating layer INS6.

[0153] Here, the second vertical connecting line VL2 and the second horizontal connecting line HL2 can be used as FIG. 5 Transmission reset voltage VRST (see FIG. 5 The reset line VRL (see) FIG. 10 to FIG. 15 (This will be referred to later.) FIG. 7AThis will be described.

[0154] The second vertical connecting line VL2 and the second horizontal connecting line HL2 are in FIG. 10 The image shows a similar shape, but the connecting lines can extend in different directions. See below for reference. FIG. 6 This will be described.

[0155] On a plane (or in a plan view), the readout line RX can be positioned between the first vertical connecting line VL1 and the second vertical connecting line VL2. The readout line RX can be positioned closer to the center of the optical receiving region LRA than the first vertical connecting line VL1 and the second vertical connecting line VL2.

[0156] Reference FIG. 5 The display area DA may include a light-receiving area LRA corresponding to the optical sensor SNij and a non-emitting area NLEA adjacent to the light-receiving area LRA. The non-emitting area NLEA may be... FIG. 5 The non-luminescent region NLEA is shown in the figure.

[0157] The photosensitive element LRE may include a first electrode AE', a second electrode CE', a hole control layer HCL', an electron control layer ECL', and a photoelectric conversion layer OPD. The first electrode AE' may be... FIG. 6 The anode AE' shown in the figure, and the second electrode CE' can be FIG. 6 The cathode CE' is shown in the diagram. A portion of the first electrode AE' is exposed through a second opening PDL-OP2, which can be defined within a pixel-defining film PDL. The light-receiving region LRA corresponds to the second opening PDL-OP2.

[0158] First electrode AE' and FIG. 7A The first electrode AE ​​shown is formed using the same process. The second electrode CE', hole control layer HCL', and electron control layer ECL' can be formed with... FIG. 6 The second electrode CE, hole control layer HCL, and electron control layer ECL shown in the figure have an integral shape. FIG. 7A The second electrode CE' and FIG. 6 The second electrode CE can be a different region of the common electrode. The common electrode can be deposited with an open mask to have a monolithic shape. FIG. 7A Hole control layer HCL' and FIG. 6 The hole control layer (HCL) can also be different regions of a common hole control layer, and FIG. 7B Electronic control layer ECL' and FIG. 5 The Electronic Control Layer (ECL) can also be different regions of the common electronic control layer.

[0159] FIG. 6 It is an illustrative representationFIG. 7A The image shows a cross-sectional view of the light-sensing element LRE, the first sensing transistor T1', and the second sensing transistor T2' of the optical sensor SNij. For simplicity, the image is shown with... FIG. 6 and FIG. 7A For a detailed description of the same configuration as described in [the previous section], please refer to [the relevant documentation]. FIG. 7B and FIG. 7A The description. FIG. 7B It is an illustrative representation of the relationship with FIG. 7B The cross-section of the optical sensor SNij is shown in the view of the cross-section of the different optical sensors SNij.

[0160] Reference FIG. 5 The third vertical connection line VL3 can be positioned on the seventh insulating layer INS7. The third vertical connection line VL3 can be positioned on the same layer as the third connection electrode CNE3' and can be formed using the same process. The third horizontal connection line HL3 can be positioned on the fourth insulating layer INS4. The third horizontal connection line HL3 can be positioned on the same layer as the second sensing gate electrode G2' and can be formed using the same process. The third vertical connection line VL3 can be connected to the third horizontal connection line HL3 through a third via CNT3 passing through the fifth insulating layer INS5, the sixth insulating layer INS6, and the seventh insulating layer INS7.

[0161] The third vertical connecting line VL3 and the third horizontal connecting line HL3 can be arranged on different layers. However, the layers on which the third vertical connecting line VL3 and the third horizontal connecting line HL3 are arranged are not limited to... FIG. 5 The diagram is shown and can be changed as needed.

[0162] For example, the third vertical connection line VL3 can be positioned on the sixth insulating layer INS6 and formed in the same process as the second connection electrode CNE2'. The third horizontal connection line HL3 can be positioned on the fifth insulating layer INS5 and formed in the same process as the first connection electrode CNE1'. The third vertical connection line VL3 can be connected to the third horizontal connection line HL3 through a through-hole passing through the sixth insulating layer INS6.

[0163] Here, the third vertical connection line VL3 and the third horizontal connection line HL3 can be connected to the pixel driving circuit PC (see...). FIG. 5 The DC signal is transmitted. For example, the third vertical connection line VL3 and the third horizontal connection line HL3 can be used to transmit the second initialization voltage AINT (see...). FIG. 10 to FIG. 15 The second initialization line VIL2 (see) FIG. 7B (This will be referred to later.) FIG. 10 This will be described.

[0164] The third vertical connecting line VL3 and the third horizontal connecting line HL3 are in FIG. 5 The image shows a similar shape, but the connecting lines can extend in different directions. See below for reference. FIG. 5 This will be described.

[0165] The fourth vertical connection line VL4 can be positioned on the seventh insulating layer INS7. The fourth vertical connection line VL4 can be positioned on the same layer as the third connecting electrode CNE3' and can be formed using the same process. The fourth horizontal connection line HL4 can be positioned on the fifth insulating layer INS5. The fourth horizontal connection line HL4 can be positioned on the same layer as the first connecting electrode CNE1' and can be formed using the same process. The fourth vertical connection line VL4 can be connected to the fourth horizontal connection line HL4 through a fourth through-hole CNT4 passing through the sixth insulating layer INS6 and the seventh insulating layer INS7.

[0166] The fourth vertical connecting line VL4 and the fourth horizontal connecting line HL4 can be arranged on different layers. However, the layers on which the fourth vertical connecting line VL4 and the fourth horizontal connecting line HL4 are arranged are not limited to... FIG. 10 to FIG. 15 The diagram is shown and can be changed as needed.

[0167] For example, the fourth vertical connection line VL4 can be positioned on the sixth insulating layer INS6 and formed in the same process as the second connection electrode CNE2'. The fourth horizontal connection line HL4 can be positioned on the fourth insulating layer INS4 and can be formed in the same process as the second sensing gate electrode G2'. The second vertical connection line VL2 can be connected to the second horizontal connection line HL2 through vias passing through the fifth insulating layer INS5 and the sixth insulating layer INS6.

[0168] Here, the fourth vertical connection line VL4 and the fourth horizontal connection line HL4 can be used to transmit the second drive voltage ELVSS (see [link]). FIG. 7B The second power line PL2 (see) FIG. 10 (This will be referred to later.) FIG. 8 This will be described.

[0169] The fourth vertical connecting line VL4 and the fourth horizontal connecting line HL4 are in FIG. 4 The image shows a similar shape, but the connecting lines can extend in different directions. See below for reference. FIG. 5 This will be described.

[0170] FIG. 8 It shows the arrangement in FIG. 8 The OLED light-emitting element in a portion of the display area DA shown in the figure (see FIG. 6A view of the arrangement of the light sensing element LRE in a plane (or in a plan view).

[0171] FIG. 6 A separate illustration shows a unit region RPU arranged repeatedly in the display area DA. At least one pixel PX1, PX2, PX3 or PX4 and an optical sensor SN are arranged to correspond to the unit region RPU. A combination of pixels PX1, PX2, PX3 and PX4 corresponding to a unit region RPU can be defined as a unit pixel PXU.

[0172] According to some embodiments, a unit pixel PXU includes a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. However, the number of pixels in the unit pixel PXU can be varied. The first pixel PX1 may include a first light-emitting element OLED-R and a first pixel driving circuit PC1 electrically connected to the first light-emitting element OLED-R; the second pixel PX2 may include a (2-1) light-emitting element OLED-G1 and a second pixel driving circuit PC2 electrically connected to the (2-1) light-emitting element OLED-G1; the third pixel PX3 may include a third light-emitting element OLED-B and a third pixel driving circuit PC3 electrically connected to the third light-emitting element OLED-B; and the fourth pixel PX4 may include a (2-2) light-emitting element OLED-G2 and a fourth pixel driving circuit PC4 electrically connected to the (2-2) light-emitting element OLED-G2.

[0173] FIG. 7A An optical sensor SN corresponding to a unit pixel PXU is shown, but multiple optical sensor SNs corresponding to a unit pixel PXU can be provided as needed. The optical sensor SN may include a light sensing element LRE and a sensor driving circuit SNC electrically connected to the light sensing element LRE.

[0174] The first light-emitting element OLED-R, the (2-1)th light-emitting element OLED-G1, the third light-emitting element OLED-B, and the (2-2)th light-emitting element OLED-G2 of the unit pixel PXU, along with the photosensitive element LRE, can be arranged in any manner (such as...) within each of the unit regions RPU. Arrangement (such as stripe arrangement, etc.). In the following text, the light-emitting elements OLED-R, OLED-G1, OLED-B, and OLED-G2 corresponding to the unit pixel PXU are defined as unit light-emitting elements UO. The arrangement state of the unit light-emitting elements UO and the photosensitive elements LRE in the unit region RPU can be the same.

[0175] The first light-emitting element OLED-R generates a first color of light (e.g., red light), the (2-1) light-emitting elements OLED-G1 and (2-2) light-emitting elements OLED-G2 generate a second color of light (e.g., green light), and the third light-emitting element OLED-B generates a third color of light (e.g., blue light). The emitting area of ​​the third light-emitting element OLED-B can be the largest, and the emitting areas of the (2-1) light-emitting elements OLED-G1 and (2-2) light-emitting elements OLED-G2 can be the smallest.

[0176] According to some embodiments, the first light-emitting element OLED-R and the third light-emitting element OLED-B can be arranged on the same line (e.g., in the same row), and the first light-emitting element OLED-R and the third light-emitting element OLED-B can be spaced apart from each other in the second direction DR2. The photosensitive element LRE can be positioned between the first light-emitting element OLED-R and the third light-emitting element OLED-B in the second direction DR2. The (2-1) light-emitting element OLED-G1 and the (2-2) light-emitting element OLED-G2 are arranged on the same line (e.g., in the same row), but on a line different from the line of the first light-emitting element OLED-R and the third light-emitting element OLED-B (e.g., in a row different from the row of the first light-emitting element OLED-R and the third light-emitting element OLED-B). The (2-1) light-emitting element OLED-G1 can be positioned on one side of the photosensitive element LRE in the first direction DR1. According to some embodiments, the (2-1) light-emitting element OLED-G1 is positioned above the photosensitive element LRE.

[0177] According to some embodiments of this disclosure, the RPU (Remote Processing Unit) can be classified based on the arrangement of the pixel driving circuit PC and the sensor driving circuit SNC. The pixel driving circuit PC may include a first pixel driving circuit PC1, a second pixel driving circuit PC2, a third pixel driving circuit PC3, and a fourth pixel driving circuit PC4. The four pixel driving circuits (e.g., the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4) and one sensor driving circuit SNC can be arranged in each of the RPUs.

[0178] The first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4 can be arranged on the second direction DR2. The sensor driving circuit SNC can be positioned between two adjacent pixel driving circuits among the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4. For example, the sensor driving circuit SNC can be positioned on the second direction DR2 between the second pixel driving circuit PC2 and the third pixel driving circuit PC3. However, the arrangement of the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, the fourth pixel driving circuit PC4, and the sensor driving circuit SNC is not limited to this.

[0179] On a plane (or in a planar diagram), each of the first light-emitting element OLED-R, the (2-1)th light-emitting element OLED-G1, the third light-emitting element OLED-B, and the (2-2)th light-emitting element OLED-G2 may overlap with or not overlap with the corresponding driving circuit among the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4. For example, when FIG. 9 When the third connecting electrode CNE3 has an extended shape in the plane (or in the planar view), the light-emitting element OLED connected to the third connecting electrode CNE3 may not overlap with the corresponding second pixel driving circuit PC2, which is similar to the (2-1) light-emitting element OLED-G1.

[0180] The arrangement of all first pixel driving circuits PC1, second pixel driving circuit PC2, third pixel driving circuit PC3, fourth pixel driving circuit PC4, first light-emitting element OLED-R, (2-1) light-emitting element OLED-G1, third light-emitting element OLED-B and (2-2) light-emitting element OLED-G2 within the cell region RPU has been described, but the embodiments according to this disclosure are not limited thereto.

[0181] According to some embodiments of this disclosure, any one of the four pixel driving circuits (e.g., first pixel driving circuit PC1, second pixel driving circuit PC2, third pixel driving circuit PC3, and fourth pixel driving circuit PC4) arranged in the first unit region of the RPU can be connected to any one of the first light-emitting element OLED-R, the (2-1)th light-emitting element OLED-G1, the third light-emitting element OLED-B, and the (2-2)th light-emitting element OLED-G2 arranged in the second unit region adjacent to the first unit region. For example, when FIG. 4 When the third connecting electrode CNE3 extends further from the first unit region to the second unit region in the plane (or in the plan view), the driving circuit located in the first unit region and the light-emitting element located in the second unit region can constitute a pixel.

[0182] Furthermore, the arrangement of both the sensor driving circuit (SNC) and the light sensing element (LRE) within the cell region (RPU) has been described, but embodiments according to this disclosure are not limited thereto. For example, when FIG. 7A When the third connecting electrode CNE3 extends further from the first unit region to the second unit region in the plane (or in the plan view), the driving circuit located in the first unit region and the photosensitive element located in the second unit region can constitute an optical sensor.

[0183] FIG. 7B It shows through FIG. 9 , FIG. 5 and FIG. 7A The diagram shows the process by which the optical sensor SNij ensures fingerprint information as biometric information.

[0184] Reference FIG. 7B The display device DD may include multiple optical sensors SN. Each of the optical sensors SN can be coupled with... FIG. 5 , FIG. 10 and FIG. 10 The optical sensor SNij shown has the same configuration. The optical sensor SN can sense the fingerprint FNT, which is provided on the display panel DP by the finger FN. The OLED is composed of light-emitting elements of pixels PX (see [link]). FIG. 5 The generated light can be provided to the fingerprint FNT and reflected by it. The fingerprint FNT is defined by valleys and ridges, and the optical reflectivities of the valleys and ridges are different from each other. Multiple optical sensors SN receive the light reflected from the valleys or ridges according to their positions. Information about the fingerprint FNT can be obtained using the information sensed by the multiple optical sensors SN.

[0185] FIG. 5This is a plan view illustrating data line DL, vertical connecting line VL, and horizontal connecting line HL according to some embodiments of the present disclosure.

[0186] Reference FIG. 5 The vertical connecting line VL can extend in the first direction DR1. Multiple vertical connecting lines VL can be provided, and these multiple vertical connecting lines VL can be arranged in the second direction DR2. The two closest vertical connecting lines VL among the multiple vertical connecting lines VL can be spaced apart from each other in the second direction DR2, with one of the readout lines RX located between them.

[0187] Horizontal connectors HL can extend in the second direction DR2. Multiple horizontal connectors HL can be provided, and these multiple horizontal connectors HL can be arranged in the first direction DR1. Vertical connectors VL and horizontal connectors HL can be connected to each other to form a grid shape.

[0188] The readout line RX can be connected to the sensor drive circuit SNC and extend in the first direction DR1. The readout line RX can overlap with the sensor drive circuit SNC. The readout line RX can also not overlap with the pixel drive circuit PC.

[0189] The readout line RX may include a first readout portion RX-1 and a second readout portion RX-2. The first readout portion RX-1 may overlap with the first sensor driving circuit SNC1 and may extend in the first direction DR1. The second readout portion RX-2 may overlap with the second sensor driving circuit SNC2 and may extend in the first direction DR1. Here, the readout line RX may be the j-th readout line RXj (see...). FIG. 5 ).

[0190] Data lines DL can be connected to the pixel driving circuit PC and extend in the first direction DR1. Data lines DL may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. The first data line DL1 and the third data line DL3 may overlap with the second pixel driving circuit PC2, and the second data line DL2 and the fourth data line DL4 may overlap with the third pixel driving circuit PC3. The first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 may be spaced apart from each other and may be arranged in the second direction DR2. Here, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 are illustratively shown as lines of the proximity sensor driving circuit SNC among multiple data lines DL, and the number of data lines DL is not limited to this.

[0191] Here, data line DL can be the j-th data line DLj (see...) FIG. 5 ).

[0192] The vertical connecting line VL may include a first vertical connecting line VL1, a second vertical connecting line VL2, a third vertical connecting line VL3, and a fourth vertical connecting line VL4. These three vertical connecting lines can be arranged in the second direction DR2. The two closest vertical connecting lines among VL1, VL2, VL3, and VL4 can be spaced apart from each other in the second direction DR2, and one of the readout lines RX lies between them.

[0193] The first vertical connecting line VL1 can be positioned to the left of the first readout portion RX-1 and extend in the first direction DR1, and the second vertical connecting line VL2 can be positioned to the right of the first readout portion RX-1 and extend in the first direction DR1. The first vertical connecting line VL1 can overlap with the first sensor driving circuit SNC1, and the second vertical connecting line VL2 can overlap with the first sensor driving circuit SNC1. The first readout portion RX-1 can overlap with the first sensor driving circuit SNC1.

[0194] The first vertical connecting line VL1 can be positioned in the second direction DR2 between the first data line DL1 and the first readout portion RX-1. In the plane (or in a plan view), the first vertical connecting line VL1 can be positioned closer to the first readout portion RX-1 than the first data line DL1. A first DC signal can be transmitted to the first vertical connecting line VL1.

[0195] Here, the first DC signal can be a signal transmitted to the pixel driving circuit PC. For example, the first DC signal can be the first initialization voltage VINT (see...). FIG. 5 ), second initialization voltage AINT (see FIG. 5 ) and the second drive voltage ELVSS (see FIG. 1 One of them. The first DC signal can be transmitted to the pixel drive circuit PC through the first horizontal connection line HL1 connected to the first vertical connection line VL1.

[0196] The first vertical connection line VL1 can be electrically connected to the pixel driver circuit PC to transmit the first DC signal. Because the first DC signal transmitted to the pixel driver circuit PC is transmitted to the first vertical connection line VL1, a separate vertical wiring is not required in the pixel driver circuit PC. For example, when the first DC signal is the first initialization voltage VINT (see... FIG. 5 When ), it is not necessary to use the first initialization voltage VINT (see FIG. 5The data is transmitted via separate vertical wiring to the pixel drive circuit PC. Therefore, even when adding a display device DD (see...) FIG. 5 When the resolution is low, the difficulty of integrated wiring can also be reduced.

[0197] The first vertical connecting line VL1 can be closer to the center of the first sensor driving circuit SNC1 than the first data line DL1. The first vertical connecting line VL1 can be positioned on the second direction DR2 between the first data line DL1 and the first readout portion RX-1 to prevent or reduce the influence of the first data line DL1 on the sensing signal RS flowing through the first readout portion RX-1 (see...). FIG. 5 For example, even at the data voltage VD (see...) FIG. 5 When the pulse signal is applied to the first data line DL1, the data voltage VD can also be shielded by the first DC signal flowing through the first vertical connection line VL1, and therefore can remain unaffected by the sensing signal RS of the first readout section RX-1 (see...). FIG. 5 In this way, the first vertical connection line VL1 can prevent or reduce the coupling between the first data line DL1 connected to the pixel drive circuit PC and the first readout portion RX-1 connected to the sensor drive circuit SNC.

[0198] The second vertical connection line VL2 can be positioned on the second direction DR2 between the second data line DL2 and the first readout portion RX-1. The second vertical connection line VL2 can be electrically connected to the first sensor drive circuit SNC1 and can extend on the first direction DR1. In the plane (or in a plan view), the second vertical connection line VL2 can be positioned closer to the first readout portion RX-1 than the second data line DL2. A second DC signal can be transmitted to the second vertical connection line VL2.

[0199] The second DC signal can be a signal with a potential different from that of the first DC signal described above.

[0200] Here, the second DC signal can be a signal transmitted to the sensor drive circuit SNC. For example, the second DC signal can be the reset voltage VRST (see [link to relevant documentation]). FIG. 5 The second DC signal can be transmitted to the first sensor drive circuit SNC1 via the second vertical connection line VL2. That is, the second vertical connection line VL2 can be used as the transmission reset voltage VRST through which the second DC signal is transmitted (see [reference]). FIG. 5 The reset line VRL (see) FIG. 5 ).

[0201] The second vertical connecting line VL2 can be closer to the center of the first sensor driving circuit SNC1 than the second data line DL2. The second vertical connecting line VL2 can be positioned on the second direction DR2 between the second data line DL2 and the first readout portion RX-1 to prevent or reduce the influence of the second data line DL2 on the sensing signal RS flowing through the first readout portion RX-1 (see...). FIG. 5 For example, even at the data voltage VD (see...) FIG. 5 When the pulse signal is applied to the second data line DL2, the data voltage VD can also be shielded by the second DC signal flowing through the second vertical connection line VL2, and therefore can remain unaffected by the sensing signal RS of the first readout section RX-1 (see...). FIG. 5 In this way, the second vertical connection line VL2 can prevent or reduce the coupling between the second data line DL2 connected to the pixel drive circuit PC and the first readout portion RX-1 connected to the sensor drive circuit SNC.

[0202] The first readout section RX-1 can be positioned between the closest first vertical connecting line VL1 and the second vertical connecting line VL2 within the vertical connecting lines VL. Therefore, the first readout section RX-1 can minimize the influence of the first data line DL1 and the second data line DL2 located outside the first vertical connecting line VL1 and the second vertical connecting line VL2. The first vertical connecting line VL1 and the second vertical connecting line VL2 can be used as shielding wiring.

[0203] The third vertical connecting line VL3 can be positioned to the left of the second readout portion RX-2 and extend along the first direction DR1, and the fourth vertical connecting line VL4 can be positioned to the right of the second readout portion RX-2 and extend along the first direction DR1. The third vertical connecting line VL3 can overlap with the second sensor driving circuit SNC2, and the fourth vertical connecting line VL4 can overlap with the second sensor driving circuit SNC2. The second readout portion RX-2 can overlap with the second sensor driving circuit SNC2.

[0204] The third vertical connection line VL3 can be positioned on the second direction DR2 between the third data line DL3 and the second readout portion RX-2. In the plane (or in a plan view), the third vertical connection line VL3 can be positioned closer to the first readout portion RX-1 than the third data line DL3. A third DC signal can be transmitted to the third vertical connection line VL3. The third DC signal can be a signal with a potential different from the first and second DC signals described above.

[0205] Here, the third DC signal can be a signal transmitted to the pixel driving circuit PC. For example, the third DC signal can be the first initialization voltage VINT (see...). FIG. 1), second initialization voltage AINT (see FIG. 5 ) and the second drive voltage ELVSS (see FIG. 5 One of them. The third DC signal can be transmitted to the pixel drive circuit PC through the third horizontal connection line HL3 connected to the third vertical connection line VL3.

[0206] The third vertical connection line VL3 can be electrically connected to the pixel driver circuit PC to transmit the third DC signal. Because the third DC signal transmitted to the pixel driver circuit PC is transmitted via the third vertical connection line VL3, a separate vertical wiring is not required in the pixel driver circuit PC. For example, when the third DC signal is the second initialization voltage AINT (see... FIG. 5 When ), it is not necessary to use the second initialization voltage AINT (see FIG. 5 The data is transmitted via separate vertical wiring to the pixel drive circuit PC. Therefore, even when adding a display device DD (see...) FIG. 5 When the resolution is low, the difficulty of integrated wiring can also be reduced.

[0207] The third vertical connection line VL3 can be closer to the center of the second sensor drive circuit SNC2 than the third data line DL3. The third vertical connection line VL3 can be positioned on the second direction DR2 between the third data line DL3 and the second readout section RX-2 to prevent or reduce the influence of the third data line DL3 on the sensing signal RS flowing through the second readout section RX-2 (see...). FIG. 5 For example, even at the data voltage VD (see...) FIG. 5 When the pulse signal is applied to the third data line DL3, the data voltage VD can also be shielded by the third DC signal flowing through the third vertical connection line VL3, and therefore can remain unaffected by the sensing signal RS of the second readout section RX-2 (see...). FIG. 5 In this way, the third vertical connection line VL3 can prevent or reduce coupling between the third data line DL3 connected to the pixel drive circuit PC and the second readout section RX-2 connected to the sensor drive circuit SNC.

[0208] The fourth vertical connection line VL4 can be positioned on the second direction DR2 between the fourth data line DL4 and the second readout portion RX-2. In the plane (or in a plan view), the fourth vertical connection line VL4 can be positioned closer to the second readout portion RX-2 than the fourth data line DL4. A fourth DC signal can be transmitted to the fourth vertical connection line VL4. The fourth DC signal can be a signal with a potential different from the potentials of the first, second, and third DC signals described above.

[0209] Here, the fourth DC signal can be a signal transmitted to the pixel driving circuit PC. For example, the fourth DC signal can be the first initialization voltage VINT (see...). FIG. 1 ), second initialization voltage AINT (see FIG. 5 ) and the second drive voltage ELVSS (see FIG. 5 One of them. The fourth DC signal can be transmitted to the pixel drive circuit PC through the fourth horizontal connection line HL4 connected to the fourth vertical connection line VL4.

[0210] The fourth vertical connection line VL4 can be electrically connected to the pixel driver circuit PC to transmit the fourth DC signal. Because the fourth DC signal transmitted to the pixel driver circuit PC is transmitted via the fourth vertical connection line VL4, a separate vertical wiring is not required in the pixel driver circuit PC. For example, when the fourth DC signal is the second initialization voltage AINT (see... FIG. 5 When this is the case, it is not necessary to use the second drive voltage ELVSS (see...). FIG. 10 The data is transmitted via separate vertical wiring to the pixel drive circuit PC. Therefore, even when adding a display device DD (see...) FIG. 7A When the resolution is low, the difficulty of integrated wiring can also be reduced.

[0211] The fourth vertical connection line VL4 can be closer to the center of the second sensor drive circuit SNC2 than the fourth data line DL4. The fourth vertical connection line VL4 can be positioned on the second direction DR2 between the fourth data line DL4 and the second readout section RX-2 to prevent or reduce the influence of the fourth data line DL4 on the sensing signal RS flowing through the second readout section RX-2 (see...). FIG. 7B For example, even at the data voltage VD (see...) FIG. 7A When the pulse signal is applied to the fourth data line DL4, the data voltage VD can also be shielded by the fourth DC signal flowing through the fourth vertical connection line VL4, and therefore can remain unaffected by the sensing signal RS of the second readout section RX-2 (see...). FIG. 7A In this way, the fourth vertical connection line VL4 can prevent or reduce coupling between the fourth data line DL4 connected to the pixel drive circuit PC and the second readout section RX-2 connected to the sensor drive circuit SNC.

[0212] The horizontal connecting line HL may include a first horizontal connecting line HL1, a second horizontal connecting line HL2, a third horizontal connecting line HL3, and a fourth horizontal connecting line HL4. The first horizontal connecting line HL1, the second horizontal connecting line HL2, the third horizontal connecting line HL3, and the fourth horizontal connecting line HL4 may be arranged in the first direction DR1. FIG. 7BThe diagram shows a structure in which the second horizontal connecting line HL2, the third horizontal connecting line HL3, the first horizontal connecting line HL1, and the fourth horizontal connecting line HL4 are arranged in the first direction DR1 in the order of the second horizontal connecting line HL2, the third horizontal connecting line HL3, the first horizontal connecting line HL1, and the fourth horizontal connecting line HL4. However, the arrangement order of the first horizontal connecting line HL1, the second horizontal connecting line HL2, the third horizontal connecting line HL3, and the fourth horizontal connecting line HL4 is not limited to this.

[0213] The first horizontal connection line HL1 can be electrically connected to the pixel driving circuit PC and can extend along the second direction DR2. The first horizontal connection line HL1 can pass through the insulating layer INS1 to INS7 (see...). FIG. 7A and FIG. 7A The first through-holes CNT1 of some insulating layers in the first vertical connection line VL1 are connected to the first horizontal connection line HL1 and the first vertical connection line VL1. The first horizontal connection line HL1 and the first vertical connection line VL1 can be electrically connected to each other to transmit a first DC signal. The first horizontal connection line HL1 and the first vertical connection line VL1 connected to each other can have a grid shape. That is, the first vertical connection line VL1 can be provided as multiple first vertical connection lines VL1, the first horizontal connection line HL1 can be provided as multiple first horizontal connection lines HL1, and the multiple first vertical connection lines VL1 and the multiple first horizontal connection lines HL1 can have a grid shape.

[0214] The first horizontal connecting line HL1 can overlap with the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, the fourth pixel driving circuit PC4, the first sensor driving circuit SNC1, and the second sensor driving circuit SNC2. The first horizontal connecting line HL1 and the first vertical connecting line VL1 can be arranged on different layers and can be electrically connected to each other through a first via CNT1. The first horizontal connecting line HL1 can be electrically connected to the first vertical connecting line VL1 through the first via CNT1 located at the intersection of the first vertical connecting line VL1 and the first horizontal connecting line HL1. The first via CNT1 can overlap with the first sensor driving circuit SNC1. Here, the first via CNT1 can overlap with... FIG. 7B The first through hole CNT1 is the same.

[0215] The second horizontal connecting line HL2 can extend along the second direction DR2. The second horizontal connecting line HL2 can pass through the insulation layers INS1 to INS7 (see...). FIG. 7B and FIG. 7AThe second through-holes CNT2 of some insulating layers are connected to the second vertical connecting line VL2. The second horizontal connecting line HL2 and the second vertical connecting line VL2 can be electrically connected to each other to transmit a second DC signal. The second horizontal connecting line HL2 and the second vertical connecting line VL2 connected to each other can have a grid shape. That is, the second vertical connecting line VL2 can be provided as multiple second vertical connecting lines VL2, the second horizontal connecting line HL2 can be provided as multiple second horizontal connecting lines HL2, and the multiple second vertical connecting lines VL2 and the multiple second horizontal connecting lines HL2 can have a grid shape.

[0216] The second horizontal connection line HL2 can overlap with the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, the fourth pixel driving circuit PC4, the first sensor driving circuit SNC1, and the second sensor driving circuit SNC2. The second horizontal connection line HL2 and the second vertical connection line VL2 can be arranged on different layers and can be electrically connected to each other through the second via CNT2. The second horizontal connection line HL2 can be electrically connected to the second vertical connection line VL2 through the second via CNT2 located at the intersection of the second vertical connection line VL2 and the second horizontal connection line HL2. The second via CNT2 can overlap with the first sensor driving circuit SNC1. Here, the second via CNT2 can be... FIG. 7B The second through-hole CNT2 is the same.

[0217] The third horizontal connection line HL3 can be electrically connected to the pixel drive circuit PC and can extend along the second direction DR2. The third horizontal connection line HL3 can pass through the insulating layers INS1 to INS7 (see...). FIG. 7B and FIG. 10 Some of the insulating layers in the third vias CNT3 are connected to the third vertical connecting line VL3. The third horizontal connecting line HL3 and the third vertical connecting line VL3 can be electrically connected to each other to transmit a third DC signal. The third horizontal connecting line HL3 and the third vertical connecting line VL3 connected to each other can have a grid shape. That is, the third vertical connecting line VL3 can be provided as multiple third vertical connecting lines VL3, the third horizontal connecting line HL3 can be provided as multiple third horizontal connecting lines HL3, and the multiple third vertical connecting lines VL3 and the multiple third horizontal connecting lines HL3 can have a grid shape.

[0218] The third horizontal connection line HL3 can overlap with the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, the fourth pixel driving circuit PC4, the first sensor driving circuit SNC1, and the second sensor driving circuit SNC2. The third horizontal connection line HL3 and the third vertical connection line VL3 can be arranged on different layers and can be electrically connected to each other through a third via CNT3. The third horizontal connection line HL3 can be electrically connected to the third vertical connection line VL3 through a third via CNT3 located at the intersection of the third vertical connection line VL3 and the third horizontal connection line HL3. The third via CNT3 can overlap with the second sensor driving circuit SNC2. Here, the third via CNT3 can be... FIG. 10 The third through hole CNT3 is the same.

[0219] The fourth horizontal connection line HL4 can be electrically connected to the pixel drive circuit PC and can extend along the second direction DR2. The fourth horizontal connection line HL4 can pass through the insulating layers INS1 to INS7 (see...). FIG. 11 and FIG. 10 The fourth through-hole CNT4 of some insulating layers in the circuit is connected to the fourth vertical connection line VL4. The fourth horizontal connection line HL4 and the fourth vertical connection line VL4 can be electrically connected to each other to transmit a fourth DC signal. The fourth horizontal connection line HL4 and the fourth vertical connection line VL4 connected to each other can have a grid shape. That is, the fourth vertical connection line VL4 can be provided as multiple fourth vertical connection lines VL4, the fourth horizontal connection line HL4 can be provided as multiple fourth horizontal connection lines HL4, and the multiple fourth vertical connection lines VL4 and the multiple fourth horizontal connection lines HL4 can have a grid shape.

[0220] The fourth horizontal connection line HL4 can overlap with the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4, as well as the first sensor driving circuit SNC1 and the second sensor driving circuit SNC2. The fourth horizontal connection line HL4 and the fourth vertical connection line VL4 can be arranged on different layers and can be electrically connected to each other through the fourth via CNT4. The fourth horizontal connection line HL4 can be electrically connected to the fourth vertical connection line VL4 through the fourth via CNT4 located at the intersection of the fourth vertical connection line VL4 and the fourth horizontal connection line HL4. The fourth via CNT4 can overlap with the second sensor driving circuit SNC2. Here, the fourth via CNT4 can be... FIG. 11 The fourth through hole, CNT4, is the same.

[0221] FIG. 12 to FIG. 15The arrangement of the first contact hole CH1, the second contact hole CH2, the third contact hole CH3 and the fourth contact hole CH4, the first vertical connecting line VL1, the second vertical connecting line VL2, the third vertical connecting line VL3 and the fourth vertical connecting line VL4, and the first horizontal connecting line HL1, the second horizontal connecting line HL2, the third horizontal connecting line HL3 and the fourth horizontal connecting line HL4 shown is not limited to the following. FIG. 12 The arrangement structure is shown in the figure.

[0222] FIG. 7A yes FIG. 7B A magnified plan view of region AA'.

[0223] Reference FIG. 12 In a plan view (or planar diagram), the first vertical connecting line VL1 can be positioned close to the first readout portion RX-1, relative to the first data line DL1. In a plan view (or planar diagram), the second vertical connecting line VL2 can be positioned close to the first readout portion RX-1, relative to the second data line DL2. In a plan view (or planar diagram), the first vertical connecting line VL1 and the second vertical connecting line VL2 can surround the first readout portion RX-1.

[0224] Because the DC signal flows through the first vertical connection line VL1 and the second vertical connection line VL2, the influence of the first data line DL1 and the second data line DL2 on the first readout section RX-1 can be prevented or reduced. The first vertical connection line VL1 can prevent or reduce the influence of the data signal transmitted to the first data line DL1, which is located to the left of the first readout section RX-1, on the sensing signal transmitted to the first readout section RX-1. The second vertical connection line VL2 can prevent or reduce the influence of the data signal transmitted to the second data line DL2, which is located to the right of the first readout section RX-1, on the sensing signal transmitted to the first readout section RX-1.

[0225] FIG. 7B This is a plan view illustrating the stacked structure of data lines, vertical connecting lines, and horizontal connecting lines according to some embodiments of the present disclosure.

[0226] FIG. 15 This shows the location of the fourth insulating layer INS4 (see...). FIG. 13 and FIG. 7A The third horizontal connection line HL3 in the third gate layer GPT on the ) is... That is, FIG. 7B The third horizontal connection line HL3 shown can be connected to the second gate electrode G2' (see reference). FIG. 13 They are positioned on the same layer and formed using the same process. The third horizontal connector HL3 can extend on the second direction DR2 and can be connected to the third vertical connector VL3 through the third through-hole CNT3 (see...). FIG. 7AThe third through-hole CNT3 can overlap with the second sensor drive circuit SNC2.

[0227] The third horizontal connection line HL3 can be electrically connected to the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4. A second initialization voltage AINT can be applied to the third horizontal connection line HL3. The second initialization voltage AINT applied to the third horizontal connection line HL3 can be transmitted to the third vertical connection line VL3 and the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4.

[0228] FIG. 7B The arrangement on the fifth insulating layer INS5 is shown (see FIG. 7A and FIG. 7B The first horizontal connecting line HL1, the second horizontal connecting line HL2, and the fourth horizontal connecting line HL4 in the first set of conductive patterns CNP1 on the surface. That is to say... FIG. 14 The first horizontal connector HL1, the second horizontal connector HL2, and the fourth horizontal connector HL4 shown can be connected with... FIG. 14 and FIG. 15 The first connecting electrode CNE1' (see FIG. 15 and FIG. 15 They are arranged on the same layer and formed by the same process. In a plane (or in a plan view), the first horizontal connecting line HL1, the second horizontal connecting line HL2, and the fourth horizontal connecting line HL4 may not overlap each other.

[0229] The first horizontal connecting line HL1, the second horizontal connecting line HL2, and the fourth horizontal connecting line HL4 can extend in the second direction DR2. Each of the first horizontal connecting line HL1 and the fourth horizontal connecting line HL4 can be electrically connected to the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4. The second horizontal connecting line HL2 can be electrically connected to the sensor driving circuit SNC.

[0230] The first horizontal connecting line HL1 can be connected to the first vertical connecting line VL1 through the first through hole CNT1 (see...). FIG. 14 The first via CNT1 can overlap with the first sensor drive circuit SNC1. A first initialization voltage VINT can be applied to the first horizontal connection line HL1. The first initialization voltage VINT applied to the first horizontal connection line HL1 can be transmitted to the first vertical connection line VL1 (see...). FIG. 7A (and the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3 and the fourth pixel driving circuit PC4.)

[0231] The second horizontal connecting line HL2 can be connected to the second vertical connecting line VL2 through the second through-hole CNT2 (see...). FIG. 14 The second via CNT2 can overlap with the first sensor drive circuit SNC1. A reset voltage VRST can be applied to the second horizontal connection line HL2. The reset voltage VRST applied to the second horizontal connection line HL2 can be transmitted to the second vertical connection line VL2 and the first sensor drive circuit SNC1.

[0232] The fourth horizontal connector HL4 can be connected to the fourth vertical connector VL4 via the fourth through-hole CNT4 (see...). FIG. 7A The fourth via CNT4 can overlap with the second sensor drive circuit SNC2. The second drive voltage ELVSS can be applied to the fourth horizontal connection line HL4. The second drive voltage ELVSS applied to the fourth horizontal connection line HL4 can be transmitted to the fourth vertical connection line VL4 (see...). FIG. 13 ) and the second sensor drive circuit SNC2.

[0233] FIG. 13 The arrangement on the sixth insulating layer INS6 is shown (see FIG. 15 The first vertical connecting line VL1 and the first readout portion RX-1 in the second set of conductive patterns CNP2 on the image. That is, FIG. 15 The first vertical connecting line VL1 and the first readout section RX-1 shown in the figure can be connected to... FIG. 15 The second connecting electrode CNE2' is arranged in the same layer and can be formed by the same process. In the plane (or in a plan view), the first vertical connecting line VL1 and the first readout portion RX-1 may not overlap each other.

[0234] The first vertical connecting line VL1 and the first readout portion RX-1 can extend along the first direction DR1. The first vertical connecting line VL1 can be electrically connected to the first horizontal connecting line HL1 (see...). FIG. 7A (and the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3 and the fourth pixel driving circuit PC4.)

[0235] The first vertical connecting line VL1 can be connected to the first horizontal connecting line HL1 through the first through hole CNT1 (see...). FIG. 7BThe first via CNT1 can overlap with the first sensor driving circuit SNC1. The first initialization voltage VINT can be transmitted to the first vertical connection line VL1. As described above, the first initialization voltage VINT applied to the first horizontal connection line HL1 can be transmitted to the first vertical connection line VL1 and the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3, and the fourth pixel driving circuit PC4.

[0236] The first readout section RX-1 can be connected to the second readout section RX-2 via the through-hole CNT-RX (see...). FIG. 15 The through-hole CNT-RX can overlap with the sensor drive circuit SNC. The sensing signal RS can be transmitted to the first readout section RX-1. The first readout section RX-1 and the second readout section RX-2 (see...) FIG. 7A It can be electrically connected to the sensor drive circuit SNC.

[0237] FIG. 7B The arrangement on the seventh insulating layer INS7 is shown (see FIG. 7A and FIG. 7B The third set of conductive patterns CNP3 on the image contains the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4, the second readout section RX-2, and the second vertical connecting line VL2, the third vertical connecting line VL3, and the fourth vertical connecting line VL4. In other words, FIG. 14 The first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 shown, the second readout section RX-2, and the second vertical connecting line VL2, the third vertical connecting line VL3, and the fourth vertical connecting line VL4 can be connected to... FIG. 14 and FIG. 15 The third connecting electrode CNE3' (see FIG. 13 and FIG. 12 They are arranged on the same layer and can be formed by the same process. On the plane (or in a plan view), the first data line DL1, the second data line DL2, the third data line DL3 and the fourth data line DL4, the second readout section RX-2, and the second vertical connecting line VL2, the third vertical connecting line VL3 and the fourth vertical connecting line VL4 may not overlap with each other.

[0238] The first data line DL1 can overlap with and be electrically connected to the second pixel driving circuit PC2, and can extend in the first direction DR1. The second data line DL2 can overlap with and be electrically connected to the third pixel driving circuit PC3, and can extend in the first direction DR1. The third data line DL3 can overlap with and be electrically connected to the second pixel driving circuit PC2, and can extend in the first direction DR1. The fourth data line DL4 can overlap with and be electrically connected to the third pixel driving circuit PC3, and can extend in the first direction DR1. The data voltage VD required by the pixel driving circuits PC2 and PC3 can be applied to the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4.

[0239] The second readout section RX-2 can be electrically connected to the first readout section RX-1 via the through-hole CNT-RX (see...). FIG. 12 The sensing signal RS can be transmitted to the second readout section RX-2. The first readout section RX-1 and the second readout section RX-2 (see...) FIG. 13 and FIG. 13 This can form the readout line RX.

[0240] The second vertical connecting line VL2 can be connected to the second horizontal connecting line HL2 through the second through hole CNT2 (see...). FIG. 16 The second via CNT2 can overlap with the first sensor drive circuit SNC1. A reset voltage VRST can be applied to the second vertical connection line VL2. The second vertical connection line VL2 can be electrically connected to the first sensor drive circuit SNC1 to provide the reset voltage VRST to the first sensor drive circuit SNC1.

[0241] The third vertical connecting line VL3 can be connected to the third horizontal connecting line HL3 through the third through-hole CNT3 (see...). FIG. 16 The third via CNT3 can overlap with the second sensor drive circuit SNC2. The second initialization voltage AINT can be transmitted to the third vertical connection line VL3. As described above, it is applied to the third horizontal connection line HL3 (see...). FIG. 10 The second initialization voltage AINT can be transmitted to the third vertical connection line VL3 and the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3 and the fourth pixel driving circuit PC4.

[0242] The fourth vertical connector VL4 can be connected to the fourth horizontal connector HL4 through the fourth through-hole CNT4 (see...). FIG. 10The fourth via CNT4 can overlap with the second sensor drive circuit SNC2. The second drive voltage ELVSS can be transmitted to the fourth vertical connection line VL4. As described above, it is applied to the fourth horizontal connection line HL4 (see above). FIG. 16 The second driving voltage ELVSS can be transmitted to the fourth vertical connection line VL4 and the first pixel driving circuit PC1, the second pixel driving circuit PC2, the third pixel driving circuit PC3 and the fourth pixel driving circuit PC4.

[0243] FIG. 16 This is a plan view illustrating data line DL, vertical connecting line VL, and horizontal connecting line HL according to some embodiments of the present disclosure. ​ In the middle, only the vertical connecting line VL was changed (see...) ​ ) and horizontal connector HL (see ​ The layout is the same as the other configurations, and therefore descriptions of the same configurations will be omitted.

[0244] Reference ​ The horizontal connecting line HL may include a first horizontal connecting line HL1, a second horizontal connecting line HL2, a third horizontal connecting line HL3, and a fourth horizontal connecting line HL4. The first horizontal connecting line HL1, the second horizontal connecting line HL2, the third horizontal connecting line HL3, and the fourth horizontal connecting line HL4 may be arranged in the first direction DR1. According to... ​ The first horizontal connecting line HL1, the second horizontal connecting line HL2, the third horizontal connecting line HL3, and the fourth horizontal connecting line HL4 can be arranged in the display area DA in the order of the third horizontal connecting line HL3, the first horizontal connecting line HL1, the fourth horizontal connecting line HL4, and the second horizontal connecting line HL2 in the opposite direction to the first direction DR1.

[0245] The first vertical connecting line VL1 and the first horizontal connecting line HL1 can be electrically connected through the first through-hole CNT1. The first through-hole CNT1 can overlap with the first sensor driving circuit SNC1. The second vertical connecting line VL2 and the second horizontal connecting line HL2 can be electrically connected through the second through-hole CNT2. The second through-hole CNT2 can overlap with the first sensor driving circuit SNC1. The third vertical connecting line VL3 and the third horizontal connecting line HL3 can be electrically connected through the third through-hole CNT3. The third through-hole CNT3 can overlap with the second sensor driving circuit SNC2. The fourth vertical connecting line VL4 and the fourth horizontal connecting line HL4 can be electrically connected through the fourth through-hole CNT4. The fourth through-hole CNT4 can overlap with the second sensor driving circuit SNC2.

[0246] In the display device according to this disclosure, the vertical connecting line to which the DC signal is applied can be positioned between the data line and the readout line and thus serve as a shielded wiring, preventing or reducing the signal affecting the data line of the readout line.

[0247] Furthermore, the signals transmitted to the pixel driving circuit can be applied to a grid-shaped network of vertical and horizontal connecting lines, eliminating the need for separate wiring in the pixel driving circuit and thus reducing integration complexity.

[0248] Although various aspects of some embodiments of this disclosure have been described above with reference to them, it is to be understood that various modifications and changes can be made to this disclosure by those skilled in the art or those of ordinary skill in the art without departing from the spirit and scope of this disclosure as set forth in the appended claims. Therefore, the technical scope of the embodiments according to this disclosure is not limited to the detailed description in the specification, but should be defined by the appended claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: The substrate layer includes the display area and the non-display area; Circuit element layer, on the substrate layer; and A display element layer is provided on the circuit element layer, and the display element layer includes light-emitting elements and light-receiving elements that overlap with the display area. The circuit element layer includes: Pixel driving circuit, connected to the light-emitting element; The sensor driving circuit is connected to the light receiving element; A readout line is connected to a plurality of said sensor drive circuits, and the readout line extends in a first direction; A first data line is connected to a plurality of said pixel driving circuits, and the first data line extends in the first direction; A first vertical connecting line lies between the first data line and the readout line in a second direction intersecting the first direction, and the first vertical connecting line extends in the first direction and is configured to receive a first DC signal; and An insulating layer is configured to cover the first vertical connecting line and the first data line, and The first DC signal is a signal transmitted to the plurality of pixel driving circuits.

2. The display device according to claim 1, wherein, The circuit element layer also includes: A first horizontal connecting line is electrically connected to a plurality of the pixel driving circuits. The first horizontal connecting line extends in the second direction and is connected to the first vertical connecting line through a first through-hole passing through the insulating layer. The first horizontal connecting line is configured to receive the first DC signal.

3. The display device according to claim 2, wherein, The first vertical connecting line and the first horizontal connecting line are on different layers.

4. The display device according to claim 2, wherein, The first vertical connecting line is provided as multiple first vertical connecting lines. Wherein, the first horizontal connecting line is provided as multiple first horizontal connecting lines, and The plurality of first vertical connecting lines and the plurality of first horizontal connecting lines have a grid shape.

5. The display device according to claim 4, wherein, The readout lines are between the closest first vertical connecting lines among the plurality of first vertical connecting lines.

6. The display device according to claim 1, wherein, The circuit element layer also includes: A second data line is connected to a plurality of the pixel driving circuits, the second data line being spaced apart from the first data line and extending in the first direction; and A second vertical connection line is located between the second data line and the readout line in the second direction, and the second vertical connection line extends in the first direction and is configured to receive a second DC signal.

7. The display device according to claim 6, wherein, The second DC signal is transmitted to multiple sensor drive circuits.

8. The display device according to claim 6, wherein, The circuit element layer also includes: The second horizontal connecting line extends in the second direction and is connected to the second vertical connecting line through a second through-hole passing through the insulating layer, and the second horizontal connecting line is configured to receive the second DC signal.

9. The display device according to claim 8, wherein, The second vertical connecting line and the second horizontal connecting line are on different layers.

10. The display device according to claim 8, wherein, The second vertical connecting line is provided as multiple second vertical connecting lines. The second horizontal connecting line is provided as multiple second horizontal connecting lines, and The plurality of second vertical connecting lines and the plurality of second horizontal connecting lines have a grid shape.

11. The display device according to claim 8, wherein, The readout line is located between the first vertical connecting line and the second vertical connecting line.

12. The display device according to claim 1, wherein, Each of the plurality of sensor driving circuits is located between two adjacent pixel driving circuits in the plurality of pixel driving circuits.

13. The display device according to claim 1, wherein, The first vertical connecting line overlaps with a corresponding one of the plurality of sensor driving circuits.

14. The display device according to claim 6, wherein, The second vertical connecting line overlaps with one of the multiple sensor driving circuits.

15. The display device according to claim 1, wherein, The first vertical connecting line is closer to the center of the corresponding one of the plurality of sensor driving circuits than the first data line.

16. The display device according to claim 1, wherein, The first vertical connecting line is electrically connected to a plurality of the pixel driving circuits.

17. An electronic device, wherein, The electronic device includes a display panel and a window on the display panel. The display panel includes: The substrate layer includes the display area and the non-display area; Circuit element layer, on the substrate layer; and A display element layer is provided on the circuit element layer, and the display element layer includes light-emitting elements and light-receiving elements that overlap with the display area. The circuit element layer includes: Pixel driving circuit, connected to the light-emitting element; The sensor driving circuit is connected to the light receiving element; A readout line is connected to a plurality of said sensor drive circuits, and the readout line extends in a first direction; The first data line and the second data line are each connected to a plurality of the pixel driving circuits. The first data line and the second data line extend in the first direction and are spaced apart from each other in a second direction intersecting the first direction. A corresponding one of the plurality of sensor driving circuits is located between the first data line and the second data line. The first vertical connecting line and the second vertical connecting line are each electrically connected to a plurality of the pixel driving circuits or a plurality of the sensor driving circuits. The first vertical connecting line and the second vertical connecting line are configured to transmit DC signals, and the first vertical connecting line and the second vertical connecting line are spaced apart from each other in the second direction. A corresponding sensor driving circuit is located between the first vertical connecting line and the second vertical connecting line. An insulating layer is configured to cover the first data line and the second data line, as well as the first vertical connecting line and the second vertical connecting line. Among them, compared to the first data line, the first vertical connecting line is closer to the readout line, and Among them, compared to the second data line, the second vertical connecting line is closer to the readout line.

18. The electronic device according to claim 17, wherein, The circuit element layer also includes: A first horizontal connecting line is electrically connected to a plurality of the pixel driving circuits, the first horizontal connecting line extends in the second direction, and the first horizontal connecting line is connected to the first vertical connecting line through a first through-hole passing through the insulating layer; and The second horizontal connecting line is electrically connected to a plurality of the pixel driving circuits, the second horizontal connecting line extends in the second direction, and the second horizontal connecting line is connected to the second vertical connecting line through a second through-hole passing through the insulating layer.

19. The electronic device according to claim 17, wherein, The first vertical connecting line is configured to transmit a first DC signal, and the second vertical connecting line is configured to transmit a second DC signal that is different from the first DC signal.

20. The electronic device according to claim 19, wherein, The first DC signal is a signal transmitted to the plurality of pixel driving circuits, and The second DC signal is a signal transmitted to the multiple sensor drive circuits.

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