Display panel and display device

Abstract

The display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of data lines, a plurality of data outgoing lines, a plurality of electrostatic discharge circuits, at least one first voltage transmission line and at least one second voltage transmission line. The substrate comprises a display area and a first frame area located on one side of the display area in the first direction. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data outgoing lines are located in the first frame area and are connected with the plurality of data lines. The plurality of electrostatic discharge circuits are located in the first frame area and are connected with the plurality of data outgoing lines. The first voltage transmission line and the second voltage transmission line are located in the first frame area and connected with the electrostatic discharge circuits. The first voltage transmission line and the second voltage transmission line are located on different conductive layers.

Description

TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. With the continuous development of display technology, the display device with OLED as the light emitting device and thin film transistor (TFT) for signal control has become the mainstream product in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The present application embodiment provides a display panel and a display device.

[0005] In one aspect, the present application embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead-out lines, a plurality of electrostatic discharge circuits, at least one first voltage transmission line, and at least one second voltage transmission line. The substrate comprises: a display area and a first frame area located on one side of the display area along a first direction. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of data lines are located in the display area and configured to provide data signals to the plurality of sub-pixels. The plurality of data lead-out lines are located in the first frame area and connected with the plurality of data lines. The plurality of electrostatic discharge circuits are located in the first frame area and connected with the plurality of data lead-out lines. The at least one first voltage transmission line is located in the first frame area and connected with the plurality of electrostatic discharge circuits and configured to provide a first voltage signal. The at least one second voltage transmission line is located in the first frame area and connected with the plurality of electrostatic discharge circuits and configured to provide a second voltage signal, wherein the second voltage signal is different from the first voltage signal. The at least one first voltage transmission line and the at least one second voltage transmission line are located in different conductive layers.

[0006] In some example embodiments, the at least one first voltage transmission line is located on a side away from the substrate of the at least one second voltage transmission line; or the at least one second voltage transmission line is located on a side away from the substrate of the at least one first voltage transmission line.

[0007] In some example embodiments, the display panel comprises at least: a first source-drain metal layer and a second source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate. The at least one first voltage transmission line is located on the first source-drain metal layer, and the at least one second voltage transmission line is located on the second source-drain metal layer; or, the at least one second voltage transmission line is located on the first source-drain metal layer, and the at least one first voltage transmission line is located on the second source-drain metal layer.

[0008] In some example embodiments, the display panel comprises at least: a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate, and the third source-drain metal layer is located on a side of the second source-drain metal layer away from the substrate. The at least one first voltage transmission line is located on the first source-drain metal layer or the second source-drain metal layer, and the at least one second voltage transmission line is located on the third source-drain metal layer; or, the at least one second voltage transmission line is located on the first source-drain metal layer or the second source-drain metal layer, and the at least one first voltage transmission line is located on the third source-drain metal layer.

[0009] In some example embodiments, the display panel comprises at least: two first voltage transmission lines and one second voltage transmission line, the two first voltage transmission lines and the second voltage transmission line all extend along a second direction, and the second voltage transmission line is located between the two first voltage transmission lines along a first direction; the second direction intersects the first direction. Or, the display panel comprises at least: two second voltage transmission lines and one first voltage transmission line, the two second voltage transmission lines and the first voltage transmission line all extend along the second direction, and the first voltage transmission line is located between the two second voltage transmission lines along the first direction.

[0010] In some example embodiments, the plurality of electrostatic discharge circuits are arranged in the first direction and the second direction. The plurality of electrostatic discharge circuits are arranged in at least two rows in the first direction, each row of electrostatic discharge circuits comprises a plurality of electrostatic discharge circuits arranged in the second direction; two rows of electrostatic discharge circuits are connected to the same first voltage transmission line or the same second voltage transmission line. Wherein, the data lead connected by the first row of electrostatic discharge circuits and the data lead connected by the second row of electrostatic discharge circuits are located in different conductive layers.

[0011] In some exemplary embodiments, the electrostatic discharge circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first terminal of the first transistor is electrically connected to the second voltage transmission line; the gate and second terminal of the first transistor are electrically connected to the first terminal of the second transistor; the gate and second terminal of the second transistor are electrically connected to the first terminal of the third transistor and the data lead; the gate and second terminal of the third transistor are electrically connected to the first terminal of the fourth transistor; and the second terminal of the fourth transistor is electrically connected to the first voltage transmission line. The arrangement of the first, second, third, and fourth transistors in the first row of the electrostatic discharge circuit along the first direction is opposite to the arrangement of the first, second, third, and fourth transistors in the second row of the electrostatic discharge circuit along the first direction.

[0012] In some exemplary embodiments, the display panel further includes: an organic planarization layer, a first inorganic insulating layer, and a touch-sensitive inorganic insulating layer. The organic planarization layer has an isolation groove surrounding the plurality of electrostatic discharge circuits in the first bezel region. The first inorganic insulating layer is located on the side of the organic planarization layer closest to the substrate. The touch-sensitive inorganic insulating layer is located on the side of the organic planarization layer furthest from the substrate. The touch-sensitive inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

[0013] In some exemplary embodiments, the display panel further includes a touch protection layer. The touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate. The orthographic projection of the touch protection layer onto the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits onto the substrate.

[0014] In some exemplary embodiments, the display panel further includes a touch protection layer and a metal overlay layer. The touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate, and has a cutout area in the first border region. The orthographic projection of the cutout area onto the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits onto the substrate. The metal overlay layer is located on the side of the touch protection layer away from the substrate, and fills the cutout area.

[0015] In some exemplary embodiments, the first border region includes: a first sub-region, a bent region, and a second sub-region arranged sequentially along a first direction away from the display region; the plurality of electrostatic discharge circuits, the at least one first voltage transmission line, and the at least one second voltage transmission line are located in the second sub-region.

[0016] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0017] On the other hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead-out lines, a plurality of electrostatic discharge circuits, and an organic planarization layer. The substrate includes: a display area and a first border region located on one side of the display area along a first direction. The first border region includes: a first sub-region, a bent region, and a second sub-region arranged sequentially along a first direction away from the display area. The plurality of sub-pixels are disposed on one side of the substrate and located in the display area. The plurality of data lines are located in the display area and configured to provide data signals to the plurality of sub-pixels. The plurality of data lead-out lines are located in the first border region and connected to the plurality of data lines. The plurality of electrostatic discharge circuits are located in the first border region and connected to the plurality of data lead-out lines. The organic planarization layer has isolation grooves surrounding the plurality of electrostatic discharge circuits in a second sub-region of the first border region.

[0018] In some exemplary embodiments, the display panel further includes a first inorganic insulating layer and a touch-sensitive inorganic insulating layer. The first inorganic insulating layer is located on the side of the organic planarization layer closest to the substrate; the touch-sensitive inorganic insulating layer is located on the side of the organic planarization layer furthest from the substrate; the touch-sensitive inorganic insulating layer is in contact with the first inorganic insulating layer through the isolation groove.

[0019] In some exemplary embodiments, the display panel further includes a touch protection layer and a metal overlay layer. The touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate, and has a cutout area in a second sub-region of the first bezel area. The orthographic projection of the cutout area onto the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits onto the substrate. The metal overlay layer is located on the side of the touch protection layer away from the substrate, and fills the cutout area.

[0020] The display panel provided in this embodiment reduces the electric field strength between the first and second voltage transmission lines by placing them on different conductive layers, thus improving moisture corrosion and reducing electrochemical corrosion, thereby enhancing the corrosion resistance of the electrostatic discharge circuit. Alternatively, by providing isolation grooves around multiple electrostatic discharge circuits in the organic planarization layer, moisture barrier can be achieved, improving the corrosion of the traces in the electrostatic discharge circuit and thus enhancing its corrosion resistance.

[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0023] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0025] Figure 3A This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0026] Figure 3B This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0027] Figure 3C This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0028] Figure 3D This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0029] Figure 4 This is a partial wiring diagram of the first border region according to at least one embodiment of the present disclosure;

[0030] Figure 5 This is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0031] Figure 6 This is a partial planar schematic diagram of the first border region according to at least one embodiment of the present disclosure;

[0032] Figure 7A for Figure 6 A schematic diagram of a display panel after the first semiconductor layer has been formed;

[0033] Figure 7B for Figure 6 A schematic diagram of the display panel after the second gate metal layer has been formed;

[0034] Figure 7C for Figure 6 A schematic diagram of the display panel after the first source / drain metal layer has been formed;

[0035] Figure 8 for Figure 6 A partial cross-sectional view along the QQ' direction;

[0036] Figure 9 This is another partial planar schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0037] Figure 10 for Figure 9 A schematic diagram of the display panel after the first source / drain metal layer has been formed;

[0038] Figure 11 for Figure 9 A partial cross-sectional view along the RR' direction;

[0039] Figure 12 This is another partial planar schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0040] Figure 13 This is another partial schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0041] Figure 14 for Figure 13 A magnified view of a portion of the central region S1;

[0042] Figure 15 This is a partial cross-sectional schematic diagram of the first border region according to at least one embodiment of the present disclosure;

[0043] Figure 16 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0044] Figure 17 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0045] Figure 18 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0046] Figure 19 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0047] Figure 20 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0048] Figure 21 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0049] Figure 22 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0050] Figure 23 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0051] Figure 24This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0052] Figure 25 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0054] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0056] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0057] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. "Joining" can include "electrical connection," which includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components. Those skilled in the art will understand the meaning of the above terms in this disclosure as appropriate.

[0058] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0059] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0060] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0061] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0062] In this specification, "approximately" and "roughly" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0063] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0064] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0065] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display panel can be a closed polygon including linear edges. The display panel can include a display area AA and a border area BB surrounding the display area AA. For example, the display area AA can include a first display edge (lower display edge) and a second display edge (upper display edge) positioned opposite each other in a first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) positioned opposite each other in a second direction D2. The first and second display edges can be parallel linear edges, and the third and fourth display edges can also be parallel linear edges. Adjacent linear edges can be connected by curved edges (e.g., arc edges).

[0066] In some examples, such as Figure 1As shown, the border area BB may include: a first border area B1 and a fourth border area B4 located on both sides of the display area AA along the first direction D1, and a second border area B2 and a third border area B3 located on both sides of the display area AA along the second direction D2. The first border area B1 may connect to the first display edge, the second border area B2 may connect to the third display edge, the third border area B3 may connect to the fourth display edge, and the fourth border area B4 may connect to the second display edge. The first border area B1 may communicate with the second border area B2 and the third border area B3, and the third border area B4 may communicate with the second border area B2 and the third border area B3. After the first border area B1, the second border area B2, the third border area B3, and the fourth border area B4 are connected, they can surround the display area AA. For example, the first border area B1 may also be called the lower border area of ​​the display panel, the second border area B2 may also be called the left border area of ​​the display panel, the third border area B3 may also be called the right border area of ​​the display panel, and the fourth border area B4 may also be called the upper border area of ​​the display panel. However, this embodiment is not limited in this respect.

[0067] Figure 2 This is a schematic diagram of the first border region according to at least one embodiment of the present disclosure. In some examples, such as... Figure 1 and Figure 2 As shown, the first border region B1 may include: a first sub-region B11, a bent region B12, and a second sub-region B13 arranged sequentially along the side away from the display region AA in the first direction D1. The first sub-region B11 may also be referred to as a first fan-out region. The first sub-region B11 may communicate with the second border region B2 and the third border region B3, and is connected to the display region AA. The bent region B12 may connect the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back side of the display region AA.

[0068] In some examples, such as Figure 2 As shown, the second sub-region B13 of the first border region B1 may include: a second fan-out region B131, a circuit setting region B132, a third fan-out region B133, a first signal access region B134, and a second signal access region B135, sequentially arranged along the direction away from the bending region B12 in the first direction D1. The first border region B1 may be provided with multiple data leads, which can be electrically connected one-to-one with multiple data lines in the display area.

[0069] In some examples, the circuit setup area B132 can be equipped with multiple electrostatic discharge (ESD) circuits, which can be electrically connected to multiple data leads in a one-to-one correspondence. These ESD circuits can be configured to prevent ESD damage to the display panel by eliminating static electricity. The circuit setup area B132 can also be equipped with multiple test circuits, which can be configured to provide test data signals to the data lines of the display area AA.

[0070] In some examples, the first signal access area B134 may be provided with a plurality of first contact pads, which may be configured to connect to an integrated circuit (IC). The second signal access area B135 may be provided with a plurality of second contact pads, which may be configured to bond to an external flexible printed circuit board (FPC). At least one first contact pad in the first signal access area B134 and at least one second contact pad in the second signal access area B135 may be connected by wiring.

[0071] In some examples, such as Figure 1 As shown, the display area AA of the display panel may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and light emission control signals, or may include scan signals, reset control signals, and light emission control signals.

[0072] In some examples, the second direction D2 can be the extension direction of the grid lines GL within the display area AA (e.g., the row direction); the first direction D1 can be the extension direction of the data lines within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0073] In some examples, a pixel unit of the display area AA may include three sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and a third sub-pixel emitting a third color light (e.g., green light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For example, a pixel unit may include four sub-pixels, which may include one sub-pixel emitting red light, one sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0074] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves the product yield.

[0075] In some examples, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0076] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0077] Figure 3A This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 3A The diagram illustrates the structure of a sub-pixel within the display area. In this example, the pixel circuitry includes both low-temperature polysilicon thin-film transistors (LTPTs) and oxide thin-film transistors (OTFTs). The display panel in this example can integrate a touch structure, such as a mutual capacitance touch structure, forming an FMLOC structure.

[0078] In some examples, such as Figure 3A As shown, in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, and the pixel circuit for each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0079] In some examples, Figure 3A The illustration uses an example where each sub-pixel includes a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 can be an oxide thin-film transistor.

[0080] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (also referred to as a second planarization layer) may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can also be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors in the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the sixth insulating layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the seventh insulating layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0081] In some examples, such as Figure 3AAs shown, the first semiconductor layer of the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least: a second electrode 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0082] In some examples, such as Figure 3AAs shown, the first source-drain metal layer of the display area may include at least: a first source 211 and a first drain 212 of a first type transistor 21, and a second source 221 and a second drain 222 of a second type transistor 22. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer may include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 in the pixel circuit through the fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. This example demonstrates the electrical connection between the pixel circuit and the light-emitting element via the first adapter electrode 241.

[0083] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer and the third gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer; and the first power lines of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer of the display area may further include a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate.

[0084] In some examples, such as Figure 3AAs shown, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on an eighth insulating layer 108 and electrically connected to a first transition electrode 241 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0085] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0086] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0087] In some examples, such as Figure 3A As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0088] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0089] In some examples, such as Figure 3AAs shown, in the direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a touch protective layer (TOC) 154, arranged sequentially. The touch buffer layer 150 and the touch interlayer insulating layer 153 can be inorganic insulating layers, and the touch protective layer 154 can be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions can be an integral structure interconnected. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions can be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer 153. However, this embodiment is not limited in this respect. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0090] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0091] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0092] Figure 3B This is another partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 3BAs shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. An eighth insulating layer 108 may be disposed between the second and third source / drain metal layers, and a ninth insulating layer 109 (also referred to as a third planarization layer) may be disposed on the side of the third source / drain metal layer away from the substrate 10. Both the eighth insulating layer 108 and the ninth insulating layer 109 may be organic insulating layers. The third source / drain metal layer may include at least a second transition electrode 242. The second transition electrode 242 may be connected to the first transition electrode 241 located in the second source / drain metal layer through a via formed in the eighth insulating layer 108. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 241 and the second transition electrode 242. For the remaining structure of the display area of ​​the display panel in this example, please refer to [reference needed]. Figure 3A The description of the illustrated embodiment is omitted here.

[0093] Figure 3C This is another partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present disclosure. In some examples, the transistor types of the multiple pixel transistors in the pixel circuit can be the same, for example, they can all be low-temperature polycrystalline silicon thin-film transistors. Figure 3C The illustration takes as an example that each sub-pixel includes a first-type transistor 21 and a capacitor 23.

[0094] In some examples, such as Figure 3C As shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and an eighth insulating layer 108 may be disposed on the side of the second source / drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, while the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the sixth insulating layer 106 may be inorganic insulating layers. The remaining structure of the display area of ​​the display panel in this example can be found in [reference needed]. Figure 3A The description of the illustrated embodiment is omitted here.

[0095] Figure 3D This is another partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 3DAs shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. An eighth insulating layer 108 may be disposed between the second and third source / drain metal layers, and a ninth insulating layer 109 (also referred to as a third planarization layer) may be disposed on the side of the third source / drain metal layer away from the substrate 10. Both the eighth insulating layer 108 and the ninth insulating layer 109 may be organic insulating layers. The third source / drain metal layer may include at least: a second transition electrode 242. The second transition electrode 242 may be connected to the first transition electrode 241 located in the second source / drain metal layer through a via formed in the eighth insulating layer 108. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 241 and the second transition electrode 242. For the remaining structure of the display area of ​​the display panel in this example, please refer to [reference needed]. Figure 3C The description of the illustrated embodiment is omitted here.

[0096] Figure 4 This is a partial wiring diagram of the first border region of at least one embodiment of the present disclosure. Figure 4 The diagram mainly shows the data lead-out lines in the first border area, while the other traces in the first border area are omitted.

[0097] In some examples, such as Figure 4 As shown, the data leads in the first border area may include a first data lead 261 located in the first sub-region B11 and a second data lead 262 located in the second sub-region. Multiple data leads in the first border area can be electrically connected to multiple data lines in the display area in a one-to-one correspondence. Specifically, the multiple first data leads 261 in the first sub-region B11 can be configured to connect to multiple data lines DL in the display area AA in a fan-out routing manner. The multiple first data leads 261 and the multiple data lines DL can be electrically connected in a one-to-one correspondence. For example, the multiple first data leads 261 can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0098] In some examples, the bending region B12 may be provided with multiple data bending connection lines 263. These multiple data bending connection lines 263 may be electrically connected one-to-one with multiple first data leads 261. For example, the multiple data bending connection lines 263 may be located in the second source / drain metal layer. However, this embodiment is not limited to this. In other examples, the multiple data bending connection lines in the bending region may be located in the first source / drain metal layer.

[0099] In some examples, multiple second data leads 262 can extend from the second fan-out region B131 to the third fan-out region B133. The multiple second data leads 262 can be electrically connected to multiple data bend connection lines 263 in a one-to-one correspondence. For example, the multiple second data leads 262 can be alternately arranged in the first gate metal layer and the second gate metal layer. Multiple first data leads 261 and multiple second data leads 262 can be connected via multiple data bend connection lines 263. The multiple second data leads 262 can be connected to multiple electrostatic discharge circuits within the circuit setting region B132 and extend to the first signal access region B134, connecting to the first contact pad within the first signal access region B134. For example, the multiple second data leads 262 can be electrically connected to multiple electrostatic discharge circuits in a one-to-one correspondence.

[0100] Figure 5 This is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, such as... Figure 5 As shown, at least one electrostatic discharge circuit is connected to a data lead SL (e.g., second data lead 262) and configured to release static electricity from the connected data lead SL. An electrostatic discharge circuit may include: a first transistor ST1, a second transistor ST2, a third transistor ST3, and a fourth transistor ST4. The first terminal of the first transistor ST1 is electrically connected to a second voltage transmission line VGL; the gate and second terminal of the first transistor ST1 are electrically connected to the first terminal of the second transistor ST2; the gate and second terminal of the second transistor ST2 are electrically connected to the data lead SL corresponding to the electrostatic discharge circuit; the first terminal of the third transistor ST3 is electrically connected to the data lead SL corresponding to the electrostatic discharge circuit; the gate and second terminal of the third transistor ST3 are electrically connected to the first terminal of the fourth transistor ST4; and the gate and second terminal of the fourth transistor ST4 are electrically connected to the first voltage transmission line VGH. The transistor types of the first transistor ST1, second transistor ST2, third transistor ST3, and fourth transistor ST4 can be the same, for example, all can be P-type transistors or all can be N-type transistors.

[0101] In some examples, the first voltage transmission line VGH can be configured to transmit a first voltage signal, and the second voltage transmission line VGL can be configured to transmit a second voltage signal. The first voltage signal can be greater than the second voltage signal.

[0102] In one example, an electrostatic discharge circuit can be provided to prevent the accumulation of static electricity in the data leads from causing discharge breakdown and damage, thereby releasing the static electricity accumulated in the data leads and protecting the data leads.

[0103] In another example, the electrostatic discharge circuit may include two transistors, each with one terminal connected to its own gate, forming an equivalent diode connection. The signal line to be protected is connected between the two "diodes," and the other two terminals of the two "diodes" are connected to a first voltage transmission line VGH and a second voltage transmission line VGL, respectively. Thus, when a momentary high voltage (e.g., 100V) occurs in the signal line due to the accumulation of positive charge, one of the "diodes" conducts, releasing the positive charge in the signal line; conversely, when a momentary low voltage (e.g., -100V) occurs in the signal line due to the accumulation of negative charge, the other "diode" conducts, releasing the negative charge in the signal line.

[0104] In some implementations, a voltage difference exists between the first and second voltage transmission lines connected to the multiple electrostatic discharge circuits in the second sub-region. Under reliable operation, this area is prone to metal corrosion, leading to display abnormalities. The display panel provided in this embodiment improves the corrosion resistance of the electrostatic discharge circuit by optimizing its configuration.

[0105] Figure 6 This is a partial planar schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 7A for Figure 6 A schematic diagram of a display panel after the first semiconductor layer has been formed. Figure 7B for Figure 6 A schematic diagram of the display panel after the second gate metal layer has been formed. Figure 7C for Figure 6 A schematic diagram of the display panel after the first source / drain metal layer is formed. Figure 8 for Figure 6 A partial cross-sectional view along the QQ' direction.

[0106] In some examples, such as Figure 6 As shown, multiple electrostatic discharge circuits in the second sub-region can be arranged in an array along the first direction D1 and the second direction D2. Multiple electrostatic discharge circuits arranged along the second direction D2 form a row of electrostatic discharge circuits, and multiple electrostatic discharge circuits arranged along the first direction D1 form a column of electrostatic discharge circuits. For example, the circuit arrangement area of ​​the second sub-region can be arranged with two rows and multiple columns of electrostatic discharge circuits. Specifically, the row of electrostatic discharge circuits closer to the bending area is the first row of electrostatic discharge circuits 401, and the row of electrostatic discharge circuits farther from the bending area is the second row of electrostatic discharge circuits 402.

[0107] In some examples, such as Figure 6As shown, the two rows of electrostatic discharge circuits can be connected to the same second voltage transmission line VGL. The first voltage transmission line VGHa connected to the first row of electrostatic discharge circuits 401 can be located on the side of the second voltage transmission line VGL closer to the bending region, and the first voltage transmission line VGHb connected to the second row of electrostatic discharge circuits 402 can be located on the side of the second voltage transmission line VGL away from the bending region. The second voltage transmission line VGL, the first voltage transmission lines VGHa, and VGHb can all extend along the second direction D2, and the second voltage transmission line VGL can be located between the two first voltage transmission lines VGHa and VGHb in the first direction D1.

[0108] In some examples, such as Figure 6 As shown, the arrangement of the four transistors in the first row of electrostatic discharge circuit 401 along the first direction D1 can be the opposite of the arrangement of the four transistors in the second row of electrostatic discharge circuit 402 along the first direction D1. Specifically, the first transistor ST1, the second transistor ST2, the third transistor ST3, and the fourth transistor ST4 of each electrostatic discharge circuit (e.g., electrostatic discharge circuit 40a) in the first row of electrostatic discharge circuit 401 can be arranged sequentially from the second voltage transmission line VGL to the first voltage transmission line VGHa along the first direction D1; the first transistor ST1, the second transistor ST2, the third transistor ST3, and the fourth transistor ST4 of each electrostatic discharge circuit (e.g., electrostatic discharge circuit 40b) in the second row of electrostatic discharge circuit 402 can be arranged sequentially from the second voltage transmission line VGL to the first voltage transmission line VGHb along the first direction D1.

[0109] The structure of the electrostatic discharge circuit will be explained below using the first row of electrostatic discharge circuit 401 as an example.

[0110] In some examples, such as Figure 6 and Figure 7A As shown, the first semiconductor layer in the first frame region may include: active layers of transistors for multiple electrostatic discharge circuits, such as the active layer ST10 of the first transistor ST1, the active layer ST20 of the second transistor ST2, the active layer ST30 of the third transistor ST3, and the active layer ST40 of the fourth transistor ST4 of the electrostatic discharge circuit 40a. The active layers ST10 of the first transistor ST1, ST20 of the second transistor ST2, ST30 of the third transistor ST3, and ST40 of the fourth transistor ST4 of an electrostatic discharge circuit may be an integral structure. For example, the orthogonal projection of this integral structure onto the substrate may be a strip extending along the first direction D1.

[0111] In some examples, such as Figure 6 and Figure 7BAs shown, the first gate metal layer in the first frame region may include: multiple second data leads 262a, and the gates of transistors in multiple electrostatic discharge circuits (e.g., the gate ST11 of the first transistor ST1, the gate ST21 of the second transistor ST2, the gate ST31 of the third transistor ST3, and the gate ST41 of the fourth transistor ST4, including the electrostatic discharge circuit 40a). The gates ST11 of the first transistor ST1, ST21 of the second transistor ST2, ST31 of the third transistor ST3, and ST41 of the fourth transistor ST4 in an electrostatic discharge circuit may all extend along the second direction D2 and be aligned along the first direction D1. The orthogonal projection of the gates ST11 of the first transistor ST1, ST21 of the second transistor ST2, ST31 of the third transistor ST3, and ST41 of the fourth transistor ST4 onto the substrate may be strips extending along the second direction D2.

[0112] In some examples, such as Figure 6 and Figure 7B As shown, the second gate metal layer in the first border region may include multiple second data leads 262b. The multiple second data leads 262a and 262b may extend at least along a first direction D1 and be alternately arranged along a second direction D2. One second data lead 262a and one second data lead 262b may be provided between two adjacent columns of electrostatic discharge circuits.

[0113] In some examples, such as Figure 6 and Figure 7CAs shown, the first source / drain metal layer in the first border region may include: two first voltage transmission lines VGHa and VGHb, and multiple connection electrodes (e.g., a first connection electrode 331, a second connection electrode 332, a third connection electrode 333, a fourth connection electrode 334, and a fifth connection electrode 335). The orthographic projection of the first connection electrode 331, the second connection electrode 332, the fourth connection electrode 334, and the fifth connection electrode 335 onto the substrate may be strip-shaped extending along the first direction D1, and the orthographic projection of the third connection electrode 333 onto the substrate may be approximately L-shaped. Specifically, the first connection electrode 331 can be connected to the gate ST41 and active layer ST40 of the fourth transistor ST4; the second connection electrode 332 can be connected to the gate ST31 and active layer ST30 of the third transistor ST3; the third connection electrode 333 can be connected to the gate ST21 and active layer ST20 of the second transistor ST2, as well as a second data lead 262a (or a second data lead 262b); the fourth connection electrode 334 can be connected to the gate ST11 and active layer ST10 of the first transistor ST1; and the fifth connection electrode 335 can be connected to the active layer ST10 of the first transistor ST1. The first connection electrode 331 connected to the first row of electrostatic discharge circuit 401 and the connected first voltage transmission line VGHa can be an integral structure. The first connection electrode 331 connected to the second row of electrostatic discharge circuit 402 and the connected first voltage transmission line VGHb can be an integral structure.

[0114] In some examples, such as Figure 6 As shown, the second source / drain metal layer in the first frame region may include at least a second voltage transmission line VGL. The second voltage transmission line VGL may extend at least along the second direction D2. The second voltage transmission line VGL may be connected to a plurality of fifth connection electrodes 335 located in the first source / drain metal layer. For example, the length of the second voltage transmission line VGL along the first direction D1 may be greater than the length of the first voltage transmission line VGHa (or VGHb) along the first direction D1.

[0115] In some examples, the film layer of the display area of ​​the display panel is as follows: Figure 3C As shown in the example, Figure 8As shown, within the first border area, a display inorganic insulating layer 301 can be disposed on the side of the first voltage transmission lines VGHa and VGHb located in the first source / drain metal layer near the substrate 10. The display inorganic insulating layer 301 may include, for example, a stacked first insulating layer 101, a second insulating layer 102, and a third insulating layer 103. A sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) are disposed on the side of the first voltage transmission lines VGHa and VGHb located in the first source / drain metal layer away from the substrate 10. An eighth insulating layer 108 (also referred to as a second planarization layer) is disposed on the side of the second voltage transmission line VGL located in the second source / drain metal layer away from the substrate 10. A touch interlayer insulating layer 153 and a touch protection layer 154 are disposed on the side of the eighth insulating layer 108 away from the substrate 10. The orthographic projection of the touch interlayer insulating layer 153 and the touch protection layer 154 onto the substrate 10 can cover the orthographic projection of multiple electrostatic discharge circuits onto the substrate 10.

[0116] This example demonstrates how placing the first voltage transmission line and the second voltage transmission line in different conductive layers—specifically, the first voltage transmission line in the first source / drain metal layer and the second voltage transmission line in the second source / drain metal layer—can reduce the electric field strength between the first and second voltage transmission lines, improve water vapor corrosion, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic discharge circuit.

[0117] Figure 9 This is another partial planar schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 10 for Figure 9 A schematic diagram of the display panel after the first source / drain metal layer is formed. Figure 11 for Figure 9 A partial cross-sectional view along the RR' direction.

[0118] In some examples, such as Figure 9 to Figure 11As shown, multiple electrostatic discharge circuits in the second sub-region are arranged in an array along the first direction D1 and the second direction D2, for example, in two rows and multiple columns. The two rows of electrostatic discharge circuits are connected to the same second voltage transmission line VGL, and each row of electrostatic discharge circuits is connected to a first voltage transmission line. Specifically, the first row of electrostatic discharge circuits 401 is connected to the first voltage transmission line VGHa, and the second row of electrostatic discharge circuits 402 is connected to the first voltage transmission line VGHb. The first voltage transmission lines VGHa and VGHb can be located in the second source / drain metal layer, and the second voltage line VGL can be located in the first source / drain metal layer. The second voltage line VGL and the multiple fifth connection electrodes 335 located in the first source / drain metal layer can be an integral structure. The first voltage line VGHa can be connected to the first connection electrode 331 located in the first source / drain metal layer and connected to the first row of electrostatic discharge circuits 401; the first voltage line VGHb can be connected to the first connection electrode 331 located in the first source / drain metal layer and connected to the second row of electrostatic discharge circuits 402. The remaining structure of the electrostatic discharge circuit in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0119] This example demonstrates how placing the first voltage transmission line and the second voltage transmission line in different conductive layers, with the first voltage transmission line disposed in the second source / drain metal layer and the second voltage transmission line disposed in the first source / drain metal layer, can reduce the electric field strength between the first and second voltage transmission lines, improve water vapor corrosion, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic discharge circuit.

[0120] Figure 12 This is another partial planar schematic diagram of the first border region according to at least one embodiment of the present disclosure. In some examples, such as Figure 12 As shown, the two rows of electrostatic discharge circuits can share a first voltage transmission line VGH. The second voltage transmission line VGLa connected to the first row of electrostatic discharge circuits 401 can be located on the side of the first voltage transmission line VGH closer to the bending region, and the second voltage transmission line VGLb connected to the second row of electrostatic discharge circuits 402 can be located on the side of the first voltage transmission line VGH away from the bending region. The first voltage transmission line VGH, the second voltage transmission lines VGLa and VGLb can all extend along the second direction D2, and the first voltage transmission line VGH can be located between the two second voltage transmission lines VGLa and VGLb in the first direction D1.

[0121] In some examples, such as Figure 12As shown, the arrangement of the four transistors in the first row of electrostatic discharge circuit 401 along the first direction D1 can be the opposite of the arrangement of the four transistors in the second row of electrostatic discharge circuit 402 along the first direction D1. Specifically, the first transistor ST1, the second transistor ST2, the third transistor ST3, and the fourth transistor ST4 of each electrostatic discharge circuit in the first row of electrostatic discharge circuit 401 can be arranged sequentially along the first direction D1 from the second voltage transmission line VGLa to the first voltage transmission line VGH; similarly, the first transistor ST1, the second transistor ST2, the third transistor ST3, and the fourth transistor ST4 of each electrostatic discharge circuit in the second row of electrostatic discharge circuit 402 can be arranged sequentially along the first direction D1 from the second voltage transmission line VGLb to the second voltage transmission line VGH.

[0122] In this example, the first voltage transmission line VGH is located in the second source-drain metal layer, and the two second voltage transmission lines VGLa and VGLb are located in the first source-drain metal layer. This reduces the electric field strength between the first and second voltage transmission lines, improves moisture corrosion, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic discharge circuit. Further descriptions of the display panel in this example can be found in the foregoing embodiments and will not be repeated here. In other examples, the first voltage transmission line VGH may be located in the first source-drain metal layer, and the two second voltage transmission lines VGLa and VGLb may be located in the second source-drain metal layer.

[0123] Figure 13 This is another partial schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 14 for Figure 13 A magnified view of a portion of the central region S1. Figure 15 This is a partial cross-sectional schematic diagram of the first border region according to at least one embodiment of the present disclosure. Figure 15 for Figure 13 A partial cross-sectional view along the PP' direction. Figure 15 Only a portion of the membrane layer is shown in the diagram. Figure 13 The diagram mainly shows the data lead-out lines in the first border area, while the other traces in the first border area are omitted.

[0124] In some examples, such as Figure 13 to Figure 15 As shown, the organic planar layer of the first border region may have isolation recesses 50 surrounding multiple electrostatic discharge circuits. For example, the isolation recesses 50 may surround the circuit region B132. For example, the orthographic projection of the isolation recesses 50 onto the substrate may be a rectangular ring. In other examples, the orthographic projection of the isolation recesses 50 onto the substrate may be other shapes such as a circular ring or an elliptical ring.

[0125] The film layer of the display area of ​​the display panel, such as Figure 3C For example,Figure 15 As shown, the organic planarization layer in the first border region may include: a stacked seventh insulating layer 107 and an eighth insulating layer 108. The organic planarization layer in the first border region may include: a first flat portion and a second flat portion separated by an isolation groove 50. The first flat portion may be the portion surrounded by the isolation groove 50, and the second flat portion may be the portion surrounding the isolation groove 50. For example, the orthographic projection of the first flat portion onto the substrate may cover the orthographic projection of multiple electrostatic discharge circuits 40 onto the substrate. The touch-sensitive inorganic insulating layer located on the side of the organic planarization layer away from the substrate 10 may be a touch-sensitive interlayer insulating layer 153. The touch-sensitive interlayer insulating layer 153 may contact the first inorganic insulating layer through the isolation groove 50. The first inorganic insulating layer may be a sixth insulating layer 106 (also referred to as a passivation layer). In other examples, ... Figure 3C Taking the membrane structure shown as an example, when the sixth insulating layer is omitted, the first inorganic insulating layer can be the third insulating layer, and the interlayer insulating layer of the touch control can contact the third insulating layer through the isolation groove; Figure 3A Taking the illustrated film structure as an example, when the sixth insulating layer is omitted, the first inorganic insulating layer can be the fifth insulating layer. The interlayer insulating layer of the touch control can contact the fifth insulating layer through the isolation groove. Since it is necessary to remove part of the inorganic insulating layer in the bending area to improve bending performance, it is easy to increase the risk of moisture intrusion in the second sub-region. In this example, by setting the isolation groove in the organic planarization layer, and making the inorganic insulating layer on the side of the organic planarization layer away from the substrate and the side closer to the substrate contact each other through the isolation groove, moisture barrier can be achieved, improving the trace corrosion in the circuit setting area, thereby enhancing the corrosion resistance of the electrostatic discharge circuit.

[0126] In some examples, such as Figure 14As shown, the circuit setting area B132 can be equipped with multiple electrostatic discharge circuits 40 and multiple test circuits. The multiple test circuits can be located on the side of the multiple electrostatic discharge circuits 40 away from the second fan-out area B131. First peripheral power lines 61 can be set on both sides of the multiple electrostatic discharge circuits 40 along the second direction D2. The first peripheral power lines 61 can be configured to provide a first power signal to the sub-pixels of the display area. For example, the first peripheral power lines 61 can be located in the first source / drain metal layer or the second source / drain metal layer. The multiple electrostatic discharge circuits 40 can be connected to first voltage transmission lines VGHa and VGHb, and to a second voltage transmission line VGL. The first voltage transmission lines VGHa and VGHb can be connected to a first voltage connection line 411, and the second voltage line VGL can be connected to a second voltage connection line 421. The first voltage connection line 411 and the second voltage connection line 421 can extend at least along the first direction D1, and the second voltage connection line 421 can be located on the side of the first voltage connection line 411 away from the multiple electrostatic discharge circuits 40. The first voltage connection line 411 and the second voltage connection line 421 can extend to the second signal access area B135 and connect to the corresponding second contact pad within the second signal access area B135. For example, the first voltage connection line 411 and the second voltage connection line 421 can be located in the first source-drain metal layer. The first voltage connection line 411 and the first voltage transmission lines VGHa and VGHb located in the first source-drain metal layer can be an integral structure, and the second voltage transmission line VGL located in the second source-drain metal layer can be connected to the second voltage connection line 421 through an opening in the insulating layer.

[0127] This example demonstrates how placing the first voltage transmission line and the second voltage transmission line in different conductive layers—specifically, the first voltage transmission line in the first source-drain metal layer and the second voltage transmission line in the second source-drain metal layer—can reduce the electric field strength between the two voltage transmission lines, improve moisture corrosion, and thus reduce electrochemical corrosion, thereby enhancing the corrosion resistance of the electrostatic discharge circuit. Furthermore, by creating isolation grooves around multiple electrostatic discharge circuits in the organic planarization layer, moisture barrier properties can be achieved, reducing trace corrosion in the circuit area and further improving the corrosion resistance of the electrostatic discharge circuit.

[0128] Figure 16 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 16 It can be Figure 13 Another partial cross-sectional schematic diagram along the PP' direction, showing only a portion of the film layer. In some examples, such as... Figure 16As shown, the organic planar layer (including the stacked seventh insulating layer 107 and eighth insulating layer 108) in the first border region may have isolation recesses 50 surrounding multiple electrostatic discharge circuits. First voltage transmission lines VGHa and VGHb may be located in the first source-drain metal layer, and the second voltage transmission line VGL may be located in the second source-drain metal layer.

[0129] This example, by placing the first voltage transmission line and the second voltage transmission line in different conductive layers—the first voltage transmission line in the second source / drain metal layer and the second voltage transmission line in the first source / drain metal layer—can reduce the electric field strength between the first and second voltage transmission lines, improve moisture corrosion, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic discharge circuit. Furthermore, by providing isolation grooves 50 around the multiple electrostatic discharge circuits in the organic planarization layer, moisture barrier properties can be achieved, improving the corrosion resistance of the traces in the circuit area and further enhancing the corrosion resistance of the electrostatic discharge circuit. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments and will not be repeated here.

[0130] Figure 17 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 17 It can be Figure 13 Another partial cross-sectional schematic diagram along the PP' direction, showing only a portion of the film layer. In some examples, such as... Figure 17 As shown, the organic planar layer (including the seventh insulating layer 107 and the eighth insulating layer 108) in the first border region may have isolation recesses 50 surrounding multiple electrostatic discharge circuits. First voltage transmission lines VGHa and VGHb may be located in the first source / drain metal layer, and the second voltage transmission line VGL may be located in the second source / drain metal layer. A metal cover layer (MCL) 16 is also provided on the side of the touch protection layer 154 away from the substrate 10. The metal cover layer 16 may be configured to cover traces in the bending area. The touch protection layer 154 may have a cutout area 1540 in the first border region, which may expose a portion of the surface of the interlayer insulating layer 153 away from the substrate 10. For example, the cutout area 1540 and the orthographic projection of the isolation recesses 50 onto the substrate 10 may partially overlap, or they may not overlap; for example, the isolation recesses 50 may surround the cutout area 1540. The metal cover layer 16 may fill within the cutout area 1540. The orthographic projection of the cutout area 1540 onto the substrate 10 can cover the orthographic projection of multiple electrostatic discharge circuits onto the substrate 10. For example, the material of the metal overlay 16 may include an organic insulating material. In this example, by removing the touch protection layer above the electrostatic discharge circuit, the stress on the electrostatic discharge circuit after the metal overlay is applied can be reduced. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0131] Figure 18 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 18 It can be Figure 13 Another partial cross-sectional schematic diagram along the PP' direction, showing only a portion of the film layer. In some examples, such as... Figure 18 As shown, the organic planar layer (including the stacked seventh insulating layer 107 and eighth insulating layer 108) in the first bezel region may have isolation recesses 50 surrounding multiple electrostatic discharge circuits. First voltage transmission lines VGHa and VGHb may be located in the second source / drain metal layer, and second voltage transmission line VGL may be located in the first source / drain metal layer. The touch protection layer 154 in the first bezel region may have a cutout area 1540, and a metal overlay layer 16 may fill the cutout area 1540. The orthographic projection of the cutout area 1540 onto the substrate 10 may cover the orthographic projection of the multiple electrostatic discharge circuits onto the substrate 10. This example reduces the stress on the electrostatic discharge circuits after the metal overlay layer is applied by removing the touch protection layer above the electrostatic discharge circuits. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments and will not be repeated here.

[0132] Figure 19 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 19 It can be Figure 13 Another partial cross-sectional schematic diagram along the PP' direction, showing only a portion of the film layer. In some examples, such as... Figure 19 As shown, the organic planarization layer (including the stacked seventh insulating layer 107 and eighth insulating layer 108) in the first frame region may have isolation grooves 50 surrounding multiple electrostatic discharge circuits. The first voltage transmission lines VGHa and VGHb, and the second voltage transmission line VGL may all be located in the first source-drain metal layer. The touch interlayer insulating layer 153 can contact the sixth insulating layer 106 through the isolation grooves 50. The orthographic projection of the touch protection layer 154 onto the substrate 10 may cover the orthographic projection of the multiple electrostatic discharge circuits onto the substrate 10. This example, by providing isolation grooves surrounding multiple electrostatic discharge circuits in the organic planarization layer, can mitigate the risk of moisture intrusion caused by partial removal of the inorganic insulating layer in the bending area, achieving moisture barrier and improving the corrosion resistance of the electrostatic discharge circuits by reducing trace corrosion in the circuit area. In other examples, the first voltage transmission lines VGHa and VGHb, and the second voltage line VGL may all be located in the second source-drain metal layer. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments and will not be repeated here.

[0133] Figure 20 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure.Figure 20 It can be Figure 13 Another partial cross-sectional schematic diagram along the PP' direction, showing only a portion of the film layer. In some examples, such as... Figure 20 As shown, the first voltage transmission lines VGHa and VGHb, and the second voltage transmission line VGL can all be located in the first source / drain metal layer. The touch protection layer 154 can have a cutout area 1540 in the first border region, and the metal cover layer 16 can fill the cutout area 1540. The orthogonal projection of the cutout area 1540 onto the substrate 10 can cover the orthogonal projection of multiple electrostatic discharge circuits onto the substrate 10. In this example, by removing the touch protection layer 154 above the electrostatic discharge circuits, the stress on the electrostatic discharge circuits after the metal cover layer 16 is applied can be reduced. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0134] Figure 21 to Figure 24 This is another partial cross-sectional schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 21 to Figure 24 It can be Figure 13 Another partial cross-sectional view along the PP' direction is shown, illustrating only a portion of the film layer. This example uses the film layer of the display area of ​​a display panel as an example. Figure 3B or Figure 3D As shown in the example, Figure 21 to Figure 24 As shown, the organic planarization layer in the first border region may include: a stacked seventh insulating layer 107, an eighth insulating layer 108, and a ninth insulating layer 109. The touch-sensitive inorganic insulating layer located on the side of the organic planarization layer away from the substrate 10 may be a touch-sensitive interlayer insulating layer 153. The touch-sensitive interlayer insulating layer 153 may contact the first inorganic insulating layer through the isolation groove 50. The first inorganic insulating layer may be a sixth insulating layer 106 (or a passivation layer).

[0135] In some examples, such as Figure 21 As shown, the first voltage transmission lines VGHa and VGHb can be located in the third source-drain metal layer, and the second voltage transmission line VGL can be located in the first source-drain metal layer. Figure 22 As shown, the first voltage transmission lines VGHa and VGHb can be located in the first source-drain metal layer, and the second voltage transmission line VGL can be located in the third source-drain metal layer. Figure 23 As shown, the first voltage transmission lines VGHa and VGHb can be located in the third source-drain metal layer, and the second voltage transmission line VGL can be located in the second source-drain metal layer. Figure 24 As shown, the first voltage transmission lines VGHa and VGHb can be located in the second source-drain metal layer, and the second voltage transmission line VGL can be located in the third source-drain metal layer.

[0136] This example, by placing the first voltage transmission line and the second voltage transmission line in different conductive layers, reduces the electric field strength between the first and second voltage transmission lines, improves moisture corrosion, thereby reducing electrochemical corrosion and enhancing the corrosion resistance of the electrostatic discharge circuit. Furthermore, by providing isolation grooves 50 around the multiple electrostatic discharge circuits in the organic planarization layer, moisture barrier can be achieved, improving the corrosion resistance of the traces in the circuit area and further enhancing the corrosion resistance of the electrostatic discharge circuit. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0137] In other examples, when the circuit structure layer of the display panel further includes a third source / drain metal layer, a third planarization layer, a fourth source / drain metal layer, and a fourth planarization layer located on the side of the second source / drain metal layer away from the substrate, the first voltage transmission line and the second voltage transmission line in the first frame region can be located in different source / drain metal layers. For example, the first voltage transmission line can be located in the fourth source / drain metal layer, and the second voltage transmission line can be located in the third source / drain metal layer, the second source / drain metal layer, or the first source / drain metal layer. The organic insulating layer with the isolation groove can include a stacked first planarization layer, a second planarization layer, a third planarization layer, and a fourth planarization layer.

[0138] This embodiment also provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead-out lines, a plurality of electrostatic discharge circuits, and an organic planarization layer. The substrate includes: a display area and a first border region located on one side of the display area along a first direction. The first border region includes: a first sub-region, a bent region, and a second sub-region arranged sequentially along a first direction away from the display area. The plurality of sub-pixels are disposed on one side of the substrate and located in the display area. The plurality of data lines are located in the display area and configured to provide data signals to the plurality of sub-pixels. The plurality of data lead-out lines are located in the first border region and connected to the plurality of data lines. The plurality of electrostatic discharge circuits are located in the first border region and connected to the plurality of data lead-out lines. The organic planarization layer has isolation grooves surrounding the plurality of electrostatic discharge circuits in a second sub-region of the first border region.

[0139] This embodiment improves the risk of moisture intrusion caused by the removal of part of the inorganic insulation layer in the bending area by setting isolation grooves around multiple electrostatic discharge circuits in the organic planarization layer. It can achieve moisture barrier, improve the wiring corrosion in the circuit setting area, and thus enhance the corrosion resistance of the electrostatic discharge circuit.

[0140] In some exemplary embodiments, the display panel may further include a first inorganic insulating layer and a touch-sensitive inorganic insulating layer. The first inorganic insulating layer is located on the side of the organic planarization layer closest to the substrate; the touch-sensitive inorganic insulating layer is located on the side of the organic planarization layer furthest from the substrate. The touch-sensitive inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove. For example, the touch-sensitive inorganic insulating layer may include a touch-interlayer insulating layer. This example, by providing an isolation groove in the organic planarization layer and making the inorganic insulating layer on the side of the organic planarization layer furthest from the substrate and the side close to the substrate contact each other through the isolation groove, can achieve moisture barrier, improve the trace corrosion situation in the circuit setting area, and thus enhance the corrosion resistance of the electrostatic discharge circuit.

[0141] In some exemplary embodiments, the display panel may further include a touch protection layer and a metal overlay layer. A touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate. The touch protection layer has a cutout area in a second sub-region of the first bezel area, the orthographic projection of the cutout area onto the substrate covering the orthographic projection of the plurality of electrostatic discharge circuits onto the substrate. The metal overlay layer is located on the side of the touch protection layer away from the substrate, and the metal overlay layer fills the cutout area. This example reduces the stress on the electrostatic discharge circuits after the metal overlay layer is applied by removing the touch protection layer above the electrostatic discharge circuits.

[0142] For a description of the display panel in this example, please refer to the description of the foregoing embodiments, and therefore it will not be repeated here.

[0143] Figure 25 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 25 As shown, this embodiment provides a display device 91, including the display panel 910 of the aforementioned embodiment. In some examples, the display panel 910 can be an OLED display panel, such as an OLED display panel with an integrated touch structure. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, or it can be a product or component with both touch and display functions. In some examples, the display device 91 can be a wearable display device, for example, one that can be worn on the human body in some way. For example, the display device 91 can be a smartwatch, smart bracelet, etc. However, this embodiment is not limited to this.

[0144] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0145] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, characterized in that, include: The substrate includes: a display area and a first border area located on one side of the display area along a first direction; Multiple sub-pixels are disposed on one side of the substrate and located in the display area; Multiple data lines are located in the display area and configured to provide data signals to the multiple sub-pixels; Multiple data leads are located in the first border area and connected to the multiple data lines; Multiple electrostatic discharge circuits are located in the first frame area and connected to the multiple data lead-out lines; At least one first voltage transmission line is located in the first frame area and connected to the plurality of electrostatic discharge circuits, configured to provide a first voltage signal; At least one second voltage transmission line is located in the first frame area and connected to the plurality of electrostatic discharge circuits, configured to provide a second voltage signal, the second voltage signal being different from the first voltage signal; The at least one first voltage transmission line and the at least one second voltage transmission line are located in different conductive layers.

2. The display panel according to claim 1, characterized in that, The at least one first voltage transmission line is located on the side of the at least one second voltage transmission line away from the substrate; or, the at least one second voltage transmission line is located on the side of the at least one first voltage transmission line away from the substrate.

3. The display panel according to claim 2, characterized in that, The display panel includes at least: a first source / drain metal layer and a second source / drain metal layer disposed on the substrate; the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate; The at least one first voltage transmission line is located in the first source-drain metal layer, and the at least one second voltage transmission line is located in the second source-drain metal layer; or, the at least one second voltage transmission line is located in the first source-drain metal layer, and the at least one first voltage transmission line is located in the second source-drain metal layer.

4. The display panel according to claim 2, characterized in that, The display panel includes at least: a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate; the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate; The at least one first voltage transmission line is located in the first source-drain metal layer or the second source-drain metal layer, and the at least one second voltage transmission line is located in the third source-drain metal layer; or, the at least one second voltage transmission line is located in the first source-drain metal layer or the second source-drain metal layer, and the at least one first voltage transmission line is located in the third source-drain metal layer.

5. The display panel according to claim 1, characterized in that, The display panel includes at least two first voltage transmission lines and one second voltage transmission line, wherein both the two first voltage transmission lines and the second voltage transmission line extend along a second direction, and the second voltage transmission line is located between the two first voltage transmission lines along the first direction; the second direction intersects the first direction. Alternatively, the display panel may include at least two second voltage transmission lines and one first voltage transmission line, wherein both the two second voltage transmission lines and the first voltage transmission line extend along the second direction, and the first voltage transmission line is located between the two second voltage transmission lines along the first direction.

6. The display panel according to claim 5, characterized in that, The plurality of electrostatic discharge circuits are arranged in an array along the first direction and the second direction; The plurality of electrostatic discharge circuits are arranged in at least two rows along the first direction, and each row of electrostatic discharge circuits includes a plurality of electrostatic discharge circuits arranged along the second direction. The two electrostatic discharge circuits are connected to the same first voltage transmission line or the same second voltage transmission line; The data leads connected to the first row of electrostatic discharge circuits and the data leads connected to the second row of electrostatic discharge circuits are located on different conductive layers.

7. The display panel according to claim 6, characterized in that, The electrostatic discharge circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The first terminal of the first transistor is electrically connected to the second voltage transmission line, the gate and the second terminal of the first transistor are electrically connected to the first terminal of the second transistor, the gate and the second terminal of the second transistor are electrically connected to the first terminal of the third transistor and the data lead-out line, the gate and the second terminal of the third transistor are electrically connected to the first terminal of the fourth transistor, and the second terminal of the fourth transistor is electrically connected to the first voltage transmission line. The arrangement of the first transistor, second transistor, third transistor, and fourth transistor in the first row of the electrostatic discharge circuit along the first direction is opposite to the arrangement of the first transistor, second transistor, third transistor, and fourth transistor in the second row of the electrostatic discharge circuit along the first direction.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display panel also includes: An organic planarization layer having an isolation groove surrounding the plurality of electrostatic discharge circuits in the first border region; The first inorganic insulating layer is located on the side of the organic planarization layer closest to the substrate; The touch-sensitive inorganic insulating layer is located on the side of the organic planarization layer away from the substrate; The touch-sensitive inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

9. The display panel according to claim 8, characterized in that, The display panel also includes: A touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate; The orthographic projection of the touch protection layer onto the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits onto the substrate.

10. The display panel according to claim 8, characterized in that, The display panel also includes: A touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate. The touch protection layer has a cutout area in the first frame area. The orthographic projection of the cutout area on the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits on the substrate. A metal overlay is located on the side of the touch protection layer away from the substrate, and the metal overlay fills the cutout area.

11. The display panel according to claim 1, characterized in that, The first frame area includes: a first sub-region, a bent region, and a second sub-region arranged sequentially along a first direction away from the display area; the plurality of electrostatic discharge circuits, the at least one first voltage transmission line, and the at least one second voltage transmission line are located in the second sub-region.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

13. A display panel, characterized in that, include: The substrate includes: a display area and a first border area located on one side of the display area along a first direction, wherein the first border area includes: a first sub-region, a bent region and a second sub-region arranged sequentially along a first direction away from the display area; Multiple sub-pixels are disposed on one side of the substrate and located in the display area; Multiple data lines are located in the display area and configured to provide data signals to the multiple sub-pixels; Multiple data leads are located in the first border area and connected to the multiple data lines; Multiple electrostatic discharge circuits are located in the second sub-region of the first frame area and are connected to the multiple data leads; An organic planarization layer has an isolation groove surrounding the plurality of electrostatic discharge circuits in a second sub-region of the first border region.

14. The display panel according to claim 13, characterized in that, The display panel also includes: The first inorganic insulating layer is located on the side of the organic planarization layer closest to the substrate; The touch-sensitive inorganic insulating layer is located on the side of the organic planarization layer away from the substrate; The touch-sensitive inorganic insulating layer contacts the first inorganic insulating layer through the isolation groove.

15. The display panel according to claim 14, characterized in that, The display panel also includes: A touch protection layer is located on the side of the touch inorganic insulating layer away from the substrate. The touch protection layer has a cutout area in a second sub-region of the first frame area. The orthographic projection of the cutout area onto the substrate covers the orthographic projection of the plurality of electrostatic discharge circuits onto the substrate. A metal overlay is located on the side of the touch protection layer away from the substrate, and the metal overlay fills the cutout area.

Images