Display panel and display device
By adjusting the thickness and dielectric constant of the bottom insulating layer and optimizing the transistor structure, the problem of uneven low grayscale display in OLED display panels was solved, and the subthreshold swing and saturation characteristics were improved within a limited space, thus improving display uniformity.
Patent Information
- Application Number
- CN202511591675.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-02-03
AI Technical Summary
Organic light-emitting diode (OLED) display panels suffer from non-uniformity issues when displaying low grayscale levels, resulting in poor image uniformity. Existing technologies make it difficult to adjust the subthreshold swing and saturation characteristics of transistors without adding masks or affecting other transistors.
By adjusting the thickness and dielectric constant of the bottom insulating layer, the structure of the first transistor is optimized. Combined with the electrical connection between the conductive part and the source, the subthreshold swing and saturation characteristics of the transistor are improved, and the impact on other transistors is reduced.
Without adding a mask or affecting other transistors, the uniformity of low grayscale display is improved, and the current stability and display effect are enhanced.
Smart Images
Figure CN121463687A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] Organic light-emitting diode (OLED) display panels may exhibit uneven low-grayscale display in actual use. This is attributed to the large fluctuations in low-grayscale current, which leads to poor regional uniformity and ultimately results in poor uniformity of the displayed image.
[0003] To improve the uniformity of the display, the driving transistors can be adjusted to improve their driving characteristics, but this may require adding a mask or adjusting the gate insulating layer, which may affect other transistors.
[0004] Therefore, it has become a challenge to adjust the subthreshold swing and saturation characteristics of transistors within the limited space of the transistor while minimizing the increase in mask size and the impact on other transistors. Summary of the Invention
[0005] This application provides a display panel and a display device to at least partially solve the above-mentioned technical problems.
[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel having a first transistor, wherein the display panel includes: a bottom metal layer; a bottom insulating layer located on the bottom metal layer; a first active layer located on the bottom insulating layer, including a first active pattern of the first transistor; at least one insulating layer located on the first active layer; a first metal layer located on the first active layer; a second metal layer located on the first metal layer, including a first source of the first transistor; wherein the bottom metal layer includes a first gate of the first transistor, the first gate being located below the bottom insulating layer to be insulated from the first active pattern through the bottom insulating layer, and the first metal layer includes a conductive portion electrically connected to the first source.
[0007] Optionally, the thickness of the bottom insulating layer is greater than the thickness of the at least one insulating layer.
[0008] Optionally, the at least one insulating layer includes two insulating layers, the two insulating layers including a first insulating layer and a second insulating layer, the first insulating layer including a first insulating portion and a first second insulating portion, and the second insulating layer including a second first insulating portion and a second second insulating portion; the conductive portion is stacked on the first active pattern through the second first insulating portion and the first first insulating portion in sequence; the display panel further includes a second transistor, the display panel further includes a second active layer, the second active layer including a second active pattern of the second transistor, the first metal layer including a second gate of the second transistor, the second gate being stacked on the first second insulating portion through the second second insulating portion and the second active pattern in sequence; wherein, the thickness of the bottom insulating layer is greater than the sum of the thicknesses of the first first insulating portion and the first second insulating portion.
[0009] Optionally, the dielectric constant of the bottom insulating layer is less than the dielectric constant of the at least one insulating layer.
[0010] Optionally, the at least one insulating layer includes two insulating layers, the two insulating layers including a first insulating layer and a second insulating layer, the first insulating layer including a first insulating portion and a first second insulating portion, and the second insulating layer including a second first insulating portion and a second second insulating portion; the conductive portion is stacked on the first active pattern through the second first insulating portion and the first first insulating portion in sequence; the display panel further includes a second transistor, the display panel further includes a second active layer, the second active layer is located between the first insulating layer and the second insulating layer, and includes a second active pattern of the second transistor, the first metal layer includes a second gate of the second transistor, the second gate is stacked on the first second insulating portion through the second second insulating portion and the second active pattern in sequence; wherein, the dielectric constant of the bottom insulating layer is less than the dielectric constant of the first first insulating portion and the first second insulating portion.
[0011] Optionally, the bottom insulating layer has a first interface with the first active pattern; the display panel also has a third transistor, the first active layer further includes a third active pattern of the third transistor, the first metal layer further includes a third gate of the third transistor, and the third gate is stacked on the third active pattern through the at least one insulating layer, so that there is a third interface between the at least one insulating layer and the third active pattern; wherein, the interface defect state density of the first interface is greater than the interface defect state density of the third interface.
[0012] Optionally, the bottom insulating layer includes a first insulating layer and a second insulating layer stacked together; wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
[0013] Optionally, the thickness of the bottom insulating layer ranges from 2000 angstroms to 5000 angstroms.
[0014] Optionally, from a perspective along the thickness direction of the display panel, the channel region of the first active pattern is located within the boundary of the conductive portion, and at least a portion of the doped region of the first active pattern is located outside the boundary of the conductive portion.
[0015] Optionally, the channel region of the first active pattern is also located within the boundary of the first gate, wherein, in the extending direction of the first gate, the distance by which the edge of the first gate extends beyond the edge of the conductive portion is less than or equal to 2 μm.
[0016] Optionally, the first transistor is located in the display area of the display panel and is a driving transistor of the pixel driving circuit; and / or, the display panel further has a second transistor located in the non-display area of the display panel and is a transistor of the gate driving circuit, wherein the second transistor is located above the bottom insulating layer; and / or, the display panel further has a third transistor located in the non-display area of the display panel and is a switching transistor of the pixel driving circuit, wherein the third transistor is located above the bottom insulating layer.
[0017] According to a second aspect of this application, a display device is provided, including a display panel as described above.
[0018] In the display panel and display device of this application embodiment, the influence on the insulating layer between the first conductive layer and the second conductive layer can be reduced by adjusting the thickness of the bottom insulating layer, thereby adjusting the subthreshold swing of the first transistor. Furthermore, the saturation characteristics of the first transistor can be improved by electrically connecting the conductive part located in the first metal layer to the first source. This achieves the adjustment of the subthreshold swing and saturation characteristics of the transistor within the limited space of the transistor, while minimizing the increase of the mask and the influence on other transistors.
[0019] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0022] Figure 1 This is a schematic diagram of a display device provided in an exemplary embodiment of this application; Figure 2 This is a schematic diagram of the film layer structure of the display panel of the display device provided in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of the film layer structure of the display panel of the display device provided in an exemplary embodiment of this application.
[0023] Explanation of reference numerals in the attached figures: 100. Display panel; TMC (Timing Controller); GDR (Gate Driver); GAMMA (Gamma Reference Voltage Generator); SDR (Data Driver); AA, Display area; NA, Non-display area; GL, Grid line; DL, Data line; SP, Subpixel; IMG, Image Data; CONT, Input Control Signal; CONT1, First Control Signal; CONT2, Second Control Signal; CONT3, Third Control Signal; DATA, Data Signal; VGREF, Gamma Reference Voltage; T1, the first transistor; T2, the second transistor; T3, the third transistor; SUB, substrate; LS, bottom metal layer; BI, bottom insulating layer; ACT1, first active layer; GI1, first insulating layer; ACT2, second active layer; GI2, second insulating layer; GE, first metal layer; GI3, third insulating layer; ILD, interlayer insulating layer; SD, second metal layer; PV, passivation layer; A1, First active pattern; A2, Second active pattern; A3, Third active pattern; CP, Conductive portion; G1, First gate; G2, Second gate; G3, Third gate; S1, First source; D1, First drain; S2, Second source; D2, Second drain; S3, Third source; D3, Third drain; SR1, the first interface; SR3, the third interface. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0025] This application provides a display device, with reference to... Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a timing controller (TMC), a gate driver (GDR), a gamma reference voltage generator (GAMMA), and a data driver (SDR).
[0026] The display panel 100 has a display area AA on which an image is displayed and a non-display area NA adjacent to the display area AA. The non-display area NA may surround the display area AA. The display panel 100 may be an OLED (Organic Light Emitting Diode) display panel.
[0027] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple sub-pixels SP electrically connected to the gate lines GL and data lines DL. The gate lines GL may extend in a first direction, and the data lines DL may extend in a second direction intersecting the first direction. For example, the first direction may be perpendicular to the second direction, but is not limited thereto. The sub-pixels SP may include pixel driving circuitry and light-emitting units (e.g., OLED light-emitting devices). The pixel driving circuitry drives the light-emitting units to emit light under the drive of the gate lines GL and data lines DL.
[0028] The timing controller (TMC) receives input image data (IMG) and input control signals (CONT) from an external device (e.g., a host or application processor). For example, the input image data (IMG) may include red, green, and blue image data. In addition to red, green, and blue image data, the input image data (IMG) may also include white image data. Instead of red, green, and blue image data, the input image data (IMG) may include magenta, cyan, and yellow image data. The input control signals (CONT) may include a master clock signal and a data enable signal. The master clock signal provides the display system with a master timing reference for setting the rate at which data is sent and processed. The data enable signal indicates when valid data is sent for display. The input control signals (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal. The vertical synchronization signal indicates the start of a new frame by synchronizing the start of each vertical scan. The horizontal synchronization signal marks the start of each new subpixel row or horizontal line.
[0029] The timing controller (TMC) generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.
[0030] The timing controller (TMC) generates a first control signal (CONT1) based on the input control signal (CONT) to control the operation of the gate driver (GDR), and outputs the first control signal (CONT1) to the gate driver (GDR). The first control signal (CONT1) may include a vertical start signal and a gate clock signal. The vertical start signal indicates the start of each vertical scan, and the gate clock signal controls the timing of row activation to drive each row sequentially from top to bottom.
[0031] The timing controller (TMC) generates a second control signal (CONT2) based on the input control signal (CONT) to control the operation of the data driver (SDR), and outputs the second control signal (CONT2) to the data driver (SDR). The second control signal (CONT2) may include a horizontal start signal and a load signal. The horizontal start signal indicates the start of a new horizontal line for the sub-pixel SP. The load signal can be used to maintain synchronization between the image data being processed and the physical sub-pixel SP being driven.
[0032] The timing controller (TMC) generates a data signal (DATA) based on the input image data (IMG). The timing controller (TMC) then outputs the data signal (DATA) to the data driver (SDR).
[0033] The timing controller (TMC) generates a third control signal (CONT3) based on the input control signal (CONT) to control the operation of the gamma reference voltage generator (GAMMA), and outputs the third control signal (CONT3) to the GAMMA. The voltage generated by the GAMMA helps control the brightness and color accuracy of each sub-pixel (SP).
[0034] The gate driver GDR generates a gate signal to drive the gate line GL in response to a first control signal CONT1 received from the timing controller TMC. The gate driver GDR can output the gate signal to the gate line GL. In embodiments of the present invention, the gate driver GDR is integrated in the non-display area NA of the display panel 100 to form a gate driving circuit within the display panel 100.
[0035] The Gamma Reference Voltage Generator (GAMMA) generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the timing controller (TMC). The GAMMA provides the gamma reference voltage VGREF to the data driver (SDR). The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.
[0036] In this embodiment, the Gamma reference voltage generator (GAMMA) can be located in the timing controller (TMC) or the data driver (SDR).
[0037] The data driver SDR receives a second control signal CONT2 and a data signal DATA from the timing controller TMC, and a gamma reference voltage VGREF from the gamma reference voltage generator GAMMA. The data driver SDR uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. For example, the data driver SDR can transform digital input image data IMG into precise analog voltages (i.e., data voltages) capable of driving each sub-pixel SP in the display panel 100, adjusted according to gamma correction provided by the gamma reference voltage VGREF. The data driver SDR outputs the data voltage to the data line DL.
[0038] In the embodiments of this invention, the data driver SDR is integrated into the non-display area NA of the display panel 100.
[0039] Please see Figure 2 The display panel 100 has a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 and the third transistor T3 are located in the display area AA of the display panel and serve as the driving transistor and switching transistor of the pixel driving circuit, respectively. The second transistor T2 is located in the non-display area NA of the display panel and serves as the transistor of the gate driving circuit.
[0040] The display panel includes a substrate SUB, a bottom metal layer LS, a bottom insulating layer BI, a first active layer ACT1, a first insulating layer GI1, a second active layer ACT2, a second insulating layer GI2, a first metal layer GE, a third insulating layer GI3, an interlayer insulating layer ILD, a second metal layer SD, and a passivation layer PV.
[0041] The substrate SUB can be made of inorganic materials. Specifically, the substrate SUB can be formed of glass, metal, or ceramic. The substrate SUB can also be made of organic materials, such as a single layer formed of polyimide or multiple layers formed by repeatedly stacking polyimide through coating and curing.
[0042] The bottom metal layer LS is located above the substrate SUB. It should be noted that the bottom metal layer LS is not necessarily located at the very bottom of the display panel; its position is lower than the active layer. The bottom metal layer LS includes a light-shielding layer, which includes the first gate G1 of the first transistor T1. In this embodiment, the light-shielding layer primarily blocks ambient light from affecting the active layer, and it can be made of metallic materials such as Mo, Cr, Al, Cu, Ti, and their alloys.
[0043] The bottom insulating layer BI is located on the bottom metal layer LS. In this embodiment, the bottom insulating layer BI includes a buffer layer. The buffer layer may include one or more inorganic insulating layers, such as silicon oxide or silicon nitride. The buffer layer can provide a planarization layer on the upper surface of the substrate SUB and can prevent or prevent impurities and moisture from penetrating from the substrate SUB into the display unit (i.e., the organic light-emitting element). In this embodiment, the thickness of the bottom insulating layer BI ranges from 2000 angstroms to 5000 angstroms. If the thickness of the bottom insulating layer BI is less than 2000 angstroms, the subthreshold swing of the first transistor T1 will be smaller, and the moisture barrier performance will be worse. If the thickness of the bottom insulating layer BI is greater than 5000 angstroms, it will result in an excessively thick display panel.
[0044] The first active layer ACT1, located on the bottom insulating layer BI, includes the first active pattern A1 of the first transistor T1 and the third active pattern A3 of the third transistor T3. The first active layer ACT1 can be formed of a metal oxide, such as IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ITZO (Indium Tin Zinc Oxide), or IGZTO (Indium Gallium Zinc Tin Oxide). The first active pattern A1 and the third active pattern A3 are divided into a channel region and source and drain regions formed on both sides of the channel region. The channel region is undoped and is an intrinsic semiconductor. The source and drain regions are doped with conductive impurities and are impurity semiconductors. The impurities doped in the source and drain regions can be either P-type or N-type impurities. If necessary, full-surface ion doping can be performed to improve the conductivity of the exposed areas of the active layer. In this embodiment, the thickness of the first active layer ACT1 is 100 angstroms to 1000 angstroms.
[0045] The first insulating layer GI1, located on the first active layer ACT1, includes a first insulating portion GI11, a first second insulating portion GI12, and a first third insulating portion GI13. In this embodiment, the first active layer ACT1 may be a plurality of layers or a single layer comprising at least one of tetraethyl orthosilicate (TEOS), silicon nitride, and silicon oxide. In this embodiment, the thickness of the first insulating layer GI1 is 300 angstroms to 1000 angstroms.
[0046] The second active layer ACT2, located on the first insulating layer GI1, includes the second active pattern A2 of the second transistor T2. The second active layer ACT2 can be formed of a high-mobility metal oxide with a higher mobility than the first active layer ACT1, such as IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ITZO (Indium Tin Zinc Oxide), or IGZTO (Indium Gallium Zinc Tin Oxide). If necessary, full-surface ion doping can be performed to improve the conductivity of the exposed areas of the active layer. In this embodiment, the thickness of the second active layer ACT2 is 100-1000 angstroms.
[0047] The second insulating layer GI2, located on the second active layer ACT2, includes a second first insulating portion GI21, a second second insulating portion GI22, and a second third insulating portion GI23. In this embodiment, the second insulating layer GI2 may be a plurality of layers or a single layer comprising at least one of tetraethyl orthosilicate (TEOS), silicon nitride, and silicon oxide. In this embodiment, the thickness of the second insulating layer GI2 is 1000 angstroms to 3000 angstroms.
[0048] A first metal layer GE is located on the first active layer ACT1. The first metal layer GE can be formed as multiple layers or a single layer comprising low-resistance materials such as Al, Ti, Mo, Cu, Ni and their alloys, or materials with high corrosion resistance. The first metal layer GE includes a conductive portion CP of a first transistor T1, a second gate G2 of a second transistor T2, and a third gate G3 of a third transistor T3. The conductive portion CP is stacked on the first active pattern A1 sequentially through a second insulating portion GI21 and a first insulating portion GI11, and overlaps with the channel region A11 of the first active pattern A1. The second gate G2 is stacked on the first insulating portion GI12 sequentially through a second insulating portion GI22 and a second active pattern A2, and overlaps with the channel region of the second active pattern A2. The third gate G3 is stacked on the third active pattern A3 sequentially through a second insulating portion GI23 and a first insulating portion GI13, and overlaps with the channel region of the third active pattern A3. In this embodiment, the thickness of the first metal layer GE is 2000 angstroms to 8000 angstroms. In this embodiment, metal patterns are first etched onto the conductive portion CP, the second gate G2, and the third gate G3. Then, the metal patterns are used as a self-aligned mask to etch the first insulating layer GI1 and the second insulating layer GI2.
[0049] The third insulating layer GI3 is located on the first metal layer GE. In this embodiment, the third insulating layer GI3 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate (TEOS), silicon nitride, and silicon oxide.
[0050] An interlayer insulating layer (ILD) is located on the third insulating layer GI3. In this embodiment, the interlayer insulating layer (ILD) may be formed as multiple layers or a single layer, for example, of tetraethyl orthosilicate (TEOS), silicon nitride, or silicon oxide.
[0051] The second metal layer SD, located on the interlayer insulating layer ILD, includes a first source S1 and a first drain D1 of a first transistor T1, a second source S2 and a second drain D2 of a second transistor T2, and a third source S3 and a third drain D3 of a third transistor T3. The first source S1 is connected to the source region of a first active pattern A1, and the first drain D1 is connected to the drain region of the first active pattern A1. The second source S2 is connected to the source region of a second active pattern A2, and the second drain D2 is connected to the drain region of the second active pattern A2. The third source S3 is connected to the source region of a third active pattern A3, and the third drain D3 is connected to the drain region of the third active pattern A3. In this embodiment, the second metal layer SD can be formed as multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or their alloys, or a material with high corrosion resistance. For example, the second metal layer SD can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or others.
[0052] A passivation layer PV is located on the second metal layer SD. In this embodiment, the passivation layer PV can be formed as multiple layers or a single layer, for example, of tetraethyl orthosilicate (TEOS), silicon nitride, or silicon oxide, and can be formed of an organic material with a low dielectric constant (e.g., polyimide). If necessary, a planarization layer can be fabricated to replace the passivation layer PV, with openings made at the junction of the second metal layer SD and the pixel electrode.
[0053] The bottom metal layer LS includes the first gate G1 of the first transistor T1. The first gate G1 is located below the bottom insulating layer BI to insulate it from the first active pattern A1 through the bottom insulating layer BI. The conductive part CP is electrically connected to the first source S1. The voltage signal can be provided by the traces in the non-display area NA and connected to the first source S1 through the conductive part CP. In this way, within the limited structural space of the first transistor T1, the SS (subthreshold swing) of the first transistor T1 can be adjusted by adjusting the thickness of the bottom insulating layer BI without affecting other transistors or adding a mask. At the same time, the voltage signal can be connected to the first source S1 through the conductive part CP located in the first metal layer GE, thereby improving the saturation characteristics of the first transistor T1 and improving the problem of uneven low grayscale display.
[0054] In some embodiments, please continue reading Figure 2 The bottom metal layer LS includes a light-shielding layer, and the bottom insulating layer BI includes a buffer layer. The light-shielding layer includes a first gate G1, which is located below the buffer layer to insulate it from the first active pattern A1. In this way, the bottom metal layer LS can simultaneously achieve gate control and light-shielding functions, simplifying the film structure. The buffer layer not only effectively blocks the diffusion of substrate impurities into the active layer but also acts as a gate insulating layer to adjust the subthreshold swing of the first transistor T1.
[0055] In some embodiments, please continue reading Figure 2 The conductive portion CP is stacked on the first active pattern A1 via the second insulating portion GI21 and the first insulating portion GI11. The thickness of the bottom insulating layer BI is greater than the sum of the thicknesses of the second insulating portion GI21 and the first insulating portion GI11. By increasing the thickness of the bottom insulating layer BI, making it thicker than the upper insulating layer, the subthreshold swing of the first transistor T1 can be increased, improving the stability of low grayscale current.
[0056] In this embodiment, the conductive part CP is stacked on the first active pattern A1 through two insulating layers. Of course, the number of insulating layers can be adjusted as needed; for example, one, three, or four insulating layers can be used. Specifically, when the first active pattern A1 of the first transistor T1, the second active pattern A2 of the second transistor T2, and the third active pattern A3 of the third transistor T3 are located on the same active layer, the display panel can retain only one insulating layer. Thus, the conductive part CP is stacked on the first active pattern A1 through at least one insulating layer, and the thickness of the bottom insulating layer BI is greater than the thickness of at least one insulating layer.
[0057] In some embodiments, please continue reading Figure 2The conductive portion CP is stacked on the first active pattern A1 via the second insulating portion GI21 and the first insulating portion GI11. The dielectric constant of the bottom insulating layer BI is less than that of the second insulating portion GI21 and the first insulating portion GI11. By reducing the dielectric constant of the bottom insulating layer BI, making it less than that of the first insulating layer GI1 and the second insulating layer GI2, the subthreshold swing of the first transistor T1 can be increased, improving the stability of low grayscale current. It should be noted that the dielectric constants of the second insulating portion GI21 and the first insulating portion GI11 refer to the dielectric constant of the second insulating portion GI21 and the first insulating portion GI11 as a whole.
[0058] In this embodiment, the conductive portion CP is stacked on the first active pattern A1 sequentially through two insulating layers. Of course, the number of insulating layers can be adjusted as needed, for example, one, three, or four layers. For example, when the first active pattern A1 of the first transistor T1, the second active pattern A2 of the second transistor T2, and the third active pattern A3 of the third transistor T3 are located on the same active layer, the display panel can retain only one insulating layer. In this way, the conductive portion CP is stacked on the first active pattern A1 through at least one insulating layer, and the dielectric constant of the bottom insulating layer BI is less than the dielectric constant of at least one insulating layer.
[0059] In some embodiments, please continue reading Figure 2 The bottom insulating layer BI has a first interface SR1 between itself and the first active pattern A1, and the first insulating layer GI1 has a third interface SR3 between itself and the third active pattern A3. The interface defect state density of the first interface SR1 is greater than that of the third interface SR3. By increasing the defect degree of the interface between the bottom insulating layer BI and the first active pattern A1, making the interface defect state density of the first interface SR1 greater than that of the third interface SR3, the subthreshold swing of the first transistor T1 can be increased, thus improving the stability of low grayscale current.
[0060] In some embodiments, please continue reading Figure 2 From a viewing angle along the thickness direction of the display panel, the channel region A11 of the first active pattern A1 is located within the boundary of the conductive portion CP, and at least a portion of the doped region A12 of the first active pattern A1 is located outside the boundary of the conductive portion CP. For example, from a viewing angle along the thickness direction of the display panel, the conductive portion CP completely covers the channel region A11 of the first active pattern A1, and the side of the doped region A12 of the first active pattern A1 that is away from the channel region extends out of the conductive portion CP. The conductive portion CP can also serve as a barrier material during doping of the first active pattern A1, reducing the number of dopant ions entering the channel region.
[0061] Further, please refer to Figure 3 The channel region of the first active pattern A1 is also located within the boundary of the first gate G1, wherein, in the extending direction of the first gate G1, the distance d from the edge of the first gate G1 to the edge of the conductive portion CP is less than or equal to 2 μm. When the distance from the edge of the first gate G1 to the edge of the conductive portion CP is greater than 2 μm, the on-state current of the first transistor T1 will decrease.
[0062] In some embodiments, please continue reading Figure 3 The bottom insulating layer BI comprises a first insulator layer BI1 and a second insulator layer BI2 stacked together. The dielectric constant of the first insulator layer BI1 is lower than that of the second insulator layer BI2, and the thickness of the first insulator layer BI1 is greater than that of the second insulator layer BI2. In this embodiment, the first insulator layer BI1 comprises an inorganic insulating layer, which includes materials such as silicon oxide. The second insulator layer BI2 comprises an inorganic insulating layer, which includes materials such as silicon nitride. Through the composite insulating layer design of a low-dielectric-thickness layer and a high-dielectric-thinness layer, the bottom insulating layer BI, with a fixed thickness, can have a low dielectric constant, which can increase the subthreshold swing of the first transistor T1 and improve the stability of low grayscale current.
[0063] For example, the second insulator layer BI2 may also be located above the first insulator layer BI1. Of course, the first insulator layer BI1 may also be located above the second insulator layer BI2.
[0064] In some embodiments, the bottom insulating layer BI includes an interconnected intermediate insulating portion (not shown) and a peripheral insulating portion (not shown). The intermediate insulating portion is located between the first gate G1 and the first active pattern A1, and the peripheral insulating portion is located around the periphery of the first buffer portion. The thickness of the intermediate insulating portion is greater than the thickness of the peripheral insulating portion. By locally increasing the thickness of the bottom insulating layer BI at the location corresponding to the first transistor T1, making the intermediate insulating portion protrude beyond the peripheral insulating portion, the subthreshold swing of the first transistor T1 can be increased without altering the surrounding environment of other transistors, significantly reducing the impact on other transistors.
[0065] In some embodiments, the bottom insulating layer BI includes an interconnected intermediate insulating portion (not shown) and a peripheral insulating portion (not shown). The intermediate insulating portion is located between the first gate G1 and the first active pattern A1, and the peripheral insulating portion is located around the periphery of the first buffer portion. The dielectric constant of the intermediate insulating portion is lower than that of the peripheral insulating portion. Specifically, a groove may be provided at the top of the bottom insulating layer BI corresponding to the first gate G1, and the groove may be filled with a material having a lower dielectric constant than that of the peripheral insulating portion to form the intermediate insulating portion. By locally changing the dielectric constant of the bottom insulating layer BI corresponding to the first transistor T1, the subthreshold swing of the first transistor T1 can be increased without altering the surrounding environment of other transistors, significantly reducing the impact on other transistors.
[0066] Embodiments of this application also provide a display device, including the display apparatus as described above. The display device can be an electronic device such as a smartphone, television, in-vehicle device, or computer.
[0067] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0069] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0070] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel having a first transistor, characterized in that, The display panel includes: Bottom metal layer; A bottom insulating layer is located on the bottom metal layer; A first active layer, located on the bottom insulating layer, includes a first active pattern of the first transistor; At least one insulating layer is located on the first active layer; A first metal layer is located on the at least one insulating layer; A second metal layer is located on the first metal layer and includes the first source of the first transistor; The bottom metal layer includes a first gate of the first transistor, which is located below the bottom insulating layer to be insulated from the first active pattern through the bottom insulating layer. The first metal layer also includes a conductive portion electrically connected to the first source.
2. The display panel according to claim 1, characterized in that, The thickness of the bottom insulating layer is greater than the thickness of the at least one insulating layer.
3. The display panel according to claim 2, characterized in that, The at least one insulating layer includes two insulating layers, the two insulating layers including a first insulating layer and a second insulating layer. The first insulating layer includes a first first insulating portion and a first second insulating portion, and the second insulating layer includes a second first insulating portion and a second second insulating portion. The conductive portion is stacked on the first active pattern in sequence through the second first insulating portion and the first first insulating portion. The display panel also has a second transistor, and the display panel further includes a second active layer, the second active layer including a second active pattern of the second transistor. The first metal layer includes a second gate of the second transistor, and the second gate is stacked on the first second insulating portion in sequence through the second second insulating portion and the second active pattern. The thickness of the bottom insulating layer is greater than the sum of the thicknesses of the first insulating portion and the first and second insulating portions.
4. The display panel according to claim 1, characterized in that, The dielectric constant of the bottom insulating layer is less than the dielectric constant of the at least one insulating layer.
5. The display panel according to claim 4, characterized in that, The at least one insulating layer includes two insulating layers, the two insulating layers including a first insulating layer and a second insulating layer. The first insulating layer includes a first first insulating portion and a first second insulating portion, and the second insulating layer includes a second first insulating portion and a second second insulating portion. The conductive portion is stacked on the first active pattern in sequence through the second first insulating portion and the first first insulating portion. The display panel also has a second transistor, and the display panel further includes a second active layer, the second active layer including a second active pattern of the second transistor. The first metal layer includes a second gate of the second transistor, and the second gate is stacked on the first second insulating portion in sequence through the second second insulating portion and the second active pattern. The dielectric constant of the bottom insulating layer is less than that of the first insulating portion and the first and second insulating portions.
6. The display panel according to claim 1, characterized in that, The bottom insulating layer has a first interface with the first active pattern; the display panel also has a third transistor, the first active layer further includes a third active pattern of the third transistor, the first metal layer further includes a third gate of the third transistor, the third gate is stacked on the third active pattern through the at least one insulating layer, and a third interface is formed between the at least one insulating layer and the third active pattern. The interface defect state density of the first interface is greater than that of the third interface.
7. The display panel according to claim 1, characterized in that, The bottom insulating layer includes a first insulating layer and a second insulating layer stacked together; wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
8. The display panel according to claim 1, characterized in that, The thickness of the bottom insulating layer ranges from 2000 angstroms to 5000 angstroms.
9. The display panel according to any one of claims 1-8, characterized in that, From a perspective along the thickness direction of the display panel, the channel region of the first active pattern is located within the boundary of the conductive portion, and at least a portion of the doped region of the first active pattern is located outside the boundary of the conductive portion.
10. The display panel according to claim 9, characterized in that, The channel region of the first active pattern is also located within the boundary of the first gate, wherein, in the extending direction of the first gate, the distance by which the edge of the first gate extends beyond the edge of the conductive portion is less than or equal to 2 μm.
11. The display panel according to any one of claims 1-8, characterized in that, The first transistor is located in the display area of the display panel and is a driving transistor of the pixel driving circuit; and / or The display panel also has a second transistor located in the non-display area of the display panel, which is a transistor of the gate driving circuit, wherein the second transistor is located above the bottom insulating layer; and / or The display panel also has a third transistor located in the display area of the display panel. The third transistor is a switching transistor of the pixel driving circuit, and is located above the bottom insulating layer.
12. A display device, characterized in that, Includes the display panel as described in any one of claims 1-11.