Display substrate, display panel and display device

Abstract

The invention discloses a display substrate, a display panel and a display device, and relates to the technical field of display. The display substrate comprises a substrate body, a display area and a non-display area, wherein the display area and the non-display area are arranged on one side of the substrate body. The non-display area comprises a gate drive circuit, the gate drive circuit comprises a first capacitor, the first capacitor comprises a plurality of sub-capacitors which are sequentially arranged in a stacked mode in the normal direction of the substrate, orthographic projections of the sub-capacitors on the substrate are at least partially overlapped, and the sub-capacitors are connected in parallel; the display area comprises a plurality of sub-pixels, each sub-pixel comprises a switch transistor and a transparent electrode, and a grid electrode of the switch transistor is connected with a grid electrode driving circuit; in the normal direction of the substrate, the first capacitor is located on the side, close to the substrate, of the transparent electrode.

Description

Display substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Technology

[0002] Screen-to-body ratio refers to the proportion of the effective display area on a screen, usually expressed as a percentage. Screens with a higher screen-to-body ratio have a larger display area, thus improving the user's viewing experience.

[0003] Overview

[0004] This disclosure provides a display substrate, including: a substrate, and a display area and a non-display area disposed on one side of the substrate;

[0005] The non-display area includes a gate driving circuit, the gate driving circuit includes a first capacitor, the first capacitor includes: a plurality of sub-capacitors stacked sequentially along the normal direction of the substrate, the orthographic projections of the plurality of sub-capacitors on the substrate at least partially overlap, and the plurality of sub-capacitors are connected in parallel to each other;

[0006] The display area includes multiple sub-pixels, each sub-pixel including a switching transistor and a transparent electrode, the gate of the switching transistor being connected to the gate driving circuit;

[0007] In the normal direction of the substrate, the first capacitor is located on the side of the transparent electrode closer to the substrate.

[0008] In some embodiments, the transparent electrode includes a pixel electrode and a common electrode, the pixel electrode being connected to the first electrode of the switching transistor; and

[0009] The plurality of sub-capacitors are located on the side of the pixel electrode and the common electrode that is close to the substrate.

[0010] In some embodiments, the sub-capacitor includes a lower electrode and an upper electrode stacked along the normal direction of the substrate, with the lower electrode located on the side of the upper electrode closer to the substrate.

[0011] The plurality of sub-capacitors includes a first sub-capacitor and a second sub-capacitor arranged adjacent to each other. The first sub-capacitor is located on the side of the second sub-capacitor closer to the substrate. The upper electrode of the first sub-capacitor and the lower electrode of the second sub-capacitor are the same electrode, and the lower electrode of the first sub-capacitor is connected to the upper electrode of the second sub-capacitor.

[0012] In some embodiments, the lower plate of the first sub-capacitor is connected to the upper plate of the second sub-capacitor through a first through-hole, which is located between the lower plate of the first sub-capacitor and the upper plate of the second sub-capacitor.

[0013] In some embodiments, the non-display area further includes:

[0014] A transparent pattern is disposed on the side of the first capacitor facing away from the substrate, and is disposed in the same layer as the transparent electrode and made of the same material; and

[0015] The lower electrode of the first sub-capacitor is connected to the transparent pattern through a second via, and the upper electrode of the second sub-capacitor is connected to the transparent pattern through a third via. The second via is located between the lower electrode of the first sub-capacitor and the transparent pattern, and the third via is located between the upper electrode of the second sub-capacitor and the transparent pattern.

[0016] In some embodiments, the sub-capacitor includes two plates stacked along the normal direction of the substrate, and at least one of the plates in each sub-capacitor is a metal plate, the metal plate comprising an opaque metal material.

[0017] In some embodiments, at least two of the metal plates of the plurality of sub-capacitors have orthographically projected boundaries that at least partially overlap on the substrate.

[0018] In some embodiments, the sub-capacitor includes two plates stacked along the normal direction of the substrate, and the plurality of plates constituting the first capacitor include at least one of the following:

[0019] The first electrode plate is disposed in the same layer as the gate of the switching transistor and is made of the same material;

[0020] The second electrode plate is disposed on the same layer as the second electrode of the switching transistor and is made of the same material.

[0021] The third electrode plate is disposed on the same layer as the channel of the switching transistor and includes a conductive channel material; and

[0022] The fourth electrode plate is disposed on the same layer as the shielding pattern of the switching transistor, and the shielding pattern is disposed on the side of the channel near the substrate.

[0023] In some embodiments, the first capacitor includes a first plate and a second plate, and the first plate and the second plate are disposed adjacent to each other.

[0024] In some embodiments, the first capacitor includes a first electrode and a second electrode, and at least one of the electrodes is disposed between the first electrode and the second electrode in the normal direction of the substrate.

[0025] In some embodiments, the first capacitor includes:

[0026] The fourth electrode plate, the third electrode plate, and the first electrode plate are sequentially stacked along the normal direction of the substrate, with the fourth electrode plate disposed close to the substrate; and

[0027] The shielding pattern is disposed on the same layer as the second electrode of the switching transistor, and the fourth electrode plate is the same electrode plate as the second electrode plate.

[0028] In some embodiments, the first capacitor includes:

[0029] The fourth electrode plate, the third electrode plate, the first electrode plate, and the second electrode plate are sequentially stacked along the normal direction of the substrate, with the fourth electrode plate disposed close to the substrate.

[0030] In some embodiments, the first capacitor includes:

[0031] The fourth electrode plate, the first electrode plate, and the second electrode plate are sequentially stacked along the normal direction of the substrate, with the fourth electrode plate disposed close to the substrate.

[0032] In some embodiments, the distance between the fourth electrode and the third electrode along the normal direction of the substrate is less than or equal to 3000 angstroms.

[0033] In some embodiments, the channel of the switching transistor comprises an oxide semiconductor material.

[0034] In some embodiments, the gate drive circuit further includes an output transistor, and one electrode of the first capacitor is connected to the gate of the output transistor, and the other electrode is connected to the first electrode of the output transistor.

[0035] In some embodiments, the gate drive circuit includes a plurality of cascaded shift registers, each shift register including the output transistor and the first capacitor, and the output terminal of the shift register is connected to the first terminal of the output transistor and the gate of the switching transistor, respectively.

[0036] This disclosure provides a display panel including a display substrate as described in any embodiment.

[0037] In some embodiments, the display panel further includes:

[0038] A counter substrate is disposed opposite to the display substrate, wherein the display area and the non-display area are located on the side of the substrate closer to the counter substrate; and

[0039] A liquid crystal layer is disposed between the display substrate and the opposing substrate.

[0040] This disclosure provides a display device, including:

[0041] The display panel as described in any embodiment; and

[0042] A driving circuit, connected to the display panel, is used to drive the display panel to display images.

[0043] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below.

[0044] Brief description of the attached diagram

[0045] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0046] Figure 1 shows a schematic diagram of a planar structure of a display substrate;

[0047] Figure 2 shows a schematic diagram of the structure of the first example of a display substrate provided in this disclosure;

[0048] Figure 3 shows a schematic diagram of the equivalent structure of the first capacitor in the first embodiment and the first capacitor in the first display substrate example provided in this disclosure;

[0049] Figure 4 shows a schematic diagram of the structure of a second example of a display substrate provided in this disclosure;

[0050] Figure 5 shows a schematic diagram of the equivalent structure of the first capacitor in the second embodiment and the first capacitor in the second display substrate example provided in this disclosure;

[0051] Figure 6 shows a schematic diagram of the structure of the third display substrate example provided in this disclosure;

[0052] Figure 7 shows a schematic diagram of the equivalent structure of the first capacitor in the third embodiment and the first capacitor in the third display substrate example provided in this disclosure;

[0053] Figure 8 shows a schematic diagram of the planar structure of the first capacitor in the first display substrate example provided in this disclosure;

[0054] Figure 9 shows a schematic diagram of the equivalent circuit structure of a shift register;

[0055] Figure 10 shows a schematic diagram of a planar structure of a shift register;

[0056] Figure 11 shows the capacitance value of the first capacitor in the first display substrate example provided in this disclosure and the result of comparing it with the capacitance value of the first capacitor in the first embodiment as a control group;

[0057] Figure 12 shows a schematic diagram of the fabrication process of the first example of a display substrate provided in this disclosure;

[0058] Figure 13 shows the capacitance value of the first capacitor in the second display substrate example provided in this disclosure and the result of comparing it with the capacitance value of the first capacitor in the second embodiment as a control group;

[0059] Figure 14 shows the capacitance value of the first capacitor in the third display substrate example provided in this disclosure under two buffer layer thicknesses, and the results of comparing the capacitance value of the first capacitor in the third embodiment as a control group.

[0060] Figure 15 shows a schematic cross-sectional view of a display panel.

[0061] Detailed description

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0063] In this disclosure, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain) and its source (source terminal, source region, or source), and current can flow through the drain, the channel region, and the source. In this disclosure, the channel region refers to the region through which current primarily flows.

[0064] In this disclosure, the transistor can be a thin-film transistor or a field-effect transistor, etc. This disclosure uses a thin-film transistor as an example for illustration.

[0065] In this disclosure, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this disclosure, the "source" and "drain" can be interchanged.

[0066] In related technologies, the pixel circuit of a liquid crystal display (LCD) panel includes one or two transistors, which is relatively simple, thus enabling ultra-high pixel density (Pixels Per Inch, PPI), i.e., the number of pixels per inch. LCD panels have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In ADS mode, both the pixel electrode and the common electrode are located on one side of the display substrate. In TN and VA modes, the pixel electrode and the common electrode are located on opposite sides of the liquid crystal layer, with the pixel electrode on one side of the display substrate and the common electrode on the opposite substrate side. The working principle of ADS mode is that the liquid crystal molecules lie in a plane parallel to the substrate. When there is no voltage, light passes through the lower polarizer and forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot rotate, so it is absorbed by the upper polarizer and cannot be emitted. When a voltage is applied, a lateral electric field is formed on both sides of the liquid crystal, and the liquid crystal molecules align along the direction of the electric field. Light passing through the lower polarizer and the liquid crystal layer becomes elliptically polarized and can pass through the upper polarizer. The working principle of TN mode is that, in the absence of voltage, the liquid crystal molecules are twisted and aligned at 90° under the action of the alignment film. Light passes through the lower polarizer and the liquid crystal molecules and exits from the upper polarizer. When a voltage is applied, except for the liquid crystal near the upper and lower alignment films, most of the other liquid crystal molecules are vertically aligned. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. Because it is parallel to the polarization axis of the upper polarizer, the light is absorbed and cannot escape. The working principle of VA mode is that the liquid crystal molecules are aligned perpendicular to the substrate. In the absence of voltage, light passing through the lower polarizer forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot rotate, so it is absorbed by the upper polarizer and cannot escape. When a voltage is applied, the liquid crystal molecules deflect along the direction of the electric field. Light passing through the lower polarizer and the liquid crystal layer becomes elliptically polarized and can pass through the upper polarizer.

[0067] The structure of the display substrate is described below using ADS mode as an example.

[0068] This disclosure provides a display substrate, as shown in FIG1, which includes: a substrate 11 (not shown in FIG1), and a display area AA and a non-display area NA disposed on one side of the substrate 11.

[0069] As shown in Figure 1, the non-display area NA includes a gate drive circuit GOA, which includes a first capacitor C (not shown in Figure 1). The display area AA includes a switching transistor T1 and a transparent electrode TE, and the gate G of the switching transistor T1 is connected to the gate drive circuit GOA.

[0070] For example, as shown in FIG1, the display area AA includes a scan line GL extending in the row direction and a data line DL extending in the column direction. The scan line GL and the data line DL intersect each other to form a plurality of sub-pixels PX. Each sub-pixel PX includes a switching transistor T1 and a transparent electrode TE.

[0071] As shown in Figures 2, 4, or 6, the first capacitor C includes a plurality of sub-capacitors C1 sequentially stacked along the normal direction f1 of the substrate 11. The orthographic projections of the plurality of sub-capacitors C1 on the substrate 11 at least partially overlap, and the plurality of sub-capacitors C1 are connected in parallel with each other. Specifically, along the normal direction f1 of the substrate 11, the plurality of sub-capacitors C1 are located on the side of the transparent electrode TE closest to the substrate 11.

[0072] In Figures 2, 4, or 6, a shows a planar structural diagram of the display area AA and the non-display area NA, and b shows a cross-sectional structural diagram of the display area CC' and the non-display area BB'.

[0073] Referring to Figure 3b, an equivalent structural schematic diagram of the first capacitor C shown in Figure 2 is shown. The first capacitor C in Figure 2 includes two sub-capacitors C1 stacked and connected in parallel. Referring to Figure 5b, an equivalent structural schematic diagram of the first capacitor C shown in Figure 4 is shown. The first capacitor C in Figure 4 includes three sub-capacitors C1 stacked and connected in parallel. Referring to Figure 7b, an equivalent structural schematic diagram of the first capacitor C shown in Figure 6 is shown. The first capacitor C in Figure 6 includes two sub-capacitors C1 stacked and connected in parallel.

[0074] Since the first capacitor C includes multiple sub-capacitors C1 connected in parallel, and the orthographic projections of the multiple sub-capacitors C1 on the substrate 11 overlap, the technical solution of this disclosure can increase the capacitance value per unit area of ​​the first capacitor C. While keeping the capacitance value of the first capacitor C unchanged, the area occupied by the first capacitor C can be reduced, thereby saving the space occupied by the gate drive circuit GOA and reducing the bezel size.

[0075] For example, multiple sub-capacitors C1 in the first capacitor C can be formed synchronously with the display area AA, without the need to increase the number of masks. The process is simple and feasible, which is beneficial to improving product specifications.

[0076] For example, the transparent electrode TE can be made of transparent conductive materials, such as metal oxides like ITO, IZO, IGZO, IGO, and ZTO. Transparent conductive materials have higher transmittance of visible light than metallic materials.

[0077] For example, as shown in FIG2, FIG4 or FIG6, the transparent electrode TE includes a pixel electrode E1 and a common electrode E2, wherein the pixel electrode E1 is connected to the first terminal of the switching transistor T1. In this case, the first capacitor C is located on the side of the pixel electrode E1 and the common electrode E2 near the substrate 11.

[0078] As shown in b of any one of Figures 3, 5 and 7, the sub-capacitor C1 includes two plates JB stacked along the normal direction f1 of the substrate 11, such as a lower plate and an upper plate stacked together, with the lower plate located on the side of the upper plate closer to the substrate 11.

[0079] For example, as shown in b of any one of Figures 3, 5 and 7, the plurality of sub-capacitors C1 include a first sub-capacitor C11 and a second sub-capacitor C12 arranged adjacent to each other. The first sub-capacitor C11 is located on the side of the second sub-capacitor C12 that is close to the substrate 11. The upper electrode of the first sub-capacitor C11 and the lower electrode of the second sub-capacitor C12 are the same electrode JB, and the lower electrode of the first sub-capacitor C11 is connected to the upper electrode of the second sub-capacitor C12.

[0080] For example, the first sub-capacitor C11 and the second sub-capacitor C12 are two adjacent sub-capacitors C1 in the first capacitor C. For example, as shown in Figure 5b, the first capacitor C includes three sub-capacitors C1 stacked together. The first sub-capacitor C11 and the second sub-capacitor C12 can be two adjacent sub-capacitors C1 that are far away from the substrate 11, or they can be two adjacent sub-capacitors C1 that are close to the substrate 11 (as shown in Figure 5b).

[0081] For example, as shown in FIG2, FIG4 or FIG6, the non-display area NA further includes: a transparent pattern TP, which is disposed on the side of the first capacitor C away from the substrate 11, and is disposed in the same layer as the transparent electrode TE and is made of the same material.

[0082] The transparent pattern TP can be set in the same layer as the pixel electrode E1 (as shown in Figure 2, Figure 4 or Figure 6) or the common electrode E2. This disclosure does not make any specific limitation in this regard.

[0083] In order to connect the lower plate of the first sub-capacitor C11 to the upper plate of the second sub-capacitor C12, in some examples, as shown in Figure 4, the lower plate of the first sub-capacitor C11 and the upper plate of the second sub-capacitor C12 are connected through a first via H1, which is located between the lower plate of the first sub-capacitor C11 and the upper plate of the second sub-capacitor C12.

[0084] To connect the lower plate of the first sub-capacitor C11 to the upper plate of the second sub-capacitor C12, in some other examples, as shown in Figure 2 or Figure 6, the lower plate of the first sub-capacitor C11 is connected to the transparent pattern TP through a second via H2, and the upper plate of the second sub-capacitor C12 is connected to the transparent pattern TP through a third via H3. The second via H2 is located between the lower plate of the first sub-capacitor C11 and the transparent pattern TP, and the third via H3 is located between the upper plate of the second sub-capacitor C12 and the transparent pattern TP.

[0085] In this example, the lower plate of the first sub-capacitor C11 and the upper plate of the second sub-capacitor C12 are connected by a transparent pattern TP bridge.

[0086] For example, as shown in Figures 2, 4, or 6, the plurality of plates JB constituting the first capacitor C may include: a first plate JB1, which is disposed in the same layer as the gate G of the switching transistor T1 and is made of the same material. The gate G of the switching transistor T1 is, for example, disposed in the same layer as the scan line GL.

[0087] For example, as shown in Figures 2, 4, or 6, the plurality of plates JB constituting the first capacitor C may include a second plate JB2, which is disposed in the same layer as the second electrode S of the switching transistor T1 and is made of the same material. The second electrode S of the switching transistor T1 is, for example, disposed in the same layer as the data line DL.

[0088] For example, as shown in FIG2 or FIG4, the plurality of plates JB constituting the first capacitor C may include: a third plate JB3, which is disposed in the same layer as the channel CH of the switching transistor T1 and includes a conductive channel CH material.

[0089] For example, the channel CH material of the switching transistor T1 is IGZO, and correspondingly, the material of the third plate JB3 is conductive IGZO.

[0090] For example, as shown in FIG2, FIG4 or FIG6, the plurality of plates JB constituting the first capacitor C may include: a fourth plate JB4, which is disposed in the same layer as the shielding pattern ZD of the switching transistor T1, and the shielding pattern ZD is disposed on the side of the channel CH near the substrate 11.

[0091] For example, as shown in FIG4 or FIG6, the first capacitor C includes a first plate JB1 and a second plate JB2, and the first plate JB1 and the second plate JB2 are arranged adjacent to each other.

[0092] For example, as shown in FIG2, the first capacitor C includes a first electrode JB1 and a second electrode JB2, and at least one electrode JB is disposed between the first electrode JB1 and the second electrode JB2 in the normal direction f1 of the substrate 11. In FIG2, a third electrode JB3 is disposed between the first electrode JB1 and the second electrode JB2.

[0093] For example, at least one electrode JB in each sub-capacitor C1 is a metal electrode, which comprises an opaque metal material.

[0094] For example, the first electrode plate JB1, the second electrode plate JB2, and the fourth electrode plate JB4 can all be metal electrodes.

[0095] For example, at least two metal plates of the plurality of sub-capacitors C1 have orthogonal projection boundaries on the substrate 11 that at least partially overlap. This further saves the area occupied by the first capacitor C.

[0096] Referring to Figure 8, a schematic diagram of the planar structure of the first capacitor C shown in Figure 2 is presented. As can be seen from Figure 8, the boundaries of the first plate JB1 and the second plate JB2 roughly coincide within the effective area of ​​the first capacitor C.

[0097] For example, as shown in Figures 2, 4, or 6, the switching transistor T1 has a top-gate structure, meaning that the gate G of the switching transistor T1 is located on the side of the channel CH away from the substrate 11. Of course, the switching transistor T1 can also have a bottom-gate structure, meaning that the gate G of the switching transistor T1 is located on the side of the channel CH closer to the substrate 11. This disclosure does not specifically limit this.

[0098] In some embodiments, the channel CH of the switching transistor T1 comprises a semiconductor material M1OaNb, wherein M1 is a single metal or a combination of multiple metals, a > 0 and b ≥ 0, O represents oxygen, and N represents nitrogen. That is, the semiconductor material is a metal oxide material or a metal nitride material. Suitable metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth doped oxides (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel CH can be amorphous, partially crystalline, single crystal or polycrystalline, and can also be a single layer or multilayer structure.

[0099] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the channel CH material includes indium gallium zinc oxide (IGZO).

[0100] For example, as shown in FIG9, the gate drive circuit GOA further includes an output transistor M3, and one electrode of the first capacitor C is connected to the gate of the output transistor M3, and the other electrode is connected to the first electrode of the output transistor M3.

[0101] For example, as shown in FIG9, the gate drive circuit GOA includes a plurality of cascaded shift registers 91. Each shift register 91 includes an output transistor M3 and a first capacitor C, and the output terminal OUT of the shift register 91 is connected to the first terminal of the output transistor M3 and the gate G of the switching transistor T1, respectively. The output terminal OUT of the shift register 91 and the gate G of the switching transistor T1 are connected through a scan line GL.

[0102] For example, a schematic diagram of a shift register 91 is shown with reference to FIG9. As shown in FIG9, the shift register 91 includes multiple transistors and a capacitor, and the multiple transistors include an output transistor M3. The shift register 91 shown in FIG9 is an 18T1C structure, that is, it includes 18 transistors (such as M1 to M18) and 1 capacitor (such as a first capacitor C).

[0103] It should be noted that the number of transistors and capacitors included in shift register 91 can be adjusted according to actual needs, and this disclosure does not impose specific limitations on this.

[0104] Referring to Figure 10, a schematic diagram showing the area proportions of the components in the shift register 91 in some embodiments is provided. As shown in Figure 10, in some embodiments, the area occupied by the first capacitor C is approximately 6000-10000 μm. 2 (e.g., 8000μm) 2 (Second only to the output transistor M3, which occupies an area of ​​16000-20000μm) 2 (e.g., 18000μm) 2 ).

[0105] The technical solutions provided in this disclosure are illustrated below with reference to Figures 2, 4, and 6.

[0106] In the first example, as shown in Figure 2, the first capacitor C includes a fourth electrode JB4, a third electrode JB3, and a first electrode JB1, which are sequentially stacked along the normal direction f1 of the substrate 11. The fourth electrode JB4 is disposed close to the substrate 11. The shielding pattern ZD is disposed on the same layer as the second electrode S of the switching transistor T1. The fourth electrode JB4 and the second electrode JB2 are the same electrode JB.

[0107] As shown in Figure 2, the fourth electrode JB4 and the third electrode JB3 constitute the first sub-capacitor C11, with the fourth electrode JB4 being the lower electrode of the first sub-capacitor C11 and the third electrode JB3 being the upper electrode of the first sub-capacitor C11. The third electrode JB3 and the first electrode JB1 constitute the second sub-capacitor C12, with the third electrode JB3 being the lower electrode of the second sub-capacitor C12 and the first electrode JB1 being the upper electrode of the second sub-capacitor C12. The fourth electrode JB4 and the first electrode JB1 are connected to the transparent pattern TP through the second via H2 and the third via H3. The transparent pattern TP is disposed on the same layer as the pixel electrode E1. The third electrode JB3 is also connected to the output terminal OUT of the shift register 91, and the fourth electrode JB4 and the first electrode JB1 are also connected to the gate of the output transistor M3.

[0108] As shown in Figure 2, the first capacitor C further includes: a buffer layer disposed between the fourth plate JB4 and the third plate JB3, and a gate insulating layer GI disposed between the third plate JB3 and the first plate JB1. The buffer layer may include, for example, stacked silicon nitride (such as SiNx, x>0) and silicon oxide (such as SiOy, y>0), and the gate insulating layer GI may include, for example, silicon oxide (such as SiOz, z>0), and the values ​​of x, y, and z may be the same or different.

[0109] Referring to FIG11, the capacitance value of the first capacitor C shown in the first example and the result of comparison with the capacitance value of the first capacitor in the first embodiment as a control group are shown. In the first example, the first capacitor C is equivalent to the first sub-capacitor C11 and the second sub-capacitor C12 connected in parallel (as shown in FIG3b), and the first capacitor C in the first embodiment is equivalent to the first sub-capacitor C11 and the second sub-capacitor C12 connected in series (as shown in FIG3a).

[0110] As shown in Figure 11, the capacitance per unit area of ​​the first capacitor C in the first example is approximately four times that of the first capacitor C in the first embodiment. Therefore, while keeping the capacitance value of the first capacitor C constant, the area of ​​the first capacitor C in the first example can be reduced by 25%. For example, the area of ​​the first capacitor C in the first embodiment is 8000 μm. 2 In the first example, the effective area of ​​the first capacitor C is approximately 2000 μm. 2 Including the area occupied by the vias, the total area occupied by the first capacitor C is approximately 3000μm. 2 The total area occupied by the second via H2 and the third via H3 is approximately 630 μm. 2 The overlap hole HD between the third electrode plate JB3 and the output terminal OUT of the shift register 91 occupies an area of ​​approximately 300μm. 2 .

[0111] In this disclosure, the vacuum permittivity ε0 is taken as 8.85 × 10⁻⁶ when calculating the capacitance value. -12 Farads per meter. The dielectric constant of silicon nitride (such as SiN) is 6.9 farads per meter, and that of silicon oxide (such as SiO) is 3.9 farads per meter.

[0112] In the first example, the thickness of silicon nitride in the buffer layer can be greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, such as 3500 angstroms (as shown in Figure 11). The thickness of silicon oxide in the buffer layer can be greater than or equal to 200 angstroms and less than or equal to 1000 angstroms, such as 500 angstroms (as shown in Figure 11). The thickness of silicon oxide in the gate insulating layer GI can be greater than or equal to 500 angstroms and less than or equal to 4000 angstroms, such as 2000 angstroms (as shown in Figure 11).

[0113] Referring to Figure 12, the preparation process of the first example includes the following steps:

[0114] Step 1: A patterned first metal layer MT1 and a buffer layer are sequentially formed on one side of the substrate 11. The first metal layer MT1 includes a masking pattern ZD, a fourth electrode JB4, a data line DL, the second electrode S of the switching transistor T1, and the output terminal OUT of the shift register 91, as shown in Figure 12a.

[0115] Step 2: Using a halftone mask, a patterned semiconductor layer SC is formed on the buffer layer, as shown in Figure 12b. The semiconductor layer SC includes a first semiconductor pattern SC1 and a second semiconductor pattern SC2. The first semiconductor pattern SC1 is used to form the third electrode JB3, and the second semiconductor pattern SC2 is used to form the active layer of the switching transistor T1, which includes a channel CH.

[0116] Step 3: Ash the photoresist PR on the semiconductor layer SC so that the first semiconductor pattern SC1 is exposed, while the second semiconductor pattern SC2 is still covered by the photoresist PR, as shown in Figure 12c.

[0117] Step 4: Conduct the exposed first semiconductor pattern SC1 into a conductor. The first semiconductor pattern SC1 after conductor treatment is the third electrode JB3, as shown in d in Figure 12.

[0118] Step 5: Remove the photoresist PR, and sequentially form a patterned gate insulating layer GI and a second metal layer MT2 on the semiconductor layer SC. Then, perform a conductor-forming process on the exposed second semiconductor pattern SC2, as shown in e of Figure 12. The second metal layer MT2 includes the gate G of the switching transistor T1 and the first electrode JB1. The orthographic projection patterns of the gate insulating layer GI and the second metal layer MT2 on the substrate 11 can be the same.

[0119] Step 6: Sequentially form a first passivation layer PVX1, an organic layer RS, a common electrode E2 layer, a second passivation layer PVX2, and a pixel electrode E1 layer on the second metal layer MT2, as shown in f of Figure 12. The common electrode E2 layer includes a common electrode E2, and the pixel electrode E1 layer includes a pixel electrode E1 and a transparent pattern TP.

[0120] In the second example, as shown in Figure 4, the first capacitor C includes a fourth electrode JB4, a third electrode JB3, a first electrode JB1, and a second electrode JB2, which are sequentially stacked along the normal direction f1 of the substrate 11, with the fourth electrode JB4 disposed close to the substrate 11.

[0121] As shown in Figure 4, the fourth electrode JB4 and the third electrode JB3 form a sub-capacitor C1, with JB4 being the lower electrode and JB3 being the upper electrode. The third electrode JB3 and the first electrode JB1 form a first sub-capacitor C11, with JB3 being the lower electrode and JB1 being the upper electrode. The first electrode JB1 and the second electrode JB2 form a second sub-capacitor C12, with JB1 being the lower electrode and JB2 being the upper electrode. The fourth electrode JB4 and the first electrode JB1 are connected by a transparent pattern TP, which is disposed on the same layer as the pixel electrode E1. The third electrode JB3 and the second electrode JB2 are connected by a first via H1. The third plate JB3 and the second plate JB2 are also connected to the output terminal OUT of the shift register 91, and the fourth plate JB4 and the first plate JB1 are also connected to the gate of the output transistor M3.

[0122] As shown in Figure 4, the first capacitor C further includes: a buffer layer disposed between the fourth plate JB4 and the third plate JB3, a gate insulating layer GI disposed between the third plate JB3 and the first plate JB1, and an interlayer dielectric layer ILD disposed between the first plate JB1 and the second plate JB2. The buffer layer may include, for example, stacked silicon nitride (e.g., SiNy, y>0) and silicon oxide (e.g., SiOx, x>0), the gate insulating layer GI may include, for example, silicon oxide (e.g., SiOx, x>0), and the interlayer dielectric layer ILD may include, for example, at least one of silicon oxide (e.g., SiOx, x>0), silicon nitride (e.g., SiNy, y>0), silicon oxynitride (e.g., SiON), and silicon oxide (e.g., SiOx, x>0).

[0123] Referring to Figure 13, the capacitance value of the first capacitor C shown in the second example and the result of comparing it with the capacitance value of the first capacitor in the second embodiment as a control group are shown. In the second example, the first capacitor C is equivalent to three sub-capacitors C1 connected in parallel (as shown in Figure 5b), while the first capacitor C in the second embodiment is equivalent to one sub-capacitor C1 (as shown in Figure 5a).

[0124] As shown in Figure 13, the capacitance per unit area of ​​the first capacitor C in the second example is approximately four times that of the first capacitor C in the second embodiment. Therefore, while keeping the capacitance value of the first capacitor C unchanged, the area of ​​the first capacitor C in the second example can be reduced by 25%. For example, the area of ​​the first capacitor C in the second embodiment is 8000 μm. 2 In the second example, the effective area of ​​the first capacitor C is approximately 2000 μm. 2Including the area occupied by the vias, the total area occupied by the first capacitor C is approximately 3000μm. 2 .

[0125] In the second example, the buffer layer comprises stacked silicon nitride and silicon oxide, the gate insulating layer GI comprises silicon oxide, and the interlayer dielectric layer ILD comprises silicon oxide, silicon nitride, and silicon oxide stacked sequentially. The thickness of the silicon nitride in the buffer layer can be greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, such as 3500 angstroms (as shown in Figure 13). The thickness of the silicon oxide in the buffer layer can be greater than or equal to 200 angstroms and less than or equal to 1000 angstroms, such as 500 angstroms (as shown in Figure 13). The thickness of the silicon oxide in the gate insulating layer GI can be greater than or equal to 500 angstroms and less than or equal to 4000 angstroms, such as 2000 angstroms (as shown in Figure 13). The thickness of the silicon oxide in the interlayer dielectric layer ILD can be greater than or equal to 500 angstroms and less than or equal to 2000 angstroms, such as 1000 angstroms (as shown in Figure 13). The thickness of silicon nitride in the interlayer dielectric layer (ILD) can be greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms, such as 2000 angstroms (as shown in Figure 13).

[0126] In the third example, as shown in Figure 6, the first capacitor C includes a fourth electrode JB4, a first electrode JB1, and a second electrode JB2, which are sequentially stacked along the normal direction f1 of the substrate 11. The fourth electrode JB4 is disposed close to the substrate 11.

[0127] As shown in Figure 6, the fourth electrode JB4 and the first electrode JB1 constitute the first sub-capacitor C11, with the fourth electrode JB4 being the lower electrode of the first sub-capacitor C11 and the first electrode JB1 being the upper electrode of the first sub-capacitor C11. The first electrode JB1 and the second electrode JB2 constitute the second sub-capacitor C12, with the first electrode JB1 being the lower electrode of the second sub-capacitor C12 and the second electrode JB2 being the upper electrode of the second sub-capacitor C12. The fourth electrode JB4 and the second electrode JB2 are connected to the transparent pattern TP through the second via H2 and the third via H3. The transparent pattern TP is disposed on the same layer as the pixel electrode E1. The fourth electrode JB4 and the second electrode JB2 are also connected to the output terminal OUT of the shift register 91, and the first electrode JB1 is also connected to the gate of the output transistor M3.

[0128] As shown in Figure 6, the first capacitor C further includes: a buffer layer and a gate insulating layer GI disposed between the fourth electrode JB4 and the first electrode JB1, and an interlayer dielectric layer ILD disposed between the first electrode JB1 and the second electrode JB2. The buffer layer includes, for example, stacked silicon nitride (such as SiNy, y>0) and silicon oxide (such as SiOx, x>0), the gate insulating layer GI includes, for example, silicon oxide (such as SiOx, x>0), and the interlayer dielectric layer ILD includes, for example, at least one of silicon oxide (such as SiOx, x>0), silicon nitride (such as SiNy, y>0), silicon oxynitride (such as SiON), and silicon oxide (such as SiOx, x>0).

[0129] Referring to Figure 14, the capacitance values ​​of the first capacitor C shown in the third example under two different buffer layer thicknesses are shown, and the results are compared with the capacitance value of the first capacitor in the third embodiment as a control group. In the third example, the first capacitor C is equivalent to the first sub-capacitor C11 and the second sub-capacitor C12 connected in parallel (as shown in Figure 7b), and the first capacitor C in the third embodiment is equivalent to the second sub-capacitor C12 (as shown in Figure 7a).

[0130] In the third example, the buffer layer comprises stacked silicon nitride and silicon oxide, the gate insulating layer GI comprises silicon oxide, and the interlayer dielectric layer ILD comprises silicon oxide, silicon nitride, and silicon oxide stacked sequentially. The thickness of the silicon nitride in the buffer layer can be greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, such as 1500 angstroms (as shown in Figure 14b) or 3500 angstroms (as shown in Figure 14a). The thickness of the silicon oxide in the buffer layer can be greater than or equal to 200 angstroms and less than or equal to 1000 angstroms, such as 500 angstroms (as shown in Figure 14). The thickness of the silicon oxide in the gate insulating layer GI can be greater than or equal to 500 angstroms and less than or equal to 4000 angstroms, such as 2000 angstroms (as shown in Figure 14). The thickness of the silicon oxide in the interlayer dielectric layer ILD can be greater than or equal to 500 angstroms and less than or equal to 2000 angstroms, such as 1000 angstroms (as shown in Figure 14). The thickness of silicon nitride in the interlayer dielectric layer (ILD) can be greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms, such as 2000 angstroms (as shown in Figure 14).

[0131] As shown in Figure 14a, with a buffer layer thickness of 3500 Å + 500 Å, the capacitance per unit area of ​​the first capacitor C shown in the third example is approximately 1.7 times that of the first capacitor C in the third embodiment. For example, the area of ​​the first capacitor C in the third embodiment is 8000 μm. 2 In the third example, the effective area of ​​the first capacitor C is approximately 4700 μm. 2Including the area occupied by the vias, the total area occupied by the first capacitor C is approximately 5350μm. 2 .

[0132] As shown in Figure 14b, with a buffer thickness of 1500 Å + 500 Å, the capacitance of the first capacitor C in the third example is approximately twice that of the first capacitor C in the third embodiment. For example, the area of ​​the first capacitor C in the third embodiment is 8000 μm. 2 In the third example, the effective area of ​​the first capacitor C plus the area occupied by the via gives a total area of ​​approximately 4650 μm for the first capacitor C. 2 .

[0133] In the first example, if the buffer layer is too thin, it could cause a short circuit in the conductive layers above and below the buffer layer. In the second and third examples, the thickness of the buffer layer can be further reduced, for example, to less than or equal to 3000 angstroms, such as 2000 angstroms.

[0134] For example, in the second example, the distance between the fourth electrode JB4 and the third electrode JB3 along the normal direction f1 of the substrate 11 is less than or equal to 3000 angstroms, such as 2000 angstroms.

[0135] This disclosure provides a display panel including a display substrate 151 as provided in any embodiment.

[0136] Those skilled in the art will understand that the display panel provided in this disclosure has the advantages of the aforementioned display substrate.

[0137] For example, as shown in FIG15, the display panel is a liquid crystal display panel, and the display panel further includes: a counter substrate 152, which is disposed opposite to the display substrate 151, with the display area AA and the non-display area NA located on the side of the substrate 11 close to the counter substrate 152; and a liquid crystal layer 153 disposed between the display substrate 151 and the counter substrate 152.

[0138] This disclosure provides a display device, including a display panel as provided in any embodiment, and a driving circuit connected to the display panel for driving the display panel to display an image.

[0139] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the aforementioned display panel.

[0140] The display device disclosed herein can be any product or component with display function, such as a display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc.

[0141] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0142] In this disclosure, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0143] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0144] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0145] The polygons used in this specification are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc. They may have minor deformations due to tolerances, and may include chamfers, fillets, curved edges, and other variations.

[0146] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0147] The use of “for” or “configured to” in this disclosure implies an open and inclusive language that does not preclude applicability to or configuration to devices for performing additional tasks or steps.

[0148] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0149] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between two equal items less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between two flush items less than or equal to 5% of either one's dimension.

[0150] It should be understood that when a layer or element is referred to as being disposed on one side of another layer or substrate, it may be that the layer or element is directly disposed on the other layer or substrate, or it may be that there is an intermediate layer between the layer or element and the other layer or substrate.

[0151] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown in this disclosure, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, comprising: A substrate, a display region and a non-display region disposed on one side of the substrate; The non-display region comprises a gate drive circuit, and the gate drive circuit comprises a first capacitor, the first capacitor comprises: a plurality of sub-capacitors which are sequentially stacked along the normal direction of the substrate, and the plurality of sub-capacitors at least partially overlap in orthographic projection on the substrate, and the plurality of sub-capacitors are connected in parallel with each other; The display region comprises a plurality of sub-pixels, and the sub-pixel comprises a switching transistor and a transparent electrode, and the gate of the switching transistor is connected with the gate drive circuit; In the normal direction of the substrate, the first capacitor is located on the side of the transparent electrode close to the substrate. 2.The display substrate of claim 1, wherein, The transparent electrode comprises a pixel electrode and a common electrode, the pixel electrode is connected with the first electrode of the switching transistor; and The plurality of sub-capacitors are located on the side of the pixel electrode and the common electrode close to the substrate. 3.The display substrate of claim 1, wherein, The sub-capacitor comprises a lower plate and an upper plate which are stacked along the normal direction of the substrate, and the lower plate is located on the side of the upper plate close to the substrate; The plurality of sub-capacitors comprise a first sub-capacitor and a second sub-capacitor which are adjacently arranged, the first sub-capacitor is located on the side of the second sub-capacitor close to the substrate, the upper plate of the first sub-capacitor and the lower plate of the second sub-capacitor are the same plate, and the lower plate of the first sub-capacitor and the upper plate of the second sub-capacitor are connected. 4.The display substrate of claim 3, wherein, The lower plate of the first sub-capacitor and the upper plate of the second sub-capacitor are connected through a first via, and the first via is located between the lower plate of the first sub-capacitor and the upper plate of the second sub-capacitor. 5.The display substrate of claim 3, wherein, The non-display region further comprises: A transparent pattern is disposed on the side of the first capacitor away from the substrate, and is disposed in the same layer and made of the same material as the transparent electrode; and The lower plate of the first sub-capacitor and the transparent pattern are connected through a second via, and the upper plate of the second sub-capacitor and the transparent pattern are connected through a third via, the second via is located between the lower plate of the first sub-capacitor and the transparent pattern, and the third via is located between the upper plate of the second sub-capacitor and the transparent pattern. 6.The display substrate of claim 1, wherein, The sub-capacitor comprises two plates which are stacked along the normal direction of the substrate, at least one plate in each of the sub-capacitors is a metal plate, and the metal plate comprises an opaque metal material. 7.The display substrate of claim 6, wherein, The orthographic projection boundaries of at least two metal plates in the plurality of sub-capacitors on the substrate at least partially coincide. 8.The display substrate of claim 1, wherein, The sub-capacitor comprises two plates which are stacked along the normal direction of the substrate, and the plurality of plates constituting the first capacitor comprise at least one of the following: A first plate which is disposed in the same layer and made of the same material as the gate of the switching transistor; A second plate which is disposed in the same layer and made of the same material as the second electrode of the switching transistor; A third plate which is disposed in the same layer as the channel of the switching transistor, and comprises a conductive channel material; And A fourth plate which is disposed in the same layer as the shielding pattern of the switching transistor, and the shielding pattern is disposed on the side of the channel close to the substrate. 9.The display substrate of claim 8, wherein, The first capacitor comprises the first plate and the second plate, and the first plate is arranged adjacent to the second plate. 10.The display substrate of claim 8, wherein, The first capacitor comprises the first plate and the second plate, and at least one of the plates is arranged between the first plate and the second plate in the normal direction of the substrate. 11.The display substrate of claim 8, wherein, The first capacitor comprises: The fourth plate, the third plate and the first plate are sequentially stacked in the normal direction of the substrate, and the fourth plate is arranged close to the substrate. The shielding pattern is arranged in the same layer as the second electrode of the switching transistor, and the fourth plate and the second plate are the same plate. 12.The display substrate of claim 8, wherein, The first capacitor comprises: The fourth plate, the third plate, the first plate and the second plate are sequentially stacked in the normal direction of the substrate, and the fourth plate is arranged close to the substrate. 13.The display substrate of claim 8, wherein, The first capacitor comprises: The fourth plate, the first plate and the second plate are sequentially stacked in the normal direction of the substrate, and the fourth plate is arranged close to the substrate. 14.The display substrate of claim 12, wherein, In the normal direction of the substrate, the distance between the fourth plate and the third plate is less than or equal to 3000 angstroms. 15.The display substrate of claim 1, wherein, The channel of the switching transistor comprises an oxide semiconductor material. 16.The display substrate according to any one of claims 1 to 15, wherein The gate drive circuit further comprises an output transistor, and one electrode of the first capacitor is connected to the gate of the output transistor, and the other electrode is connected to the first electrode of the output transistor. 17.The display substrate of claim 16, wherein, The gate drive circuit comprises a plurality of shift registers connected in series, each of the shift registers comprises the output transistor and the first capacitor, and the output terminals of the shift registers are respectively connected to the first electrodes of the output transistors and the gates of the switching transistors.

18. A display panel, comprising the display substrate according to any one of claims 1 to 17.

19. The display panel of claim 18, wherein, The display panel further comprises: An opposite substrate arranged opposite to the display substrate, the display area and the non-display area are located on the side of the substrate close to the opposite substrate; and A liquid crystal layer arranged between the display substrate and the opposite substrate.

20. A display device, comprising: The display panel according to claim 18 or 19; And A drive circuit connected to the display panel, for driving the display panel to display a picture.

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