Electromagnetic spectrum abnormal signal monitoring method and system based on double acquisition and comparison

Abstract

The invention relates to the technical field of communication, discloses an electromagnetic spectrum abnormal signal monitoring method and system based on double acquisition and comparison, and aims to solve the problems of asynchronous double-channel sampling and high abnormal signal omission ratio and false alarm rate caused by clock drift and physical path delay in the prior art. According to the method, a hardware-level self-adaptive clock synchronization compensation circuit is constructed, clock path delay is quantized and offset in real time before analog-to-digital conversion, and a first sampling clock and a second sampling clock which are accurately synchronized are generated; a dual-channel ADC is used for synchronously collecting the same radio frequency signal, and abnormal signals are judged and identified through spectrum coherence analysis and differential spectrum threshold. The system comprises a main clock unit, a self-adaptive synchronous compensation circuit, a dual-channel ADC module and a data processing comparison module. The picosecond-level synchronization precision is achieved, external time service is not needed, the missing detection and false alarm rate is remarkably reduced, and the method is suitable for high-reliability frequency spectrum monitoring in the complex electromagnetic environment.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a method and system for monitoring electromagnetic spectrum anomaly signals based on dual acquisition and comparison. Background Technology

[0002] Monitoring anomaly signals in the electromagnetic spectrum is crucial in fields such as wireless communication, radar detection, and electromagnetic environment monitoring. The dual-sample comparison method, as an effective anomaly detection technique, relies on simultaneously sampling the same signal twice and identifying anomalies through data comparison. However, this method is highly dependent on the accuracy of the time synchronization between the two samplings.

[0003] In existing technologies, dual-channel sampling is usually clocked by an independent crystal oscillator. The inherent clock drift and physical path delays introduced by PCB traces, buffers, etc., can cause the dual-channel sampling time to lose synchronization, resulting in signal phase shift and spectrum distortion, which significantly increases the false alarm rate and false alarm rate of abnormal signals.

[0004] Existing technologies attempt to address the aforementioned problems through various approaches, but all have significant limitations. While software interpolation correction methods can align timestamps post-hoc, they introduce additional computational overhead and distortion of the original sampling due to reliance on high-order interpolation algorithms, and the error increases exponentially in scenarios with large phase differences. GPS time synchronization methods are limited by urban multipath effects and signal loss in indoor / tunnel scenarios, making it difficult to guarantee synchronization accuracy on mobile platforms, resulting in a high false alarm rate. Although fiber optic direct connection synchronization methods can achieve sub-microsecond synchronization, the system is costly and has poor vibration resistance, making it unsuitable for complex environments such as the field or vehicles. Fundamentally, these solutions all focus on correction at the "result level," neglecting the physical delay fluctuations introduced by PCB traces, buffers, and ADC latches in the hardware link, failing to achieve process compensation from the source of data acquisition.

[0005] Therefore, there is an urgent need for an innovative technical solution that requires no external dependence, has hardware-level real-time compensation capabilities, low power consumption, and can stably maintain sub-microsecond synchronization accuracy across the entire temperature range. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method and system for monitoring electromagnetic spectrum abnormal signals based on dual acquisition and comparison. It aims to overcome the problems of misalignment of dual acquisition data, decreased coherence, and high false alarm rate of abnormal signals caused by hardware-level time synchronization defects, especially the uncontrollability of clock source drift and physical transmission path delay.

[0007] To address the aforementioned technical problems, this invention provides a method for monitoring electromagnetic spectrum anomaly signals based on dual-acquisition comparison. By constructing a hardware-level, closed-loop, adaptive delay compensation circuit before the clock signal reaches the analog-to-digital converter, the method quantifies and actively compensates for clock physical path transmission delays caused by environmental changes and component aging in real time. This ensures precise alignment of dual-channel acquisition at the sampling time, achieving high-precision and high-reliability monitoring of electromagnetic spectrum anomaly signals.

[0008] On the one hand, the present invention provides a method for monitoring electromagnetic spectrum anomaly signals based on dual acquisition and comparison, which includes the following steps: S1, the original clock signal is generated by the master clock generation unit; S2, input the original clock signal to the adaptive clock synchronization compensation circuit, the adaptive clock synchronization compensation circuit performs real-time quantization and feedforward compensation of physical path delay, and generates a pair of first sampling clock and second sampling clock after synchronization compensation; S3, the first sampling clock and the second sampling clock drive the first analog-to-digital converter and the second analog-to-digital converter respectively to perform the first timing acquisition and the second timing acquisition on the same radio frequency input signal, and obtain the first digital signal sequence and the second digital signal sequence respectively; S4, the data processing and comparison module receives the first digital signal sequence and the second digital signal sequence, and identifies and outputs abnormal signal indications by performing spectral coherence analysis and differential spectral threshold decision.

[0009] As one embodiment of the present invention, the adaptive clock synchronization compensation circuit performs real-time quantization and feedforward compensation operations for physical path delay, specifically including: The clock distribution network inside the adaptive clock synchronization compensation circuit distributes the original clock signal to the first compensation channel and the second compensation channel. In the first compensation channel, a first calibration pulse is periodically generated using a first physical path delay quantization unit, and it is returned through a first calibration loop that matches the physical transmission path from the first sampling clock to the first analog-to-digital converter, thereby measuring the round-trip transmission time of the first calibration pulse, and calculating a first delay quantization value characterizing the first physical path delay based on the round-trip transmission time. The first closed-loop control logic unit generates a first digital control word based on the first delay quantization value and outputs it to the first digital control delay line set on the main clock path of the first compensation channel. The first digital control delay line applies a precise compensation delay to the original clock signal flowing through it based on the first digital control word. This compensation delay and the first physical path delay form a preset cancellation relationship in terms of value, and finally output the first sampling clock. Perform physical path delay quantization and compensation operations on the second compensation channel in the same manner as the first compensation channel, and output the second sampling clock.

[0010] Furthermore, the first calibration loop that matches the physical transmission path is a metal wire laid on the printed circuit board that is completely consistent with the clock signal trace from the first sampling clock to the first analog-to-digital converter in terms of length, width, stack-up structure, number of vias, and characteristic impedance. The start and end points of the first calibration loop are both connected to the first physical path delay quantization unit.

[0011] Furthermore, the first physical path delay quantization unit specifically includes a time-to-digital converter, which quantizes the time interval between the first calibration pulse leaving the starting point and returning to the ending point through an internal tap delay chain and latch array, with a quantization resolution of 10 ps.

[0012] The first closed-loop control logic unit obtains the one-way time value of the first physical path delay by performing a division by two operation and subtracting the inherent internal delay constant of the device based on the output of the time-to-digital converter.

[0013] Furthermore, the first digital control delay line is composed of a series of cascaded logic gate units with variable delay characteristics. The first digital control word is a 16-bit binary number used to control the number of conducting logic gate units and the bias current of each unit, thereby realizing the step adjustment of the clock signal delay with an adjustment step accuracy of 5ps.

[0014] The pre-defined offsetting relationship between the compensated delay and the first physical path delay is such that the total delay after compensation is stabilized at a fixed system target delay value.

[0015] As one embodiment of the present invention, the data processing and comparison module performs spectral coherence analysis and differential spectral threshold determination, specifically including: The data processing and comparison module first applies the Blackman-Harris window function to the first digital signal sequence and the second digital signal sequence, respectively; Next, a 4096-point Fast Fourier Transform is performed on the two windowed sequences to obtain the first frequency domain spectrum and the second frequency domain spectrum. Calculate the coherence function values ​​of the first and second frequency domain spectra at each frequency point. The coherence function is defined as the ratio of the square of the modulus of the cross power spectral density to the product of the respective power spectral densities. The calculated coherence function value is compared with a preset coherence threshold of 999‰. If the coherence function value at any frequency point is lower than the coherence threshold, an abnormal signal is determined to exist. In parallel, the differential spectrum of the first frequency domain spectrum and the second frequency domain spectrum is calculated and compared with the dynamic noise floor. If the amplitude of any signal peak in the differential spectrum exceeds ten decibels of the dynamic noise floor, an abnormal signal is determined to exist. When either the coherence analysis or the differential spectrum threshold decision is true, the data processing and comparison module will eventually output an abnormal signal indication.

[0016] According to another aspect of the present invention, an electromagnetic spectrum anomaly signal monitoring system based on dual acquisition and comparison is provided, comprising: The master clock generation unit is used to generate the original clock signal; An adaptive clock synchronization compensation circuit is connected to the output of the main clock generation unit. It is used to receive the original clock signal, perform real-time quantization and feedforward compensation of physical path delay, and output a pair of synchronized compensation first sampling clock and second sampling clock. The dual-channel analog-to-digital converter module includes a first analog-to-digital converter and a second analog-to-digital converter. The first analog-to-digital converter and the second analog-to-digital converter respectively receive a first sampling clock and a second sampling clock as their sampling references and are connected to the same radio frequency input signal source to perform first timing acquisition and second timing acquisition, and respectively output a first digital signal sequence and a second digital signal sequence. The data processing and comparison module has its input terminals connected to the output terminals of the first analog-to-digital converter and the second analog-to-digital converter, respectively. It is used to receive the first digital signal sequence and the second digital signal sequence, and to identify and output abnormal signal indications by performing spectral coherence analysis and differential spectral threshold decision.

[0017] As one embodiment of the present invention, the adaptive clock synchronization compensation circuit includes: A clock distribution network is used to distribute the original clock signal to the first compensation channel and the second compensation channel; The first physical path delay quantization unit is disposed in the first compensation channel and is used to periodically generate a first calibration pulse and transmit it through the first calibration loop to measure and calculate a first delay quantization value characterizing the first physical path delay. The first digital control delay line is connected in series on the main clock path of the first compensation channel and is used to apply a precise compensation delay to the original clock signal flowing through it according to the externally input digital control word. The first closed-loop control logic unit has its input connected to the output of the first physical path delay quantization unit and its output connected to the control terminal of the first digital control delay line, and is used to generate and output a digital control word according to the first delay quantization value. The system also includes a second physical path delay quantization unit, a second digital control delay line, and a second closed-loop control logic unit, which have functions and structures corresponding to the first physical path delay quantization unit, the first digital control delay line, and the first closed-loop control logic unit mentioned above, together forming a second compensation channel.

[0018] Furthermore, the master clock generation unit employs a temperature-compensated crystal oscillator with an operating frequency of 100MHz. Both the first and second analog-to-digital converters in the dual-channel analog-to-digital converter module have 14-bit resolution and a sampling rate set to 100MSa / s.

[0019] The data processing and comparison module, as well as the closed-loop control logic unit in the adaptive clock synchronization compensation circuit, are all integrated into a single field-programmable gate array (FPGA) chip.

[0020] Furthermore, the system also includes a temperature sensing unit, which is located on the printed circuit board area where the adaptive clock synchronization compensation circuit is located, for real-time monitoring of the circuit board's operating temperature.

[0021] The first and second closed-loop control logic units also use the output of the temperature sensing unit as an auxiliary input to increase the execution frequency of the physical path delay quantization operation when there are sudden temperature changes, thereby accelerating the compensation response. The baseline execution period of the physical path delay quantization operation is 10ms, and when the temperature change rate exceeds 1° / s, the execution period is shortened to 1ms.

[0022] In summary, this application includes at least one of the following beneficial technical effects: 1. This invention constructs a closed-loop adaptive clock synchronization compensation circuit to directly quantify and actively cancel clock physical path delays caused by factors such as temperature and aging at the hardware level, before sampling occurs. This process compensation eliminates synchronization errors at their source, avoiding the data distortion, high computational resource consumption, and failure under large phase differences inherent in existing software interpolation correction methods. It ensures the integrity and accuracy of the original sampled data, with a compensation processing delay of less than one hundred nanoseconds.

[0023] 2. The synchronization compensation scheme proposed in this invention is completely self-contained and does not require the use of GPS signals, fiber optic networks, or other external reference clocks. Therefore, this system can work stably in signal-shielded environments such as indoors, tunnels, and underground, as well as in complex scenarios such as vehicle-mounted operation, completely solving the problems of poor environmental adaptability and low reliability of existing external time synchronization schemes.

[0024] 3. By employing a time-to-digital converter for picosecond-level delay quantization and combining it with a digitally controlled delay line for fine compensation, this invention can stably control the synchronization error between the two channels to within 1μs, covering the entire operating temperature range of -40°C to 85°C. Furthermore, the entire compensation circuit is implemented based on a field-programmable gate array (FPGA), with a total power consumption of less than ten milliwatts, fully meeting the requirements of battery-powered portable or field monitoring equipment.

[0025] 4. Due to the high-precision alignment of sampling times, the coherence of the two-times acquired data is maintained at an ideal level close to one, greatly improving the sensitivity and reliability of spectrum comparison. Compared with existing technologies, this invention can effectively suppress spectrum broadening and frequency shift artifacts caused by clock drift and path delay, thereby reducing the false alarm rate and missed detection rate of abnormal signals, providing a solid technical guarantee for the effective regulation of the electromagnetic spectrum. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the overall technical architecture of an electromagnetic spectrum anomaly signal monitoring method and system based on dual acquisition and comparison provided by the present invention. Detailed Implementation

[0027] To further illustrate the technical means and effects adopted by the present invention in order to achieve the intended purpose, the following detailed description is provided in conjunction with the accompanying drawings and preferred embodiments, based on specific implementation methods of the present invention.

[0028] Reference Figure 1 As shown, this invention provides a method and system for monitoring electromagnetic spectrum abnormal signals based on dual acquisition comparison. Its core lies in constructing a closed-loop, adaptive, hardware-level clock synchronization compensation mechanism. Before the analog-to-digital converter (ADC) sampling action occurs, the clock signal delay caused by changes in ambient temperature, component aging, and differences in physical transmission paths is quantified and feedforwarded in real time to ensure that the sampling times of the first ADC and the second ADC are strictly aligned when performing two independent acquisitions of the same RF input signal.

[0029] Based on this, by performing high-precision spectral coherence analysis and differential spectral threshold decision on two digital signal sequences, a high-sensitivity and low-false-alarm-rate identification of abnormal electromagnetic signals such as sudden interference and illegal transmission can be achieved.

[0030] A method for monitoring electromagnetic spectrum anomaly signals based on dual-acquisition comparison includes the following steps: Step S1: The master clock generation unit generates the original clock signal.

[0031] The master clock generation unit uses a temperature-compensated crystal oscillator with a nominal operating frequency of 100MHz. This temperature-compensated crystal oscillator integrates a temperature sensor and a compensation network, and can control the frequency stability within ±0.5ppm within the operating temperature range of -40°C to 85°C.

[0032] The original clock signal is output in single-ended or differential form and transmitted to the input port of the adaptive clock synchronization compensation circuit via impedance-matched microstrip lines.

[0033] The original clock signal serves as the time reference for the entire system, and its phase noise is below -150dBc / Hz at a 100kHz offset, ensuring sufficient time-domain purity for subsequent sampling processes.

[0034] Step S2: The original clock signal is input to the adaptive clock synchronization compensation circuit. The adaptive clock synchronization compensation circuit performs real-time quantization and feedforward compensation of physical path delay to generate a pair of synchronized compensation first sampling clock and second sampling clock.

[0035] The core function of the adaptive clock synchronization compensation circuit is to eliminate the physical path delay difference between the original clock signal distribution point and the sampling latches of the two analog-to-digital converters. The adaptive clock synchronization compensation circuit includes a clock distribution network and two symmetrical compensation channels (the first compensation channel and the second compensation channel). Each compensation channel is equipped with a physical path delay quantization unit, a digital control delay line, and a closed-loop control logic unit.

[0036] Within the first compensation channel, the clock distribution network copies and distributes the original clock signal to the master clock path and the first physical path delay quantization unit of the first compensation channel. The first physical path delay quantization unit periodically generates a first calibration pulse. The generation of the first calibration pulse is based on the original clock signal, ensuring that its rising edge is strictly aligned with the edge of the original clock signal output by the clock distribution network. This can be achieved by, for example, through a phase-locked loop (PLL) or a trigger circuit.

[0037] The first calibration pulse is injected into a first calibration loop, which is a metal wire laid on a printed circuit board. Its length, line width, stack-up structure, number of vias, dielectric material, and characteristic impedance are completely consistent with the actual clock trace from the output of the first digital control delay line to the input of the first analog-to-digital converter sampling latch. Therefore, the transmission delay introduced by the first calibration loop accurately reproduces the delay characteristics of the actual sampling path. After being transmitted through the first calibration loop, the first calibration pulse returns to the input of the first physical path delay quantization unit.

[0038] The first physical path delay quantization unit integrates a time-to-digital converter, which is based on a tapped delay chain architecture. The tapped delay chain consists of 128 cascaded inverters, with each stage having a delay of approximately 10 ps.

[0039] When the first calibration pulse leaves the starting point, the delay chain is started; when the return pulse reaches the ending point, the state of each stage of the current delay chain is latched.

[0040] The round-trip time can be determined by reading the highest-level index that is set. The quantization resolution of the time-to-digital converter is 10 ps, ​​and its nonlinearity error is less than ±1.5 ps. The first physical path delay quantization unit performs a division operation based on the round-trip time measurement value and subtracts the known internal buffer and comparator inherent delay constant (which is measured during factory calibration and stored in non-volatile memory) to finally obtain the first delay quantization value characterizing the one-way delay of the first physical path.

[0041] The first delay quantization value is sent to the first closed-loop control logic unit, which is a state machine logic implemented inside the field-programmable gate array. The first closed-loop control logic unit compares the first delay quantization value with the preset system target delay value, which is set to 5ns. The system target delay value takes into account the analog-to-digital converter setup time, clock jitter margin, and overall system timing margin. If the measured delay is greater than the system target delay value, the compensation delay needs to be increased; if it is less than the system target delay value, the compensation delay needs to be reduced.

[0042] The first closed-loop control logic unit calculates a 16-bit binary first digital control word based on the deviation. Each bit of the first digital control word corresponds to the enable state or bias current of a first-level variable delay unit in the digital control delay line.

[0043] The first digitally controlled delay line is connected in series on the main clock path of the first compensation channel, located between the clock distribution network output and the first analog-to-digital converter. This first digitally controlled delay line is composed of 64 cascaded programmable delay units, each of which consists of a differential pair of transistors. Its delay can be continuously adjusted by adjusting the tail current source. Driven by a 16-bit control word, the total delay of the delay line can be adjusted in 5-ps steps within the range of 0 to 320ps.

[0044] The first digital control delay line applies a precise compensation delay to the original clock signal flowing through it based on the first digital control word, so that the total delay of the original clock signal after passing through the first digital control delay line and the subsequent physical path is equal to the system target delay value, and the final output signal is the first sampling clock.

[0045] The second compensation channel performs the same physical path delay quantization and compensation operation as the first compensation channel. The second physical path delay quantization unit generates a second calibration pulse, measures the second physical path delay through the second calibration loop, and the second closed-loop control logic unit generates a second digital control word to control the second digital control delay line to apply corresponding compensation to the original clock signal, outputting a second sampling clock.

[0046] Because the two compensation channels are strictly symmetrical in terms of physical layout, device selection and control logic, and each independently completes closed-loop adjustment, the first sampling clock and the second sampling clock are highly consistent in phase, and the synchronization error between the two channels is stably controlled within 1μs, with a typical value of 300ps.

[0047] The adaptive clock synchronization compensation circuit also integrates a temperature sensing unit, which is a silicon-based temperature sensor, located on the printed circuit board near the clock distribution network and compensation channel.

[0048] The temperature sensing unit outputs the current ambient temperature value every 10ms. Both the first closed-loop control logic unit and the second closed-loop control logic unit receive this temperature value as an auxiliary input.

[0049] When the detected temperature change rate exceeds 1° / s, the closed-loop control logic unit shortens the execution cycle of the physical path delay quantization operation from 10ms to 1ms to accelerate the response to the dielectric constant drift caused by the rapid temperature change, and ensures that the synchronous compensation can still maintain high accuracy in the case of rapid temperature change.

[0050] In step S3, the first sampling clock and the second sampling clock drive the first analog-to-digital converter and the second analog-to-digital converter respectively to perform first timing acquisition and second timing acquisition on the same radio frequency input signal, and obtain the first digital signal sequence and the second digital signal sequence respectively.

[0051] Both the first and second analog-to-digital converters are high-speed analog-to-digital converter chips with 14-bit resolution and a sampling rate of 100MSa / s. They share the same RF front-end amplifier and filter output to ensure that the input signals are completely consistent.

[0052] The first sampling clock is connected to the sampling clock input pin of the first analog-to-digital converter, and the second sampling clock is connected to the sampling clock input pin of the second analog-to-digital converter.

[0053] Under the synchronous compensation mechanism, the two analog-to-digital converters sample the input signal at the same absolute time point, with a sampling time deviation of less than 500ps. Each analog-to-digital converter continuously collects 4096 sampling points, forming a digital signal sequence of length 4096.

[0054] The first analog-to-digital converter outputs a first digital signal sequence, and the second analog-to-digital converter outputs a second digital signal sequence. Both are transmitted to the data processing and comparison module through a high-speed parallel interface or a serial JESD204B interface.

[0055] In step S4, the data processing and comparison module receives the first digital signal sequence and the second digital signal sequence, and identifies and outputs an abnormal signal indication by performing spectral coherence analysis and differential spectral threshold decision.

[0056] The data processing and comparison module first applies a Blackman-Harris window function to the first and second digital signal sequences, respectively. The time-domain expression of this window function is: Where N=4096, =0.35875, =0.48829, =0.14128, =0.01168, windowing operation is used to suppress spectral leakage and improve frequency domain resolution.

[0057] Subsequently, a 4096-point Fast Fourier Transform was performed on the two windowed sequences to obtain the first frequency domain spectrum. Second frequency domain spectrum The Fast Fourier Transform employs a radix-2 time decimation algorithm and is implemented in a pipelined manner within a field-programmable gate array, with a processing delay of less than 200 μs.

[0058] Next, the coherence function values ​​of the first and second frequency domain spectra at each frequency point are calculated. The coherence function is defined as the ratio of the squared magnitude of the cross-power spectral density estimated by averaging multiple frames of data to the product of the individual power spectral densities estimated by averaging multiple frames of data. Its mathematical expression is: in, The cross-power spectral density is obtained by averaging multiple frames of data; and These are the self-power spectral densities of the first and second signals, respectively.

[0059] The coherence function value lies between zero and one. Ideally, for perfectly consistent signals, the coherence function value approaches one. If there are abnormal signal disturbances, the coherence will decrease significantly.

[0060] The calculated coherence function value is compared with a preset coherence threshold, which is set to 999‰. If the coherence function value at any frequency point is lower than this threshold, an abnormal signal is determined to exist at that frequency point.

[0061] In parallel, the difference spectrum between the first and second frequency domain spectra is calculated. .

[0062] Meanwhile, the data processing and comparison module estimates the dynamic noise floor of the current frequency band in real time. The dynamic noise floor is obtained by statistically analyzing the historical minimum amplitude of each frequency point through a sliding window and correcting it in combination with ambient temperature and gain settings. If the amplitude of any signal peak in the differential spectrum exceeds ten decibels of the dynamic noise floor, it is determined that there is an abnormal signal.

[0063] When either the coherence analysis or the differential spectrum threshold decision is true, the data processing and comparison module finally outputs an abnormal signal indication. The abnormal signal indication includes the center frequency, bandwidth, duration, and confidence level of the abnormal signal, and is reported to the upper monitoring system through the universal asynchronous transceiver interface or the Ethernet interface.

[0064] An electromagnetic spectrum anomaly signal monitoring system based on dual acquisition and comparison includes a master clock generation unit, an adaptive clock synchronization compensation circuit, a dual-channel analog-to-digital conversion module, and a data processing and comparison module.

[0065] The master clock generation unit outputs the original clock signal to the adaptive clock synchronization compensation circuit. The adaptive clock synchronization compensation circuit outputs the first sampling clock and the second sampling clock to the dual-channel analog-to-digital converter module. The dual-channel analog-to-digital converter module receives the same RF input signal and, driven by the first sampling clock and the second sampling clock, outputs the first digital signal sequence and the second digital signal sequence to the data processing and comparison module, respectively. The data processing and comparison module executes the above analysis process and outputs an abnormal signal indication.

[0066] The clock distribution network, physical path delay quantization unit, digital control delay line, and closed-loop control logic unit in the adaptive clock synchronization compensation circuit are all integrated into a single field-programmable gate array chip.

[0067] The dual-channel analog-to-digital converter module uses two identical high-speed analog-to-digital converter chips in QFN package with symmetrical pin layout. The RF input signal is fed into the analog input terminals of the two analog-to-digital converters via a 1-to-2 power divider. The power divider has an insertion loss of less than 0.5dB, an amplitude imbalance of less than 0.2dB, and a phase imbalance of less than 1°.

[0068] The system was validated in the full temperature range of -40°C to 85°C. After working continuously for 24 hours in a high-temperature environment of 85°C, the dual-channel synchronization error remained stable within 700ps.

[0069] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects.

[0070] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment includes only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method of electromagnetic spectrum anomaly signal monitoring based on double acquisition contrast, characterized in that, The method comprises the following steps: S1, generating an original clock signal by a master clock generation unit; S2, inputting the original clock signal into an adaptive clock synchronization compensation circuit, and the adaptive clock synchronization compensation circuit performing physical path delay real-time quantization and feedforward compensation operations to generate a pair of first and second sampling clock signals after synchronization compensation; S3, the first and second sampling clock signals respectively driving first and second analog-to-digital converters to perform first and second time sequence sampling on the same radio frequency input signal, and obtaining first and second digital signal sequences respectively; S4, a data processing and comparison module receiving the first and second digital signal sequences, and identifying and outputting an abnormal signal indication by performing spectral coherence analysis and differential spectral threshold decision.

2. The dual-acquisition contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 1, wherein, The adaptive clock synchronization compensation circuit performs physical path delay real-time quantization and feedforward compensation operations, specifically including: A clock distribution network inside the adaptive clock synchronization compensation circuit distributes the original clock signal to a first compensation channel and a second compensation channel; In the first compensation channel, a first physical path delay quantization unit is used to periodically generate a first calibration pulse, and the first calibration pulse is returned through a first calibration loop matched with the physical transmission path of the first sampling clock to the first analog-to-digital converter, so as to measure the round-trip transmission time of the first calibration pulse, and calculate a first delay quantization value representing the first physical path delay based on the round-trip transmission time; A first closed-loop control logic unit generates a first digital control word based on the first delay quantization value, and outputs the first digital control word to a first digital control delay line arranged on the master clock path of the first compensation channel; The first digital control delay line applies an accurate compensation delay to the original clock signal passing through it according to the first digital control word, and the compensation delay forms a preset offset relationship in value with the first physical path delay, and finally outputs the first sampling clock; The second compensation channel performs physical path delay quantization and compensation operations consistent with the first compensation channel, and outputs the second sampling clock.

3. The dual-acquisition-contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 2, wherein, The first calibration loop matched with the physical transmission path is a section of metal wire on the printed circuit board, which is completely consistent with the clock signal wire of the first sampling clock to the first analog-to-digital converter in length, width, layer structure, via hole number and characteristic impedance, and the starting point and the ending point of the first calibration loop are connected to the first physical path delay quantization unit.

4. The dual-acquisition contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 3, wherein, The first physical path delay quantization unit specifically includes a time-to-digital converter, which quantizes the time interval between the departure of the first calibration pulse from the starting point and the return of the ending point through an internal tap delay chain and a latch array, and the quantization resolution is 10ps; The first closed-loop control logic unit obtains the one-way time value of the first physical path delay based on the output of the time-to-digital converter by performing a divide-by-two operation and subtracting an inherent device internal delay constant.

5. The dual-acquisition-contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 4, wherein, The first digital control delay line is composed of a series of cascaded logic gate units with variable delay characteristics, the first digital control word is a 16-bit binary number, which is used to control the number of turned-on logic gate units and the bias current of each unit, so as to realize step adjustment of the delay amount of the clock signal, and the adjustment step precision is 5 ps; the preset offset relationship formed by the compensation delay and the first physical path delay in the value is that the total delay after compensation is stabilized at a fixed system target delay value.

6. The dual-acquisition contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 1, wherein, The data processing and comparison module performs frequency spectrum coherence analysis and differential spectrum threshold decision, specifically including: The data processing and comparison module first applies a Blackman-Harris window function to the first digital signal sequence and the second digital signal sequence respectively; A 4096-point fast Fourier transform is performed on the two windowed sequences respectively to obtain a first frequency domain spectrum and a second frequency domain spectrum; The coherence function value of the first frequency domain spectrum and the second frequency domain spectrum at each frequency point is calculated, and the coherence function is defined as the ratio of the modulus square of the cross power spectral density to the product of the respective power spectral densities; The calculated coherence function value is compared with a preset coherence threshold, and the coherence threshold is 999‰, if the coherence function value of any frequency point is lower than the coherence threshold, it is determined that there is an abnormal signal; Meanwhile, the differential spectrum of the first frequency domain spectrum and the second frequency domain spectrum is calculated, and compared with a dynamic noise floor, if the amplitude of any signal peak in the differential spectrum exceeds the dynamic noise floor by ten decibels, it is determined that there is an abnormal signal; When either result of the coherence analysis or the differential spectrum threshold decision is true, the data processing and comparison module finally outputs an abnormal signal indication.

7. The dual-acquisition contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 2, wherein, It also includes a temperature sensing unit arranged in the printed circuit board area where the adaptive clock synchronization compensation circuit is located, for real-time monitoring of the working temperature of the circuit board; the first closed-loop control logic unit and the second closed-loop control logic unit also take the output of the temperature sensing unit as an auxiliary input, for increasing the execution frequency of the physical path delay quantization operation and accelerating the compensation response when the temperature changes dramatically; the reference execution period of the physical path delay quantization operation is 10 ms, and when the temperature change rate exceeds 1° / s, the execution period is shortened to 1 ms.

8. The dual-acquisition contrast-based electromagnetic spectrum anomaly signal monitoring method of claim 1, wherein, The main clock generation unit adopts a temperature-compensated crystal oscillator, and its working frequency is 100 MHz; The first analog-to-digital converter and the second analog-to-digital converter both have a resolution of 14 bits, and the sampling rate is set to 100 MSa / s; The data processing and comparison module and the closed-loop control logic units in the adaptive clock synchronization compensation circuit are all integrated in a field programmable gate array chip.

9. An electromagnetic spectrum anomaly signal monitoring system based on dual-acquisition contrast, characterized in that, It includes: A main clock generation unit for generating an original clock signal; An adaptive clock synchronization compensation circuit connected to the output end of the main clock generation unit for receiving the original clock signal and performing physical path delay real-time quantization and feedforward compensation operation, and outputting a pair of first sampling clock and second sampling clock after synchronization compensation; The dual-channel analog-to-digital conversion module comprises a first analog-to-digital converter and a second analog-to-digital converter, the first analog-to-digital converter and the second analog-to-digital converter respectively receive a first sampling clock and a second sampling clock as a sampling reference, and are connected to the same radio frequency input signal source, for performing first timing acquisition and second timing acquisition, and respectively output a first digital signal sequence and a second digital signal sequence; The data processing and comparison module is connected to the output ends of the first analog-to-digital converter and the second analog-to-digital converter, for receiving the first digital signal sequence and the second digital signal sequence, and identifying and outputting an abnormal signal indication by performing spectrum coherence analysis and differential spectrum threshold decision.

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