Equipment adaptive time synchronization method and device, terminal equipment and storage medium

Abstract

The invention is suitable for the technical field of intelligent terminals, and provides an equipment adaptive time synchronization method and device, terminal equipment and a storage medium, and the method comprises the steps: periodically detecting the instantaneous deviation between the local time of the equipment and the network reference time according to a synchronization period; calculating a predicted time error according to the instantaneous deviation, a predicted time window and a clock drift rate, the clock drift rate being determined based on the instantaneous deviation; the predicted time error is compared with an allowable error threshold value, and if the predicted time error is larger than the allowable error threshold value, time synchronization operation is triggered; after the time synchronization operation is triggered, the synchronization period is dynamically adjusted according to the clock drift rate, and the adjusted synchronization period is used for determining the time for detecting the instantaneous deviation next time. According to the invention, the device can adaptively balance time precision and resource consumption, so that the synchronization effect of high precision, low power consumption and network friendliness is realized.

Description

Technical Field

[0001] This application relates to the field of smart terminal technology, and in particular to a device adaptive time synchronization method, apparatus, terminal device, and storage medium. Background Technology

[0002] In many fields such as the Internet of Things (IoT), smart campuses, and industrial control, various intelligent terminal devices, such as electronic class signs, industrial control panels, and IoT data acquisition terminals, all rely on high-precision local clocks (RTCs) to ensure the normal operation of core functions. For example, electronic class signs in smart campuses need to display class schedules, collect attendance data, and perform scheduled power on / off tasks based on accurate time. Control terminals in industrial control scenarios need time synchronization to ensure the timing consistency of instructions executed by each node. Currently, these devices typically use the Network Time Protocol (NTP) for periodic time synchronization, and the synchronization effect directly affects the reliability of related functions.

[0003] In existing technologies, device time synchronization often adopts a fixed-period synchronization strategy. However, this strategy has inherent defects: on the one hand, the device's clock crystal will drift with temperature changes and device aging, and the drift rate is not constant. A fixed long synchronization period cannot correct the rapidly accumulated time deviation in time, resulting in a non-negligible error in device time. On the other hand, when the device clock itself is very stable, a fixed short synchronization period will still frequently initiate network synchronization, causing unnecessary network traffic and device power consumption.

[0004] Therefore, how to enable devices to adaptively balance time accuracy and resource consumption, thereby achieving high-precision, low-power, and network-friendly synchronization, is a problem that needs to be solved. Summary of the Invention

[0005] This application provides a device adaptive time synchronization method, apparatus, terminal device, and storage medium, which enables the device to adaptively balance time accuracy and resource consumption, thereby achieving a high-precision, low-power, and network-friendly synchronization effect.

[0006] In a first aspect, embodiments of this application provide a device adaptive time synchronization method, including: According to the synchronization cycle, the instantaneous deviation between the device's local time and the network reference time is periodically detected; The prediction time error is calculated based on the instantaneous deviation, the prediction time window, and the clock drift rate, wherein the clock drift rate is determined based on the instantaneous deviation. The predicted time error is compared with the allowable error threshold. If the predicted time error is greater than the allowable error threshold, a time synchronization operation is triggered. After the time synchronization operation is triggered, the synchronization period is dynamically adjusted according to the clock drift rate, wherein the adjusted synchronization period is used to determine the timing for the next detection of the instantaneous deviation.

[0007] In one possible implementation of the first aspect, determining the clock drift rate based on the instantaneous deviation during the first synchronization cycle includes: The clock drift rate is determined based on the instantaneous deviation and the time interval between the device's startup and the current detection. Alternatively, a preset initial drift rate can be used as the clock drift rate.

[0008] In one possible implementation of the first aspect, determining the clock drift rate based on the instantaneous deviation during non-first synchronization cycles includes: The current drift rate is determined based on the instantaneous deviation within the current synchronization cycle and the time interval between the completion of the last time synchronization operation and the start of this detection. Retrieve the recorded historical drift rate dataset; The clock drift rate is determined by fitting the historical drift rate dataset with the current drift rate using a smoothing algorithm.

[0009] In one possible implementation of the first aspect, the method further includes: After performing the time synchronization operation, a silent period is initiated, during which time synchronization operations are prohibited; or... After performing the time synchronization operation, the allowable error threshold is increased by a preset offset, and after a preset time or after the next time synchronization operation is completed, the allowable error threshold is restored to its original value.

[0010] In one possible implementation of the first aspect, dynamically adjusting the synchronization period based on the clock drift rate includes: Calculate the target period based on the allowable error threshold and the clock drift rate, such that the product of the target period and the clock drift rate is less than the allowable error threshold; The synchronization period is updated based on the target period.

[0011] In one possible implementation of the first aspect, updating the synchronization period based on the target period includes: Read the preset maximum and minimum synchronization periods, and constrain the target period between the maximum and minimum synchronization periods; If the clock drift rate is zero or the calculated target period exceeds the maximum synchronization period, then the synchronization period is set to the maximum synchronization period.

[0012] In one possible implementation of the first aspect, before comparing the prediction time error with the allowable error threshold, the method further includes: Determine whether the absolute value of the instantaneous deviation exceeds the absolute maximum tolerable deviation; If so, a time synchronization operation will be immediately triggered and an alarm will be generated.

[0013] Secondly, embodiments of this application provide a device adaptive time synchronization apparatus, comprising: The deviation detection unit is used to periodically detect the instantaneous deviation between the device's local time and the network reference time according to the synchronization cycle; An error prediction unit is used to calculate a prediction time error based on the instantaneous deviation, the prediction time window, and the clock drift rate, wherein the clock drift rate is determined based on the instantaneous deviation. A time synchronization unit is used to compare the predicted time error with an allowable error threshold. If the predicted time error is greater than the allowable error threshold, a time synchronization operation is triggered. The period adjustment unit is used to dynamically adjust the synchronization period according to the clock drift rate after the time synchronization operation is triggered, wherein the adjusted synchronization period is used to determine the timing for the next detection of the instantaneous deviation.

[0014] Thirdly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the device adaptive time synchronization method as described in the first aspect above.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the device adaptive time synchronization method as described in the first aspect above.

[0016] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the device adaptive time synchronization method as described in the first aspect above.

[0017] In this embodiment, the instantaneous deviation between the device's local time and the network reference time is periodically detected according to a synchronization cycle. The time offset is acquired in real time, providing accurate basic data support for subsequent error prediction and synchronization decisions. Then, the clock drift rate is determined based on this instantaneous deviation, and the predicted time error is calculated in conjunction with a prediction time window. This enables proactive prediction of future time deviation trends, overcoming the lag of passive response in fixed-cycle synchronization. Furthermore, the timing of synchronization is determined by comparing the predicted time error with an allowable error threshold. If the predicted time error exceeds the allowable error threshold, a time synchronization operation is triggered. This effectively avoids unnecessary synchronization operations when the predicted error is within the allowable range, effectively reducing unnecessary network requests, lowering network load, and reducing device power consumption. Moreover, after triggering the time synchronization operation, the synchronization cycle is dynamically adjusted according to the clock drift rate, allowing the synchronization frequency to adapt to the actual drift characteristics of the device's clock. This solution enables the device to intelligently balance synchronization accuracy and resource consumption while ensuring time accuracy, ultimately achieving a high-precision, low-power, and network-friendly synchronization effect. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the implementation of the device adaptive time synchronization method provided in this application embodiment; Figure 2 This is a flowchart illustrating a specific implementation of the device adaptive time synchronization method for determining the clock drift rate provided in this application embodiment; Figure 3 This is a flowchart illustrating a specific implementation of the device adaptive time synchronization method for generating alarm prompts provided in this application embodiment; Figure 4 This is a flowchart illustrating a specific implementation of step S104 in the device adaptive time synchronization method provided in this application embodiment; Figure 5 This is a flowchart illustrating a specific implementation of the device adaptive time synchronization method for verifying and updating the synchronization period provided in this application embodiment; Figure 6 This is a structural block diagram of the device adaptive time synchronization device provided in the embodiments of this application; Figure 7 This is a schematic diagram of the terminal device provided in the embodiments of this application. Detailed Implementation

[0020] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0021] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0022] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0024] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0026] By way of example and not limitation, the device adaptive time synchronization method provided in this application is applicable to various types of terminal devices that need to perform device adaptive time synchronization. Specific terminal devices may include mobile phones, tablets, wearable devices, laptops, ultra-mobile personal computers (UMPCs), desktop computers, interactive large screens, electronic class signs, and servers, etc. This application does not impose any restrictions on the specific type of terminal device.

[0027] Figure 1 The implementation flow of the device adaptive time synchronization method provided in this application embodiment is illustrated. The method flow includes steps S101 to S104. The specific implementation principle of each step is as follows: Step S101: Periodically detect the instantaneous deviation between the device's local time and the network reference time according to the synchronization cycle.

[0028] The synchronization cycle refers to the time interval between the execution of a complete detection, prediction, and decision-making process by the equipment, that is, the duration between two adjacent detection operations.

[0029] At the moment each synchronization cycle arrives, the device performs a detection operation, which simultaneously acquires the device's local time and the network reference time, and determines the instantaneous deviation based on both.

[0030] In one possible implementation, the detection operation is triggered by a monotonic timer, which does not depend on the device's local time and avoids inaccurate detection timing due to device local time drift.

[0031] The device's local time originates from its internal real-time clock (RTC), which naturally drifts during device operation and is a time reference that needs to be corrected. The network reference time is a standard time obtained from a time server via the NTP protocol, used to ensure time accuracy and consistency. The instantaneous deviation is determined based on the difference between the device's local time and the network reference time. The instantaneous deviation directly reflects the degree and state of the time offset between the device's local time and the standard time at the moment of detection, and its unit is seconds.

[0032] In this embodiment, the synchronization period is an adaptive variable that dynamically adapts to changes in the device clock state. Its initial value can be preset according to the needs of the device application scenario, but after each time synchronization operation is triggered, the synchronization period will be dynamically adjusted according to the device's clock drift rate.

[0033] For example, in a smart campus scenario, the initial synchronization period of the electronic class sign is set to 3600 seconds. When the electronic class sign reaches 3600 seconds, a detection operation is triggered to read the device's local time. Simultaneously, it requests the network reference time from the campus network time server via the Network Time Protocol (NAT) and calculates the instantaneous error between the device's local time and the network reference time. If the calculated local time is 2.1 seconds slower than the network reference time, the instantaneous deviation at that moment is +2.1 seconds. The subsequent synchronization period of the electronic class sign will be dynamically adjusted based on the clock drift rate.

[0034] In this embodiment, by periodically detecting instantaneous deviations, the device's time offset is continuously and proactively sensed, avoiding the accumulation of time deviations due to long-term lack of detection, thus providing accurate basic data support for subsequent error prediction and synchronization decisions.

[0035] Step S102: Calculate the prediction time error based on the instantaneous deviation, the prediction time window, and the clock drift rate, wherein the clock drift rate is determined based on the instantaneous deviation.

[0036] The prediction time window is a preset future time period, a parameter used for forward error prediction, and its initial value is a preset value. In one possible implementation, the initial value of the prediction time window is set based on experience or scenario requirements, for example, 3600 seconds. From the second calculation of the prediction time error onwards, the setting of the prediction time window depends on the previous synchronization cycle.

[0037] Clock drift rate refers to the offset of a device's local time relative to the network reference time per unit of time, measured in seconds per second. Clock drift rate reflects the rate at which a device's time drifts.

[0038] Predicted time error refers to the time deviation that the device may experience at the end of the predicted time window, based on the current instantaneous deviation and clock drift rate.

[0039] In one possible implementation, the prediction time error is calculated and determined according to the following formula (1): (1) in, Indicates the prediction time error. R represents the instantaneous deviation, and R represents the time drift rate. This indicates the prediction time window.

[0040] In this embodiment, the predicted time error is used to determine whether a time synchronization operation needs to be triggered subsequently. By quantifying the rate of time drift of the device through the clock drift rate and combining it with the predicted time window to actively estimate future errors, it is possible to predict in advance whether the time accuracy will exceed the allowable range, thus avoiding time deviations exceeding the allowable range due to lag correction.

[0041] In one possible implementation, a preset initial drift rate is used as the clock drift rate during the first synchronization cycle. This preset initial drift rate is an empirical or theoretical value set before the device leaves the factory or during the device initialization phase, and it does not depend on the initial detection result. The preset initial drift rate is used as the clock drift rate even when the instantaneous deviation is zero or invalid.

[0042] In one possible implementation, the preset initial drift rate can be set based on the accuracy specifications of the RTC chip used by the device and stored in the device's memory. For example, it can be set directly to 0 seconds / second (assuming the device clock is ideal and drift-free), or set to a conservative positive or negative empirical value (such as ±0.0002 seconds / second).

[0043] For example, for a batch of electronic class signs in a smart campus that use crystal oscillators of the same precision, the initial drift rate can be uniformly set to 0 seconds / second in the factory configuration, and the device clock of the electronic class sign is initially considered to be drift-free.

[0044] In this embodiment, during the first synchronization cycle, there is no need to wait for the detection operation to be triggered and the instantaneous deviation calculation to be performed. The preset initial drift rate is directly read from the device storage unit and used as the current clock drift rate. This avoids the risk that the instantaneous deviation data may be unreliable due to the delay or failure of the first network request in the early stage of device startup, thereby calculating the abnormal drift rate.

[0045] In one possible implementation, during the first synchronization cycle, the clock drift rate is determined based on the instantaneous deviation and the time interval between the device's startup and the current detection. Specifically, the clock drift rate is determined based on the ratio of the instantaneous deviation to the time interval between the device's startup and the current detection.

[0046] The time interval between device startup and the current test refers to the length of time elapsed from when the device is powered on to when the current test operation is triggered. This time interval can be measured using an independent monotonic timer. In scenarios where the first test operation is successfully completed within the first synchronization cycle, the average time drift rate of the device from startup to the current moment can be reflected by dividing the instantaneous deviation detected for the first time by the clock drift rate determined by this time interval.

[0047] For example, when a smart meter is powered on for the first time, its internal monotonic timer records the time interval from startup to the first detection operation as 10,000 seconds. The device's local time obtained during the first detection is compared with the network reference time, and the instantaneous deviation is calculated to be +1.0 second (i.e., the local time is 1.0 second ahead). Therefore, the clock drift rate at this time is: 1.0 second / 10,000 seconds = 0.0001 seconds / second. This value indicates that the smart meter's device clock is on average 0.0001 seconds ahead of the standard time.

[0048] In this embodiment, the initial clock drift rate based on the actual operating performance of the device is quickly estimated using the first segment of operating data after the device is started. This ensures that an accurate and effective clock drift rate can be obtained within the first synchronization cycle, providing a relatively objective initial basis for subsequent prediction time error calculation. Compared with a fixed preset value, it can reflect the initial characteristics of the device more quickly.

[0049] As one possible implementation of this application, during non-first synchronization cycles... Figure 2 This paper illustrates a specific implementation flow of determining the clock drift rate in the device adaptive time synchronization method provided in an embodiment of this application, which is described in detail below: A1: Determine the current drift rate based on the instantaneous deviation within the current synchronization cycle and the time interval between the completion of the last time synchronization operation and the start of this detection.

[0050] The time interval between the completion of the last time synchronization operation and the start of the current detection refers to the length of time elapsed from the moment the device completed the last time synchronization operation to the moment the current detection operation is triggered within the current synchronization cycle. This time interval is also obtained through the device's built-in monotonic timer, independent of the device's local time, ensuring the accuracy of the duration data. Specifically, in scenarios where the detection operation is successfully completed in a period other than the first synchronization cycle, the current drift rate is determined based on the ratio of the currently detected instantaneous deviation to the time interval between the completion of the last time synchronization operation and the start of the current detection. This current drift rate reflects the average drift rate within the most recent period without synchronization intervention. Normally, if the device successfully triggers and completes the time synchronization operation in the previous synchronization cycle, the time interval between the start of the current detection and the completion of the last time synchronization operation is numerically equal to the length of the current synchronization cycle. In abnormal situations where the predicted time error does not exceed the allowable error threshold for multiple consecutive synchronization cycles, and therefore no time synchronization operation is triggered, the time interval between the start of the current detection and the completion of the last actual time synchronization operation will be the cumulative sum of the durations of multiple consecutive synchronization cycles.

[0051] For example, suppose an industrial gateway completes a time synchronization operation at 10:00 AM, and the instantaneous deviation is reset to zero after synchronization. Subsequently, the device operates according to a dynamically adjusted synchronization cycle, and initiates the next detection at 2:00 PM (i.e., 4 hours later). The detection shows that the current instantaneous deviation is +1.44 seconds. Therefore, the time interval from the last synchronization to this detection is 4 hours (14400 seconds). The current drift rate is the ratio of +1.44 seconds to 14400 seconds, which is +0.0001 seconds. This current drift rate quantifies the trend of the industrial gateway's device clock gaining an average of 0.0001 seconds per second over the past 4 hours.

[0052] A2: Obtain the recorded historical drift rate dataset.

[0053] The historical drift rate dataset is a collection of clock drift rates calculated for all completed synchronization cycles prior to the current synchronization cycle. If the current cycle is the second synchronization cycle, meaning the device has only completed one time synchronization operation, then the historical drift rate dataset only includes the clock drift rates calculated for the first synchronization cycle.

[0054] In one possible implementation, the historical drift rate dataset is stored in the device's non-volatile memory unit, with each data entry accompanied by a corresponding timestamp used to record the synchronization period corresponding to the respective clock drift rate.

[0055] The historical drift rate dataset reflects the time drift patterns of devices at different stages, and its size increases as the device's operating time grows.

[0056] A3: The clock drift rate is determined by fitting the historical drift rate dataset with the current drift rate using a smoothing algorithm.

[0057] Smoothing algorithms are used to reduce data fluctuations and make data more stable. By using smoothing algorithms to fit historical drift rate datasets with the current drift rate, a more stable, reliable clock drift rate that better reflects the true long-term drift trend of the device clock is determined, thereby improving the reliability of predicted time errors.

[0058] In one possible implementation, the smoothing algorithm includes any one of a moving average, a weighted average, or an exponentially weighted moving average.

[0059] In one possible implementation, the clock drift rate is the average of the current drift rate and the historical clock drift rates in the historical drift rate dataset.

[0060] In one possible implementation, the clock drift rate R is determined according to the following formula (2): (2) Where α is the smoothing factor, 0 < α < 1, The current drift rate, This represents the mean of historical clock drift rates in the historical drift rate dataset. Adjusting α controls the trust weights between the current drift data and the historical drift data.

[0061] In this embodiment, the impact of fluctuations in single-cycle data is weakened by smooth fitting, resulting in a stable and reliable clock drift rate. This allows the clock drift rate to better reflect the long-term real drift trend of the device, avoiding distortion in subsequent prediction time error calculations and unreasonable synchronization cycle adjustments due to single data deviations, thereby improving the accuracy and stability of the entire time synchronization mechanism.

[0062] Step S103: Compare the predicted time error with the allowable error threshold. If the predicted time error is greater than the allowable error threshold, then trigger the time synchronization operation.

[0063] The permissible error threshold is a preset maximum acceptable time deviation value for the device. This permissible error threshold can be set according to the accuracy requirements of the device's application scenario. For example, for electronic class sign devices used for attendance statistics, the permissible error threshold can be set to 3 seconds; for industrial control equipment with higher accuracy requirements, it can be set to 0.5 seconds. The permissible error threshold is the core benchmark for determining whether synchronization needs to be triggered.

[0064] Time synchronization refers to the process by which a device sends a time synchronization request to a time server via the network to obtain the latest network reference time, and then corrects the device's local time according to the network reference time to make the device's local time consistent with the network reference time. After the time synchronization operation is completed, the deviation of the device's local time is cleared to zero.

[0065] In this embodiment, the calculated prediction time error is compared with a preset allowable error threshold. Time synchronization is triggered only when the prediction time error is greater than the allowable error threshold. If the prediction time error is less than or equal to the allowable error threshold, synchronization is not triggered and the detection and judgment are postponed to the next synchronization cycle.

[0066] For example, the electronic class sign device has a preset allowable error threshold of 3 seconds. Based on the instantaneous deviation, the prediction time window, and the clock drift rate, the predicted time error is calculated to be 4 seconds. The 4 seconds are compared with the allowable error threshold of 3 seconds. Since 4 seconds > 3 seconds, the time synchronization operation is triggered: the device sends a synchronization request to the campus network time server to obtain the latest network reference time and corrects the device's local time to the network reference time. After the synchronization is completed, the instantaneous deviation is cleared to zero. If the calculated predicted time error is 2 seconds, which is less than the allowable error threshold of 3 seconds, the synchronization operation is not triggered, and the device waits for the next synchronization cycle to perform the detection.

[0067] In this embodiment, by comparing the predicted time error with the allowable error threshold, potential time accuracy risks can be accurately identified in the future. Synchronization is triggered only when a risk exists, thus achieving precise triggering of time synchronization operations, effectively reducing the frequency of synchronization operations, thereby reducing network bandwidth usage and device power consumption, and achieving rational utilization of resources.

[0068] As one possible implementation of this application, such as Figure 3 As shown, before comparing the prediction time error with the allowable error threshold, the method further includes: B1: Determine whether the absolute value of the instantaneous deviation exceeds the absolute maximum tolerance deviation.

[0069] The absolute value of the instantaneous deviation directly reflects the actual degree to which the equipment time deviates from the standard time at the moment of detection, and is the core basis for judging whether the equipment is in a state of serious inaccuracy. The absolute maximum tolerable deviation is the maximum time deviation limit that the equipment can tolerate.

[0070] In one possible implementation, the absolute maximum tolerance deviation is a preset value. When the device's time deviation (the absolute value of the instantaneous deviation) exceeds this absolute maximum tolerance deviation, it will directly lead to the failure of the device's core functions, such as errors in attendance statistics and disruptions in scheduled tasks. Therefore, the preset value of the absolute maximum tolerance deviation is higher than the allowable error threshold.

[0071] B2: If so, the time synchronization operation will be triggered immediately and an alarm will be generated.

[0072] When the absolute value of the instantaneous deviation exceeds the absolute maximum tolerable deviation, a time synchronization request is immediately sent to the time server to obtain the latest network reference time, and the device's local time is forcibly corrected to the network reference time. At the same time, an alarm is generated to indicate that the device's time is seriously inaccurate, and subsequent prediction time error calculation and comparison steps are no longer performed.

[0073] In one possible implementation, the alarm output method can be set according to the application scenario, including but not limited to flashing local indicator lights on the device (such as high-frequency flashing of a red indicator light), sending alarm messages to the backend management system (alarm information includes device number, time of inaccuracy, instantaneous deviation value, etc.), and emitting alarm sounds through the device's built-in speaker. The alarm should continue until the device completes time synchronization and the deviation returns to the allowable range, after which it should be automatically cleared by the system or manually cleared by the backend administrator.

[0074] For example, the allowable error threshold for electronic class signage is 3 seconds, and the absolute maximum tolerance deviation can be set to 10 seconds; the allowable error threshold for industrial control equipment is 0.5 seconds, and the absolute maximum tolerance deviation can be set to 2 seconds. When the time deviation of the electronic class signage exceeds 10 seconds, or the time deviation of the industrial control equipment exceeds 2 seconds, a time synchronization operation is immediately triggered, and an alarm is generated to remind the user that the equipment is faulty.

[0075] When the instantaneous deviation exceeds the absolute maximum tolerable deviation, the core function of the equipment is at risk of failure. No further prediction calculation is needed, and emergency handling must be initiated immediately. This application embodiment quickly identifies the scenario through pre-judgment, quickly eliminates severe time deviation through emergency synchronization, and visualizes the problem through alarm prompts.

[0076] Step S104: After triggering the time synchronization operation, dynamically adjust the synchronization period according to the clock drift rate.

[0077] The adjusted synchronization period is used to determine the timing for the next detection of the instantaneous deviation.

[0078] In this embodiment, the timing of the synchronization period adjustment depends on the triggering of the time synchronization operation. That is, the synchronization period adjustment is only performed after the time synchronization operation is triggered. The core basis for the adjustment is the clock drift rate calculated in step S102.

[0079] In one possible implementation, when the clock drift rate is high, the synchronization period can be shortened accordingly to ensure time accuracy, and when the clock drift rate is low, the synchronization period can be appropriately extended to save resources, thereby achieving an adaptive balance between time accuracy and resource consumption.

[0080] As one possible implementation of this application Figure 4 A specific implementation flow of step S104 in the device adaptive time synchronization method provided in this application embodiment is shown below: C1: Calculate the target period based on the allowable error threshold and the clock drift rate, such that the product of the target period and the clock drift rate is less than the allowable error threshold.

[0081] The target period is the theoretical synchronization period length obtained through quantitative calculation in order to achieve the goal of ensuring that the time deviation within the synchronization period does not exceed the allowable error threshold.

[0082] In this embodiment, " "As a constraint, the reasonable range of values ​​for the target period is calculated through mathematical derivation. Then, the largest reasonable value within this range is selected as the target period. Selecting the largest reasonable value can maximize the extension of the synchronization period and reduce the synchronization frequency to reduce resource consumption."

[0083] C2: Update the synchronization period based on the target period.

[0084] The update synchronization cycle refers to determining the effective duration of the next synchronization cycle based on the calculated target cycle, storing this effective duration in the device, replacing the original synchronization cycle, and using it to trigger the next detection operation.

[0085] In this embodiment, the constraints for determining the target period are based on the clock drift rate and the allowable error threshold. This ensures that the target period meets the time accuracy requirements of the device and avoids deviations exceeding the allowable range due to excessively long synchronization periods. At the same time, selecting the largest reasonable value as the target period can minimize the synchronization frequency while ensuring accuracy, thereby reducing network bandwidth usage and device power consumption, and achieving a preliminary balance between accuracy and resource consumption.

[0086] The target period is not the final effective synchronization period. It needs to be verified before it can be determined whether to adopt it directly or after adjustment.

[0087] As one possible implementation of this application Figure 5 The following is a detailed implementation flow of verifying the update synchronization period in the device adaptive time synchronization method provided in this application embodiment: D1: Read the preset maximum synchronization period and minimum synchronization period, and constrain the target period between the maximum synchronization period and the minimum synchronization period.

[0088] The preset maximum synchronization period is the longest allowed value of the synchronization period preset by the device, while the preset minimum synchronization period is the shortest allowed value of the synchronization period preset by the device.

[0089] The purpose of setting a maximum synchronization period is to prevent the device from not performing time checks for a long time due to an excessively long synchronization period, thus failing to detect sudden clock drift anomalies in a timely manner. On the other hand, the purpose of setting a minimum synchronization period is to prevent the synchronization operation from being too frequent due to an excessively short synchronization period, which would over-consume network bandwidth and device power consumption, and at the same time indicate that the device may have clock drift anomalies.

[0090] In this embodiment, the updated synchronization period is compared with two limits (maximum synchronization period and minimum synchronization period) to perform range constraints, and the updated synchronization period is constrained to be between the maximum synchronization period and the minimum synchronization period. That is, the updated synchronization period is constrained to not exceed the maximum synchronization period and not be less than the minimum synchronization period.

[0091] D2: If the clock drift rate is zero or the calculated target period exceeds the maximum synchronization period, then the synchronization period is set to the maximum synchronization period.

[0092] When the clock drift rate is zero, theoretically the device has no time drift, or the target period exceeds the maximum synchronization period. In this case, the synchronization period is set to the maximum synchronization period.

[0093] In one possible implementation, if the updated synchronization period is between the maximum and minimum synchronization periods (inclusive of both limits), the updated synchronization period is retained as the effective period; if the updated synchronization period is greater than the maximum synchronization period, the maximum synchronization period is used as the effective period; if the updated synchronization period is less than the minimum synchronization period, the minimum synchronization period is used as the effective period, and an alarm is generated to indicate that the device clock drift rate is abnormal and there may be a hardware failure.

[0094] In this embodiment, the synchronization period after the initial update is constrained by two preset limits: a maximum synchronization period and a minimum synchronization period. This ensures the rationality of the synchronization period and the safety of device operation, preventing the failure to detect sudden drift due to an excessively long synchronization period, or the waste of resources due to an excessively short synchronization period. When the clock drift rate is zero, using the maximum synchronization period minimizes resource consumption. When the target period exceeds the maximum limit, using the maximum synchronization period balances the need to extend the synchronization period with the need to ensure timely detection, avoiding imbalance in the synchronization strategy under extreme scenarios.

[0095] In one possible implementation, after performing the time synchronization operation, a quiet period is initiated, during which triggering the time synchronization operation is prohibited. The quiet period refers to a preset fixed duration after the device completes the time synchronization operation, during which the device is prohibited from triggering the time synchronization operation again. During the quiet period, regardless of whether the calculated predicted time error is greater than the allowable error threshold, the device will not initiate a new network synchronization request until the quiet period ends.

[0096] In one possible implementation, the quiet period can be set according to the clock stability requirements of the device's application scenario, and the quiet period may vary in different application scenarios. The timing of the quiet period is also implemented through the device's built-in monotonic timer, which does not depend on the device's local time.

[0097] In this embodiment, by setting a quiet period to force the device to cool down synchronously, synchronization is avoided from being triggered again in a short time after the time synchronization operation is completed. This reduces unnecessary resource consumption and ensures the stability of the device clock, which can effectively enhance device stability and save network resources.

[0098] In one possible implementation, after performing the time synchronization operation, the permissible error threshold is increased by a preset offset, and after a preset time or after completing the next time synchronization operation, the permissible error threshold is restored to its original value. The preset offset is a fixed value set in advance to increase the permissible error threshold. This value is set according to the clock stability characteristics after device synchronization, and the preset offset is less than the absolute maximum tolerable deviation.

[0099] After performing a time synchronization operation, a preset offset is temporarily added to the original allowable error threshold to obtain a temporary allowable error threshold. Subsequent determinations regarding whether to trigger synchronization are based on this temporary allowable error threshold, not the original threshold. After a preset duration or after the next time synchronization operation is completed, the temporary allowable error threshold is restored to the original allowable error threshold.

[0100] In one possible implementation, the allowable error threshold is adaptively increased or decreased based on the long-term operating status of the device or changes in external network conditions. Specifically, the quality of the network connection between the monitoring device and the time server is monitored; when the network connection quality is higher than a preset standard, the allowable error threshold is increased; when the network connection quality is lower than the preset standard, the allowable error threshold is decreased.

[0101] In this embodiment of the application, by dynamically adjusting the allowable error threshold, the short-term stability of the device clock after synchronization and the flexibility of the synchronization strategy can be effectively balanced.

[0102] As can be seen from the above, in this embodiment, by periodically detecting the instantaneous deviation between the device's local time and the network reference time according to the synchronization cycle, the time offset is obtained in real time, providing accurate basic data support for subsequent error prediction and synchronization decisions. Then, based on the instantaneous deviation, the clock drift rate is determined, and the predicted time error is calculated in combination with the prediction time window, realizing the proactive prediction of future time deviation trends. This overcomes the lag of passive response in fixed-cycle synchronization. Furthermore, by comparing the predicted time error with the allowable error threshold, it is determined whether to trigger the synchronization operation. If the predicted time error is greater than the allowable error threshold, the time synchronization operation is triggered, which can effectively avoid unnecessary synchronization operations when the predicted error is within the allowable range, effectively reducing unnecessary network requests, reducing network load and device power consumption. Moreover, after triggering the time synchronization operation, the synchronization cycle is dynamically adjusted according to the clock drift rate, so that the synchronization frequency can adapt to the actual drift characteristics of the device clock. This solution enables the device to intelligently balance synchronization accuracy and resource consumption while ensuring time accuracy, ultimately achieving a high-precision, low-power, and network-friendly synchronization effect.

[0103] As one possible implementation of this application, the adaptive time synchronization method provided in this embodiment can be extended from a single device to a device cluster, achieving better synchronization management through cloud collaboration. In this implementation, multiple devices deployed in the same area or scenario, while running the single-machine adaptive synchronization method, periodically report their own operating data, such as instantaneous deviation, calculated clock drift rate, chip temperature, device runtime, and geographical location information, to a cloud server. The cloud server aggregates this operating data, constructs a large database of drift characteristics covering a wide range of hardware conditions and environmental factors, and uses a machine learning model to analyze the implicit correlation and long-term variation patterns between clock drift rate and temperature, season, hardware batch, and aging degree, thereby training and generating a predictive drift model. Subsequently, when each device needs to determine a synchronization strategy, it can send a query request containing its current operating status (such as current temperature and cumulative runtime) to the drift model on the cloud server. The drift model performs inference and returns a suggested synchronization cycle value optimized for the current operating status of the device. The device can adopt this suggested value as its next synchronization cycle, thereby obtaining a more accurate and forward-looking synchronization rhythm than relying solely on its own limited historical data. The embodiments of this application upgrade the adaptive learning of a single point to the collaborative intelligence of a cluster, further improving the synchronization accuracy and long-term energy efficiency.

[0104] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0105] Corresponding to the device adaptive time synchronization method described in the above embodiments, Figure 6 A structural block diagram of the device adaptive time synchronization device provided in the embodiments of this application is shown. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0106] Reference Figure 6 The adaptive time synchronization device of the equipment includes: a deviation detection unit 61, an error prediction unit 62, a time synchronization unit 63, and a period adjustment unit 64, wherein: Deviation detection unit 61 is used to periodically detect the instantaneous deviation between the device's local time and the network reference time according to the synchronization cycle; Error prediction unit 62 is used to calculate prediction time error based on the instantaneous deviation, prediction time window and clock drift rate, wherein the clock drift rate is determined based on the instantaneous deviation; The time synchronization unit 63 is used to compare the predicted time error with the allowable error threshold. If the predicted time error is greater than the allowable error threshold, a time synchronization operation is triggered. The period adjustment unit 64 is used to dynamically adjust the synchronization period according to the clock drift rate after the time synchronization operation is triggered, wherein the adjusted synchronization period is used to determine the timing for the next detection of the instantaneous deviation.

[0107] As one possible implementation of this application, the error prediction unit 62 includes: The first drift rate determination module is used to determine the clock drift rate within the first synchronization cycle based on the instantaneous deviation and the time interval between the device's self-start and the current detection; or, to use a preset initial drift rate as the clock drift rate.

[0108] As one possible implementation of this application, the error prediction unit 62 includes: The second drift rate determination module is used to determine the current drift rate based on the instantaneous deviation within the current synchronization cycle and the time interval between the completion of the last time synchronization operation and the start of the current detection; obtain the recorded historical drift rate dataset; and use a smoothing algorithm to fit the historical drift rate dataset with the current drift rate to determine the clock drift rate.

[0109] As one possible implementation of this application, the device adaptive time synchronization device further includes: The hysteresis processing unit is used to initiate a silent period after performing the time synchronization operation, during which the triggering of the time synchronization operation is prohibited; or, after performing the time synchronization operation, increase the allowable error threshold by a preset offset, and restore the allowable error threshold to its original value after a preset duration or after the next time synchronization operation is completed.

[0110] As one possible implementation of this application, the period adjustment unit 64 includes: The period adjustment module is used to calculate a target period based on the allowable error threshold and the clock drift rate, so that the product of the target period and the clock drift rate is less than the allowable error threshold; and to update the synchronization period based on the target period.

[0111] As one possible implementation of this application, the period adjustment module is further configured to: Read the preset maximum synchronization period and minimum synchronization period, and constrain the target period between the maximum synchronization period and the minimum synchronization period; if the clock drift rate is zero or the calculated target period exceeds the maximum synchronization period, then set the synchronization period to the maximum synchronization period.

[0112] As one possible implementation of this application, the device adaptive time synchronization device further includes: An alarm notification unit is used to determine whether the absolute value of the instantaneous deviation exceeds the absolute maximum tolerable deviation; if so, it immediately triggers a time synchronization operation and generates an alarm notification.

[0113] As can be seen from the above, in this embodiment, by periodically detecting the instantaneous deviation between the device's local time and the network reference time according to the synchronization cycle, the time offset is obtained in real time, providing accurate basic data support for subsequent error prediction and synchronization decisions. Then, based on the instantaneous deviation, the clock drift rate is determined, and the predicted time error is calculated in combination with the prediction time window, realizing the proactive prediction of future time deviation trends. This overcomes the lag of passive response in fixed-cycle synchronization. Furthermore, by comparing the predicted time error with the allowable error threshold, it is determined whether to trigger the synchronization operation. If the predicted time error is greater than the allowable error threshold, the time synchronization operation is triggered, which can effectively avoid unnecessary synchronization operations when the predicted error is within the allowable range, effectively reducing unnecessary network requests, reducing network load and device power consumption. Moreover, after triggering the time synchronization operation, the synchronization cycle is dynamically adjusted according to the clock drift rate, so that the synchronization frequency can adapt to the actual drift characteristics of the device clock. This solution enables the device to intelligently balance synchronization accuracy and resource consumption while ensuring time accuracy, ultimately achieving a high-precision, low-power, and network-friendly synchronization effect.

[0114] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0115] This application embodiment also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements... Figures 1 to 5 The steps of any device adaptive time synchronization method are represented.

[0116] This application embodiment also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements... Figures 1 to 5 The steps of any device adaptive time synchronization method are represented.

[0117] This application also provides a computer program product that, when run on a terminal device, causes the terminal device to execute the implementation of... Figures 1 to 5 The steps of any device adaptive time synchronization method are represented.

[0118] Figure 7 This is a schematic diagram of a terminal device provided in an embodiment of this application. For example... Figure 7 As shown, the terminal device 7 in this embodiment includes: a processor 70, a memory 71, and a computer program 72 stored in the memory 71 and executable on the processor 70. When the processor 70 executes the computer program 72, it implements the steps in the aforementioned embodiments of the device adaptive time synchronization method, for example... Figure 1 Steps S101 to S104 are shown. Alternatively, when the processor 70 executes the computer program 72, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 6 The functions of units 61 to 64 are shown.

[0119] For example, the computer program 72 may be divided into one or more modules / units, which are stored in the memory 71 and executed by the processor 70 to complete this application. The one or more modules / units may be a series of computer-readable instruction segments capable of performing a specific function, which describe the execution process of the computer program 72 in the terminal device 7.

[0120] The terminal device 7 may include, but is not limited to, a processor 70 and a memory 71. Those skilled in the art will understand that... Figure 7 This is merely an example of terminal device 7 and does not constitute a limitation on terminal device 7. It may include more or fewer components than shown, or combine certain components, or different components. For example, terminal device 7 may also include input / output devices, network access devices, buses, etc.

[0121] The processor 70 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0122] The memory 71 can be an internal storage unit of the terminal device 7, such as a hard disk or memory of the terminal device 7. The memory 71 can also be an external storage device of the terminal device 7, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the terminal device 7. Furthermore, the memory 71 can include both internal and external storage units of the terminal device 7. The memory 71 is used to store the computer program and other programs and data required by the terminal device. The memory 71 can also be used to temporarily store data that has been output or will be output.

[0123] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0124] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0125] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0127] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A device adaptive time synchronization method, characterized in that, include: According to the synchronization cycle, the instantaneous deviation between the device's local time and the network reference time is periodically detected; The prediction time error is calculated based on the instantaneous deviation, the prediction time window, and the clock drift rate, wherein the clock drift rate is determined based on the instantaneous deviation. The predicted time error is compared with the allowable error threshold. If the predicted time error is greater than the allowable error threshold, a time synchronization operation is triggered. After the time synchronization operation is triggered, the synchronization period is dynamically adjusted according to the clock drift rate, wherein the adjusted synchronization period is used to determine the timing for the next detection of the instantaneous deviation.

2. The method according to claim 1, characterized in that, During the first synchronization cycle, determining the clock drift rate based on the instantaneous deviation includes: The clock drift rate is determined based on the instantaneous deviation and the time interval between the device's startup and the current detection. Alternatively, a preset initial drift rate can be used as the clock drift rate.

3. The method according to claim 1, characterized in that, During non-first synchronization cycles, determining the clock drift rate based on the instantaneous deviation includes: The current drift rate is determined based on the instantaneous deviation within the current synchronization cycle and the time interval between the completion of the last time synchronization operation and the start of this detection. Retrieve the recorded historical drift rate dataset; The clock drift rate is determined by fitting the historical drift rate dataset with the current drift rate using a smoothing algorithm.

4. The method according to claim 1, characterized in that, The method further includes: After performing the time synchronization operation, a silent period is initiated, during which time synchronization operations are prohibited; or... After performing the time synchronization operation, the allowable error threshold is increased by a preset offset, and after a preset time or after the next time synchronization operation is completed, the allowable error threshold is restored to its original value.

5. The method according to claim 1, characterized in that, The step of dynamically adjusting the synchronization period based on the clock drift rate includes: Calculate the target period based on the allowable error threshold and the clock drift rate, such that the product of the target period and the clock drift rate is less than the allowable error threshold; The synchronization period is updated based on the target period.

6. The method according to claim 5, characterized in that, The step of updating the synchronization period based on the target period includes: Read the preset maximum and minimum synchronization periods, and constrain the target period between the maximum and minimum synchronization periods; If the clock drift rate is zero or the calculated target period exceeds the maximum synchronization period, then the synchronization period is set to the maximum synchronization period.

7. The method according to any one of claims 1 to 6, characterized in that, Before comparing the prediction time error with the allowable error threshold, the method further includes: Determine whether the absolute value of the instantaneous deviation exceeds the absolute maximum tolerable deviation; If so, a time synchronization operation will be immediately triggered and an alarm will be generated.

8. A device adaptive time synchronization device, characterized in that, include: The deviation detection unit is used to periodically detect the instantaneous deviation between the device's local time and the network reference time according to the synchronization cycle; An error prediction unit is used to calculate a prediction time error based on the instantaneous deviation, the prediction time window, and the clock drift rate, wherein the clock drift rate is determined based on the instantaneous deviation. A time synchronization unit is used to compare the predicted time error with an allowable error threshold. If the predicted time error is greater than the allowable error threshold, a time synchronization operation is triggered. The period adjustment unit is used to dynamically adjust the synchronization period according to the clock drift rate after the time synchronization operation is triggered, wherein the adjusted synchronization period is used to determine the timing for the next detection of the instantaneous deviation.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the device adaptive time synchronization method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the device adaptive time synchronization method as described in any one of claims 1 to 7.

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