Wide voltage power supply band-gap reference source circuit, ferroelectric memory and circuit control method

Abstract

The invention relates to the technical field of circuits, in particular to a wide-voltage power supply band-gap reference source circuit, a ferroelectric memory and a circuit control method.The circuit comprises a voltage stabilizing circuit, a starting circuit, a control circuit, a temperature compensation circuit and an amplifying circuit, and the voltage stabilizing circuit conducts voltage stabilizing adjustment on a received voltage signal to obtain a voltage stabilizing signal; the starting circuit is used for generating an activation signal according to the voltage-stabilizing signal; the control circuit is respectively connected with the voltage stabilizing circuit and the starting circuit to generate a reference control signal; the temperature compensation circuit obtains a temperature compensation signal according to the reference control signal; and the amplifying circuit is respectively connected with the other circuit points to generate a final reference circuit signal, so that the problem that the performance of the ferroelectric memory is reduced due to the fact that the suppression capability of the circuit on external power supply noise and ripple waves is reduced under the condition that the external power supply voltage is relatively wide and relatively high in the prior art is solved, and the overall performance of the ferroelectric memory is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a wide voltage supply bandgap reference source circuit, ferroelectric memory and circuit control method. BACKGROUND

[0002] At present, when the external supply voltage is wide and high, the current mirror of the bandgap reference source maintaining constant current gradually fails due to the channel modulation effect, resulting in the decrease of the PSR of the bandgap reference source, and the suppression ability of the circuit to the noise or ripple from the external supply is reduced, thereby causing the performance of the ferroelectric memory to decrease.

[0003] In view of the above problems, the related art designs a voltage stabilizer in front of the bandgap reference source, so that the external supply is supplied to the bandgap reference source through the voltage stabilizer, so that the supply of the bandgap reference source is reduced under high voltage, the PSR is improved, and the overall circuit performance is improved.

[0004] However, the voltage stabilizer in the related art reduces the high voltage supply, but also reduces the low voltage supply, reduces the circuit performance of the bandgap reference source, and causes the performance of the ferroelectric memory to decrease, which needs to be solved urgently. SUMMARY

[0005] The present application provides a wide voltage supply bandgap reference source circuit, ferroelectric memory and circuit control method to solve the problem of the related art that the suppression ability of the circuit to the noise and ripple from the external supply is reduced under the condition that the external supply voltage is wide and high, thereby improving the overall performance of the ferroelectric memory.

[0006] To achieve the above purpose, the first aspect of the present application provides a wide voltage supply bandgap reference source circuit, comprising: a voltage stabilizing circuit, a starting circuit, a control circuit, a temperature compensation circuit and an amplification circuit, wherein, The voltage stabilizing circuit is used for stabilizing and adjusting the received voltage signal to obtain a stabilized voltage signal; The starting circuit is used for generating an activation signal according to the stabilized voltage signal; The control circuit is connected with the voltage stabilizing circuit and the starting circuit respectively, and is used for obtaining a reference control signal according to the control signal and the stabilized voltage signal; The temperature compensation circuit is used for obtaining a temperature compensation signal according to the reference control signal; The amplification circuit is connected with the voltage stabilizing circuit, the starting circuit, the control circuit and the temperature compensation circuit respectively, and is used for receiving the stabilized voltage signal, the activation signal, the reference control signal and the temperature compensation current signal to obtain a final reference circuit signal.

[0007] Further, in some embodiments, the voltage stabilizing circuit comprises: a first to fourth MOS transistor, a first to fifth diode, a first resistor, a second resistor and a first capacitor, wherein, a source of the first MOS transistor is connected with a first power access node, a gate of the first MOS transistor is connected with a gate of the second MOS transistor, a drain of the first MOS transistor is connected with a drain of the fourth MOS transistor and a connection node between the first MOS transistor and the second MOS transistor respectively; a source of the second MOS transistor is connected with the first power access node, a drain of the second MOS transistor is connected with a gate of the third MOS transistor, one end of the first resistor and one end of the second resistor respectively; a source of the third MOS transistor is connected with the first power access node, a drain of the third MOS transistor is connected with an output terminal of the voltage stabilizing circuit; a source of the fourth MOS transistor is connected with a ground node, a gate of the fourth MOS transistor is connected with a connection node between the fourth diode and the fifth diode; the other end of the first resistor is connected with one end of the first capacitor; the other end of the first capacitor is connected with the output terminal of the voltage stabilizing circuit the other end of the second resistor is connected with the ground node; an anode of the first diode is connected with the output terminal of the voltage stabilizing circuit, a cathode of the first diode is connected with an anode of the second diode; a cathode of the second diode is connected with an anode of the third diode; a cathode of the third diode is connected with an anode of the fourth diode; a cathode of the fourth diode is connected with an anode of the fifth diode; a cathode of the fifth diode is connected with the ground node.

[0008] Further, in some embodiments, the starting circuit comprises: a fifth to tenth MOS transistor and a second capacitor, wherein, a source of the fifth MOS transistor is connected with a second power access node, a gate of the fifth MOS transistor is connected with a connection node between a gate of the sixth MOS transistor and a source of the ninth MOS transistor, a drain of the fifth MOS transistor is connected with a gate of the seventh MOS transistor and a drain of the tenth MOS transistor; a source of the sixth MOS transistor is connected with the second power access node, a gate of the sixth MOS transistor is connected with the connection node between the gate of the fifth MOS transistor and the source of the ninth MOS transistor, a drain of the sixth MOS transistor is connected with one end of the second capacitor; The source of the seventh MOS is connected with the ground node, the gate of the seventh MOS is connected with the connecting node between the drain of the fifth MOS and the drain of the tenth MOS, and the drain of the seventh MOS is connected with the second output end 210 of the temperature compensation circuit; The source of the eighth MOS is connected with the ground node, the gate of the eighth MOS is connected with the connecting node between the drain of the fifth MOS and the drain of the tenth MOS, and the drain of the eighth MOS is connected with the first output end 209 of the temperature compensation circuit; The source of the ninth MOS is connected with the connecting node between the gate of the fifth MOS and the gate of the sixth MOS, the gate of the ninth MOS is connected with the second power access node, and the drain of the ninth MOS is connected with the ground node. The source of the tenth MOS is connected with the ground node, the gate of the tenth MOS is connected with the amplification circuit, and the drain of the tenth MOS is connected with the drain of the fifth MOS.

[0009] The other end of the second capacitor is connected with the ground node.

[0010] Further, in some embodiments, the temperature compensation circuit comprises: A first temperature compensation unit, an input end of the first temperature compensation unit is connected with the output end of the starting circuit, and the first temperature compensation unit is used for obtaining a first compensation signal according to the reference control signal A second temperature compensation unit, an input end of the second temperature compensation unit is connected with the output end of the starting circuit, and the second temperature compensation unit is used for obtaining a temperature compensation signal according to the reference control signal, and the second temperature compensation unit is used for obtaining a second compensation signal according to the reference control signal.

[0011] Further, in some embodiments, the first temperature compensation unit comprises eleventh to sixteenth MOS, wherein, The source of the eleventh MOS is connected with the third power access node, the gate of the eleventh MOS is connected with the voltage input end of the second temperature compensation unit, and the drain of the eleventh MOS is connected with the connecting node between the drain of the fourteenth MOS and the drain of the fifteenth MOS. The source of the twelfth MOS is connected with the third power access node, the gate of the twelfth MOS is connected with the voltage input end of the first temperature compensation unit, and the drain of the twelfth MOS is connected with the drain of the sixteenth MOS. The source of the thirteenth MOS tube is connected with the third power access node, the gate of the thirteenth MOS tube is connected with the gate of the fourteenth MOS tube, and the drain of the thirteenth MOS tube is connected with the starting circuit; The source of the fourteenth MOS tube is connected with the third power access node, the gate of the fourteenth MOS tube is connected with the gate of the thirteenth MOS tube, and the drain of the fourteenth MOS tube is connected with the connecting node between the drain of the eleventh MOS tube and the drain of the fifteenth MOS tube; The source of the fifteenth MOS tube is connected with the ground node, the gate of the fifteenth MOS tube is connected with the gate of the sixteenth MOS tube, and the drain of the fifteenth MOS tube is connected with the drain of the eleventh MOS tube; The source of the sixteenth MOS tube is connected with the ground node, the gate of the sixteenth MOS tube is connected with the gate of the fifteenth MOS tube, and the drain of the sixteenth MOS tube is connected with the drain of the twelfth MOS tube; Further, in some embodiments, the second temperature compensation unit comprises seventeenth to twenty-second MOS tubes, wherein, The source of the seventeenth MOS tube is connected with the third power access node, the gate of the seventeenth MOS tube is connected with the voltage input end of the first temperature compensation unit, and the drain of the seventeenth MOS tube is connected with the connecting node between the drain of the twentieth MOS tube and the drain of the twenty-first MOS tube; The source of the eighteenth MOS tube is connected with the third power access node, the gate of the twelfth MOS tube is connected with the voltage input end of the second temperature compensation unit, and the drain of the twelfth MOS tube is connected with the drain of the twenty-second MOS tube; The source of the nineteenth MOS tube is connected with the third power access node, the gate of the nineteenth MOS tube is connected with the gate of the twentieth MOS tube, and the drain of the nineteenth MOS tube is connected with the drain of the thirteenth MOS tube; The source of the twentieth MOS tube is connected with the third power access node, the gate of the twentieth MOS tube is connected with the gate of the nineteenth MOS tube, and the drain of the twentieth MOS tube is connected with the connecting node between the drain of the seventeenth MOS tube and the drain of the twenty-first MOS tube; The source of the twenty-first MOS tube is connected with the ground node, the gate of the twenty-first MOS tube is connected with the gate of the sixteenth MOS tube, and the drain of the twenty-first MOS tube is connected with the drain of the eleventh MOS tube; The source of the twenty-second MOS tube is connected with the ground node, the gate of the twenty-second MOS tube is connected with the gate of the twenty-first MOS tube, and the drain of the twenty-second MOS tube is connected with the drain of the eighteenth MOS tube. Further, in some embodiments, the first to fifth diodes in the voltage stabilizing circuit adopt a diode clamping structure.

[0012] Further, in some embodiments, the first MOS tube, the second MOS tube and the third MOS tube are P-type MOS tubes, and the fourth MOS tube is an N-type MOS tube.

[0013] The wide-voltage-supply bandgap reference source circuit provided by the embodiment of the present application can adjust an external supply voltage signal based on a voltage stabilizing circuit to obtain a stabilized voltage signal; the starting circuit receives the stabilized voltage signal and generates an activation signal according to the stabilized voltage signal, and inputs the activation signal into the voltage stabilizing circuit, the control circuit, the temperature compensation circuit and the amplification circuit; the control circuit receives the control activation signal and the stabilized voltage signal to obtain a reference control signal; the temperature compensation circuit receives the reference control signal to obtain a temperature compensation signal; and the amplification circuit receives the stabilized voltage signal, the activation signal, the reference control signal and the temperature compensation current signal to obtain a final reference circuit signal, thereby solving the problem of the decline of the ferroelectric memory performance caused by the decline of the noise and ripple suppression capability of the circuit from the external power supply in the related art under the condition of a wide and high external supply voltage, and improving the overall performance of the ferroelectric memory.

[0014] The second aspect embodiment of the present application provides a ferroelectric memory comprising the wide-voltage-supply bandgap reference source circuit of the first aspect embodiment.

[0015] The ferroelectric memory provided by the embodiment of the present application solves the problem of the decline of the ferroelectric memory performance caused by the decline of the noise and ripple suppression capability of the circuit from the external power supply in the related art under the condition of a wide and high external supply voltage, and improves the overall performance of the ferroelectric memory, through the wide-voltage-supply bandgap reference source circuit described above.

[0016] The third aspect embodiment of the present application provides a wide-voltage-supply bandgap reference source circuit control method, which adopts the wide-voltage-supply bandgap reference source circuit of the first aspect embodiment, and comprises the following steps: Adjusting an external supply voltage signal based on a voltage stabilizing circuit to obtain a stabilized voltage signal; Receiving the stabilized voltage signal by a starting circuit, and generating an activation signal according to the stabilized voltage signal, and inputting the activation signal into the voltage stabilizing circuit, the control circuit, the temperature compensation circuit and the amplification circuit; The control activation signal and the voltage stabilization signal are received by a control circuit to obtain a reference control signal; The reference control signal is received by a temperature compensation circuit to obtain a temperature compensation signal; The voltage stabilization signal, the activation signal, the reference control signal and the temperature compensation signal are received by an amplification circuit to obtain a final reference circuit signal.

[0017] The wide-voltage-supply bandgap reference source circuit control method provided by the embodiment of the present application solves the problem of ferroelectric memory performance decline caused by the decline of the noise and ripple suppression capability of the circuit from external power supply in the related art under the condition of wide external supply voltage and high voltage, and improves the overall performance of the ferroelectric memory.

[0018] Additional aspects and advantages of the present application will be made apparent by the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which: Figure 1 The block schematic diagram of the wide-voltage-supply bandgap reference source circuit provided by the embodiment of the present application is shown in the figure; Figure 2 The structural schematic diagram of the voltage stabilization circuit provided by one specific embodiment of the present application is shown in the figure; Figure 3 The structural schematic diagram of the start-up circuit provided by one specific embodiment of the present application is shown in the figure; Figure 4 The structural schematic diagram of the temperature compensation circuit provided by one specific embodiment of the present application is shown in the figure; Figure 5 The structural schematic diagram of the two-stage Miller operational amplifier circuit provided by one specific embodiment of the present application is shown in the figure; Figure 6 The structural schematic diagram of the wide-voltage-supply bandgap reference source circuit provided by one specific embodiment of the present application is shown in the figure; Figure 7 The flow chart of the wide-voltage-supply bandgap reference source circuit control method provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0020] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0021] The following describes, with reference to the accompanying drawings, a wide-voltage-powered bandgap reference source circuit, a ferroelectric memory, and a circuit control method provided according to embodiments of the present invention. First, the wide-voltage-powered bandgap reference source circuit provided according to embodiments of the present invention will be described with reference to the accompanying drawings.

[0022] Specifically, Figure 1 This is a block diagram of a wide-voltage-powered bandgap reference source circuit provided in an embodiment of the present invention.

[0023] like Figure 1 As shown, the wide-voltage-supply bandgap reference source circuit 10 includes: a voltage regulator circuit 100, a startup circuit 200, a control circuit 300, a temperature compensation circuit 400, and an amplifier circuit 500. The voltage regulator circuit 100 regulates the received voltage signal to obtain a regulated signal; the startup circuit 200 generates an activation signal based on the regulated signal; the control circuit 300 is connected to both the voltage regulator circuit 100 and the startup circuit 200, and generates a reference control signal based on the control signal and the regulated signal; the temperature compensation circuit 400 generates a temperature compensation signal based on the reference control signal; and the amplifier circuit 500 is connected to the voltage regulator circuit 100, the startup circuit 200, the control circuit 300, and the temperature compensation circuit 400 to receive the regulated signal, the activation signal, the reference control signal, and the temperature compensation current signal to obtain the final reference circuit signal.

[0024] Alternatively, in some embodiments, such as Figure 2 As shown, the voltage regulator circuit 100 includes: first to fourth MOSFETs, first to fifth diodes, a first resistor 111, a second resistor 112, and a first capacitor 113, wherein... The source of the first MOSFET 101 is connected to the first power access node 105, the gate of the first MOSFET 101 is connected to the gate of the second MOSFET 102, and the drain of the first MOSFET 101 is connected to the drain of the fourth MOSFET 104 and the connection node between the first MOSFET 101 and the second MOSFET 102. The source of the second MOS transistor 102 is connected to the first power access node 105, and the drain of the second MOS transistor 102 is connected to the gate of the third MOS transistor 103, one end of the first resistor 111, and one end of the second resistor 112, respectively. The source of the third MOS transistor 103 is connected to the first power access node 105, and the drain of the third MOS transistor 103 is connected to the output terminal of the voltage stabilizing circuit; The source of the fourth MOS transistor 104 is connected to the ground node, and the gate of the fourth MOS transistor 104 is connected to the connection node between the fourth diode 109 and the fifth diode 110; The other end of the first resistor 111 is connected to one end of the first capacitor 113; The other end of the first capacitor 113 is connected to the output terminal of the voltage stabilizing circuit The other end of the second resistor 112 is connected to the ground node; The anode of the first diode 106 is connected to the output terminal of the voltage stabilizing circuit, and the cathode of the first diode 106 is connected to the anode of the second diode 107; The cathode of the second diode 107 is connected to the anode of the third diode 108; The cathode of the third diode 108 is connected to the anode of the fourth diode 109; The cathode of the fourth diode 109 is connected to the anode of the fifth diode 110; The cathode of the fifth diode 110 is connected to the ground node.

[0025] As a possible implementation, the third MOS transistor 103, the fourth MOS transistor 104, the first resistor 111 and the second resistor 112 in the voltage stabilizing circuit 100 form a feedback loop. When the voltage at the first power access node 105 rises, the third MOS transistor 103 is turned on, so that the gate voltage of the fourth MOS transistor 104 rises, and the fourth MOS transistor 104 is turned on. When the output voltage rises, the gate voltage of the fourth MOS transistor 104 rises, and the current through the fourth MOS transistor 104 increases. Due to the replication effect of the current mirror structure, the gate voltage of the third MOS transistor 103 also rises, the current through the third MOS transistor 103 decreases, and the output voltage also decreases due to the negative feedback effect. When the voltage at the first power access node 105 is lower than the conduction voltage of the first to fifth diodes, it is clamped, and the circuit realizes the pre-regulation function. Thus, the voltage stabilizing circuit 100 can maintain the voltage almost unchanged under low voltage condition and significantly reduce the voltage under high voltage condition when modulating the external supply voltage, so as to adjust the wide supply voltage range to a smaller range, supply power to the bandgap reference source, and further improve the performance of the bandgap reference source under high voltage external power supply.

[0026] It should be noted that the threshold voltages of different types of diodes in the voltage stabilizing circuit 100 are different, and different voltage stabilizers with different clamping voltages can be designed according to specific designs, and the size of the MOS transistor can be adjusted according to actual conditions, which is not limited here.

[0027] Further, in some embodiments, as shown, the start-up circuit 200 includes: fifth to tenth MOS transistors and a second capacitor 208, wherein, Figure 3 The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206; The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206; The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206; The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206; The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206; The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206; The source of the fifth MOS transistor 201 is connected to the second power access node 207, the gate of the fifth MOS transistor 201 is connected to the connection node between the gate of the sixth MOS transistor 202 and the source of the ninth MOS transistor 205, and the drain of the fifth MOS transistor 201 is connected to the gate of the seventh MOS transistor 203 and the drain of the tenth MOS transistor 206;

[0028] The other end of the second capacitor 208 is connected to the ground node.

[0029] As a possible implementation, after the bandgap reference circuit is powered on, the fifth MOS transistor 201 and the sixth MOS transistor 202 in the starting circuit 200 are turned on, and the output current of the sixth MOS transistor charges the second capacitor 208. When the seventh MOS transistor 203 is turned on, the voltage at the gates of M1 and M2 is reduced, so that the bandgap reference core circuit is started. When the voltage of the second capacitor 208 continues to rise to a preset threshold, the fifth MOS transistor 201 and the sixth MOS transistor 202 are cut off. Therefore, when the bandgap reference circuit is working normally, the current flowing through the starting circuit 100 is zero. When the power is turned off, the ninth MOS transistor 205 is turned on to discharge the second capacitor 208, so that the starting circuit 100 can work normally at the next power-on.

[0030] Further, in some embodiments, as shown in FIG. 4, the temperature compensation circuit 400 includes: Figure 4 The first temperature compensation unit 401 has an input end connected to the output end of the starting circuit 100, and is configured to obtain a first compensation signal according to the reference control signal. The second temperature compensation unit 402 has an input end connected to the output end of the starting circuit 100, and is configured to obtain a temperature compensation signal according to the reference control signal. The second temperature compensation unit 402 is configured to obtain a second compensation signal according to the reference control signal.

[0031] In some embodiments, the lowest temperature of the working temperature range of the first temperature compensation unit is greater than or equal to the highest temperature of the working temperature range of the second temperature compensation unit.

[0032] For example, the first temperature compensation unit 401 is configured to balance and compensate the positive temperature coefficient and negative temperature coefficient signals in a high-temperature working range (for example, 80-120°C), so as to ensure that the reference voltage meets the drift requirement in the high-temperature working range. The second temperature compensation unit 402 is configured to balance and compensate the positive temperature coefficient and negative temperature coefficient signals in a low-temperature working range (for example, -40-0°C), so as to ensure that the reference voltage meets the drift requirement in the low-temperature working range.

[0033] In some embodiments, the first temperature compensation unit 401 includes eleventh to sixteenth MOS transistors 408, wherein, The source of the eleventh MOS transistor 403 is connected to the third power access node 409, the gate of the eleventh MOS transistor 403 is connected to the voltage input end of the second temperature compensation unit, and the drain of the eleventh MOS transistor 403 is connected to a connection node between the drain of the fourteenth MOS transistor 406 and the drain of the fifteenth MOS transistor 407. ​The source of the twelfth MOS transistor 404 is connected to the third power access node 409, the gate of the twelfth MOS transistor 404 is connected to the voltage input end of the first temperature compensation unit, and the drain of the twelfth MOS transistor 404 is connected to the drain of the sixteenth MOS transistor 408; The source of the thirteenth MOS transistor 405 is connected to the third power access node 409, the gate of the thirteenth MOS transistor 405 is connected to the gate of the fourteenth MOS transistor 406, and the drain of the thirteenth MOS transistor 405 is connected to the start-up circuit; The source of the fourteenth MOS transistor 406 is connected to the third power access node 409, the gate of the fourteenth MOS transistor 406 is connected to the gate of the thirteenth MOS transistor 405, and the drain of the fourteenth MOS transistor 406 is connected to the connection node between the drain of the eleventh MOS transistor 403 and the drain of the fifteenth MOS transistor 407; The source of the fifteenth MOS transistor 407 is connected to the ground node, the gate of the fifteenth MOS transistor 407 is connected to the gate of the sixteenth MOS transistor 408, and the drain of the fifteenth MOS transistor 407 is connected to the drain of the eleventh MOS transistor 403; The source of the sixteenth MOS transistor 408 is connected to the ground node, the gate of the sixteenth MOS transistor 408 is connected to the gate of the fifteenth MOS transistor 407, and the drain of the sixteenth MOS transistor 408 is connected to the drain of the twelfth MOS transistor 404; Further, in some embodiments, the second temperature compensation unit 402 includes seventeenth to twenty-second MOS transistors, wherein, The source of the seventeenth MOS transistor 409 is connected to the third power access node 409, the gate of the seventeenth MOS transistor 409 is connected to the voltage input end of the first temperature compensation unit, and the drain of the seventeenth MOS transistor 409 is connected to the connection node between the drain of the twentieth MOS transistor 412 and the drain of the twenty-first MOS transistor 413; The source of the eighteenth MOS transistor 410 is connected to the third power access node 409, the gate of the twelfth MOS transistor is connected to the voltage input end of the second temperature compensation unit, and the drain of the twelfth MOS transistor is connected to the drain of the twenty-second MOS transistor 414; The source of the nineteenth MOS transistor 411 is connected to the third power access node 409, the gate of the nineteenth MOS transistor 411 is connected to the gate of the twentieth MOS transistor 412, and the drain of the nineteenth MOS transistor 411 is connected to the drain of the thirteenth MOS transistor; The source of the twentieth MOS transistor 412 is connected to the third power access node 409, the gate of the twentieth MOS transistor 412 is connected to the gate of the nineteenth MOS transistor 411, and the drain of the twentieth MOS transistor 412 is connected to the connection node between the drain of the seventeenth MOS transistor 409 and the drain of the twenty-first MOS transistor 413; The source of the twenty-first MOS tube 413 is connected with the ground node, the gate of the twenty-first MOS tube 413 is connected with the gate of the sixteenth MOS tube, and the drain of the twenty-first MOS tube 413 is connected with the drain of the eleventh MOS tube; The source of the twenty-second MOS tube 414 is connected with the ground node, the gate of the twenty-second MOS tube 414 is connected with the gate of the twenty-first MOS tube 413, and the drain of the twenty-second MOS tube 414 is connected with the drain of the eighteenth MOS tube 410.

[0034] Further, in some embodiments, the first to fifth diodes in the voltage stabilizing circuit 100 adopt a diode clamping structure.

[0035] Specifically, by using the characteristics that the diode is stable in forward direction and is blocked in reverse direction, the highest or lowest potential of the target node is limited by the series connection of single or multiple diodes, so that the circuit is in the potential range required for normal operation.

[0036] Further, in some embodiments, the first MOS tube 101, the second MOS tube 102 and the third MOS tube 103 are P-type MOS tubes, and the fourth MOS tube 104 is an N-type MOS tube.

[0037] Optionally, the amplifying circuit 500 of the embodiment of the present application can adopt a two-stage Miller operational amplifier, Figure 5 The two-stage Miller operational amplifier circuit structure provided according to one specific embodiment of the present application is shown in FIG. 4, in which the bias voltage of the two-stage Miller operational amplifier is provided by a self-bias current source, and the voltage gain is brought by the two-stage amplifying structure, so that the error signal can be amplified and converted into a recognizable correction signal.

[0038] In order to make the related technicians in the art better understand the wide voltage supply bandgap reference source circuit of the embodiment of the present application, the following will be explained and described in combination with specific embodiments.

[0039] Figure 6 The structure schematic diagram of the wide voltage supply bandgap reference source circuit according to one specific embodiment of the present application is shown in FIG. 5. Figure 6 As shown in FIG. 5, the wide voltage supply bandgap reference source circuit is composed of a voltage stabilizing circuit, a starting circuit, a control circuit, a temperature compensation circuit and an amplifying circuit, and the overall performance of the bandgap reference source is improved by reducing the external power supply range.

[0040] The wide-voltage power supply bandgap reference source circuit provided by the embodiment of the present application can adjust an external power supply voltage signal based on a voltage stabilizing circuit to obtain a stabilized voltage signal; the stabilized voltage signal is received by a starting circuit, and an activation signal is generated according to the stabilized voltage signal, and the activation signal is input into the voltage stabilizing circuit, a control circuit, a temperature compensation circuit and an amplification circuit; the control activation signal and the stabilized voltage signal are received by the control circuit to obtain a reference control signal; the reference control signal is received by the temperature compensation circuit to obtain a temperature compensation signal; the stabilized voltage signal, the activation signal, the reference control signal and the temperature compensation current signal are received by the amplification circuit to obtain a final reference circuit signal, thereby solving the problem of the decline of the ferroelectric memory performance caused by the decline of the noise and ripple suppression capability of the circuit from the external power supply in the related art under the condition of the wide and high external power supply voltage, and improving the overall performance of the ferroelectric memory.

[0041] The embodiment of the present application further provides a ferroelectric memory comprising the wide-voltage power supply bandgap reference source circuit.

[0042] The ferroelectric memory provided by the embodiment of the present application solves the problem of the decline of the ferroelectric memory performance caused by the decline of the noise and ripple suppression capability of the circuit from the external power supply in the related art under the condition of the wide and high external power supply voltage, and improves the overall performance of the ferroelectric memory, through the wide-voltage power supply bandgap reference source circuit.

[0043] In addition, the embodiment of the present application further provides a wide-voltage power supply bandgap reference source circuit control method as shown in the figure. Figure 7

[0044] Figure 7 The wide-voltage power supply bandgap reference source circuit control method provided by the embodiment of the present application has a flow chart as shown in the figure.

[0045] As shown in the figure, the wide-voltage power supply bandgap reference source circuit control method comprises the following steps: Figure 7 In step S701, an external power supply voltage signal is adjusted based on a voltage stabilizing circuit to obtain a stabilized voltage signal. In step S702, the stabilized voltage signal is received by a starting circuit, and an activation signal is generated according to the stabilized voltage signal, and the activation signal is input into the voltage stabilizing circuit, a control circuit, a temperature compensation circuit and an amplification circuit.

[0046] In step S703, the control activation signal and the stabilized voltage signal are received by the control circuit to obtain a reference control signal.

[0047] In step S704, the reference control signal is received by the temperature compensation circuit to obtain a temperature compensation signal.

[0048]

[0049] ​​In step S705, a final reference circuit signal is obtained according to the stabilized voltage signal, the activation signal, the reference control signal and the temperature compensation current signal received by the amplification circuit.

[0050] The wide-voltage power supply bandgap reference source circuit control method provided by the embodiment of the present application solves the problem of ferroelectric memory performance decline caused by the decline of the circuit's noise and ripple suppression capability from external power supply in the related art when the external power supply voltage is wide and high, and improves the overall performance of the ferroelectric memory.

[0051] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly and specifically limited.

[0052] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, different embodiments or examples described in the present specification and the features of different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0053] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A wide-voltage-supply bandgap reference source circuit, characterized in that, include: The circuit consists of a voltage regulator circuit, a startup circuit, a control circuit, a temperature compensation circuit, and an amplifier circuit. The voltage regulator circuit is used to regulate the received voltage signal to obtain a regulated signal; The startup circuit is used to generate an activation signal based on the regulated voltage signal; The control circuit is connected to the voltage regulator circuit and the start-up circuit respectively, and is used to obtain a reference control signal based on the control signal and the voltage regulator signal; The temperature compensation circuit is used to obtain a temperature compensation signal based on the reference control signal; The amplifier circuit is connected to the voltage regulator circuit, the startup circuit, the control circuit, and the temperature compensation circuit respectively, and is used to receive the voltage regulator signal, the activation signal, the reference control signal, and the temperature compensation current signal to obtain the final reference circuit signal.

2. The wide voltage supply bandgap reference source circuit according to claim 1, characterized in that, The voltage regulator circuit includes: first to fourth MOSFETs, first to fifth diodes, a first resistor, a second resistor, and a first capacitor, wherein, The source of the first MOS transistor is connected to the first power access node, the gate of the first MOS transistor is connected to the gate of the second MOS transistor, and the drain of the first MOS transistor is connected to the drain of the fourth MOS transistor and the connection node between the first MOS transistor and the second MOS transistor. The source of the second MOS transistor is connected to the first power access node, and the drain of the second MOS transistor is connected to the gate of the third MOS transistor, one end of the first resistor, and one end of the second resistor, respectively. The source of the third MOS transistor is connected to the first power access node, and the drain of the third MOS transistor is connected to the output terminal of the voltage regulator circuit. The source of the fourth MOS transistor is connected to the ground node, and the gate of the fourth MOS transistor is connected to the connection node between the fourth diode and the fifth diode. The other end of the first resistor is connected to one end of the first capacitor; The other end of the first capacitor is connected to the output terminal of the voltage regulator circuit. The other end of the second resistor is connected to the grounding node; The anode of the first diode is connected to the output terminal of the voltage regulator circuit, and the cathode of the first diode is connected to the anode of the second diode. The cathode of the second diode is connected to the anode of the third diode; The cathode of the third diode is connected to the anode of the fourth diode; The cathode of the fourth diode is connected to the anode of the fifth diode; The cathode of the fifth diode is connected to the grounding node.

3. The wide voltage supply bandgap reference source circuit according to claim 1, characterized in that, The startup circuit includes: fifth to tenth MOSFETs and a second capacitor, wherein, The source of the fifth MOS transistor is connected to the second power access node, the gate of the fifth MOS transistor is connected to the connection node between the gate of the sixth MOS transistor and the source of the ninth MOS transistor, and the drain of the fifth MOS transistor is connected to the gate of the seventh MOS transistor and the drain of the tenth MOS transistor. The source of the sixth MOS transistor is connected to the second power access node, the gate of the sixth MOS transistor is connected to the connection node between the gate of the fifth MOS transistor and the source of the ninth MOS transistor, and the drain of the sixth MOS transistor is connected to one end of the second capacitor. The source of the seventh MOS transistor is connected to the ground node, the gate of the seventh MOS transistor is connected to the connection node between the drain of the fifth MOS transistor and the drain of the tenth MOS transistor, and the drain of the seventh MOS transistor is connected to the second output terminal. The source of the eighth MOS transistor is connected to the ground node, the gate of the eighth MOS transistor is connected to the connection node between the drain of the fifth MOS transistor and the drain of the tenth MOS transistor, and the drain of the eighth MOS transistor is connected to the first output terminal. The source of the ninth MOS transistor is connected to the connection node between the gate of the fifth MOS transistor and the gate of the sixth MOS transistor, the gate of the ninth MOS transistor is connected to the second power supply access node, and the drain of the ninth MOS transistor is connected to the ground node. The source of the tenth MOS transistor is connected to the ground node, the gate of the tenth MOS transistor is connected to the amplifier circuit, and the drain is connected to the drain of the fifth MOS transistor. The other end of the second capacitor is connected to the grounding node.

4. The wide voltage supply bandgap reference source circuit according to claim 3, characterized in that, The temperature compensation circuit includes: A first temperature compensation unit, the input terminal of which is connected to the output terminal of the startup circuit, is used to obtain a first compensation signal based on the reference control signal. The second temperature compensation unit has its input terminal connected to the output terminal of the start-up circuit and is used to obtain a temperature compensation signal based on the reference control signal. The second temperature compensation unit is used to obtain a second compensation signal based on the reference control signal.

5. The wide voltage supply bandgap reference source circuit according to claim 4, characterized in that, The first temperature compensation unit includes: eleventh to sixteenth MOS transistors, wherein, The source of the eleventh MOS transistor is connected to the third power access node, the gate of the eleventh MOS transistor is connected to the voltage input terminal of the second temperature compensation unit, and the drain of the eleventh MOS transistor is connected to the connection node between the drain of the fourteenth MOS transistor and the drain of the fifteenth MOS transistor. The source of the twelfth MOS transistor is connected to the third power access node, the gate of the twelfth MOS transistor is connected to the voltage input terminal of the first temperature compensation unit, and the drain of the twelfth MOS transistor is connected to the drain of the sixteenth MOS transistor. The source of the thirteenth MOS transistor is connected to the third power access node, the gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor, and the drain of the thirteenth MOS transistor is connected to the startup circuit. The source of the fourteenth MOS transistor is connected to the third power access node, the gate of the fourteenth MOS transistor is connected to the gate of the thirteenth MOS transistor, and the drain of the fourteenth MOS transistor is connected to the connection node between the drain of the eleventh MOS transistor and the drain of the fifteenth MOS transistor. The source of the fifteenth MOS transistor is connected to the ground node, the gate of the fifteenth MOS transistor is connected to the gate of the sixteenth MOS transistor, and the drain of the fifteenth MOS transistor is connected to the drain of the eleventh MOS transistor. The source of the sixteenth MOS transistor is connected to the ground node, the gate of the sixteenth MOS transistor is connected to the gate of the fifteenth MOS transistor, and the drain of the sixteenth MOS transistor is connected to the drain of the twelfth MOS transistor.

6. The wide voltage supply bandgap reference source circuit according to claim 4, characterized in that, The second temperature compensation unit includes: the seventeenth to the twenty-second MOSFETs, wherein, The source of the seventeenth MOS transistor is connected to the third power access node, the gate of the seventeenth MOS transistor is connected to the voltage input terminal of the first temperature compensation unit, and the drain of the seventeenth MOS transistor is connected to the connection node between the drain of the twentieth MOS transistor and the drain of the eleventh MOS transistor. The source of the eighteenth MOS transistor is connected to the third power access node, the gate of the twelfth MOS transistor is connected to the voltage input terminal of the second temperature compensation unit, and the drain of the twelfth MOS transistor is connected to the drain of the second twelfth MOS transistor. The source of the nineteenth MOS transistor is connected to the third power access node, the gate of the nineteenth MOS transistor is connected to the gate of the twentieth MOS transistor, and the drain of the nineteenth MOS transistor is connected to the drain of the thirteenth MOS transistor. The source of the twentieth MOS transistor is connected to the third power access node, the gate of the twentieth MOS transistor is connected to the gate of the nineteenth MOS transistor, and the drain of the twentieth MOS transistor is connected to the connection node between the drain of the seventeenth MOS transistor and the drain of the twentieth MOS transistor. The source of the 21st MOS transistor is connected to the ground node, the gate of the 21st MOS transistor is connected to the gate of the 16th MOS transistor, and the drain of the 21st MOS transistor is connected to the drain of the 11th MOS transistor. The source of the twelfth MOS transistor is connected to the ground node, the gate of the twelfth MOS transistor is connected to the gate of the twelfth MOS transistor, and the drain of the twelfth MOS transistor is connected to the drain of the eighteenth MOS transistor.

7. The wide voltage supply bandgap reference source circuit according to claim 2, characterized in that, The first to fifth diodes in the voltage regulator circuit adopt a diode clamping structure.

8. The circuit according to claim 2, characterized in that, The first MOS transistor, the second MOS transistor, and the third MOS transistor are P-type MOS transistors; the fourth MOS transistor is an N-type MOS transistor.

9. A ferroelectric memory, characterized in that, include: The wide voltage-powered bandgap reference source circuit as described in any one of claims 1-8.

10. A control method for a wide-voltage-supply bandgap reference source circuit, characterized in that, The method employs a wide-voltage-powered bandgap reference source circuit as described in any one of claims 1-8, wherein the method includes the following steps: A regulated signal is obtained by adjusting the external power supply voltage signal using a voltage regulator circuit. The circuit receives a regulated voltage signal through a startup circuit, generates an activation signal based on the regulated voltage signal, and inputs the activation signal into the regulated voltage circuit, the control circuit, the temperature compensation circuit, and the amplification circuit. The control circuit receives the control activation signal and the voltage regulation signal to obtain a reference control signal. The temperature compensation signal is obtained by receiving the reference control signal through the temperature compensation circuit; The final reference circuit signal is obtained based on the regulated signal, the activation signal, the reference control signal, and the temperature compensation current signal received by the amplifier circuit.

Images