Digital LDO (Low Dropout Regulator) with zero point following compensation and quick response

Abstract

The invention relates to a digital LDO with zero point following compensation and quick response, and belongs to the field of digital-analog hybrid integrated circuits, the digital LDO comprises an LDO signal input end, a pre-amplifier, a ClassAB structure circuit and an LDO output end, the LDO signal input end is used for accessing a signal, the pre-amplifier is used for providing gain, and the ClassAB structure circuit is used for outputting the signal. The ClassAB structure circuit comprises a complementary push-pull output geminate transistor circuit, a bias circuit and a frequency compensation circuit, the complementary push-pull output geminate transistor circuit comprises a second NMOS transistor and a second PMOS transistor, the bias circuit comprises a first NMOS transistor, a first PMOS transistor and a bias current source, the bias circuit is used for determining a quiescent working point of an output stage of the ClassAB structure circuit, and the frequency compensation circuit is used for compensating the frequency of the output stage of the ClassAB structure circuit. The frequency compensation circuit comprises the first capacitor, a second capacitor and a resistor. According to the digital LDO, the precision of the output voltage is improved through feedback, a ClassAB structure is adopted to enable the circuit to have the current pulling capacity and the current sinking capacity at the same time, and the transient response capacity during load change is accelerated.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of digital-analog hybrid integrated circuits, in particular to a digital LDO (Low dropout regulator) with zero-point following compensation and fast response. BACKGROUND

[0002] In order to meet the working needs of a digital circuit, an LDO (Low dropout regulator) providing power supply for the digital circuit often needs to meet the following requirements: providing sufficient load current, meeting accuracy requirements, being able to quickly respond to changes in load current and being able to drive a large off-chip or on-chip capacitor.

[0003] A commonly used LDO structure is shown in FIG. 1. Figure 1 The output of the circuit is an open-loop structure, and the output voltage is determined by the ratio of the PMOS (Positive channel Metal Oxide Semiconductor) tubes MN1 and MN2 and the currents I1 and I2. The output tube is a source follower. When the output voltage decreases, the VGS (Gate-Source Voltage) of the MN2 tube increases, and its output current increases, so that the load can be quickly supplied with current, achieving fast response. The above-mentioned circuit output is an open loop, and the output voltage is determined only by the matching of the current sources, so the accuracy is poor. The current only has the ability of source current (current flowing out of the chip pin to drive the external load), and does not have the ability of sink current (current flowing into the chip pin from the external load and being absorbed by the chip), so when the output voltage changes from high to low, the transient response is poor due to the weak pull-down ability. SUMMARY

[0004] In order to solve the above problems, the present application is provided, which provides a digital LDO with zero-point following compensation and fast response, comprising an LDO signal input end, a pre-amplifier, a Class AB structure circuit and an LDO output end.

[0005] The LDO signal input end is used for inputting a signal and is connected with a first input end of the pre-amplifier.

[0006] The pre-amplifier is used for providing gain, a second input end of the pre-amplifier is connected with the LDO output end, an output end of the pre-amplifier is connected with a first electrode of a first capacitor, a gate of a first NMOS tube and a first end of a resistor respectively, and a power supply input end of the pre-amplifier is connected with a power supply.

[0007] The Class AB structure circuit comprises a complementary push-pull output pair tube circuit, a bias circuit and a frequency compensation circuit.

[0008] The complementary push-pull output pair tube circuit comprises a second NMOS tube and a second PMOS tube, the second NMOS tube and the second PMOS tube are in a source follower structure, the source of the second NMOS tube is connected with the source of the second PMOS tube and the LDO output terminal respectively, the drain of the second NMOS tube is connected with a power supply and the drain of the first NMOS tube respectively, the gate of the second NMOS tube is connected with the second end of the resistor and the first electrode of the second capacitor respectively, the drain of the second PMOS tube is connected with the second electrode of the second capacitor, the ground wire and the second electrode of the first capacitor respectively, the gate of the second PMOS tube is connected with the gate of the first PMOS tube, the drain of the first PMOS tube and the first end of the bias current source respectively; the source of the first NMOS tube is connected with the source of the first PMOS tube.

[0009] The bias circuit comprises a first NMOS tube, a first PMOS tube and a bias current source, the bias circuit is used for determining the static working point of the output stage of the Class AB structure circuit, the drain of the first NMOS tube is connected with a power supply, the power supply input terminal of the pre-stage amplifier and the drain of the second NMOS tube respectively, the gate of the first NMOS tube is also connected with the first electrode of the first capacitor, the gate of the first PMOS tube is connected with the gate of the second PMOS tube and the drain of the first PMOS tube respectively, the drain of the first PMOS tube is connected with the gate of the first PMOS tube and the first end of the bias current source respectively, the second end of the bias current source is connected with the second electrode of the second capacitor, the second electrode of the first capacitor, the drain of the second PMOS tube and the ground wire respectively.

[0010] The frequency compensation circuit comprises the first capacitor, the second capacitor and the resistor.

[0011] Further, the pre-stage amplifier is a transconductance amplifier.

[0012] Further, the digital LDO comprises three poles and one zero, wherein the first pole is the output terminal of the pre-stage amplifier, the second pole is the LDO output terminal, the third pole is a high-frequency parasitic pole introduced by the zero, and the zero is composed of the resistor and the second capacitor.

[0013] Further, the output pole of the digital LDO P 0 is represented as wherein, is the transconductance of the second NMOS tube, is the transconductance of the second PMOS tube, C L is the load capacitor.

[0014] Further, the zero of the digital LDOZ Represented as ,in, It is the transconductance of the second NMOS transistor. It is the transconductance of the second PMOS transistor. k It is the ratio of the transconductance of the first NMOS transistor to that of the first PMOS transistor. R This is the resistance value of the resistor. C 2 It is the capacitance value of the second capacitor.

[0015] The beneficial effects of the above-mentioned technical solutions provided in this application include at least the following: Feedback improves the accuracy of the output voltage, and the ClassAB structure enables the circuit to simultaneously have source and sink current capabilities, thus accelerating the transient response capability under load changes.

[0016] Furthermore, by introducing dynamic zeros that follow changes in the output poles, the stability problem of the feedback loop is solved.

[0017] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0018] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the embodiments of the present application to explain the application and do not constitute a limitation thereof. In the drawings: Figure 1 This is a commonly used LDO structure diagram; Figure 2 This is a structural diagram of a fast-response digital LDO with zero-point tracking compensation in an embodiment of this application; Figure 3 This is a simulation diagram of a digital LDO in an embodiment of this application. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] To address the problems existing in the prior art, embodiments of this application provide a fast-response digital LDO with zero-point tracking compensation.

[0022] This application provides a fast-response digital LDO with zero-point tracking compensation, the structure of which is as follows: Figure 2 As shown, it includes: The system comprises an LDO input terminal, a preamplifier, a Class AB circuit, and an LDO output terminal. The LDO input terminal includes an LDO signal input terminal and an LDO power input terminal. The LDO signal input terminal is used to receive a signal and is connected to the first input terminal of the preamplifier. The LDO power input terminal is used to connect to a power supply. Figure 2 In this context, Vin represents the LDO signal input terminal, and Vout represents the LDO output terminal.

[0023] The preamplifier is used to provide gain. The second input terminal of the preamplifier is connected to the output terminal of the LDO. The output terminal of the preamplifier is connected to the first electrode of the first capacitor, the gate of the first NMOS transistor, and the first end of the resistor, respectively. The power input terminal of the preamplifier is connected to the power supply.

[0024] The ClassAB structure circuit includes a complementary push-pull output pair circuit, a bias circuit, and a frequency compensation circuit.

[0025] The complementary push-pull output pair circuit includes a second NMOS transistor and a second PMOS transistor. The second NMOS transistor and the second PMOS transistor are source follower structures. The source of the second NMOS transistor is connected to the source of the second PMOS transistor and the output terminal of the LDO, respectively. The drain of the second NMOS transistor is connected to the power supply and the drain of the first NMOS transistor, respectively. The gate of the second NMOS transistor is connected to the second terminal of the resistor and the first electrode of the second capacitor, respectively. The drain of the second PMOS transistor is connected to the second electrode of the second capacitor, the ground line, and the second electrode of the first capacitor, respectively. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the first terminal of the bias current source, respectively. The source of the first NMOS transistor is connected to the source of the first PMOS transistor.

[0026] The bias circuit includes a first NMOS transistor, a first PMOS transistor, and a bias current source. The bias circuit is used to determine the static operating point of the output stage of the ClassAB structure circuit. The drain of the first NMOS transistor is connected to the power supply and the drain of the second NMOS transistor. The gate of the first NMOS transistor is also connected to the first electrode of the first capacitor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the drain of the first PMOS transistor. The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor and the first terminal of the bias current source. The second terminal of the bias current source is connected to the second electrode of the second capacitor, the second electrode of the first capacitor, the drain of the second PMOS transistor, and the ground.

[0027] The frequency compensation circuit includes a first capacitor, a second capacitor, and a resistor.

[0028] The aforementioned digital LDO modifies the LDO output stage to a Class AB structure, enabling it to simultaneously possess source and sink current capabilities. The circuit feedback point is moved to the output terminal, improving the accuracy of the output voltage through feedback. The Class AB structure is a circuit design that combines the advantages of Class A and Class B amplifiers, effectively reducing crossover distortion and improving efficiency by allowing the operating ranges of push-pull transistors to overlap.

[0029] Reference Figure 2 As shown, OTA1 is the preamplifier, providing gain. Output transistors MN2 (second NMOS transistor) and MP2 (second PMOS transistor) employ a source follower structure, forming a Class AB structure that allows the digital LDO circuit to simultaneously possess source and sink current capabilities. This LDO provides power to the digital circuit, requiring a higher source current capability; the sink current capability is only for accelerating transient response, meaning that when the output voltage changes from high to low, the MP2 transistor can accelerate this change. Therefore, a lower sink current capability is designed. MN1 (first NMOS transistor), MP1 (first PMOS transistor), and the bias current source I1 constitute the Class AB bias circuit, used to determine the quiescent operating point of the Class AB output stage. The second input terminal of the preamplifier is connected to the output terminal of the LDO, with the feedback point located at the output point. Thus, the output voltage accuracy of the circuit is mainly determined by the loop accuracy, i.e., by the gain of OTA1. The first capacitor C1, the second capacitor C2, and the resistor R implement the frequency compensation circuit.

[0030] Furthermore, the preamplifier is an operational transconductance amplifier (OTA).

[0031] Furthermore, the digital LDO includes three poles and one zero. The first pole is the output terminal of the preamplifier, the second pole is the LDO output terminal, and the third pole is an additional pole introduced by the zero. The third pole is a high-frequency parasitic pole, which is mostly located at high frequencies and has little impact on the phase margin. The zero is formed by the resistor and the second capacitor and is related to the transconductance gm of the output transistor. By introducing the output pole into the loop and using a zero that follows the changes of the output pole, frequency compensation is achieved, ensuring the stability of the circuit.

[0032] Furthermore, the output poles of the digital LDO P 0 Represented as ,in, It is the transconductance of the second NMOS transistor. It is the transconductance of the second PMOS transistor. C L It is the load capacitance. Because it is designed with a low sink current capability, Smaller.

[0033] Furthermore, the zero point of the digital LDO Z Represented as ,in, It is the transconductance of the second NMOS transistor. It is the transconductance of the second PMOS transistor. k It is the ratio of the transconductance of the first NMOS transistor to that of the first PMOS transistor. R This is the resistance value of the resistor. C 2 This refers to the capacitance value of the second capacitor. The sink current capability is designed to be lower; compared to the MN2 transistor, the MP2 transistor's transconductance decreases with load changes. The change is smaller and can be approximated as The transconductance gm of transistors MN1 and MP1, biased by I1, remains unchanged with respect to the output load. Therefore, the numerators of the output pole and zero expressions both contain [variables]. When the load current changes, As the output poles change, the zeros mentioned above also change accordingly. Therefore, by setting them appropriately... k , The values ​​of resistor R and capacitor C2 are adjusted to achieve zero-point compensation of the output pole, and the zero point can follow the change of the output pole when the output load current changes, thus achieving a following compensation effect. In this way, only one dominant pole and a high-frequency parasitic pole remain in the circuit, and the digital LDO is approximately a single-pole system, achieving circuit stability.

[0034] Based on the above digital LDO design circuit model, simulation was performed, keeping other parameters constant, and the transconductance of the second NMOS transistor was scanned. The phase margin (PM) changes accordingly. Figure 3 The vertical axis represents the phase margin PM, and the horizontal axis represents the transconductance of the second NMOS transistor. ,like Figure 3 As shown, in When the PM changes from 50ms to 500ms, the range of change is very small.

[0035] The table below shows the output poles and zeros obtained through PZ (Pole-Zero) simulation. As can be seen from the table data, the zero point changes in accordance with the output poles.

[0036]

[0037] In actual circuits, due to the characteristics of the Class AB structure, when the source current is high, the output current of MN2 increases, the current flowing through MP2 decreases, and its transconductance decreases. The zero-point following effect on the output pole is not as good as under ideal conditions, but it can still achieve a good compensation effect and realize the stability of the loop.

[0038] In this embodiment, feedback improves the accuracy of the output voltage, and the Class AB structure enables the circuit to simultaneously provide source and sink currents, accelerating transient response to load changes. By introducing a dynamic zero that follows changes in the output poles, the stability issue of the feedback loop is resolved.

[0039] Any modifications, additions, and equivalent substitutions made within the scope of the principles of this application shall still fall within the scope of the patent coverage of this application.

[0040] Unless otherwise stated, the term "connection" as used above refers to a logical relationship in the transmission of current, and does not necessarily mean a direct electrical connection. Furthermore, terms such as "first" and "second" do not indicate a sequential order, but rather distinguish between different characteristics.

Claims

1. A fast-response digital LDO with zero-point tracking compensation, characterized in that, The digital LDO includes an LDO signal input terminal, a preamplifier, a Class AB structure circuit, and an LDO output terminal. The LDO signal input terminal is used to receive signals and is connected to the first input terminal of the preamplifier; The preamplifier is used to provide gain. The second input terminal of the preamplifier is connected to the output terminal of the LDO. The output terminal of the preamplifier is connected to the first electrode of the first capacitor, the gate of the first NMOS transistor, and the first terminal of the resistor, respectively. The ClassAB structure circuit includes a complementary push-pull output pair circuit, a bias circuit, and a frequency compensation circuit. The complementary push-pull output transistor circuit includes a second NMOS transistor and a second PMOS transistor. The second NMOS transistor and the second PMOS transistor are source follower structures. The source of the second NMOS transistor is connected to the source of the second PMOS transistor and the output terminal of the LDO, respectively. The drain of the second NMOS transistor is connected to the power supply and the drain of the first NMOS transistor, respectively. The gate of the second NMOS transistor is connected to the second terminal of the resistor and the first electrode of the second capacitor, respectively. The drain of the second PMOS transistor is connected to the second electrode of the second capacitor, the ground line, and the second electrode of the first capacitor, respectively. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the first terminal of the bias current source, respectively. The source of the first NMOS transistor is connected to the source of the first PMOS transistor. The bias circuit includes a first NMOS transistor, a first PMOS transistor, and a bias current source. The bias circuit is used to determine the static operating point of the output stage of the ClassAB structure circuit. The drain of the first NMOS transistor is connected to the power supply, the power input terminal of the preamplifier, and the drain of the second NMOS transistor. The gate of the first NMOS transistor is also connected to the first electrode of the first capacitor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the drain of the first PMOS transistor. The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor and the first terminal of the bias current source. The second terminal of the bias current source is connected to the second electrode of the second capacitor, the second electrode of the first capacitor, the drain of the second PMOS transistor, and ground. The frequency compensation circuit includes a first capacitor, a second capacitor, and a resistor.

2. The digital LDO as described in claim 1, characterized in that, The preamplifier is a transconductance amplifier.

3. The digital LDO as described in claim 1, characterized in that, The digital LDO includes three poles and one zero. The first pole is the output terminal of the preamplifier, the second pole is the output terminal of the LDO, and the third pole is a high-frequency parasitic pole introduced by the zero. The zero is formed by the resistor and the second capacitor.

4. The digital LDO as described in claim 3, characterized in that, The output poles of the digital LDO P 0 Represented as ,in, It is the transconductance of the second NMOS transistor. It is the transconductance of the second PMOS transistor. C L It is the load capacitor.

5. The digital LDO as described in claim 3, characterized in that, The zero point of the digital LDO Z Represented as ,in, It is the transconductance of the second NMOS transistor. It is the transconductance of the second PMOS transistor. k It is the ratio of the transconductance of the first NMOS transistor to that of the first PMOS transistor. R This is the resistance value of the resistor. C 2 It is the capacitance value of the second capacitor.

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