A programmable logic device dynamic register configuration apparatus and a control method thereof

Abstract

The present disclosure provides a programmable logic device dynamic register configuration device and a control method thereof. The programmable logic device dynamic register configuration device comprises an external controller configured to provide configuration instructions and configuration data; a main controller configured to receive and parse the configuration data, generate a strobe signal and recombine data packets; at least one multiplexing module, each of which is configured to contain a register group; and one or more sub-controllers between the main controller and the multiplexing modules, configured to further parse the data packets and control the target register group to complete read / write operations. In addition, the present disclosure also provides a control method corresponding to the configuration device. Some embodiments of the present disclosure aim to solve the problems of high configuration switching time consumption and uncertain configuration switching time in the prior art without increasing excessive complexity and area overhead.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, specifically to a dynamic register configuration device for a programmable logic device and its control method. Background Technology

[0002] Register configuration is a core concept in embedded systems and low-level hardware programming. It refers to the process of writing specific values ​​to special function registers inside the processor through software instructions, thereby controlling the behavior, state, and function of hardware modules.

[0003] In existing technologies, the most mainstream design is the unified memory-mapped architecture. The processor core accesses all resources through a single system bus (e.g., AHB / AXI) and a lower-speed peripheral bus (e.g., APB). The key point is that the peripheral's Control and Status Register (CSR) is assigned specific, fixed physical memory addresses by the designer. When the CPU (or DMA controller) executes standard store instructions (STR) to write data to these addresses, the hardware address decoder identifies that the address falls within the address window of a specific peripheral and routes the write operation to the corresponding peripheral bus (e.g., APB). Ultimately, the data is written to the physical register unit inside the target peripheral controller. This architecture is simple and intuitive; software can configure registers by directly accessing memory addresses via pointers, but the address space allocation needs to be pre-planned and fixed.

[0004] Furthermore, bus standards like PCIe have a completely separate configuration address space. It is neither main memory nor traditional I / O space. Accessing this configuration space involves specialized protocols and transaction types (e.g., PCIe's Configuration Read / Write TLP). The key mechanism is that during system startup (or after hot-plugging), the software (BIOS / OS) discovers devices through an enumeration process and allocates configuration space resources for each device's function. The device's internal registers are mapped to the configuration space header (e.g., PCI Configuration Space Header) and its extended capability structures corresponding to their functions. The software reads and writes configuration registers using a unique address composed of the bus number, device number, function number, and register offset.

[0005] The above register configuration methods all require a dedicated and centralized register array space within the chip. This hardware layout is highly unsuitable for chip designs with multiple multiplexed modules, such as programmable logic devices. Furthermore, if dynamic register configuration needs to be implemented in a chiplet, overly complex configuration logic, such as that of a PCIe bus, is no longer appropriate. Therefore, a simpler, less resource-intensive, and reusable dynamic register configuration mode is essential.

[0006] Therefore, existing technologies still need to be improved and enhanced.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0008] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes a configuration storage device for a reconfigurable array. This configuration storage device and the configuration storage system comprising it can solve the problems of high configuration switching time and uncertain configuration switching time in the prior art without increasing excessive complexity and area overhead.

[0009] In a first aspect of this disclosure, a dynamic register configuration apparatus for a programmable logic device is provided, comprising: an external controller for providing configuration instructions and configuration data; a main controller for receiving and parsing the configuration data, generating strobe signals and reassembling data packets; at least one multiplexing module, each multiplexing module being configured to include a register group; and one or more sub-controllers are provided between the main controller and the multiplexing modules for further parsing data packets and controlling the target register group to complete read and write operations.

[0010] Furthermore, in some embodiments, the main controller and the external controller are connected via an input validity flag line, an output validity flag line, and a data line.

[0011] Furthermore, in some embodiments, the main controller and the sub-controller, and the sub-controller and the lower-level sub-controller or multiplexing module are connected by strobe lines and data lines.

[0012] Furthermore, in some embodiments, the programmable logic device dynamic register configuration device further includes: a readback signal chain structure, used to combine the readback data of multiple multiplexing modules or controllers through logical operations and then feed them back to the upper-level controller.

[0013] Furthermore, in some embodiments, the programmable logic device dynamic register configuration device, the above-mentioned logical operation is an "OR" operation or an "AND" operation.

[0014] Furthermore, in some embodiments, the programmable logic device dynamic register configuration device is configured such that: when a first-level sub-controller is provided between the main controller and the multiplexing module, the main controller and the sub-controller, and the sub-controller and the multiplexing module, are connected via gating lines and data lines; when multiple-level sub-controllers are provided between the main controller and the multiplexing module, the multiple-level sub-controllers include a first-level sub-controller directly connected to the main controller, and an Nth-level sub-controller connected to the (N-1)th-level sub-controller, where N is a positive integer greater than 2; the main controller and the first-level sub-controller, and the (N-1)th-level sub-controller and the Nth-level sub-controller, are connected via gating lines and data lines.

[0015] A second aspect of this disclosure also provides a control method for the aforementioned device, comprising: an external controller generating an input validity flag and configuration data based on a read / write request; a main controller receiving the configuration data, parsing the hierarchical address and register address of the target module, generating a strobe signal and reassembling the data packet; a sub-controller receiving the data packet, parsing and generating strobe, read / write, address, and data signals for a register group; the register group performing read / write operations based on the control signals; and the readback data being merged through a chain structure and returned to the external controller.

[0016] Furthermore, in some embodiments, the above configuration data includes: a first data packet containing the hierarchical address, register address, and read / write control information of the target module; and a second data packet, provided only during write operations, containing the configuration data to be written.

[0017] Furthermore, in some embodiments, if a write request is followed by a read request but no second data packet is received, the write request is automatically ignored and the read request is executed.

[0018] Furthermore, in some embodiments, the readback data is only valid when the output validity flag is high, and the output validity flag is generated synchronously with the valid readback data.

[0019] Furthermore, in some embodiments, the aforementioned readback data is merged step by step through logic gates, and modules that are not selected output logic 0.

[0020] A third aspect of this disclosure provides a control method for the aforementioned device, comprising: generating a first input flag signal based on a system clock and a write command, or generating a second input flag signal based on a system clock and a read command; generating write configuration data or read configuration data based on the hierarchical information of the target multiplexing module; transmitting the write configuration data and subsequent write data when the first input flag signal is determined to be at a set level; and transmitting the read configuration data when the second input flag signal is determined to be at a set level.

[0021] Furthermore, in some embodiments, if it is determined that the first input flag signal is at a set level and then the second input flag signal is at a set level, and it is determined that the transmitted write data is empty, then the transmission of the write configuration data is abandoned and the read configuration data is transmitted.

[0022] Furthermore, in some embodiments, the above-mentioned generation of write configuration data or read configuration data based on the hierarchical information of the target multiplexing module includes: generating hierarchical information of each multiplexing module based on the relationship between the controllers at each level inside the chip device and the multiplexing modules, and generating the hierarchical information of the target multiplexing module as the hierarchical information of the target multiplexing module.

[0023] Furthermore, in some embodiments, the control method further includes: generating an output flag signal after the second input flag signal according to the system clock; and acquiring readback data when the output flag signal is set to a certain level.

[0024] A fourth aspect of this disclosure provides a control method for the aforementioned device, comprising: generating a synchronous clock based on an external system clock; obtaining a first input flag signal or a second input flag signal; when it is determined that the first input flag signal is at a set level, acquiring write configuration data and write data following the write configuration data; parsing the write configuration data to extract a first-level strobe signal and selecting a target controller or target module of the first-level strobe signal according to the first-level strobe signal, and transmitting the remaining write configuration data and the write data to the selected target controller or target module; when it is determined that the second input flag signal is at a set level, acquiring read configuration data; parsing the read configuration data to extract a first-level strobe signal and selecting a target controller or target module of the first-level strobe signal according to the first-level strobe signal, and transmitting the remaining read configuration data to the selected target controller or target module.

[0025] This disclosure, compared to the prior art, includes at least the following beneficial effects:

[0026] In some embodiments, by employing a discrete controller architecture, the protocol is concise and significantly reduces hardware resource consumption (low state machine complexity and fewer LUTs required). Furthermore, in some embodiments, multi-level module reuse is supported, flexibly adapting to different levels of chip design. Further, in some embodiments, a readback signal chain structure is introduced, replacing multiplexers with logic gates, significantly saving wiring resources and area. Further, in some embodiments, dynamic read / write configuration is supported, allowing real-time updates of register contents during system operation, improving system reconfigurability. Further, in some embodiments, the protocol possesses fault tolerance capabilities, automatically handling abnormal situations such as incomplete configuration data, improving reliability. Attached Figure Description

[0027] The above and other features and advantages of the embodiments of this disclosure will become more apparent, taking into account the accompanying drawings and the following detailed description, wherein:

[0028] Figure 1 A schematic diagram of the architecture of a programmable logic device dynamic register configuration apparatus according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A schematic diagram of the internal architecture of the main multiplexing module according to an embodiment of the present disclosure is shown;

[0030] Figure 3 A schematic diagram of a multiplexer readback structure according to an embodiment of the present disclosure is shown;

[0031] Figure 4 A schematic diagram of an improved readback signal chain structure according to an embodiment of the present disclosure is shown;

[0032] Figure 5 A schematic diagram illustrating the normal read / write timing of the interaction signals between the external controller and the main controller according to an embodiment of the present disclosure is shown.

[0033] Figure 6 A schematic diagram of the timing of read / write conflicts in the interaction signals between the external controller and the main controller according to an embodiment of the present disclosure is shown.

[0034] Figure 7 A schematic diagram illustrating alternative read / write timing sequences for the interaction signals between the external controller and the main controller according to embodiments of the present disclosure is shown; and

[0035] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0036] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0037] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0038] Generally, register configuration is a core concept in embedded systems and low-level hardware programming. It refers to the process of writing specific values ​​to special function registers inside the processor through software instructions, thereby controlling the behavior, state, and function of hardware modules. Currently, there are two main register configuration architectures: 1) Unified Memory Mapping Architecture: The processor accesses all resources through the system bus (such as AHB / AXI) and peripheral bus (such as APB). The control and status registers (CSRs) of peripherals are assigned fixed physical memory addresses. When the CPU executes store instructions to write data to these addresses, the hardware address decoder routes the write operation to the corresponding peripheral bus, and finally the data is written to the physical register inside the target peripheral. This architecture is simple and intuitive, but the address space needs to be pre-planned and fixed, making it unsuitable for programmable logic devices with multiplexed modules. 2) Independent Configuration Address Space Architecture: For example, the PCIe bus standard has an independent configuration address space, accessed through dedicated protocols and transaction types. The device's internal registers are mapped to the configuration space header and its extended capability structure. Software reads and writes configuration registers using a unique address composed of the bus number, device number, function number, and register offset. This approach involves complex protocols and high hardware overhead, making it unsuitable for resource-constrained small chips or highly reusable scenarios. All the above technical solutions require an independent and centralized register array space within the chip, resulting in complex hardware layout planning, lack of support for efficient module reuse, and excessive protocol complexity and resource consumption when implementing dynamic configuration in small chips. Therefore, there is an urgent need for a simple, low-hardware-requirement, dynamic register configuration solution that supports multi-module reusability scenarios.

[0039] To address at least one of the aforementioned problems, and one or more other potential problems, exemplary embodiments of this disclosure provide a programmable logic device dynamic register configuration apparatus and its control method to solve the problems of complex protocols, high hardware resource consumption, and lack of support for multi-module reuse in the prior art. The following description, in conjunction with accompanying figures, provides a detailed explanation.

[0040] Figure 1 A schematic diagram of the architecture of a dynamic register configuration device for a programmable logic device according to an embodiment of the present disclosure is shown. In this illustrated embodiment, an external controller: located outside the chip, provides configuration instructions and timing control; a main controller: located at the top level of the chip, receives external instructions, parses and distributes them to lower levels; sub-controllers: located within each multiplexing module, receive instructions from the main controller, and directly control the registers; a register group: stores configuration data or status information; a readback chain structure: used for efficient data readback, avoiding the use of large multiplexers.

[0041] It should be understood that in this embodiment of the disclosure, a discrete controller architecture is adopted to achieve low hardware resource consumption, simplified communication protocols, and compatibility with reuse scenarios. Specifically, see [link to documentation]. Figure 1 In the example embodiment, the chip has 8 main multiplexing modules at the top level, and each main multiplexing module has 3 sub-multiplexing modules (in combination). Figure 2 Taking a 32-bit interactive data width as an example, a main controller is placed at the top layer of the chip to decode proprietary protocols, reassemble packets, and provide feedback data. Its input section mainly consists of input data validity flags and corresponding configuration data, with the configuration data having a 32-bit width. If external configuration of internal registers is required, two sets of 32-bit bits are needed to provide configuration information. The first set provides the address information and read / write control information for the multiplexing module and registers, while the second set provides the configuration data information. If external read operations are only required for internal registers, only the first set of 32-bit address and read / write control information is needed. The main controller generates a strobe signal for the main multiplexing module based on the configuration information and reassembles the acquired data. The new data packet contains the address information and configuration data provided to the sub-controller, such as... Figure 1 As shown.

[0042] Figure 2 A schematic diagram of the internal architecture of a main multiplexing module according to an embodiment of the present disclosure is shown. In some embodiments, the main controller interacts with a sub-controller located within the main multiplexing module, such as... Figure 2As shown, its main function is to decode the configuration data transmitted by the upper-level controller and transmit the relevant configuration data to the target register, or to retrieve data from the relevant target register according to the read instruction of the upper-level controller and feed it back to the upper-level controller. Its input part mainly consists of controller strobe signals and configuration data signals. The bit width of the configuration data signal is the sum of the data bit width of the configuration control information decoded by the upper-level controller and the data bit width of the configuration data information. After the sub-controller receives the strobe signal from the upper-level controller, it starts working, decoding the data into the corresponding register group strobe signals, read / write signals, address signals, and corresponding configuration data information according to the input configuration data signal. Furthermore, in some embodiments, the underlying register group can quickly configure the target register or quickly feed back the data information required by the controller after receiving the corresponding control signal.

[0043] It should be noted that, considering the large bit width of the interactive data, directly selecting the feedback data signal using a multiplexer and feeding it back to the controller would consume a significant amount of hardware resources, such as... Figure 3 As shown, such a practice is clearly unacceptable in chiplet or area-sensitive chip designs.

[0044] Therefore, in order to solve at least one of the above problems, and one or more other potential problems, the following example embodiments propose the following: Figure 4 A further improved architecture is a readback signal chain structure. This chain structure directly performs logical operations on the readback data of adjacent multiplexed modules, using an "OR" operation in the example, to reduce the occupation of wiring resources. If an "OR" operation is performed on the readback data in the readback chain structure, the controller not selected by the strobe signal will output a logic 0 for the readback data, thus not affecting the controller that needs to output readback data. Furthermore, this chain structure is a symmetrical design, still providing excellent support for module reusability.

[0045] Furthermore, in some embodiments, see [link to relevant documentation]. Figure 5This diagram illustrates the normal read / write timing of the interaction signals between the external controller and the main controller. In this example embodiment, the clock signal on the top row is a shared signal for all systems, serving as the system's synchronization reference. Furthermore, the input data validity flag and configuration data are provided by the external controller. The configuration data is only valid when the input data validity flag is high; otherwise, the data remains unchanged to prevent unnecessary power consumption. The configuration data consists of two parts: a configuration information part and a data information part. The configuration information (write) and data information 0 are input by the input data validity flag being high for two consecutive pulses. To improve the efficiency of data communication, the data information part only takes effect during "write" requests. That is, when a write operation occurs, both parts of the configuration data—configuration information and data information—are provided, as shown in the diagram: configuration information (write) + data information 0. During a "read" operation, only the configuration information (read) is needed to complete the read request, as shown in the configuration information (read) part of the diagram. Furthermore, a method is provided to address interference or misoperation, allowing the external controller to avoid interference from user misoperation. For example, refer to... Figure 6 When a user sends a set of configuration information for a "write" request, such as the configuration information (write) in the external controller configuration information shown in the diagram, but never sends any data information (i.e., the external controller data information is never input in the diagram), and instead sends configuration information for a "read" request, such as the configuration information (read) immediately following the external controller configuration information shown in the diagram, the external controller will only execute the read request and will automatically ignore the "write" request with incomplete configuration data. Furthermore, in some embodiments, the readback data and output data validity flags are provided by the main controller. Output data is valid only when the output data validity flag is high. This validity flag will output a high-level signal with the same cycle as the valid readback data at an appropriate time according to the specific pipeline design between controllers, to ensure that the external controller can obtain accurate readback data in the correct clock cycle. Furthermore, in some embodiments, referring to... Figure 5 To illustrate this more vividly, one clock cycle can be defined as one beat. Figure 5 The read request (the high-level signal for the input data validity flag in the diagram) and the output data validity flag are staggered by 4 beats because the structure in this embodiment uses a main controller and a sub-controller: First beat: The main controller parses the correct strobe signal, address, data, and other information based on the configuration data and sends it to the sub-controller; Second beat: The sub-controller parses the correct strobe signal, address, data, and other information based on the configuration data and sends it to the register group unit; Third beat: The register group outputs the corresponding readback data; Fourth beat: The main controller outputs the readback data after one beat; Alternatively, the pipeline (beating) design is not mandatory and will be determined according to different hardware performance requirements.

[0046] Furthermore, in some embodiments, synthesis Figure 1-5 The hardware architecture of this programmable logic device dynamic register configuration device includes an external controller, a main controller, sub-controllers, and a register group. The external controller is connected to the main controller via an input validity flag line and data lines. The main controller parses the configuration data packet from the external source, generates a strobe signal, reassembles the data, and sends it to the corresponding sub-controller. The sub-controller further decodes the data and controls the target register to complete the read / write operation. The configuration protocol of this programmable logic device dynamic register configuration device consists of two parts: a first set of data containing the target module's hierarchical address, register address, and read / write control information; and a second set of data (only required for write operations) containing the configuration data to be written. If an external read request is initiated, only the first set of data needs to be sent. If an external erroneous operation causes a write request to be sent without data and a read request is sent directly, the system will automatically ignore the incomplete write request and only perform the read operation. The readback mechanism of this programmable logic device dynamic register configuration device uses a readback signal chain structure in some embodiments to avoid the large amount of wiring resources consumed by using multiplexers. The readback data from each module is merged step-by-step through logic gates (such as OR gates). Modules not selected output logic 0, which does not affect the transmission of valid data. This structure is symmetrical and supports module reuse, significantly reducing area overhead. It should be understood that the write request in its timing diagram generally refers to the high level of the input data validity flag for two clock cycles. The high level in the first clock cycle corresponds to the configuration information in the configuration data, while the high level in the second clock cycle corresponds to the data information in the configuration data.

[0047] In some embodiments, the timing control of the programmable logic device dynamic register configuration device can be as follows: Figure 5In the normal read / write mode shown, the external controller provides valid configuration data when the input validity flag is high, synchronized with the clock. After parsing by the main controller, the data is pipelined to the sub-controllers and register bank. Readback data is valid when the output validity flag is high, ensuring the external controller captures data in the correct clock cycle. It should be understood that, in the diagram, the clock signal provides the system's basic timing, a continuous, equal-period square wave; flag signals (e.g., the external controller configuration flag, external controller data flag, and input data validity flag shown in the diagram) are valid within a specific clock cycle, used to identify the start or state of the corresponding data transmission phase. It should also be understood that the clock signal is the reference synchronization clock. The external controller configuration flag, high level, indicates the current configuration write phase. External controller configuration information, output when the configuration flag is valid, is configuration data. The external controller data flag, high level, indicates entry into the data transmission / reception phase. External controller data information, output when the data flag is valid, is write data. The input data validity flag indicates whether the current input data (configuration or write data) is valid. Configuration data: Configuration information received by the target device (corresponding to the configuration information of the external controller). Readback data: Read data returned by the target device in the later stages of the data phase. Output data validity flag: Indicates that the readback data is valid.

[0048] In some alternative embodiments, refer to Figure 7 The diagram illustrates the timing logic from the external controller down to the main controller. It should be understood that the read request (high level of the input data validity flag for one clock cycle, shown in dashed box 100) and the output data validity flag (high level of the output data validity flag for one clock cycle, shown in dashed box 100) are staggered by 4 clock cycles. This can be optionally adjusted according to the actual situation. For example, the first step is: the main controller parses the correct strobe signal, address, and data information from the configuration data and sends it to the sub-controller (dashed box 100); the second step is: the sub-controller parses the correct strobe signal, address, and data information from the configuration data and sends it to the register bank unit (dashed box 200); the third step is: the register bank outputs the corresponding readback data (dashed box 300); the fourth step is: the main controller outputs the readback data after one clock cycle (dashed box 400). The design of the above pipeline (steps that follow the clock cycle) will vary depending on the hardware performance requirements. Different pipeline designs (different number of clock cycles) should be considered the same design.

[0049] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0050] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A dynamic register configuration device for a programmable logic device, characterized in that, include: An external controller is used to provide configuration commands and configuration data; The main controller is used to receive and parse configuration data, generate strobe signals, and reassemble data packets. At least one multiplexing module, each multiplexing module being configured to contain a register set; One or more sub-controllers are set between the main controller and the multiplexing module to further parse data packets and control the target register group to complete read and write operations. The readback signal chain structure is used to combine the readback data from multiple multiplexing modules through logical operations and then feed it back to the main controller.

2. The configuration device according to claim 1, characterized in that, The main controller and the external controller are connected via an input validity flag line, an output validity flag line, and a data line; wherein the input validity flag is used to indicate the validity of the configuration data, and the output validity flag is used to indicate the validity of the readback data.

3. The configuration device according to claim 1, characterized in that, The main controller and the sub-controllers, as well as the sub-controllers and their subordinate sub-controllers or multiplexing modules, are connected via strobe lines and data lines.

4. The configuration device according to claim 1, characterized in that, The logical operation is either "OR" or "AND".

5. The configuration device according to claim 1, characterized in that, The configuration device is configured to: When a first-level sub-controller is set between the main controller and the multiplexing module, the main controller and the sub-controller, and the sub-controller and the multiplexing module are connected via strobe lines and data lines. When a multi-level sub-controller is configured between the main controller and the multiplexing module, the multi-level sub-controller includes a first-level sub-controller directly connected to the main controller, and an Nth-level sub-controller connected to the (N-1)th-level sub-controller, where N is a positive integer greater than 2; the main controller and the first-level sub-controller, and the (N-1)th-level sub-controller and the Nth-level sub-controller are configured to be connected via strobe lines and data lines.

6. A control method for the apparatus according to any one of claims 1-5, characterized in that, include: The external controller generates input validity flags and configuration data based on read / write requests; The main controller receives configuration data, parses the hierarchical address and register address of the target module, generates strobe signals, and reassembles the data packets; The sub-controller receives data packets, parses them, and generates strobe, read / write, address, and data signals for the register set. The register group performs read and write operations based on control signals; The readback data output from the register group is merged through a chain structure and returned to the external controller.

7. The method according to claim 6, characterized in that, The configuration data includes: The first data packet contains the target module's hierarchical address, register address, and read / write control information; The second data packet, provided only during write operations, contains the configuration data to be written.

8. The method according to claim 7, characterized in that, If a write request is followed by a read request but no second data packet is received, the write request is automatically ignored and the read request is executed.

9. The method according to claim 6, characterized in that, The readback data is only valid when the output validity flag is high, and the output validity flag is generated synchronously with the valid readback data.

10. The method according to claim 6, characterized in that, The readback data is merged step by step through logic gates, and the modules that are not selected output logic 0.

11. A control method for the apparatus according to any one of claims 1-5, characterized in that, include: Generate a first input flag signal based on the system clock and write command, or generate a second input flag signal based on the system clock and read command; Generate write configuration data or read configuration data based on the hierarchical information of the target reuse module; When it is determined that the first input flag signal is at a set level, the write configuration data and the write data following the write configuration data are transmitted. When it is determined that the second input flag signal is at the set level, the read configuration data is transmitted.

12. The control method according to claim 11, characterized in that, If, after determining that the first input flag signal is at a set level, the second input flag signal is also at a set level, and it is determined that the transmitted write data is empty, then the transmission of the write configuration data is abandoned and the read configuration data is transmitted.

13. The control method according to claim 11, characterized in that, The step of generating write configuration data or read configuration data based on the hierarchical information of the target multiplexing module includes: The hierarchy information of each multiplexing module is generated based on the relationship between the controllers and multiplexing modules within the chip device, and the hierarchy information of the target multiplexing module is generated as the hierarchy information to which the target multiplexing module belongs.

14. The control method according to claim 11, characterized in that, Also includes: The output flag signal is generated after the second input flag signal according to the system clock; When the output flag signal is determined to be at the set level, readback data is acquired.

15. A control method for the apparatus according to any one of claims 1-5, characterized in that, include: Generate a synchronous clock based on an external system clock; Obtain the first input flag signal or the second input flag signal; When it is determined that the first input flag signal is at a set level, the write configuration data and the write data after the write configuration data are obtained; the first level strobe signal is parsed from the write configuration data and the target controller or target module of the first level strobe signal is selected according to the first level strobe signal, and the remaining write configuration data and the write data are transmitted to the selected target controller or target module. When it is determined that the second input flag signal is at a set level, read configuration data is acquired; the first-level gating signal is parsed from the read configuration data and the target controller or target module of the first-level gating signal is selected according to the first-level gating signal, and the remaining read configuration data is transmitted to the selected target controller or target module.

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