Electromagnetic simulation modeling method for universal QFN packaging structure

Abstract

The invention relates to the technical field of integrated circuit packaging structure simulation, and particularly discloses an electromagnetic simulation modeling method of a universal QFN packaging structure, comprising: designing a drawing of the universal QFN packaging structure, the drawing comprising a plurality of layers, each layer comprising a closed polyline graph and a one-dimensional line graph; importing a drawing of a general QFN packaging structure, converting all closed polyline graphs into two-dimensional graphs, and keeping attributes of one-dimensional line graphs unchanged; three-dimensional modeling operation of the two-dimensional graph and the one-dimensional line segment graph is completed according to the three-dimensional modeling parameters; digging out a front half-etching region and a back half-etching region in the frame metal; and identifying the conductors with the connection relationship for naming and merging, and identifying a certain interface of the conductors for electromagnetic simulation port setting, and finally obtaining a three-dimensional electromagnetic simulation model of the universal QFN packaging structure. According to the method, the electromagnetic simulation modeling efficiency of the universal QFN packaging structure can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit package structure simulation, and particularly relates to an electromagnetic simulation modeling method of a general QFN package structure. BACKGROUND

[0002] QFN (Quard Flat No-leads Package, square flat no-lead) package is a surface mount packaging technology, the front of the chip faces up, and the back is welded to the central large-area exposed pad of the QFN frame to improve the heat dissipation efficiency and provide substrate grounding effect; the chip pad is connected to the main body of the metal frame through the metal bonding wire, and is further led out through the electric pads distributed around. The package cancels the traditional extension pins, which can effectively reduce the length of the electrical connection and the size of the package, has excellent electrical and thermal performance, and is suitable for digital / analog circuits with low electrical connection density.

[0003] With the increase of application frequency, the high-frequency parasitic effect of the package electrical connection becomes an important bottleneck restricting the performance of the circuit, and high-precision three-dimensional modeling and high-frequency electromagnetic simulation become key links of the design of the radio frequency analog device / high-speed digital circuit package. The mainstream three-dimensional electromagnetic simulation tools include Ansys platform HFSS, chip and Hermes, etc. After the two-dimensional graphics in the CAD drawing format are imported and three-dimensional modeling is performed, the bonding wire model is added. Due to the difference in human design, there is no uniform standard for the layer setting and naming method of the two-dimensional design drawing, and in most cases, simulation needs to be identified and modeled manually; at the same time, the direction of the bonding wire is mostly a type of radiation from the center of the chip outward, and it is impossible to batch-select and re-orient the drawing. A large amount of manual identification and operation leads to low efficiency of QFN package design simulation modeling. SUMMARY

[0004] The present application aims to overcome the deficiencies in the prior art, and provides an electromagnetic simulation modeling method of a general QFN package structure, which can construct a high-precision three-dimensional model suitable for three-dimensional FEM (finite element) mesh partitioning and electromagnetic port setting, and solve the problem of low three-dimensional package design modeling efficiency.

[0005] As a first aspect of the present application, an electromagnetic simulation modeling method of a general QFN package structure is provided, which comprises: Step S1: design a drawing of a general QFN package structure, the drawing comprising a plurality of layers, each layer comprising a closed polyline graph and a one-dimensional line segment graph; wherein the closed polyline graph comprises a chip outer frame, a chip pad, a package outer frame, a frame metal, a front half-etching area and a back half-etching area, and the one-dimensional line segment graph is a bonding wire from the chip pad to the frame metal; Step S2: import the drawing of the general QFN package structure based on a three-dimensional electromagnetic simulation modeling tool, convert all closed polyline patterns into two-dimensional patterns, and keep the attributes of the one-dimensional line segment patterns unchanged; Step S3: after importing the drawing of the general QFN package structure, configure the three-dimensional modeling parameters of the general QFN package structure, and complete the three-dimensional modeling operation of the two-dimensional patterns and the three-dimensional modeling operation of the one-dimensional line segment patterns according to the three-dimensional modeling parameters; Step S4: select the frame metal, the front half-etching area, and the back half-etching area to perform Boolean operation to remove the front half-etching area and the back half-etching area in the frame metal; Step S5: identify the conductors with connection relationship to perform naming merging, and identify the interface of a conductor according to the position characteristics to perform electromagnetic simulation port setting, and finally obtain the three-dimensional electromagnetic simulation model of the general QFN package structure.

[0006] Further, the drawing of the general QFN package structure further comprises: The drawing of the general QFN package structure is designed by layer differentiation and standardized naming.

[0007] Further, the converting all closed polyline patterns into two-dimensional patterns, and keeping the attributes of the one-dimensional line segment patterns unchanged further comprises: After converting all closed polyline patterns into two-dimensional patterns, the two-dimensional patterns continue to use the layer name of the closed polyline patterns, and when there are separate patterns, the naming is in the form of "layer name" + "number"; The attributes of the one-dimensional line segment patterns are kept unchanged, and the one-dimensional line segment patterns are also named in the form of "layer name" + "number"; All two-dimensional patterns and all one-dimensional line segment patterns are kept at the same default height in the vertical direction.

[0008] Further, the three-dimensional modeling parameters of the general QFN package structure include the thickness of the chip outer frame, the material of the chip outer frame, the electrical parameters of the chip outer frame, the thickness of the chip pad, the material of the chip pad, the electrical parameters of the chip pad, the thickness of the frame metal, the material of the frame metal, the electrical parameters of the frame metal, the thickness of the package outer frame, the material of the package outer frame, the electrical parameters of the package outer frame, the thickness of the front half-etching area, the thickness of the back half-etching area, the arc shape of the bonding lead, the material of the bonding lead, and the electrical parameters of the bonding lead.

[0009] Further, the completing the three-dimensional modeling operation of the two-dimensional patterns according to the three-dimensional modeling parameters further comprises: Pick up the two-dimensional graphics according to the naming features, and translate the two-dimensional graphics to the corresponding height position in the Z-axis direction, and perform batch thickening processing on the two-dimensional graphics according to the thickness parameter, and set the material, color and display transparency of the two-dimensional graphics; wherein the height position can be superimposed according to the thickness parameter, and the bottom surface of the general QFN packaging structure is taken as the Z-axis zero point, and the whole is modeled in the positive direction of the Z-axis.

[0010] Further, in the three-dimensional modeling operation of the one-dimensional line segment graphics according to the three-dimensional modeling parameters, further comprising: The bonding wires diverge from the chip center to the package frame, and the directions are different, the bonding wires are sequentially three-dimensionally modeled according to the paths of the bonding wires, and the material, color, display transparency of the bonding wires are set.

[0011] The electromagnetic simulation modeling method of the general QFN packaging structure provided by the application has the following advantages: the idea of batch processing homodirectional operation-sequential processing heterodirectional operation is adopted, the standard naming and script operation are used, the time consumption of manual operation can be greatly reduced, the two-dimensional graphics are precisely three-dimensionally modeled through preset parameters, in-situ displacement and thickening operations, a rule interface suitable for electromagnetic simulation port setting is provided, and the simulation modeling efficiency of the general QFN packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are used to provide a further understanding of the application, and constitute a part of the specification, and are used together with the following specific embodiments to explain the application, but do not constitute a limitation on the application.

[0013] Figure 1 The flowchart of the electromagnetic simulation modeling method of the general QFN packaging structure provided by the application.

[0014] Figure 2 The front view of the general QFN packaging structure in the example of the application.

[0015] Figure 3 The back view of the general QFN packaging structure in the example of the application.

[0016] Figure 4 The half-etching side view of the general QFN packaging structure in the example of the application.

[0017] Figure 5 The schematic diagram of importing the general QFN packaging structure drawing based on the three-dimensional electromagnetic simulation modeling tool in the example of the application.

[0018] Figure 6 The schematic diagram of the JEDEC_4Points bonding wire model in the example of the application.

[0019] Figure 7 A three-dimensional electromagnetic simulation model schematic diagram of a general QFN package structure in the embodiment of the present application. DETAILED DESCRIPTION

[0020] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0021] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0022] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0023] An electromagnetic simulation modeling method of a general QFN package structure is provided in the embodiment, Figure 1 A flow chart of an electromagnetic simulation modeling method of a general QFN package structure provided by the present application. As Figure 1 shown, the electromagnetic simulation modeling method of the general QFN package structure includes: Step S1: design a drawing of a general QFN package structure, the drawing includes a plurality of layers, each layer includes a closed multi-segment line pattern and a one-dimensional line segment pattern; wherein, as Figures 2-4 shown, the closed multi-segment line pattern includes a chip outer frame 1, a chip pad 2, a package outer frame 3, a frame metal 4, a front half-etching area 5 and a back half-etching area 6, and the one-dimensional line segment pattern is a bonding lead from the chip pad to the frame metal; Preferably, the design of the drawing of the general QFN package structure further includes: The drawing of the general QFN package structure is designed by layer distinction and standardized naming. For example, the chip outer frame is named as "DIE", the chip pad is named as "PAD", the package outer frame is named as "QFN_outline", the frame metal pattern is named as "QFN_metal", the front half-etching area is named as "TOP_Etching", the back half-etching area is named as "BTM_Etching", and the bonding wire is usually not displayed with the line diameter and bonding arc information, and the layer naming can be in the form of, for example, "BondingWire".

[0024] Step S2: as shown in Figure 5 , the drawing of the general QFN package structure is imported based on a three-dimensional electromagnetic simulation modeling tool (Ansys EM-HFSS), all closed polyline patterns are converted into two-dimensional patterns, and the attributes of the one-dimensional line segment patterns remain unchanged; Preferably, in the process of converting all closed polyline patterns into two-dimensional patterns and keeping the attributes of the one-dimensional line segment patterns unchanged, the process further includes: After converting all closed polyline patterns into two-dimensional patterns, the two-dimensional patterns continue to use the layer names of the closed polyline patterns, and when there are separate patterns, the naming is in the form of "layer name" + "number", for example, "PAD_1", "PAD_2"; The attributes of the one-dimensional line segment patterns remain unchanged, and the naming of the one-dimensional line segment patterns is also in the form of "layer name" + "number", for example, "BondingWire _1", "BondingWire _2"; All two-dimensional patterns and all one-dimensional line segment patterns are kept at the same default height in the vertical direction (Z-axis), for example, at the position of Z-axis 0.

[0025] Step S3: after importing the drawing of the general QFN package structure, the three-dimensional modeling parameters of the general QFN package structure are configured, and the three-dimensional modeling operation of the two-dimensional patterns and the three-dimensional modeling operation of the one-dimensional line segment patterns are completed based on the three-dimensional modeling parameters according to the automatic script; Preferably, the three-dimensional modeling parameters of the general QFN package structure include but are not limited to the thickness of the chip outer frame, the material of the chip outer frame, the electrical parameters of the chip outer frame, the thickness of the chip pad, the material of the chip pad, the electrical parameters of the chip pad, the thickness of the frame metal, the material of the frame metal, the electrical parameters of the frame metal, the thickness of the package outer frame, the material of the package outer frame, the electrical parameters of the package outer frame, the thickness of the front half-etching area, the thickness of the back half-etching area, the bonding wire arc, the material of the bonding wire, and the electrical parameters of the bonding wire.

[0026] Preferably, in the process of completing the three-dimensional modeling operation of the two-dimensional patterns according to the three-dimensional modeling parameters, the process further includes: According to the naming feature, the two-dimensional graph is picked up, and the two-dimensional graph is translated in the Z-axis direction to the corresponding height position, and the two-dimensional graph is batch thickened according to the thickness parameter, and the material, color and display transparency of the two-dimensional graph are set; wherein the height position can be calculated according to the thickness parameter, and the bottom surface of the general QFN packaging structure is taken as the zero point of the Z-axis, the whole is modeled in the positive direction of the Z-axis, and the packaging frame, the frame metal and the back half-etching area have a height of 0; the chip outer frame and the front half-etching area have a height of the frame metal thickness value; the chip pad height and the bonding wire height are the frame metal thickness value+chip thickness value. In this case, the package thickness, the frame metal thickness, the back half-etching area thickness and the chip outer frame thickness are positive values, and the chip pad thickness and the front half-etching area thickness are negative values.

[0027] Preferably, in the three-dimensional modeling operation of the one-dimensional line segment graph according to the three-dimensional modeling parameters, the following operations are further included: The bonding wire diverges from the chip center to the packaging frame, and the directions are different. The bonding wire is sequentially three-dimensionally modeled according to the path of the bonding wire, and the material, color and display transparency of the bonding wire are set. For example, based on the JEDEC_4Points bonding wire model standard, as shown in the following figure: Figure 6 The starting point of the bonding wire is the chip pad side line segment endpoint, the terminal point of the bonding wire is the frame metal side line segment endpoint, D is the bonding horizontal length, corresponding to the one-dimensional line segment length value; h1 is the bonding arc height, and the conventional value can be 200um; h2 is the bonding height difference, corresponding to the chip thickness value; Diameter is the bonding wire diameter, and the conventional value can be 25um; the cross section of the bonding wire can adopt a regular hexagon, a regular octagon or a circle.

[0028] Step S4: based on the automatic script, the frame metal, the front half-etching area and the back half-etching area are selected according to the naming to perform Boolean operation to remove the front half-etching area and the back half-etching area in the frame metal; Step S5: based on the automatic script, the conductors (chip pad, bonding wire, frame metal) having a connection relationship are identified to perform naming merging, and the interface of the conductor is identified according to the position feature to perform electromagnetic simulation port setting, as shown in the following figure: Figure 7 The three-dimensional electromagnetic simulation model of the general QFN packaging structure is finally obtained.

[0029] The application provides an electromagnetic simulation modeling method of a general QFN packaging structure. When a 2D (two-dimensional) metal frame drawing is designed, layer differentiation and standardized naming are adopted. The layers should include a chip outer frame, a chip pad, a QFN packaging outer frame, a frame metal, a front half-etching pattern, a back half-etching pattern and the like, and are depicted by closed multi-segment lines. Bonding lead paths are described by one-dimensional line segments. Automatic scripts are adopted, two-dimensional patterns are picked up according to naming features, and three-dimensional modeling is processed in batches according to the same vector. Automatic scripts are adopted to pick up one-dimensional line segments of the bonding path, to judge the bonding direction, and to sequentially process three-dimensional modeling of the bonding lead according to the line segment corresponding vector and the bonding length, wire diameter, arc and other parameters. A high-precision three-dimensional model suitable for three-dimensional FEM (finite element) mesh partitioning and electromagnetic port setting can be constructed, that is, a high-frequency electromagnetic simulation model is efficiently and accurately established, and the problem of low three-dimensional packaging design modeling efficiency is solved.

[0030] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. An electromagnetic simulation modeling method for a general QFN package structure, characterized in that, The electromagnetic simulation modeling method for the general QFN package structure includes: Step S1: Design a drawing of a general QFN package structure. The drawing includes multiple layers, each layer including a closed polyline pattern and a one-dimensional line segment pattern. The closed polyline pattern includes the chip outline, chip pads, package outline, frame metal, front half-etched area and back half-etched area. The one-dimensional line segment pattern is the bonding wire from the chip pads to the frame metal. Step S2: Import the drawings of the general QFN package structure using a 3D electromagnetic simulation modeling tool, convert all closed polyline graphics into 2D graphics, and keep the properties of the 1D line segment graphics unchanged; Step S3: After importing the drawings of the general QFN package structure, configure the three-dimensional modeling parameters of the general QFN package structure, and complete the three-dimensional modeling operation of the two-dimensional graphic and the three-dimensional modeling operation of the one-dimensional line segment graphic according to the three-dimensional modeling parameters. Step S4: Select the frame metal, the front half-etched area and the back half-etched area to perform Boolean operation to remove the front half-etched area and the back half-etched area in the frame metal; Step S5: Identify conductors with connection relationships for naming and merging, and identify a certain interface of the conductor based on its position characteristics to set the electromagnetic simulation port, finally obtaining the three-dimensional electromagnetic simulation model of the general QFN package structure.

2. The electromagnetic simulation modeling method for a general QFN package structure according to claim 1, characterized in that, The drawings for the design of the general QFN package structure also include: Drawings for the general QFN package structure are designed using layer differentiation and standardized naming.

3. The electromagnetic simulation modeling method for a general QFN package structure according to claim 1, characterized in that, The process of converting all closed polyline figures into two-dimensional figures while maintaining the properties of the one-dimensional line segment figures also includes: After converting all closed polyline graphics into two-dimensional graphics, the two-dimensional graphics retain the layer names of the closed polyline graphics. When there are separate graphics, they are named in the form of "layer name" + "number". Keeping the attributes of the one-dimensional line segment graphic unchanged, the one-dimensional line segment graphic is named in the same format of "layer name" + "number"; Keep all 2D graphics and all 1D line segment graphics at the same default height in the vertical direction.

4. The electromagnetic simulation modeling method for a general QFN package structure according to claim 1, characterized in that, The 3D modeling parameters of the general QFN package structure include chip frame thickness, chip frame material, chip frame electrical parameters, chip pad thickness, chip pad material, chip pad electrical parameters, frame metal thickness, frame metal material, frame metal electrical parameters, package frame thickness, package frame material, package frame electrical parameters, front half-etched area thickness, back half-etched area thickness, bonding wire arc shape, bonding wire material, and bonding wire electrical parameters.

5. The electromagnetic simulation modeling method for a general QFN package structure according to claim 4, characterized in that, The step of completing the 3D modeling operation of the 2D graphic based on the 3D modeling parameters also includes: The two-dimensional graphic is picked up according to the naming feature, and the two-dimensional graphic is translated to the corresponding height position in the Z-axis direction. The two-dimensional graphic is then batch thickened according to the thickness parameter, and the material, color and display transparency of the two-dimensional graphic are set. The height position can be calculated by superposition according to the thickness parameter. The bottom surface of the general QFN package structure is taken as the Z-axis zero point, and the whole is modeled in the positive Z-axis direction.

6. The electromagnetic simulation modeling method for a general QFN package structure according to claim 4, characterized in that, The step of completing the 3D modeling operation of the one-dimensional line segment graphic based on the 3D modeling parameters further includes: The bonding wires radiate from the chip center to the package outline in different directions. The bonding wires are sequentially modeled in three dimensions according to their paths, and the material, color, and transparency of the bonding wires are set.

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