Processor verification system and method, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a processor verification system and method, electronic equipment and a readable storage medium. The system comprises an equipment end and a processing end. The equipment end comprises at least two processor cores of a processor to be verified; the processing end comprises a network-on-chip, and the network-on-chip is used for data interaction among the processor cores in the equipment end; the equipment end is connected with the processing end through an optical module, and the optical module adopts a preset communication protocol. According to the invention, physical separation and logic centralized management are realized, and large-scale network-on-chip logic is stripped from a processor core end and centralized to a special processing end, so that the logic complexity of an equipment end where the processor core is located is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of on-chip network technology, and in particular to a processor verification system, method, electronic device, and readable storage medium. Background Technology

[0002] With the development of on-chip network technology, large-scale multi-core processor designs are becoming increasingly popular. To achieve high-speed communication and data consistency between cores, coherent mesh networks (CMNs) are typically used. As the number of processor cores (such as 16 cores and above) increases dramatically, the size and complexity of CMNs also grow exponentially.

[0003] When performing physical verification on the aforementioned large-scale multi-core processor chips (System on a Chip, SoC), all cores and CMN logic are typically integrated onto one or more Field-Programmable Gate Arrays (FPGAs). However, this approach results in logic and routing resources exceeding the capabilities of a single FPGA, making effective logic partitioning and routing difficult and thus challenging to implement. Summary of the Invention

[0004] The purpose of this invention is to provide a processor verification system, method, electronic device, and readable storage medium to solve the problem of the high difficulty in implementing processor verification systems. The specific technical solution is as follows: In a first aspect of the present invention, a processor verification system is provided, the system comprising a device end and a processing end; The device includes at least two processor cores of the processor to be verified; The processing end includes an on-chip network, which is used for data interaction between the processor cores in the device end; The device and the processing end are connected via an optical module, which uses a preset communication protocol.

[0005] Optionally, the device includes at least two core groups, and one core group contains at least two processor cores; The on-chip network includes multiple processing nodes; one of the processing nodes is used for data interaction between at least one processor core in the core group.

[0006] Optionally, the processing nodes include at least a first type of node and a second type of node; the number of the first type of node is the same as the number of the core group. One of the first type of nodes is used for data interaction between the processor cores in one of the core groups; A second type node is used for data interaction between at least one core group corresponding to a first type node.

[0007] Optionally, the device may further include caches corresponding to each of the processor cores and target interfaces; the target interfaces satisfy the protocol requirements corresponding to the preset communication protocol.

[0008] Optionally, each of the core groups and the processing terminal in the device are deployed on at least one programmable logic device.

[0009] Optionally, the on-chip network is a CMN network; the preset communication protocol is the CXL protocol.

[0010] In a second aspect of the present invention, a processor verification method is also provided, the method being applied to a processing end in a processor verification system, wherein the processor verification system is the processor verification system described in the first aspect; the method includes: The receiver receives transaction data packets sent by any of the processor cores in the receiving device; the transaction data packets are generated based on memory operation instructions. The target processor core corresponding to the memory operation instructions is determined based on a globally consistent catalog. Generate a spying request and send the spying request to the target processor core; Upon receiving a spy response from the target processor core based on the spy request, the system executes the memory operation instructions based on the spy response to obtain the execution result and updates the global consistency directory. A response data packet is generated based on the execution result and sent to the processor core.

[0011] In a third aspect of the present invention, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus. Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the method described in the first aspect above.

[0012] In a fourth aspect of the invention, a computer-readable storage medium is also provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the method described in the first aspect.

[0013] In a fifth aspect of the invention, a computer program product comprising instructions is also provided, which, when run on a computer, causes the computer to perform the method described in the first aspect above.

[0014] The processor verification system provided in this invention divides the verification system into a device end and a processing end. The processor core is located on the device end, and the on-chip network is located on the processing end, thereby decoupling the on-chip network and the processor core. This achieves physical separation and centralized logical management, allowing large-scale on-chip network logic to be separated from the processor core and centralized on the dedicated processing end, significantly reducing the logical complexity of the device end where the processor core resides. Simultaneously, the device end and processing end are connected via optical modules, eliminating the need for traditional low-speed input / output (IO) ports. Optical interconnection enables nanosecond-level latency between physically separated FPGA boards, ensuring the timing feasibility of the CXL.cache protocol and guaranteeing bandwidth and low latency communication between the two ends, thus improving the verification speed of the entire processor verification system. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0016] Figure 1 This is a structural diagram of a processor verification system according to an embodiment of the present invention; Figure 2 This is a structural diagram of another processor verification system in an embodiment of the present invention; Figure 3 This is a flowchart of the steps of a processor verification method provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0019] Figure 1 This is a structural diagram of a processor verification system according to an embodiment of the present invention, such as... Figure 1 As shown, the system may include a device end 11 and a processing end 12.

[0020] The device includes at least two processor cores of the processor to be verified. The processing end includes an on-chip network, which is used for data interaction between the processor cores in the device.

[0021] The device and the processing end are connected via an optical module, which uses a preset communication protocol.

[0022] The processor to be verified can be a processor design in the design phase or a completed processor design that requires verification; this embodiment of the invention does not impose any limitations on this. Accordingly, the processor to be verified can be a multi-core processor, which may include at least two processor cores.

[0023] The on-chip network mentioned above can be an on-chip network that enables data consistency (cache coherence) and high-speed interconnection between different core, cache, and input / output (IO) port devices. For example, it can be a coherent mesh network (CMN). Of course, it can also be other on-chip networks that enable data consistency and high-speed interconnection. This embodiment of the invention does not limit this.

[0024] Optionally, the processor verification system in this embodiment of the invention may be an FPGA prototype verification system for a coherent on-chip network (CMN) in a hyperscale multi-core processor, thereby facilitating cache coherency verification across FPGA boards.

[0025] The aforementioned optical module can be an optical module supporting a preset communication protocol. This preset communication protocol can be a pre-set interconnection protocol between the processor and the device, or a high-speed serial communication protocol (e.g., ComputeExpress Link, CXL), and this embodiment of the invention does not impose limitations on it. CXL can provide a high-bandwidth, low-latency, cache-coherent connection between the processor and the device, and it includes three sub-protocols: CXL.io, CXL.cache, and CXL.mem, specifically designed for heterogeneous computing and memory expansion.

[0026] Optionally, each of the core groups and the processing terminal in the device are deployed on at least one programmable logic device.

[0027] The aforementioned Field-Programmable Gate Array (FPGA) can be configured to implement specific digital logic functions. For example, the processing end can be a CMN core node FPGA, and one or more independent FPGA boards can be designed specifically to implement the logic of the entire CMN network. Accordingly, each or each group of processor cores can be independently implemented on a dedicated FPGA board. These FPGAs can contain processor cores, caches (L1 / L2), and a CXL device interface logic, serving as the CXL device end.

[0028] Furthermore, the FPGA at the device end and the processing end can be connected by optical fiber, and an optical module can be used to convert the optical signal into an electrical signal for the FPGA to read.

[0029] Furthermore, the aforementioned optical module can be an optical module supporting a preset communication protocol. This preset communication protocol can be configured according to the actual situation of the on-chip network; for example, it could be the CXL protocol. Correspondingly, the aforementioned optical module can be a high-speed pluggable optical module (Quad Small Form-factor Pluggable Double Density, QSFP-DD). It supports up to eight high-speed channels, each capable of operating at 50Gbps or 100Gbps, with a total bandwidth of 400Gbps or 800Gbps. It also features a small package size, relatively low power consumption, and supports full-duplex transmission, making it an ideal choice for achieving high-density, high-bandwidth interconnects. Many servers and FPGA boards supporting the Peripheral Component Interconnect Express (PCIe) Gen5 / Gen6 standard have already reserved QSFP-DD interfaces.

[0030] Specifically, the on-chip network can contain the following core modules, each of which can be implemented on a separate FPGA.

[0031] Router Node: This is the basic unit of CMN, responsible for routing packets from one core to another or shared resources. It needs to implement complex routing algorithms, such as XY-order routing, and handle different packet priorities. Each router contains input buffers, output buffers, an arbiter, and a routing table.

[0032] The Coherence Engine is the core of CMN, responsible for maintaining cache consistency across the entire system. It requires implementing a complex finite state machine (FSM) to handle various caching protocols (such as MESI or MOESI) and manage the shared cache directory. This engine needs to efficiently track the state of data in all core caches and send appropriate snoop requests or responses.

[0033] Shared Cache Controller: Responsible for managing L3 or other shared caches. It needs to handle requests from multiple cores and perform read and write operations according to cache consistency protocols. To achieve high throughput, the controller typically employs a multi-bank design to support parallel access.

[0034] Core Interface: Connects each CPU core to the CMN network. This interface needs to convert requests from the core (such as memory read / write and atomic operations) into CMN protocol data packet format and decode the data packets returned by CMN back to the core.

[0035] The aforementioned processing end can be used as the host processor of CXL, responsible for handling communication requests between all processor cores and maintaining data consistency protocols.

[0036] Furthermore, each or each group of processor cores is independently implemented on a dedicated FPGA board. These FPGAs contain only the processor core, cache (L1 / L2), and a CXL device interface logic, serving as the CXL device side. Further, the CMN core node FPGA and each CPU core FPGA are physically interconnected at high speed and low latency via optical modules supporting the CXL protocol. Specifically, logically, each CPU core FPGA establishes a cache-coherent connection with the CMN core node FPGA through the CXL.cache sub-protocol in the CXL protocol, thereby enabling cross-board inter-core communication and data sharing. The CMN core node FPGA maintains a global cache-coherent catalog to ensure that the L1 / L2 caches of all CPU core FPGAs are consistent with the shared data in the system.

[0037] Figure 2 This is a structural diagram of another processor verification system according to an embodiment of the present invention, such as... Figure 2 As shown, cores 1-x represent core groups deployed on different FPGAs on the device side, and these core groups can be connected via CXL cables. The on-chip network controller corresponds to the processing end, which can be connected to each core group via a switch (e.g., a CXL switch). Furthermore, each core group can also connect to the device host via Ethernet or Peripheral Component Interconnect Express (PCIe), where the host is used to read waveforms and download test files. Additionally, the processing end can also connect to peripherals.

[0038] It should be noted that when the number of processor cores is greater than 16, if all cores and CMN logic are integrated on one or more ultra-large FPGAs according to relevant technologies, the routing of traditional printed circuit boards (PCBs) often cannot meet the channel density and signal integrity requirements of serializers / deserializers (SerDes), resulting in a bottleneck in board-level electrical routing.

[0039] The processor verification system provided in this embodiment of the invention divides the verification system into a device end and a processing end. The processor core is located on the device end, and the on-chip network is located on the processing end, thereby decoupling the on-chip network and the processor core. This achieves physical separation and logical centralized management, and allows large-scale on-chip network logic to be separated from the processor core and concentrated on the dedicated processing end, significantly reducing the logical complexity of the device end where the processor core is located. Simultaneously, the device end and processing end are connected via optical modules, eliminating the need for traditional low-speed input / output (IO) ports. Optical interconnection enables nanosecond-level latency between physically separated FPGA boards, ensuring the timing feasibility of the CXL.cache protocol, guaranteeing bandwidth and low latency for communication between the two ends, and improving the verification speed of the entire processor verification system.

[0040] Optionally, the device includes at least two core groups, one of the core groups containing at least two processor cores; the on-chip network includes multiple processing nodes; and one of the processing nodes is used for data interaction between at least one of the processor cores in the core group.

[0041] Specifically, the device side of this embodiment of the invention may include at least two core groups, and a relatively small FPGA board may be used as a CPU core node. Each FPGA board may implement a processor core, its private L1 / L2 cache, and a Device interface logic conforming to the CXL specification.

[0042] Accordingly, one or more high-end FPGA boards (depending on the CMN scale) can be used as CMN core nodes (i.e., the aforementioned processing nodes). This FPGA board only implements all the CMN logic, cache coherency protocol engine, CXL Host interface, and routing logic required by the processor core for data interaction between the processor cores.

[0043] Furthermore, logically, each CPU core FPGA (core group) can establish a cache coherence connection with the CMN core node FPGA through the CXL.cache sub-protocol in the CXL protocol.

[0044] This approach separates the multi-core processor from the on-chip network. Furthermore, by using multiple processing nodes to manage different core groups, the load on each processing node can be further reduced.

[0045] Optionally, the processing node includes at least a first type of node and a second type of node; the number of the first type of node is the same as the number of the core groups; one first type of node is used for data interaction between the processor cores in one core group; one second type of node is used for data interaction between the core groups corresponding to at least one first type of node.

[0046] It should be noted that when the number of cores increases to several hundred, even the most advanced FPGAs may face issues such as logic resource exhaustion or clock frequency degradation in the CMN core node, the CXL Host. The complexity of the CMN and the processing load of the global cache coherence protocol will become new bottlenecks.

[0047] In this context, embodiments of the present invention can introduce a multi-level CXL interconnect network architecture. Specifically, a first type of node and a second type of node are configured. The first type of node is used for data interaction between processor cores within a core group, while the second type of node is used for data interaction between different core groups. For example, taking a group with 32 processor cores, the 32 cores can be divided into four clusters (core groups). Each cluster is managed by a CMN-L2 node (first type of node) FPGA, which manages cache coherency within that cluster. These four CMN-L2 node FPGAs are then connected to a CMN-L1 node (second type of node) FPGA via a higher-level CXL Fabric, which is responsible for maintaining global cache coherency.

[0048] This hierarchical tree or mesh structure can effectively distribute the logical load of CMN, improving the scalability and overall performance of the system.

[0049] Optionally, the device may further include caches corresponding to each of the processor cores and target interfaces; the target interfaces satisfy the protocol requirements corresponding to the preset communication protocol.

[0050] The aforementioned cache can be a multi-level cache, for example, it can include a first-level cache (L1) and a second-level cache (L2).

[0051] Optionally, the on-chip network is a CMN network; the preset communication protocol is the CXL protocol.

[0052] For example, to verify a SoC design containing 32 processor cores, a processor verification system may include: CMN Core Node: One or more high-end FPGA boards (depending on the CMN scale) are used as CMN core nodes. This FPGA board implements all the CMN logic, cache coherency protocol engine, CXL Host interface, and routing logic required for 32 cores.

[0053] CPU core nodes: 32 independent, relatively small-scale FPGA boards are used as CPU core nodes. Each FPGA board implements a processor core, its private L1 / L2 cache, and a device interface logic conforming to the CXL specification.

[0054] CXL Optical Interconnect Nodes: The CMN core node FPGA is interconnected at high speed with the optical module interfaces on the 32 CPU core node FPGAs via optical fiber through multiple optical modules (such as QSFP-DD or OSFP optical modules supporting the PCIe / CXL protocol). Each CPU core FPGA acts as a CXL device, sending read / write requests and cache consistency messages to the CMN core node (CXL Host) via the optical fiber link. The CMN core node then responds as a global arbitrator, thus realizing a complete CMN network.

[0055] By employing the above method, the ultra-large-scale CMN logic is separated from the CPU core FPGA and centralized onto a dedicated CMN core node FPGA, significantly reducing the logic complexity of each CPU core FPGA. This simplifies and controls the routing and partitioning of a single CPU core FPGA, while the CMN core node FPGA, focused on CMN logic, can adopt more optimized design and routing strategies, avoiding the dilemma of cramming ultra-large-scale logic into a single FPGA and solving routing and partitioning challenges. Simultaneously, because the logic is divided across multiple FPGAs, each FPGA has a smaller logic scale, allowing operation at higher clock frequencies while maintaining stability. Furthermore, high-speed, low-latency CXL optical interconnects replace the traditional low-speed I / O between FPGAs, ensuring bandwidth and low latency in inter-core communication, thus significantly improving the verification speed and efficiency of the entire system. Further, it simplifies the debugging process: when problems arise, debugging can be more targeted. If the problem lies in the CMN conformance protocol, only the CMN core node FPGA needs to be debugged; if the problem lies in a specific core, only the corresponding CPU core FPGA needs to be debugged. This modular design greatly reduces the complexity of debugging.

[0056] Figure 3 This is a flowchart illustrating the steps of a processor verification method according to an embodiment of the present invention. This method can be applied to the processing end of the processor verification system described in the foregoing embodiments. Figure 3 As shown, the method may include: Step 101: Receive a transaction data packet sent by any of the processor cores in the device; the transaction data packet is generated based on memory operation instructions.

[0057] Step 102: Determine the target processor core corresponding to the memory operation instruction based on the global consistency catalog; Step 103: Generate a spying request and send the spying request to the target processor core.

[0058] Step 104: Upon receiving a spy response from the target processor core based on the spy request, execute the memory operation instructions based on the spy response to obtain the execution result, and update the global consistency directory.

[0059] Step 105: Generate a response data packet based on the execution result and send the response data packet to the processor core.

[0060] Specifically, in this embodiment of the invention, the CMN verification of a massively multi-core processor (e.g., 32 cores) can be decomposed into the following core steps: Step 1: System Initialization and Physical Link Establishment FPGA Configuration Loading: The pre-synthesized bitstream files are loaded into the CMN core node FPGA (CXL Host) and the 32 CPU core node FPGAs (CXL Devices). The CMN core node starts the global consistency directory and arbitration logic, while the CPU core nodes start the processor soft / hard cores, L1 / L2 cache controllers, and CXL device interface logic.

[0061] CXL Physical Layer Handshake: The CMN core node FPGA initiates CXL physical layer (PHY) training with all 32 CPU core node FPGAs via the optical module interface. This process uses high-speed signals transmitted through optical fiber to negotiate data rates, clock synchronization, and signal equalization, ensuring the stability of all 32 optical interconnect links.

[0062] CXL Protocol Layer Initialization: The CMN core node (CXL Host) executes the initialization sequence, discovering and enumerating 32 CPU core nodes (CXL Devices) through the CXL.io channel.

[0063] Step 2: Establish a cache consistency domain: CXL.cache activation: The CMN core node sends a command to each CPU core node to activate the CXL.cache protocol.

[0064] Building a Consistency Directory: The CMN core node initializes its internal global consistency directory, registering the L1 / L2 caches and their IDs of all CPU core nodes into the directory, formally establishing a cache consistency domain spanning all 33 FPGA boards.

[0065] Memory space mapping: The CMN core node acts as the host, mapping the simulated system main memory space to the address space visible to all CPU core nodes, thus completing the topology and address configuration of the verification platform.

[0066] Step 3: Verify the loading and execution of the test code: Loading Verification Programs: Test programs used to verify CMN functionality (e.g., shared memory synchronization tests, locking mechanism tests, data consistency stress tests, etc.) are loaded into system memory via the I / O interface or debug port on the CMN core node.

[0067] Core Startup: The CMN core node sends a start signal to all 32 CPU cores, and the processor cores begin executing the test program loaded into memory.

[0068] Step 4: High-concurrency consistent transaction processing (verifying the core process): Core Initiation Request: A CPU core executes a memory operation instruction (e.g., Load or Store). If its private L1 / L2 cache misses or a write operation is required, the CPU core node's CXL Device interface will generate a transaction packet conforming to the CXL.cache protocol (e.g., a read request or write-back request).

[0069] CXL Optical Interconnect Transmission: This data packet is transmitted to the CMN core node FPGA with low latency via high-speed optical modules and optical fibers.

[0070] CMN Core Node Arbitration Response (Global Arbitrator): The consistency engine of the CMN core node receives the request and queries its global consistency catalog.

[0071] Based on the directory status, the CMN core node decides whether it needs to snoop on other CPU core nodes.

[0072] If snooping is required, the CMN core node immediately generates a snooping request (such as Invalidate) and efficiently sends it to the target CPU core node via the CXL optical interconnect link.

[0073] The CMN core node waits for all snoop responses, then performs the final memory operation (read and write from main memory) and updates the global directory.

[0074] Sending the final response: The CMN core node generates the final response data packet (containing data or acknowledgment information) and returns it to the CPU core node that initiated the request via the CXL optical interconnect link.

[0075] Core node reception and update: The CPU core node that initiated the request receives the response, updates its L1 / L2 cache state, and allows the processor to continue execution.

[0076] Step 5: Real-time monitoring and debugging: Data Acquisition: During the verification process, the FPGA's internal logic analyzer (such as ILA) is used to capture key signals of the CMN core node in real time (such as consistency directory status, routing path, arbitration queue status), with a focus on monitoring the correctness of the CMN protocol.

[0077] Isolation debugging: If the test fails, based on the failure report: If it is a cache consistency error, focus on checking the global consistency directory and arbitration logic of the CMN core node.

[0078] If a core malfunctions, the corresponding CPU core node is debugged separately, and the signals from its L1 / L2 cache controller and CXL Device interface are used for isolation and analysis.

[0079] Specifically, the CMN core node is essentially a complex finite state machine (FSM) and routing network. It mainly contains the following key modules: Global Coherency Directory: This is the "brain" of the CMN core nodes. It is a large in-memory structure used to store the global state of all cache lines in the system. For each shared cache line, the directory records the following information: State: The current state of the cache line in the entire system (e.g., exclusive, shared, invalid, similar to the MESI protocol).

[0080] Owner List: If the cache line is shared by one or more CPU cores, this list records the core IDs of all cores that own a copy of the cache line.

[0081] Snoop Filter: This is a fast lookup table used to filter out unnecessary snoop requests. When a CPU core sends a read request, the snoop filter can quickly determine whether the cache line might be cached by other cores, thus avoiding sending snoop requests to all cores and reducing network traffic.

[0082] The Coherence Engine is the logical unit that handles all caching protocol transactions. It receives requests from the CPU cores, queries the global consistency catalog, and takes appropriate action based on the query results.

[0083] Request / Response Queues: These are used to cache all requests from the CPU core and all responses that are about to be sent to the CPU core, to ensure the order and reliability of the data flow.

[0084] When a CMN core node receives a request from the CPU core FPGA, it responds by following these steps: Receiving and Decoding Requests: The CXL interface of the CMN core node first receives the CXL protocol data packet. The data packet is decoded to extract the original request information, such as the request type (read, write, atomic operation, etc.), memory address, and the CPU core ID that initiated the request.

[0085] Querying the global consistency directory: The consistency engine queries the global consistency directory based on the memory address in the request. This query determines the subsequent operation path: Path 1: The requested data is not in any core's cache. The CMN core node issues a read request to its simulated main memory or L3 cache. After the main memory returns the data, the CMN core node sends the data to the CPU core that initiated the request and updates the global consistency catalog, marking the cache line as exclusive to that CPU core.

[0086] Path 2: The requested data is exclusively held by another core. The CMN core node sends a snoop request to the CPU core that exclusively holds the cache line, demanding that it relinquish ownership of the cache line. The snooped core responds and sends the data to the CMN core node. Upon receiving the data, the CMN core node forwards it to the requesting CPU core, updates the directory, changes the cache line's status from "exclusive" to "shared," and adds both cores to the owner list.

[0087] Path 3: The requested data is shared across multiple cores. The CMN core node reads the data directly from its simulated main memory or L3 cache. It sends the data to the CPU core that initiated the request and updates the directory, adding that CPU core to the owner list. If the request is a write operation, the CMN core node sends an "Invalidate" prying request to all cores sharing the cache line, requiring them to discard their local cache copies to ensure data consistency.

[0088] Sending a response: After completing the query and snooping process, the consistency engine generates a response packet using the CXL protocol. This packet contains the requested data or status information and is sent back to the CPU core FPGA that initiated the request via the CXL interface of the CMN core node.

[0089] It should be noted that in existing large-scale multi-core processor designs, a coherent mesh network (CMN) is typically used to achieve high-speed communication and data consistency between cores. As the number of processor cores (such as 16 cores and above) increases dramatically, the size and complexity of the CMN also increase exponentially.

[0090] In physical verification of such ultra-large-scale multi-core processor chips (SoCs), current technologies integrate all cores and CMN logic onto one or more ultra-large FPGAs. However, due to the complexity of ultra-large-scale CMN logic, mapping it entirely onto a single or a few FPGAs leads to highly complex routing and partitioning: the logic and routing resources required by ultra-large-scale CMN logic exceed the capabilities of a single FPGA, making effective logic partitioning and routing difficult, or even impossible. This also results in low verification efficiency: even if partitioning and routing are successful, the clock frequency is severely limited due to the complex internal logic connections of the FPGA, causing the entire system to run very slowly and significantly extending the verification cycle. Furthermore, the complexity of the CMN makes it difficult to locate and isolate problems during physical board-level debugging. Once a problem occurs, the entire FPGA needs to be resynthesized and rerouted, which is extremely time-consuming and makes debugging difficult.

[0091] In one related technology, multiple FPGAs are hard-wired using SerDes (high-speed serializer / deserializer): This approach directly interconnects the SerDes pins between FPGAs, achieving high bandwidth. However, this approach has limitations: extremely high routing complexity. As the number of cores increases, a large number of pins and board-level traces need to be handled, and the routing difficulty increases exponentially, making it susceptible to signal integrity issues. Furthermore, it lacks a native coherence protocol: SerDes is only a physical layer interface, requiring developers to implement complex cache coherence protocols at the logic layer, significantly increasing design and verification difficulty. Additionally, scalability is poor: adding new cores requires redesigning the board, unlike the CXL solution which allows for simple plug-and-play expansion.

[0092] Another related technology involves interconnecting FPGAs via Ethernet or InfiniBand. This approach uses standard network protocols for interconnection and can utilize existing network equipment. However, this approach has limitations: the Ethernet or InfiniBand protocol stack has significant overhead, typically introducing higher communication latency, which negatively impacts latency-sensitive cache coherency protocols. Furthermore, these protocols often do not natively support processor-level cache coherency, requiring simulation through software or custom logic, adding further complexity and overhead. Additionally, the need to incorporate network-related mechanisms and perform various protocol-related operations during communication is time-consuming, resulting in complex communication logic that may prevent the circuit from operating at higher frequencies, reducing verification efficiency.

[0093] In this embodiment of the invention, an architecture that physically and logically decouples the CMN logic from the CPU core logic is adopted. The ultra-large-scale CMN network is concentrated on one or a few FPGAs as core nodes, while each CPU core and its private cache are distributed across their respective independent FPGAs. The CXL protocol is used as the core interconnect bridge: Instead of using general high-speed interconnects, the CXL protocol, which natively supports cache coherency (CXL.cache), is explicitly specified to connect the CMN core nodes and the CPU core nodes, thereby ensuring the accuracy of verification. Optical interconnects are implemented using the CXL protocol: The CXL protocol is combined with high-speed optical modules to achieve long-distance, high-bandwidth, low-latency inter-board communication, solving the wiring and signal integrity problems of traditional onboard electrical traces in ultra-large-scale systems. A modular and scalable verification platform is implemented based on this architecture, allowing for flexible verification of CMN designs of different scales by increasing or decreasing the number of connected CPU core FPGA boards.

[0094] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0095] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0096] Regarding the processor verification device in the above embodiments, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0097] This invention also provides an electronic device, including: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the processor verification method described above.

[0098] Reference Figure 4 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to execute the processor verification method of the aforementioned embodiment.

[0099] It should be noted that the electronic devices in the embodiments of this application include mobile electronic devices and non-mobile electronic devices.

[0100] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0101] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0102] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disk Read Only), magnetic tape, floppy disk and optical data storage devices, etc.

[0103] This invention also provides a non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform... Figure 3 The processor verification method shown.

[0104] This invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform... Figure 3 The processor verification method shown.

[0105] This application also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the processor verification method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0106] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0107] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0108] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented wholly or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0109] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0110] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0112] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0113] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0114] It should be noted that the various data-related processes in the embodiments of this application are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with the authorization granted by the owner of the corresponding device.

[0115] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0116] The processor verification system, method, electronic device, and readable storage medium provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A processor verification system, characterized by, The system comprises a device end and a processing end; The device end comprises at least two processor cores of a processor to be verified; The processing end comprises a network on chip, which is used for data interaction between the processor cores in the device end; The device end and the processing end are connected through an optical module, and the optical module adopts a preset communication protocol.

2. The system of claim 1, wherein, The device end comprises at least two core groups, and one core group comprises at least two processor cores; The network on chip comprises a plurality of processing nodes, and one processing node is used for data interaction between the processor cores in at least one core group.

3. The system of claim 2, wherein, The processing nodes comprise at least first-type nodes and second-type nodes, and the number of the first-type nodes is consistent with the number of the core groups; One first-type node is used for data interaction between the processor cores in one core group; One second-type node is used for data interaction between the core groups corresponding to at least one first-type node.

4. The system of claim 1, wherein, The device end further comprises a cache corresponding to each processor core and a target interface, and the target interface satisfies the protocol requirements corresponding to the preset communication protocol.

5. The system of claim 2, wherein, Each core group in the device end and the processing end are respectively deployed on at least one programmable logic device.

6. The system according to any one of claims 1-5, characterized in that, The network on chip is a CMN network, and the preset communication protocol is a CXL protocol.

7. A processor verification method characterized by, The method is applied to a processing end in a processor verification system, the processor verification system is the processor verification system in any one of claims 1-6, and the method comprises: Receiving a transaction data packet sent by any processor core in a device end, wherein the transaction data packet is generated based on a memory operation instruction; Determining a target processor core corresponding to the memory operation instruction based on a global consistency directory; Generating a snoop request and sending the snoop request to the target processor core; In a case where a snoop response based on the snoop request is received from the target processor core, executing the memory operation instruction based on the snoop response to obtain an execution result, and updating the global consistency directory; Generating a response data packet based on the execution result and sending the response data packet to the processor core.

8. An electronic device, comprising: The computer program is executed by the processor to implement the method in claim 7. The computer program is executed by the computer to implement the method in claim 7. The computer program is executed by the computer to implement the method in claim 7.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, ​ 10. A computer program, characterized in that, ​

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