Quantum state amplitude preparation method and related device

Abstract

The invention discloses an amplitude preparation method of a quantum state and a related device, and belongs to the technical field of quantum computing, the method comprises the following steps: determining each partial component of a target quantum state to be prepared, each partial component comprising a ground state of the target quantum state and a probability amplitude of the ground state; a plurality of target matrixes are constructed based on the probability amplitudes of the partial components, singular value decomposition is carried out on the target matrixes to obtain unitary matrixes, and quantum logic gates corresponding to the unitary matrixes obtained through decomposition act together to evolve a target quantum state into 0gt; state; constructing inverse mapping of quantum logic gates corresponding to the unitary matrixes, and acting on the initial state 0gt; an amplitude preparation quantum circuit is obtained on the quantum bit of the state, and the amplitude preparation quantum circuit is used for generating the target quantum state. According to the scheme, the amplitude preparation quantum circuit is constructed based on the idea of deentanglement, and the amplitude preparation of the quantum state can be more efficiently carried out.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum computing, and particularly relates to a quantum state amplitude preparation method and a related device. BACKGROUND

[0002] A quantum computer is a kind of physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. The quantum computer has the ability to process mathematical problems more efficiently than ordinary computers, for example, it can accelerate the time for cracking RSA keys from hundreds of years to a few hours, so it has become a key technology under research.

[0003] In quantum computing, quantum state encoding is crucial, which is a key step to convert classical information into quantum states, so that the quantum computer can process and operate these information, thereby exerting the performance advantage of quantum computing. Common quantum state encoding methods include ground state encoding, amplitude encoding, angle encoding and MPS (Matrix Product State) encoding. Among them, MPS encoding is an effective method for representing quantum states, which can effectively prepare and represent quantum states by decomposing quantum states in the form of known wave functions into a series of local tensor products. MPS encoding can effectively prepare and represent quantum states, especially those with local entanglement properties.

[0004] Therefore, if a more general quantum state amplitude preparation can be realized based on the encoding method of matrix product state, it undoubtedly has great research prospects and practical value. SUMMARY

[0005] The purpose of the application is to provide a quantum state amplitude preparation method and related device, which aims to construct an amplitude preparation quantum circuit based on the idea of disentanglement, so as to more efficiently prepare the amplitude of the quantum state.

[0006] One embodiment of the application provides a quantum state amplitude preparation method, which comprises:

[0007] determining each partial component of a target quantum state to be prepared; wherein each partial component comprises a ground state of the target quantum state and a probability amplitude of the ground state;

[0008] constructing a plurality of target matrices based on the probability amplitudes of the partial components, and performing singular value decomposition on the target matrices to obtain unitary matrices; wherein the quantum logic gates corresponding to the plurality of unitary matrices obtained by decomposition jointly act to evolve the target quantum state into a |0> state;

[0009] An inverse mapping of the quantum logic gates corresponding to the plurality of unitary matrices is constructed and applied to a quantum bit in a |0> state to obtain an amplitude preparation quantum circuit, the amplitude preparation quantum circuit being used to generate the target quantum state.

[0010] Optionally, the amplitude preparation quantum circuit comprises a plurality of encoding layers connected in series; each of the encoding layers is sequentially executed based on an action timing; each of the encoding layers comprises a plurality of target quantum logic gates executed in parallel, each of the target quantum logic gates being determined based on a conjugate transpose matrix of one of the unitary matrices.

[0011] Optionally, the target quantum logic gates in each of the encoding layers are applied to adjacent pairs of quantum bits; the amplitude preparation quantum circuit comprises at least a first encoding layer and a second encoding layer; the target quantum logic gates in the first encoding layer and the target quantum logic gates in the second encoding layer are applied to different pairs of quantum bits; wherein the different pairs of quantum bits comprise all adjacent pairs of quantum bits in the amplitude preparation quantum circuit.

[0012] Optionally, the plurality of target matrices are constructed based on the probability amplitudes of the partial components, comprising:

[0013] The number n of quantum bits of the amplitude preparation quantum circuit is determined based on the number N of basis states of the target quantum state; wherein the number n of quantum bits satisfies 2 b-1 <N≤2 n ;

[0014] For each of the encoding layers, the probability amplitudes of the plurality of partial components are rearranged into 2 2 ×2 n-2 dimensional matrices based on the sequence numbers of the target quantum bits on which the target quantum logic gates are applied, to obtain a plurality of target matrices.

[0015] Optionally, the probability amplitudes of the plurality of partial components are rearranged into 2 2 ×2 n-2 dimensional matrices based on the sequence numbers of the target quantum bits on which the target quantum logic gates are applied, comprising:

[0016] The probability amplitudes of a plurality of basis states corresponding to the sequence numbers of the target quantum bits being |00>, |01>, |10>, and |11> are sequentially taken as the 1st, 2nd, 3rd, and 4th rows of a matrix, to rearrange the 2 2 ×2 n-2 dimensional matrix; wherein the 2 n-2 probability amplitudes in each row are arranged based on the binary representation order of the corresponding basis state.

[0017] Optionally, the singular value decomposition of the target matrix comprises:

[0018] For each target matrix, singular value decomposition is performed on the target matrix to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and the left singular vector matrix is taken as the unitary matrix.

[0019] Optionally, the singular value decomposition of the target matrix further comprises:

[0020] Performing simulation evolution on the target quantum state based on quantum logic gates corresponding to the plurality of unitary matrices by using a quantum virtual machine;

[0021] Taking the final state obtained by simulation evolution as the target quantum state to be prepared, and returning to perform the step of determining each partial component of the target quantum state to be prepared until the final state obtained by simulation evolution is a |0> state, or iteration reaches a preset number of times.

[0022] Another embodiment of the present application provides an amplitude preparation device for a quantum state, the device comprising:

[0023] An acquisition module is configured to determine each partial component of a target quantum state to be prepared; wherein each partial component comprises a ground state of the target quantum state and a probability amplitude of the ground state;

[0024] A decomposition module is configured to construct a plurality of target matrices based on the probability amplitudes of the partial components, and perform singular value decomposition on the target matrices to obtain unitary matrices; wherein quantum logic gates corresponding to the plurality of unitary matrices jointly act to evolve the target quantum state into a |0> state;

[0025] An encoding module is configured to construct an inverse mapping of quantum logic gates corresponding to the plurality of unitary matrices, and act on a quantum bit with an initial state of |0> to obtain an amplitude preparation quantum circuit, wherein the amplitude preparation quantum circuit is used to generate the target quantum state.

[0026] Another embodiment of the present application provides a storage medium having a computer program stored therein, wherein the computer program is configured to execute the method described in any of the above embodiments when running.

[0027] Another embodiment of the present application provides an electronic device comprising a memory and a processor, wherein the memory has a computer program stored therein, and the processor is configured to execute the computer program to perform the method described in any of the above embodiments.

[0028] Compared with the prior art, the present application provides a quantum state amplitude preparation method and related device, in the present scheme, first, the partial components of the target quantum state to be prepared can be determined, each partial component includes a ground state of the target quantum state and the probability amplitude of the ground state. Further, a plurality of target matrices can be constructed based on the probability amplitudes of the partial components, and singular value decomposition is performed on the target matrices to obtain unitary matrices; the quantum logic gates corresponding to the plurality of unitary matrices obtained by decomposition are jointly acted to evolve the target quantum state into a |0> state. By constructing the inverse mapping of the quantum logic gates corresponding to the plurality of unitary matrices, and acting on the quantum bits with the initial state |0> state, an amplitude preparation quantum circuit can be obtained, and the target quantum state can be generated by using the amplitude preparation quantum circuit. In the present scheme, the wave function of the target quantum state to be prepared does not need to be determined in advance, but the amplitude preparation quantum circuit is constructed based on the idea of disentanglement, specifically, the inverse mapping of the quantum logic gates corresponding to the plurality of unitary matrices calculated can more efficiently perform amplitude preparation of quantum states. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A network block diagram of a quantum state amplitude preparation system provided for an embodiment of the present application;

[0030] Figure 2 A flowchart of a quantum state amplitude preparation method provided for an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a disentanglement quantum circuit provided for an embodiment of the present application;

[0032] Figure 4 A schematic diagram of a plurality of quantum logic gates corresponding to unitary matrices provided for an embodiment of the present application;

[0033] Figure 5 A schematic diagram of an inverse mapping quantum circuit provided for an embodiment of the present application;

[0034] Figure 6 A specific flowchart of singular value decomposition provided for an embodiment of the present application;

[0035] Figure 7 A schematic diagram of another plurality of quantum logic gates corresponding to unitary matrices provided for an embodiment of the present application;

[0036] Figure 8 A topological structure schematic diagram of a real quantum chip provided for an embodiment of the present application;

[0037] Figure 9 A structure diagram of a quantum state amplitude preparation device provided for an embodiment of the present application;

[0038] Figure 10A structural schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] The embodiments described below with reference to the drawings are exemplary and are used only to explain the present application and cannot be interpreted as a limitation of the present application.

[0040] Figure 1 is a network block diagram of a quantum state amplitude preparation system provided by an embodiment of the present application. The quantum state amplitude preparation system can include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and can also include additional storage, classical processors, quantum processors and other devices not shown.

[0041] The network 110 is a medium for providing a communication link between various devices and computers connected together in the quantum state amplitude preparation system, including but not limited to the Internet, an intranet, a local area network, a mobile communication network and combinations thereof, and the connection mode can adopt a wired, wireless communication link or an optical fiber cable, etc.

[0042] The server 120, the wireless device 130 and the client 140 are conventional data processing systems, which can contain data and have application programs or software tools for performing conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smartphone, a tablet, a notebook computer, a smart wearable device, etc. The storage unit 150 can include a database 151, which can be configured to store quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc. data.

[0043] The classical computing unit 160 (quantum computing unit 170) can include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data), and the classical data (quantum data) can be a boot file, an operating system image, and an application 163 (application 173), which can be used to implement a quantum algorithm compiled according to the quantum state amplitude preparation method provided by an embodiment of the present application.

[0044] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0045] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0046] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0047] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0048] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0049] Based on these differences, the design of classical logic function acting on CMOS tube and the design of quantum logic function acting on quantum bit are significantly and essentially different; the design of classical logic function acting on CMOS tube does not need to consider the individuality of CMOS tube, such as the individual identification of the CMOS tube, the position of the CMOS tube in the silicon chip, the available time length of each CMOS tube, so the classical algorithm composed of classical logic function only expresses the operation relationship of the algorithm, and does not express the dependence of the algorithm on the individuality of the CMOS tube.

[0050] And the quantum logic function acting on quantum bit needs to consider the individuality of quantum bit, such as the individual identification of quantum bit, the position of quantum bit in quantum chip, the relationship with surrounding quantum bits, and the available time length of each quantum bit. Therefore, the quantum algorithm composed of quantum logic function not only expresses the operation relationship of the algorithm, but also expresses the dependence of the algorithm on the individuality of the quantum bit.

[0051] The quantum chip can include quantum bits and channels for regulating quantum bits, and quantum logic gates are implemented through analog signals. Different combinations of analog signals are applied to quantum bits through channels for regulating quantum bits, thereby realizing quantum circuits with different functions and completing data processing. Therefore, the design of quantum logic function acting on quantum bit (including the design of whether to use quantum bit and the design of the use efficiency of each quantum bit) is the key to improving the operation performance of quantum computer, and special design is needed. This is also the uniqueness of quantum algorithm based on quantum logic function, which is essentially and significantly different from classical algorithm based on classical logic function. The above design for quantum bit is a technical problem that ordinary computing devices do not need to consider and face.

[0052] In quantum computing, quantum state encoding is crucial because it is the key step of converting classical information into quantum states, enabling quantum computers to process and manipulate this information. Without quantum state encoding, classical data cannot be understood and processed by quantum computers. And quantum state encoding allows quantum computers to use quantum superposition states for parallel processing, such as encoding different possibilities of data as superposition states, allowing multiple possibilities to be operated simultaneously, thereby accelerating the computing process. Classical data also needs to be encoded into quantum states to utilize this parallel processing capability.

[0053] Quantum state encoding enables quantum computing to fully exploit its potential to handle complex problems and address challenges that traditional computing struggles with by converting classical information into quantum states. Current quantum state encoding can use MPS (Matrix Product State) encoding when encoding multi-body quantum states with local entanglement properties. MPS encoding is an effective method for representing quantum states by decomposing quantum states in known wave function form into a series of local tensor products, which can effectively prepare and represent quantum states. Based on this, in order to realize more general quantum state amplitude preparation based on similar MPS encoding, the present application proposes a quantum state encoding method for polynomial functions and related devices.

[0054] Referring to Figure 2 , Figure 2 A quantum state amplitude preparation method provided by an embodiment of the present application includes the following steps:

[0055] Step 201, determining each partial component of a target quantum state to be prepared;

[0056] Each partial component includes a ground state of the target quantum state and a probability amplitude of the ground state.

[0057] In the field of quantum computing, amplitude encoding is a method of encoding classical data into quantum state amplitudes. In amplitude encoding, a given n quantum bits can represent a number of quantum states (i.e., the number of states that can be amplitude encoded) of 2 n For n quantum bits, all possible quantum states they can represent are a 2 n -dimensional complex vector space. Specifically, the number of all ground states that n quantum bits can represent is 2 n , which can be written as |0>, |1>, |2>, …, |2 n -1> or binary numbers, such as the ground state of 6 quantum bits represented as |000000>, |000001>, …, |111111>, etc., which is not specifically limited here.

[0058] Currently, the amplitude preparation method based on the MPS encoding method implemented by pyqpanda is based on a disentangler, which specifically disentangles quantum bits two by two in order from high to low. The MPS method can include the following steps:

[0059] First, write the wave function |ψ> in the form of a matrix product state, that is,

[0060]

[0061] Where σ1…σ LThe value of the dimension corresponding to the qubit is {0, 1} n .

[0062] The form of the above matrix product state is truncated, and then mapped to a four-order unitary matrix, so as to realize the construction of the disentanglement device and the disentanglement operation. In an embodiment, the truncation method can adopt a singular value decomposition method, and specifically, the low-rank expression characteristic of the matrix product state can be used to reduce the key dimension of the generated tensor by truncating the singular value matrix S obtained by decomposition.

[0063] The above truncation operation is iterated in the same way, and the fidelity of the action of the four-order unitary matrix is calculated based on the following formula:

[0064]

[0065] The iteration disentanglement is judged by the fidelity to determine whether the preset accuracy is reached, and finally the disentanglement quantum circuit of the wave function |ψ> can be obtained. Taking the disentanglement of 6 qubits as an example, the corresponding disentanglement quantum circuit can be as shown in Figure 3 , wherein each quantum logic gate [U1, U2, …, U5] is obtained by converting a four-order unitary matrix, and the conversion method can be Kraus-Cirac-Kitanine (KAK1) decomposition or Cosine-Sine (CS) decomposition, which is not limited here.

[0066] Correspondingly, the overall idea of the embodiment of the application is also to assume that the initial state of a quantum circuit is the target quantum state to be prepared Then, by disentangling and approximately truncating the target quantum state |ψ>, a quantum circuit that evolves the target quantum state |ψ> to the |0> state can be obtained. The above steps are classical processing processes and can be realized using a quantum simulator. Further, the inverse mapping of the above disentanglement quantum circuit can be constructed and applied to a quantum bit with an initial state of |0>, so as to realize the approximate preparation of the target quantum state |ψ> on a real quantum chip.

[0067] Then, first, the partial components of the target quantum state to be prepared need to be determined, and the target quantum state to be prepared is For example, it includes 2 n partial components, and each partial component includes a ground state |x> of the target quantum state |ψ> and a probability amplitude α x of the ground state, that is, the number N of ground states of the target quantum state |ψ> satisfies N = 2 n , wherein the square sum of the amplitude of each ground state is 1, that is,

[0068] At step 202, a plurality of target matrices are constructed based on the probability amplitudes of the partial components, and singular value decomposition is performed on the target matrices to obtain unitary matrices.

[0069] The plurality of unitary matrices obtained by decomposition correspond to quantum logic gates that jointly act to evolve the target quantum state into a |0> state.

[0070] Specifically, based on the idea of disentanglement, the probability amplitudes of the partial components determined in the above steps can be rearranged to construct a plurality of target matrices, which contain the amplitude information of the target quantum state |ψ>. Further, singular value decomposition can be performed on each target matrix to obtain its corresponding unitary matrix. Singular value decomposition (SVD) is a widely used matrix decomposition technique in numerical linear algebra, which reveals many important properties of the original matrix by decomposing it into the product of three matrices.

[0071] When a target matrix A is subjected to singular value decomposition, the left singular vector matrix U, the singular value matrix S, and the right singular vector matrix V can be obtained by multiplication. The left singular vector matrix U is an orthogonal matrix, and its column vectors are the left singular vectors of the target matrix A, representing the direction after the target matrix A acts on the standard orthogonal vectors. In an embodiment, the left singular vector matrix U can be used as the unitary matrix, so that the plurality of unitary matrices corresponding to the quantum logic gates can evolve the target quantum state |ψ> into a |0> state.

[0072] Since the target matrices in the present scheme are obtained by rearranging the probability amplitudes of the ground state of the target quantum state, each target matrix includes partial amplitude information of the target quantum state. Therefore, during the process of disentangling and approximating the target quantum state, it is not necessary to strictly follow the order of quantum bits from high to low to realize disentanglement between two quantum bits one by one, so that multiple quantum logic gates without shared quantum bits can run in parallel. Taking the use of 6 quantum bits for disentanglement as an example, the disentanglement quantum circuit in the present scheme can be as shown in Figure 4

[0073] It can be seen that, in order to achieve the same accuracy of disentanglement operation, compared with the existing MPS method, the depth of the quantum circuit required in the present scheme is reduced; or from another angle, in the case of the same depth of the circuit, the present scheme can achieve higher disentanglement accuracy.

[0074] ​Step 203, constructing the inverse mapping of the quantum logic gate corresponding to the plurality of unitary matrices and acting on the quantum bits with the initial state |0> state, to obtain an amplitude preparation quantum circuit, and the amplitude preparation quantum circuit is used to generate the target quantum state.

[0075] Specifically, taking the disentanglement circuit shown in Figure 4 as an example, the inverse mapping of the plurality of quantum logic gates contained therein can be as shown in Figure 5 , the amplitude preparation quantum circuit includes the same number of target quantum logic gates as the disentanglement circuit, and the execution timing of the plurality of target quantum logic gates executed in parallel in two groups is opposite. In an embodiment, each quantum logic gate is determined based on the conjugate transpose matrix n of the corresponding unitary matrix U . Further, the amplitude preparation quantum circuit is applied to the 6 quantum bits with the initial state |0> state, and the target quantum state

[0076] It can be seen that in the scheme provided by the embodiment of the present application, first, each partial component of the target quantum state to be prepared can be determined, and each partial component includes a ground state of the target quantum state and a probability amplitude of the ground state. Further, a plurality of target matrices can be constructed based on the probability amplitudes of the partial components, and the target matrices are singular value decomposed to obtain unitary matrices; the quantum logic gates corresponding to the plurality of unitary matrices are jointly acted to evolve the target quantum state into the |0> state. By constructing the inverse mapping of the quantum logic gates corresponding to the plurality of unitary matrices and acting on the quantum bits with the initial state |0> state, an amplitude preparation quantum circuit can be obtained, and the target quantum state can be generated by using the amplitude preparation quantum circuit. In the scheme, the wave function of the target quantum state to be prepared does not need to be determined in advance, but the amplitude preparation quantum circuit is constructed based on the idea of disentanglement, specifically, the inverse mapping of the quantum logic gates corresponding to the plurality of unitary matrices calculated, which can more efficiently perform amplitude preparation of the quantum state.

[0077] As an embodiment of the present application, the plurality of target matrices can be constructed based on the probability amplitudes of the partial components, which can include the following steps:

[0078] Step 2021, determining the number n of quantum bits of the amplitude preparation quantum circuit based on the number N of ground states of the target quantum state;

[0079] Wherein, the number n of quantum bits satisfies 2 n-1 <N≤2 n .

[0080] Specifically, for n quantum bits, all possible quantum states they can represent are a 2 n -dimensional complex vector space, that is, the number of all ground states that n quantum bits can represent is 2n The number of ground states of the target quantum state determined based on step 201 can be used to determine the number of quantum bits required for the amplitude preparation quantum circuit.

[0081] With Figure 3 As shown in the disentanglement quantum circuit, in the existing MPS encoding quantum circuit, the plurality of encoding modules for amplitude preparation of the quantum state are distributed in a ladder shape and sequentially act on every two adjacent quantum bits. Since part of the quantum bits in the quantum circuit are not subjected to quantum logic gates for a long time, the phenomenon of circuit decoherence is prone to occur.

[0082] Therefore, in a specific embodiment, the amplitude preparation quantum circuit can include a plurality of encoding layers connected in series; each of the encoding layers is sequentially executed based on the action timing sequence, each of the encoding layers includes a plurality of target quantum logic gates executed in parallel, and each of the target quantum logic gates is determined based on the conjugate transpose matrix of one of the unitary matrices.

[0083] Preferably, the target quantum logic gates in each of the encoding layers can act on adjacent pairs of quantum bits, the amplitude preparation quantum circuit includes at least a first encoding layer and a second encoding layer, the target quantum logic gates in the first encoding layer and the target quantum logic gates in the second encoding layer act on different pairs of quantum bits; and the different pairs of quantum bits include all adjacent pairs of quantum bits in the amplitude preparation quantum circuit.

[0084] Specifically, the target quantum logic gates can act on adjacent pairs of quantum bits, a plurality of target quantum logic gates executed in parallel constitute an encoding layer, and the amplitude preparation quantum circuit includes a plurality of encoding layers connected in series. In this embodiment, the target quantum logic gates in the first encoding layer and the target quantum logic gates in the second encoding layer act on different pairs of quantum bits; for example, the target quantum logic gates in the first encoding layer act on the pairs of quantum bits with serial numbers 2, 3 and 4, 5, respectively, the target quantum logic gates in the second encoding layer act on the pairs of quantum bits with serial numbers 1, 2 and 3, 4 and 5, 6, respectively, and then only two encoding layers are required to approximately achieve the amplitude preparation of the target quantum state.

[0085] With the increase of the number of encoding layers, the preparation accuracy of the amplitude preparation quantum circuit also increases, and accordingly, the classical complexity of the amplitude preparation quantum circuit is higher, which is specifically manifested in that more target quantum logic gates are required. Therefore, in the specific encoding process, a suitable number of encoding layers can be selected based on the requirement of the preparation accuracy, which is not specifically limited here.

[0086] Compared with the existing matrix product state encoding circuit in which a plurality of encoding modules are distributed in a ladder type, in the scheme, the wave function of a target quantum state to be prepared does not need to be determined in advance, the action timing of quantum gates is more free, a plurality of quantum gates can be executed in parallel, so that the situation that no quantum gate acts for a long time is avoided, thereby reducing the decoherence probability of the circuit and improving the fidelity.

[0087] In step 2022, for each encoding layer, the probability amplitudes of the plurality of partial components are rearranged into a 2 2 × 2 n-2 order matrix based on the sequence number of the target quantum bit on which the target quantum logic gate acts, to obtain a plurality of target matrices.

[0088] In a specific embodiment, the rearranging the probability amplitudes of the plurality of partial components into a 2 2 × 2 n-2 order matrix based on the sequence number of the target quantum bit on which the target quantum logic gate acts can include:

[0089] The probability amplitudes of a plurality of ground states corresponding to the sequence numbers of the target quantum bits respectively being |00>, |01>, |10>, and |11> are sequentially taken as the 1st, 2nd, 3rd, and 4th rows of a matrix, to rearrange the 2 2 × 2 n-2 order matrix; wherein the 2 n-2 probability amplitudes in each row are arranged based on the binary representation order of the corresponding ground state.

[0090] Specifically, in order to disentangle the first quantum bit and other quantum bits as much as possible, a unitary matrix U 12 needs to be acted on the first quantum bit and the second quantum bit, and the degree of entanglement between the first bit and other bits can be represented by the entanglement entropy of the SVD diagonal element, that is, the target of acting the unitary matrix U1 is to make the maximum value of the matrix diagonalization element between the first bit system and the remaining bit system tend to 1.

[0091] Suppose that the initial state of n quantum bits is |ψ>, then the quantum state after acting the unitary matrix U 12 becomes Using the one-dimensional expansion formula The above evolution result can be written as a tensor form, which is:

[0092]

[0093] For convenience of expression, the target quantum state |ψ> can be written into four parts, ψ 00 , ψ 01 , ψ 10 , ψ11 where the subscript of each part denotes the state of the first two qubits. This is divided into four vectors of length 2 n-2 , as follows:

[0094]

[0095] SVD decomposition, we have Now let The SVD decomposition result can be written as:

[0096] |U 12 [ψ1, ψ2, ψ3, ψ4] T >> = [ψ'1, ψ'2, ψ'3, ψ'4] T

[0097] or,

[0098] |U' 12 [s1v1, s2v2, s3v3, s4v4] T >>

[0099] where s i is arranged from large to small singular value.

[0100] At this time, the goal is to hope that the diagonal matrix of the diagonal element, so that it is more concentrated, thereby reducing the entanglement entropy. And its corresponding two rows are orthogonal, so its singular value is And choose any other non-unit matrix U' 12 , it is impossible to make the two eigenvalues more concentrated, that is, the SVD entropy is smaller, which means that U' 12 is the four-order unit matrix is the best choice.

[0101] Further, still taking the above-mentioned target quantum state to be prepared as an example, in order to encode it on the amplitude of 6 qubits, first need to be in the order of 1, 2; 3, 4; 5, 6 and the quantum bit order of 2, 3; 4, 5 quantum bit pairs respectively disentangled operation. To determine the unitary matrix acting on the quantum bit pair with order 1, 2, for example, the probability amplitude of multiple parts of components needs to be rearranged, which is rearranged into a 2 2 × 2 6-2 scale, that is, a 4 × 16 target matrix.

[0102] The first row of the target matrix corresponds to 16 probability amplitudes of the |00) state of the 1st and 2nd bit states of the ground state, and the 2nd, 3rd and 4th rows correspond to 16 probability amplitudes of the |01>, |10>, and |11) states of the 1st and 2nd bit states of the ground state, respectively. The 16 probability amplitudes in each row are arranged in the order of the binary representation of the corresponding ground state, so that the following target matrix C1 can be obtained:

[0103] The first row is:

[0104] α 000000 , α 000100 , α 001000 , α 001100 , α 010000 , α 010100 , α 011000 , α 011100 ,

[0105] α 100000 , α 100100 , α 101000 , α 101100 , α 110000 , α 110100 , α 111000 , α 111100

[0106] The second row is:

[0107] α 000001 , α 000101 , α 001001 , α 001101 , α 010001 , α 010101 , α 011001 , α 011101 ,

[0108] α 100001 , α 100101 , α 101001 , α 101101 , α 110001 , α 110101 , α 111001 , α 111101

[0109] The third row is:

[0110] α 000010 , α 000110 , α 001010 , α 001110 , α 010010 , α 010110 , α 011010 , α 011110 ,

[0111] α 100010 , α100110 , a 101010 , a 101110 , a 110010 , a 110110 , a 111010 , a 111110

[0112] The fourth behavior is:

[0113] a 000011 , a 000111 , a 001011 , a 001111 , a 010011 , a 010111 , a 011011 , a 011111 ,

[0114] a 100011 , a 100111 , a 101011 , a 101111 , a 110011 , a 110111 , a 111011 , a 111111

[0115] As an embodiment of the present application, as shown in Figure 6 , the singular value decomposition of the target matrix can include the following steps:

[0116] Step 2023, for each target matrix, singular value decomposition is performed on the target matrix to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and the left singular vector matrix is taken as the unitary matrix.

[0117] Then, the SVD decomposition is performed on the above-mentioned 4x16 scale target matrix C1, and the left singular vector matrix obtained is a 4x4 unitary matrix U1, which is one of the unitary matrices for evolving the target quantum state |ψ> into the |0> state; correspondingly, the conjugate transpose matrix (i.e. the inverse matrix ) is the unitary matrix mapped into the amplitude encoding quantum circuit.

[0118] Then, the same method can be used to rearrange the 3rd and 4th quantum bits as markers, i.e. 16 probability amplitudes corresponding to the 3rd and 4th bit states |00>, |01>, |10> and |11> in the ground state are rearranged into a 4x16 target matrix C2. Then, SVD decomposition is performed to obtain a unitary matrix U2, which is the second unitary matrix mapped into the amplitude encoding quantum circuit.

[0119] Similarly, it can also be determined that the unitary matrix U3 acting on the 5th and 6th quantum bits and the third unitary matrix in the amplitude encoding quantum circuit That is, as shown in Figure 4 The first layer of three quantum logic gates U1, U2, and U3 for the disentanglement operation in the quantum circuit shown in

[0120] Further, the step 202 can further include the following steps:

[0121] Step 2024, using a quantum virtual machine to perform a simulation evolution on the target quantum state based on the quantum logic gates corresponding to the plurality of unitary matrices.

[0122] Step 2025, taking the final state obtained by the simulation evolution as the target quantum state to be prepared, and returning to perform the step 201 of determining the partial components of the target quantum state to be prepared until the final state obtained by the simulation evolution is |0> state, or the iteration reaches a preset number of times.

[0123] Specifically, the quantum virtual machine can be used to perform a simulation evolution on the target quantum state |ψ> based on the first layer of three quantum logic gates U1, U2, and U3, and the final state obtained by the evolution can be taken as the target quantum state to be prepared, and the step of determining the partial components of the target quantum state to be prepared is returned. Then, in the next iteration step, the target becomes to disentangle the final state obtained by the evolution to |0> state, that is, to perform unitary matrix encoding again on the basis of the first layer of three quantum logic gates U1, U2, and U3, and the first layer of quantum logic gates cannot act on the same pair of quantum bits.

[0124] Based on the above scheme, the second layer of two quantum logic gates can be calculated, which are U4 acting on the 2nd and 3rd bits and U5 acting on the 4th and 5th bits. Then, the above steps are repeatedly performed until the final state obtained by the simulation evolution is |0> state, that is, the disentanglement is complete; or when the iteration reaches a preset number of times, it can be considered that the disentanglement operation has reached a preset accuracy. That is, the quantum circuit for disentanglement in the present scheme can be obtained, and its specific structure can be as shown in Figure 7

[0125] Then, the inverse mapping of the quantum logic gates corresponding to the plurality of unitary matrices in the quantum circuit is applied to the 6 quantum bits in the initial state |0> to obtain an amplitude preparation quantum circuit, which can generate the target quantum state |ψ>.

[0126] Based on the above technical scheme, it can be generalized to any quantum chip topology, that is, when performing amplitude preparation of the quantum state |ψ>, first, based on the topology of the real quantum chip, the binary string form of the quantum state corresponding to the positions of the two quantum bits to be connected is divided into 4 categories, such as: ψ​...0...0... ,ψ ...0...1... ,ψ ...1...0... ,ψ ...1...1… This allows us to construct the target matrix and perform deentanglement operations on the corresponding qubits.

[0127] by Figure 8 Taking the topology of a real quantum chip as an example, when it is necessary to prepare the amplitude of the target quantum state on qubits 26, 27, 28, 32, 33 and 34 in the figure, based on the connection relationship of the qubits indicated by the topology, the unentangled quantum circuit can include three layers, and the three qubit gates of each layer act on the following qubit pairs respectively:

[0128] The first layer includes: [[26,32],[27,33],[28,34]]

[0129] The second layer includes: [[26,27],[28,34],[33,32]]

[0130] The third layer includes: [[32,26],[27,28],[34,33]]

[0131] As can be seen, in this embodiment, it is not necessary to predetermine the wavefunction of the target quantum state to be prepared. Instead, an amplitude-based quantum circuit is constructed based on the idea of ​​deentanglement, specifically the inverse mapping of the quantum logic gates corresponding to the calculated multiple unitary matrices. This allows for more efficient amplitude preparation of the quantum state. Furthermore, compared to the existing MPS method, the required depth of the quantum circuit is reduced to achieve the same precision in deentanglement operations. Alternatively, with the same circuit depth as the MPS method, this scheme can achieve higher deentanglement accuracy. Moreover, this scheme can be extended to any quantum chip topology, demonstrating strong practicality.

[0132] See Figure 9 , Figure 9 An amplitude preparation device for a quantum state is provided in an embodiment of the present invention. The device may include:

[0133] The acquisition module 901 is used to determine the various components of the target quantum state to be prepared;

[0134] Each of the aforementioned components includes a ground state of the target quantum state and the probability amplitude of that ground state.

[0135] The decomposition module 902 is used to construct multiple target matrices based on the probability amplitude of the partial components, and to perform singular value decomposition on the target matrices to obtain unitary matrices;

[0136] The plurality of unitary matrices are decomposed to obtain a plurality of quantum logic gates corresponding to the plurality of unitary matrices.

[0137] The encoding module 903 is configured to construct an inverse mapping of the plurality of quantum logic gates corresponding to the plurality of unitary matrices, and act on a quantum bit with an initial state of |0> to obtain an amplitude preparation quantum circuit, where the amplitude preparation quantum circuit is used to generate the target quantum state.

[0138] The specific functions and effects of the amplitude preparation device for the quantum state can be explained in conjunction with other embodiments of the present specification, and will not be repeated here. Each module in the amplitude preparation device for the quantum state can be implemented by software, hardware, or a combination thereof. The modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each module.

[0139] Please refer to Figure 10 The embodiments of the present specification also provide a computer device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the amplitude preparation method for the quantum state in any of the above embodiments when executing the computer program. Please refer to Figure 10 The computer device can be a classical computer. The computer device can also be a quantum computer.

[0140] The embodiments of the present specification also provide a computer-readable storage medium, which stores a computer program, and the computer program makes the computer execute the amplitude preparation method for the quantum state in any of the above embodiments when executed by the computer.

[0141] The embodiments of the present specification also provide a computer program product comprising instructions, which make the computer execute the amplitude preparation method for the quantum state in any of the above embodiments when executed by the computer.

[0142] It can be understood that the specific examples in the present specification are only to help those skilled in the art better understand the embodiments of the present specification, and do not limit the scope of the present application.

[0143] It can be understood that in various embodiments of the present specification, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present specification.

[0144] It can be understood that the various embodiments described in the present specification can be implemented alone or in combination, and the embodiments of the present specification do not limit this.

[0145] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this specification belongs. The terminology used in the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. As used in this specification, the terms "may" and "can" include any one of, or a combination of, the corresponding inexcitables. As used in this specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the context clearly dictates otherwise.

[0146] It can be understood that the processor in the embodiments of the present specification can be an integrated circuit chip with processing capability of signals. In the implementation process, each step of the method embodiments described above can be completed by integrated logic circuits or instructions in the form of software in the processor. The processor described above can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the present specification can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in combination with the embodiments of the present specification can be directly embodied as a hardware coding processor to execute, or a combination of hardware and software modules in the coding processor. The software module can be located in a storage medium in the art such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, register, etc. The storage medium is located in the storage, and the processor reads the information in the storage, and combines the hardware to complete the steps of the above method.

[0147] It can be understood that the memory in the embodiments of the present specification can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) or flash memory. The volatile memory can be random access memory (RAM). It should be noted that the memory of the system and method described herein is intended to include but not limited to these and any other suitable type of memory.

[0148] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present specification.

[0149] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0150] In several embodiments provided in the present specification, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0151] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0152] In addition, each functional unit in each embodiment of the present specification can be integrated into one processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0153] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present specification or the parts of the technical solutions that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present specification. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0154] The above is only a specific embodiment of the present specification, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present specification, which should be covered within the protection scope of the present specification. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for preparing the amplitude of a quantum state, characterized in that, The method includes: Determine the components of the target quantum state to be prepared; wherein each component includes a ground state of the target quantum state and the probability amplitude of the ground state; Multiple target matrices are constructed based on the probability amplitudes of the aforementioned partial components, and singular value decomposition is performed on the target matrices to obtain unitary matrices; wherein, the quantum logic gates corresponding to the multiple unitary matrices obtained by decomposition work together to evolve the target quantum state into the |0> state; The inverse mapping of the quantum logic gates corresponding to the multiple unitary matrices is constructed and applied to the qubits with the initial state of |0> to obtain the amplitude preparation quantum circuit, which is used to generate the target quantum state.

2. The method as described in claim 1, characterized in that, The amplitude preparation quantum circuit includes multiple cascaded coding layers; wherein each coding layer is executed sequentially based on the action timing, each coding layer includes multiple target quantum logic gates executed in parallel, and each target quantum logic gate is determined based on the conjugate transpose of a unitary matrix.

3. The method as described in claim 2, characterized in that, The target quantum logic gate in each coding layer acts on adjacent qubit pairs. The amplitude preparation quantum circuit includes at least a first coding layer and a second coding layer. The target quantum logic gate in the first coding layer and the target quantum logic gate in the second coding layer act on different qubit pairs. The different qubit pairs include all adjacent qubit pairs in the amplitude preparation quantum circuit.

4. The method as described in claim 2 or 3, characterized in that, The construction of multiple target matrices based on the probability amplitudes of the partial components includes: The number of qubits n in the amplitude-based quantum circuit is determined based on the number N of the ground states of the target quantum state; wherein the number of qubits n satisfies 2 n-1 <N≤2 n ; For each of the aforementioned coding layers, based on the index of the target qubit acting on the target quantum logic gate, the probability amplitudes of the plurality of partial components are rearranged into 2. 2 ×2 n-2 From a matrix of scale, multiple target matrices are obtained.

5. The method as described in claim 4, characterized in that, The index of the target qubit based on the target quantum logic gate is used to rearrange the probability amplitudes of the multiple component parts into 2. 2 ×2 n-2 A matrix of scale, including: The probability amplitudes of the ground states of the target qubit, corresponding to the positions |00>, |01>, |10>, and |11>, are sequentially used as the 1st, 2nd, 3rd, and 4th rows of a matrix, and rearranged to obtain the 2 2 ×2 n-2 A matrix of size; where each row contains 2 n-2 The probability amplitudes are arranged according to the binary representation of the corresponding ground state.

6. The method as described in claim 5, characterized in that, The process of performing singular value decomposition on the target matrix to obtain a unitary matrix includes: For each target matrix, singular value decomposition is performed on the target matrix to obtain a multiplied left singular vector matrix, singular value matrix, and right singular vector matrix. The left singular vector matrix is ​​then used as the unitary matrix.

7. The method as described in claim 6, characterized in that, The step of performing singular value decomposition on the target matrix to obtain a unitary matrix further includes: The target quantum state is simulated and evolved using a quantum virtual machine based on the quantum logic gates corresponding to the multiple unitary matrices; The final state obtained from the simulation evolution is taken as the target quantum state to be prepared, and the step of determining each component of the target quantum state to be prepared is returned until the final state obtained from the simulation evolution is the |0> state, or the iteration reaches a preset number of times.

8. A device for preparing the amplitude of a quantum state, characterized in that, The device includes: An acquisition module is used to determine the various components of the target quantum state to be prepared; wherein each component includes a ground state of the target quantum state and the probability amplitude of the ground state; The decomposition module is used to construct multiple target matrices based on the probability amplitude of the partial components, and to perform singular value decomposition on the target matrices to obtain unitary matrices; wherein, the quantum logic gates corresponding to the multiple unitary matrices obtained by decomposition work together to evolve the target quantum state into the |0> state; The encoding module is used to construct the inverse mapping of the quantum logic gates corresponding to the multiple unitary matrices and apply it to the qubits with the initial state of |0> to obtain the amplitude preparation quantum circuit, which is used to generate the target quantum state.

9. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1-7 when it is run.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method described in any one of claims 1-7.

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