Quantum bit, quantum chip and quantum computer

Abstract

The invention discloses a quantum bit, a quantum chip and a quantum computer, and belongs to the technical field of quantum chip manufacturing. The quantum bit is arranged on the substrate and comprises a Josephson junction arranged on the surface of the substrate; the two through holes are adjacent to the Josephson junction, penetrate through the substrate and are used for forming a bit capacitor, and the bit capacitor and the Josephson junction jointly form the quantum bit. Through the above mode, the through hole type bit capacitor provided by the invention occupies a smaller area on the surface of the substrate, so that more quantum bits can be arranged on the limited surface of the substrate.

Description

Technical Field

[0001] This application belongs to the field of quantum chip manufacturing technology, and in particular relates to a quantum bit, a quantum chip, and a quantum computer. Background Technology

[0002] The core of a quantum computer is a superconducting quantum chip, and the core of a superconducting quantum chip is a superconducting qubit. In order to continuously improve the computing power of a quantum computer, more and more qubits need to be highly integrated into the superconducting quantum chip.

[0003] As the integration density of integrated circuits continues to increase, the number of I / O pins in integrated circuits is growing rapidly, and the number of I / O pins in microelectronic packages is also increasing accordingly. This undoubtedly leads to a continuous increase in interconnect density. With the development of technology, a limited number of qubits have been integrated onto the substrate surface, which is approaching the physical limit. It is no longer possible to integrate more qubits on substrates with limited dimensions, which is undoubtedly detrimental to the development of quantum computers. Summary of the Invention

[0004] The purpose of this application is to provide a quantum bit, a quantum chip, and a quantum computer to address the problem in existing technologies where the development of quantum computers has led to a physical limit on the integration of a certain number of quantum bits on the substrate surface of quantum chips, thus preventing the integration of more quantum bits. This phenomenon hinders the development of quantum computing. This invention constructs a novel type of quantum bit by using a through-hole type of bit capacitor in conjunction with a Josephson junction. The through-hole type bit capacitor, compared to the previous planar bit capacitor, reduces the space occupied by the bit capacitor on the substrate surface, shrinks the size of the quantum bit, and allows for a more compact arrangement of the quantum bit and its related electronic components, thereby enabling the expansion of more quantum bits on a limited substrate surface.

[0005] To address the aforementioned technical problems, the present invention provides a quantum bit disposed on a substrate, comprising:

[0006] Josephson junction, disposed on the surface of the substrate; and

[0007] Two vias adjacent to the Josephson junction and penetrating the substrate are used to form bit capacitors, which together with the Josephson junction constitute a quantum bit.

[0008] Preferably, all the through holes are cylinders; or, all the through holes are cuboids with a rectangular cross-section.

[0009] Preferably, the depth-to-diameter ratio of the cylindrical through hole is 5-10.

[0010] Preferably, all the through holes are perpendicular to the surface.

[0011] Preferably, the substrate is a silicon substrate or a sapphire substrate.

[0012] This application also provides a quantum chip, comprising:

[0013] The qubit described in any of the preceding claims; and

[0014] A superconducting metal layer disposed on the surface of the substrate, coplanar with the Josephson junction;

[0015] The superconducting metal layer has a window that exposes a portion of the substrate, and the qubit is disposed within the window.

[0016] Preferably, a readout bus and a readout resonant cavity are also formed in the region where the superconducting metal layer leaves the window;

[0017] One end of the read resonant cavity is coupled to the read bus, and the other end is coupled to the bit capacitor.

[0018] Preferably, one end of the read resonant cavity near the bit capacitor is disconnected from ground, while the other end is connected to ground.

[0019] Preferably, the superconducting metal layer is made of one or more of aluminum, niobium, tantalum, and titanium nitride.

[0020] This application also provides a quantum computer, including: a measurement and control system, a cooling system, and the aforementioned quantum chip.

[0021] Compared with the prior art, this application provides a bit capacitor in the form of a through-hole. It should be noted that the through-hole forming the bit capacitor must penetrate the substrate, that is, penetrate the two opposite surfaces of the substrate. One of the surfaces is provided with a Josephson junction. The bit capacitor in the form of a through-hole and the Josephson junction together form a quantum bit. This can reduce the space occupied by the bit capacitor on the substrate surface, reduce the size of the quantum bit, and make the arrangement of the quantum bit and its related electronic components more compact. Thus, more quantum bits can be expanded on the limited substrate surface. Attached Figure Description

[0022] Figure 1 A schematic diagram of a quantum bit structure provided in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of the Josephson junction and capacitor structure provided in the embodiments of this application;

[0024] Figure 3 A schematic diagram showing a substrate with a Josephson junction and a capacitor structure provided in an embodiment of this application;

[0025] Figure 4This is a schematic diagram of the structure of a quantum chip provided in an embodiment of this application.

[0026] Figure labeling: 1 - substrate, 2 - Josephson junction, 3 - via, 4 - readout resonant cavity. Detailed Implementation

[0027] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0030] Depending on the different physical systems used to construct qubits, qubits can be physically realized in various ways, including superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quantum, and photons.

[0031] Quantum computing using superconducting quantum circuits is currently the most advanced and best-performing method for realizing solid-state quantum computing. Because the energy level structure of superconducting quantum circuits can be controlled by external electromagnetic signals, the circuit design offers high controllability. Furthermore, thanks to existing mature integrated circuit technologies, superconducting quantum circuits possess scalability unmatched by most quantum physics systems.

[0032] In superconducting quantum circuits, qubits (qubits) include Josephson junctions, which are structures formed by separating two thin-film superconducting layers using a non-superconducting material. When the temperature drops to a specific cryogenic temperature (below the critical temperature, in the millikal band), the superconducting layers achieve superconductivity, allowing electron pairs to tunnel from one superconducting layer through a non-superconducting layer to the other. In a qubit, a Josephson junction (which functions as a nonlinear inductive device) is connected in parallel with one or more capacitive devices to form a nonlinear microwave oscillator, giving the qubit a resonant / transition frequency determined by the values ​​of its inductance and capacitance.

[0033] The physical basis of qubit readout is dispersion readout, which utilizes the nonlinear coupling between the qubit and the cavity to carry or transmit the information processed by the qubit as microwave signals within the microwave frequency range. The microwave signals are then captured, processed, and analyzed to obtain the coded quantum information within them. The readout circuit is a circuit coupled to the qubit, used to capture, read, and measure quantum information.

[0034] In one example of a superconducting quantum circuit, such as Figure 1 The structure of a qubit employs a single capacitor to ground, and a superconducting quantum interference device (SQUID) / superconducting quantum interference apparatus with one end grounded and the other end connected to the capacitor. This capacitor typically uses a method such as... Figure 1 The diagram shows a cross-shaped parallel-plate capacitor (Cq). The cross-shaped parallel-plate capacitor is surrounded by a ground plane (GND). Notably, there is a gap between the cross-shaped parallel-plate capacitor and the ground plane. One end of the superconducting quantum interference device (SQU) is connected (coupled) to the cross-shaped capacitor plate, and the other end is connected to the ground plane. Since the first end of the cross-shaped capacitor plate is typically used to connect the SQU, and the second end is used to couple with readout structures such as readout resonant cavities, a certain amount of space needs to be reserved near the first and second ends for wiring. For example, space needs to be reserved near the first end for arranging XY and Z signal lines. The other two ends of the cross-shaped capacitor plate are used for coupling with adjacent qubits.

[0035] Based on this structure, qubits can be integrated and expanded by arranging them in a one-dimensional chain array. Adjacent qubits are coupled and share a readout line. The reading circuit structure mainly includes a readout resonant cavity coupled to the qubit to be read and a readout line coupled to the readout resonant cavity. Each qubit independently corresponds to a resonant cavity and is connected to the readout line. Based on the coupling of their respective readout resonant cavities and the shared readout line, the state information of the qubit is transferred from the qubit to the transmission line.

[0036] However, as the integration density of integrated circuits continues to increase, the number of signal ports (I / O) on integrated circuits is also growing rapidly, and the number of pins in microelectronic packages is also increasing accordingly. This undoubtedly leads to a continuous increase in interconnect density. In response, traditional two-dimensional interconnect packaging technology can no longer solve the problems of interconnect delay and increased power consumption caused by high integration density and signals approaching physical size limits. In addition, for the above reasons, it is difficult to expand the space to accommodate more qubits for detection, which is undoubtedly a huge challenge for the development of quantum computing.

[0037] Among these, qubits require high-quality quality factor shunt capacitors, which are usually achieved by using large coplanar capacitors. In addition, readout resonant cavities used to read the state of qubits are usually composed of coplanar waveguides with a length on the order of millimeters.

[0038] In response to the above problems, the inventors of this application have proposed the following improvement ideas and verified their feasibility through experiments: In order to improve the chip integration, reduce chip power consumption, reduce interconnect delay, and increase data transmission bandwidth, three-dimensional integration technology that develops towards the Z-axis direction on the basis of two-dimensional arrangement is a highly feasible idea. The chip no longer develops only towards the two-dimensional plane of XY axis, but is stacked and developed towards the Z-axis direction, which makes the integration density per unit area of ​​the plane parallel to XY higher, the interconnect length shorter, the transmission speed improved, the power consumption reduced, and the package size smaller.

[0039] In one embodiment of this application, as follows is provided Figure 2 The illustration shows a quantum bit fabricated on a substrate 1, meaning the substrate 1 is processed, including but not limited to processes such as coating and etching on the surface of the substrate 1 to form the quantum bit. Here, the quantum bit includes a Josephson junction 2 and two vias 3 corresponding to the Josephson junction 2. The Josephson junction 2 is fabricated on a surface of the substrate 1 using methods such as oblique evaporation, and its number is at least one, determined according to the actual requirements for the number of quantum bits and the processing capabilities. Furthermore, the vias 3 are used to form a bit capacitor, and their number is specifically corresponding to the Josephson junction 2, specifically one Josephson junction 2 corresponding to two vias 3, with the two vias 3 together forming a bit capacitor. At least one of the vias 3 adjacent to or with a high coupling strength is coupled to the Josephson junction 2. It is worth noting that the vias 3 are generally obtained by etching the substrate 1, requiring a high aspect ratio. This type of bit capacitor with vias 3 can simultaneously achieve the characteristics of small size and large capacitance.

[0040] In this first embodiment of the application, a compact superconducting through-silicon via 3 is used to realize a lumped element capacitor between the quantum bit and the readout resonator. This through-silicon via 3 is a shunt capacitor with a high quality factor and can be used as a capacitor element, with a significantly reduced size compared to the prior art.

[0041] Furthermore, all the vias 3 described above are cylindrical; alternatively, the via 3 can also be a cuboid with a rectangular cross-section. In reality, the shape of the via 3 is not particularly limited. The requirement is that the two associated vias 3 (that together form a bit capacitor) are fabricated into the same shape. However, due to uncontrollable variables in the fabrication process of the vias 3, such as the different hardness of different regions of the substrate 1 material, the different etching parameters or times for each via 3, and the precision issues of the photolithography machine used to etch the vias 3 on the substrate 1, there are often some errors in the shape of the two ultimately manufactured vias 3. These errors do not have a significant negative impact on the qubit itself and are therefore acceptable. Furthermore, one of the two vias 3 is selected for connection with the Josephson junction 2 to achieve the best connection effect. Additionally, the shapes of the two vias 3 only need to satisfy the requirement of jointly forming a bit capacitor; their shapes are not restricted, meaning other shapes that meet the requirements are also acceptable.

[0042] Please refer to Figure 3 Under current technological conditions or ideal circumstances, the via 3 of the capacitor that together with the Josephson junction 2 constitutes a qubit can generally be approximately defined as a cylinder. Here, the aspect ratio of this cylindrical via 3 is 4-20, where the depth is the thickness of the substrate 1 and the diameter is the diameter of the circular cross-section. This high aspect ratio TSV via 3 can possess a large self-capacitance, which is undoubtedly a better embodiment for reducing the occupied area of ​​a qubit capacitor. According to tests conducted by the inventors of this application, this via 3-shaped qubit capacitor occupies only 1 / 20 to 1 / 30 of the area on the substrate 1 plane compared to commonly used planar capacitors.

[0043] Furthermore, in the manufacturing method of the through-hole 3, the substrate 1 is etched to form the through-hole 3. The substrate 1 can be a silicon substrate 1 or a sapphire substrate 1, or other feasible materials can also be used as the substrate 1. The surface of the substrate 1 can be treated by polishing or other methods to form a smooth and flat surface structure, which can make the flatness of the substrate 1 surface higher than that of the substrate 1 surface after etching. The specific manufacturing process shall prevail and is not limited to the above example.

[0044] It is worth noting that all the through holes 3 are perpendicular to the surface of the substrate 1 to achieve the best effect.

[0045] In another embodiment of this application, as follows is provided Figure 4The quantum chip shown includes the aforementioned qubits and a superconducting metal layer disposed coplanarly with the Josephson junction 2 on the surface of a substrate 1; wherein the superconducting metal layer forms a window exposing a portion of the substrate 1, and the qubits are disposed within the window.

[0046] For the above quantum chip, embodiments of this application also provide several methods for manufacturing the through-hole 3:

[0047] Method 1:

[0048] Step 1: Deposit a superconducting metal layer on substrate 1; the superconducting metal layer includes one or more of aluminum, niobium, tantalum, and titanium nitride;

[0049] Step 2: Etch substrate 1 and superconducting metal layer to form two through holes 3 penetrating the opposite surfaces of substrate 1;

[0050] Step 3: Etch the superconducting metal layer to form a window that exposes part of the substrate 1;

[0051] Step 4: Prepare Josephson junction 2 within the window.

[0052] Method 2:

[0053] Step 1: Etch substrate 1 to form two through holes 3 penetrating opposite surfaces;

[0054] Step 2: Deposit a superconducting metal layer on substrate 1 and form a window that exposes part of substrate 1;

[0055] Step 3: Form Josephson knot 2 within the window.

[0056] In practice, methods one and two often present the following problems: After etching vias 3 into substrate 1, photoresist needs to be applied to the surface of substrate 1 before fabricating the Josephson junction 2. However, due to the presence of vias 3, the photoresist flows into the vias 3 and even seeps to the bottom of substrate 1, making it difficult for the back side of substrate 1 to be vacuum-sealed, thus preventing photoresist spin-coating. Furthermore, cleaning the photoresist within the vias 3 after it flows in is extremely difficult, which can damage the performance of the quantum chip.

[0057] In response, the technical personnel of this application propose the following solutions: attach a polyimide film to the bottom of substrate 1, or place a silicon wafer on the bottom of substrate 1, which can prevent the photoresist from seeping to the bottom of the silicon wafer; in addition, for the problem of difficult cleaning of photoresist in via 3, EKC solution can be used, and a megasonic cleaning machine can be used to effectively clean the photoresist that has seeped into the hole (ordinary photoresist cleaning uses ultrasonic cleaning).

[0058] Method 3:

[0059] Step 1: Deposit a superconducting metal layer on substrate 1 and form a window that exposes part of substrate 1;

[0060] Step 2: Form Josephson knot 2 within the window;

[0061] Step 3: Etch substrate 1 and superconducting metal layer to form two through holes 3 penetrating the opposite surfaces of substrate 1.

[0062] For Method 3 above, the following problems often exist in practice: when fabricating the through hole 3 at the end, due to the high requirements for overlay accuracy, it is necessary to control the spacing with devices such as Josephson junction 2 very well. That is, the through hole 3 must be perfectly overlaid between the readout resonant cavity 4 and Josephson junction 2, which is extremely difficult.

[0063] In response, the technical personnel of this application propose the following solution: pre-set the overlay alignment markers and use a high-precision DUV (deep ultraviolet) exposure machine for overlay exposure.

[0064] Furthermore, a read bus and a read resonant cavity 4 are formed in the region of the superconducting metal layer away from the window; one end of the read resonant cavity 4 is coupled to the read bus, and the other end is coupled to the bit capacitor.

[0065] Furthermore, the resonant cavity 4 is in the form of a coplanar waveguide, with one end near the bit capacitor disconnected from ground and the other end connected to ground.

[0066] In addition, various circuit structures with different functions exist around the qubits in quantum chips to control their states. For example, the circuit structure includes a drive control signal line (XY-Control Line, also known as the xy control line or pulse modulation signal line) for XY rotation operations on the qubits. By applying a driving voltage signal to the circuit, the qubit can be excited by a transition; it is associated with the qubit through capacitive coupling. The circuit structure also includes a circuit structure for Z-rotation operations on the qubits, which is accomplished by a control signal line near the superconducting quantum interference device (squid); this is called the flux modulation signal line (Z-Control Line, also known as the Z control signal line or frequency modulation signal line).

[0067] As mentioned earlier, the flux control signal line is positioned near the superconducting quantum interference device (Squid). Its excitation current is inductively coupled to the Squid via a magnetic field. It's important to note that both the flux control signal line and the drive control circuitry can be used to control qubits, but their methods of qubit control differ. For example, the signal (current) transmitted by the flux control signal line generates a magnetic field. This magnetic field is applied to the Squid region and passes through it, altering the current in the Squid, thus achieving a control effect and changing the frequency of the qubit. In contrast, the drive control signal line applies a pulse to the qubit in the form of an electric field, causing a transition in the qubit's energy level.

[0068] Specifically, the material of the superconducting metal layer only needs to exhibit superconducting properties at or below the critical temperature. For example, one or more of niobium, aluminum, tantalum, and titanium nitride can be used. The selection of superconducting materials should be based on actual conditions and is not limited to the above examples.

[0069] In quantum chips (or quantum processors), integrating numerous qubits (such as superconducting qubits) can provide more powerful quantum computing performance. Therefore, with the pursuit of performance and practicality, more qubits are integrated into quantum chips. However, qubits such as superconducting qubits require various control lines, and the number of control lines increases with the number of qubits. On the other hand, the size of the chip substrate is finite. To accommodate more qubits, a reasonable spatial layout is needed, including controlling the area occupied by the qubit structure and planning the layout of the corresponding control lines.

[0070] In another embodiment of this application, a quantum computer is also provided, including: a measurement and control system, a cooling system, and the aforementioned quantum chip. Signal transmission, hierarchical settings, etc., can be referenced from other similar technologies, and will not be elaborated upon here.

[0071] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0072] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A quantum bit disposed on a substrate (1), characterized in that, include: Josephson junction (2) is disposed on the surface of the substrate (1); as well as Two vias (3) adjacent to the Josephson junction (2) and penetrating the substrate (1) are used to form bit capacitors, which together with the Josephson junction (2) constitute a quantum bit.

2. The quantum bit according to claim 1, characterized in that, All the through holes (3) are cylindrical; Alternatively, all the through holes (3) are cuboids with a rectangular cross-section.

3. The quantum bit according to claim 2, characterized in that, The depth-to-diameter ratio of the cylindrical through hole (3) is 5-10.

4. The quantum bit according to claim 1, characterized in that, All of the through holes (3) are perpendicular to the surface.

5. The quantum bit according to claim 1, characterized in that, The substrate (1) is a silicon substrate (1) or a sapphire substrate (1).

6. A quantum chip, characterized in that, include: The quantum bit according to any one of claims 1-5; as well as A superconducting metal layer disposed on the surface of the substrate (1) coplanar with the Josephson junction (2); The superconducting metal layer has a window that exposes a portion of the substrate (1), and the qubit is disposed within the window.

7. The quantum chip according to claim 6, characterized in that, A readout bus and a readout resonant cavity (4) are also formed in the region of the superconducting metal layer away from the window; One end of the reading resonant cavity (4) is coupled to the reading bus, and the other end is coupled to the bit capacitor.

8. The quantum chip according to claim 7, characterized in that, The reading resonant cavity (4) is disconnected from ground at one end near the bit capacitor, and connected to ground at the other end.

9. The quantum chip according to claim 6, characterized in that, The superconducting metal layer is made of one or more of aluminum, niobium, tantalum, and titanium nitride.

10. A quantum computer, characterized in that, include: The measurement and control system, the cooling system, and the quantum chip as described in any one of claims 6-9.

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