Thin film transistor unit and display device including same

Abstract

Embodiments of the present invention are directed to providing a thin film transistor unit and a display device including the same. The thin film transistor unit includes a first terminal; a first thin film transistor including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; a third thin film transistor including a third active layer, a third gate electrode, a third source electrode, and a third drain electrode; a fourth thin film transistor including a fourth active layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode; and a second terminal, in which a same gate voltage is configured to be simultaneously applied to the first to fourth gate electrodes, in which the first terminal is connected to the first and second drain electrodes, the second terminal is connected to the third and fourth source electrodes, and the third drain electrode is connected to the fourth drain electrode only via the first source electrode, and is connected to the fourth drain electrode only via the second source electrode.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0104337, filed on August 6, 2024, which is incorporated by reference herein as if fully set forth in its entirety. TECHNICAL FIELD

[0003] The present application relates to a thin film transistor unit and a display device, and more particularly, to a thin film transistor unit capable of reducing a heat generation temperature and a display device including the same. BACKGROUND

[0004] With the development of information society, the demand for display devices for displaying images has increased in various forms, and recently, various display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diode display devices (OLEDs) are being utilized.

[0005] In general, a display device includes a driving circuit for driving a display panel. The driving circuit includes a gate driving circuit sequentially applying a scan signal to a gate line, and a data driving circuit applying image information to a pixel through a data line in response to the scan signal of the gate driving circuit.

[0006] Recently, research is continuously conducted to reduce a heat generation temperature in a gate driving circuit of a display device.

[0007] In the past, in order to reduce a heat generation temperature in a gate driving circuit, a method of horizontally or vertically increasing a distance between heat sources was used. However, although this method can reduce a heat generation temperature by increasing a distance from a heat source, it causes a problem of increasing a size of a bezel of a display device.

[0008] Therefore, research is continuously conducted to reduce a heat generation temperature in a gate driving circuit without increasing a size of a bezel of a display device. SUMMARY

[0009] One embodiment of the present application is to provide a thin film transistor unit having crossed heat sources.

[0010] Another embodiment of the present application is to provide a thin film transistor unit in which heat sources are crossed to reduce a heat generation temperature.

[0011] Another embodiment of the present application is to provide a display device having a reduced bezel width including a thin film transistor unit having crossed heat sources.

[0012] According to an aspect of the present disclosure, the above and other objects can be achieved by providing a thin film transistor unit including a first terminal; a first thin film transistor including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; a third thin film transistor including a third active layer, a third gate electrode, a fourth thin film transistor including a fourth active layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode; and a second terminal, wherein a same gate voltage is configured to be applied to the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode at the same time, wherein the first terminal is connected to the first drain electrode and the second drain electrode, the second terminal is connected to the third source electrode and the fourth source electrode, and the third drain electrode is connected to the fourth drain electrode only via the first source electrode and only via the second source electrode.

[0013] A voltage input to the first terminal can be higher than a voltage input to the second terminal.

[0014] In a plan view, the first thin film transistor and the fourth thin film transistor can be adjacently disposed along a first direction, and in the plan view, the second thin film transistor and the third thin film transistor can be adjacently disposed along the first direction.

[0015] The first gate electrode can be connected to the second gate electrode only via the third gate electrode, and can be connected to the second gate electrode only via the fourth gate electrode.

[0016] In a plan view, the first thin film transistor and the third thin film transistor can be adjacently disposed along a second direction perpendicular to the first direction, and in the plan view, the second thin film transistor and the fourth thin film transistor can be adjacently disposed along the second direction.

[0017] In a plan view, the first thin film transistor and the second thin film transistor can be adjacently disposed along a diagonal direction between the first direction and the second direction.

[0018] In a plan view, the first active layer, the second active layer, the third active layer, and the fourth active layer can form a square in which the first active layer, the second active layer, the third active layer, and the fourth active layer are located at respective corners of the square, and the first active layer and the second active layer can be located on one diagonal of the square, and the third active layer and the fourth active layer can be located on another diagonal of the square.

[0019] The first active layer, the second active layer, the third active layer, and the fourth active layer can be spaced apart from each other.

[0020] The thin-film transistor unit further includes a third terminal connected to the first source electrode, the second source electrode, the third drain electrode, and the fourth drain electrode.

[0021] The first source electrode, the second source electrode, the third source electrode, the fourth source electrode, the first drain electrode, the second drain electrode, the third drain electrode, the fourth drain electrode, the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode can be disposed on the same layer.

[0022] Another embodiment of the present application can provide a display device including: a display panel in which a plurality of pixels are disposed; and a gate driver circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, wherein the gate driver circuit includes a stage for supplying the scan signals, and the stage includes a thin-film transistor unit according to any embodiment of the present application.

[0023] Another embodiment of the present application can provide a display device including: a display panel in which a plurality of pixels are disposed; and a gate driver circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, wherein the gate driver circuit includes a stage for supplying the scan signals, and a front dummy stage and a back dummy stage dependently connected to the stage, wherein the front dummy stage and the back dummy stage include a feedback transistor, and the feedback transistor includes a thin-film transistor unit according to any embodiment of the present application.

[0024] The front dummy stage and the back dummy stage can be disposed in a corner region of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1a is a circuit diagram of a thin-film transistor unit according to a comparative example of the present application.

[0027] Figure 1b is a circuit diagram of a thin-film transistor unit according to one embodiment of the present application.

[0028] Figure 2a is a plan view of the thin-film transistor unit of Figure 1a

[0029] Figure 2b is a cross-sectional view taken along line I-I' of Figure 2a

[0030] Figure 2c is a cross-sectional view taken along line II-II' of Figure 2a

[0031] Figure 3a ​​​is a plan view of a thin-film transistor unit according to the present application. Figure 1b is a plan view of a thin-film transistor unit according to the present application.

[0032] Figure 3b is a cross-sectional view taken along line III-III' of Figure 3a

[0033] Figure 3c is a cross-sectional view taken along line IV-IV' of Figure 3a

[0034] Figure 4a is a plan view of a thin-film transistor unit according to another embodiment of the present application.

[0035] Figure 4b is a cross-sectional view taken along line V-V' of Figure 4a

[0036] Figure 4c is a cross-sectional view taken along line VI-VI' of Figure 4a

[0037] Figure 5 is a schematic view of a display device according to another embodiment of the present application.

[0038] Figure 6 is a diagram showing an example of a display panel in which a gate driver circuit is implemented as a GIP type in a display device.

[0039] Figure 7 is a diagram showing a schematic configuration of a stage provided in a gate driver circuit of Figure 5

[0040] Figure 8 is a circuit diagram of one embodiment of a stage provided in a gate driver circuit of Figure 5

[0041] Figure 9 is a diagram showing an arrangement of stages within a display panel.

[0042] Figure 10 is a diagram showing a structure for sensing and compensating for degradation of a gate driver circuit. DETAILED DESCRIPTION

[0043] The advantages and features of the present disclosure and implementations thereof will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is defined only by the scope of the claims.

[0044] ​​​​​​The shapes, sizes, ratios, angles, and numbers disclosed in the drawings for describing embodiments of the present disclosure are merely examples and thus the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout the specification. In the following description, detailed descriptions of functions or configurations known in the art are omitted when it is determined that such descriptions would obscure the gist of the present disclosure.

[0045] In the case of using "comprise", "have", and "include" in the present disclosure, another part can be added unless "only" is used. Unless otherwise stated, a singular form can include a plural form.

[0046] In interpreting elements, the element is interpreted to include an error band, although not explicitly described.

[0047] In describing positional relationships, for example, when the positional relationship is described as "on", "above", "below", and "next to", unless "just" or "directly" is used, one or more parts can be disposed between two other parts.

[0048] Spatial relative terms such as "below", "beneath", "lower", "above", and "upper" are used herein for ease of description to describe one element or multiple elements' relationships to another element or multiple elements as illustrated in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device is turned over, the element described as being "below" or "beneath" another element would then be oriented "above" the other element. Thus, the exemplary term "below" or "beneath" can encompass both an orientation of above and below. Likewise, the exemplary term "above" or "on" can encompass both an orientation of above and below. The terms "first", "second", "third", etc. are used herein to describe various elements, but do not mean to indicate that the elements are limited to these three elements.

[0049] In describing temporal relationships, for example, when the temporal order is described as "after", "subsequent", "next", and "before", unless "just" or "directly" is used, discontinuous cases can be included.

[0050] It should be understood that, although the terms “first,” “second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0051] It should be understood that the term “at least one of’ includes all combinations of any one item with each of the other items. For example, “at least one of the first element, the second element, and the third element” can include two or more elements selected from the first, second, and third elements and all combinations of each of the first, second, and third elements.

[0052] The features of various embodiments of the present disclosure can be partially or wholly coupled or combined with each other and can be technically inter-operable and drivable in various ways as can be sufficiently understood by those skilled in the art. Embodiments of the present disclosure can be executed independently of each other or can be executed together in a mutually dependent relationship.

[0053] When adding reference numerals to components of each drawing describing embodiments of the present disclosure, the same components can have the same reference numerals as can be shown on other drawings.

[0054] In embodiments of the present disclosure, for convenience of description, a source electrode and a drain electrode are distinguished, and the source electrode and the drain electrode can be interchangeable. The source electrode can be the drain electrode, and vice versa. In addition, the source electrode in any one embodiment can be the drain electrode in another embodiment, and the drain electrode in any one embodiment can be the source electrode in another embodiment.

[0055] In some embodiments of the present disclosure, for convenience of description, a source electrode region is distinguished from a source electrode, and a drain electrode region is distinguished from a drain electrode, but embodiments of the present disclosure are not limited thereto. The source electrode region can be the source electrode, and the drain electrode region can be the drain electrode. In addition, the source electrode region can be the drain electrode, and the drain electrode region can be the source electrode.

[0056] Figure 1a is a circuit diagram of a thin film transistor unit (10a) according to a comparative example of the present invention.

[0057] Figure 1b is a circuit diagram of a thin film transistor unit (10b) according to an embodiment of the present invention.

[0058] According to one embodiment of the present invention, a thin-film transistor unit (10b) includes a first thin-film transistor (100a), a second thin-film transistor (100b), a third thin-film transistor (100c), and a fourth thin-film transistor (100d).

[0059] Figure 1b A thin-film transistor unit (10b) is shown, wherein a first thin-film transistor (100a), a second thin-film transistor (100b), a third thin-film transistor (100c) and a fourth thin-film transistor (100d) are provided.

[0060] According to one embodiment of the present invention, the first thin-film transistor (100a) includes a first active layer (130a), a first gate electrode (150a), a first source electrode (161a) and a first drain electrode (162a).

[0061] According to one embodiment of the present invention, the second thin-film transistor (100b) includes a second active layer (130b), a second gate electrode (150b), a second source electrode (161b), and a second drain electrode (162b).

[0062] According to one embodiment of the present invention, the third thin-film transistor (100c) includes a third active layer (130c), a third gate electrode (150c), a third source electrode (161c), and a third drain electrode (162c).

[0063] According to one embodiment of the present invention, the fourth thin-film transistor (100d) includes a fourth active layer (130d), a fourth gate electrode (150d), a fourth source electrode (161d), and a fourth drain electrode (162d).

[0064] A thin-film transistor unit (10b) according to one embodiment of the present invention includes a first terminal (115a) and a second terminal (115b).

[0065] At this time, the voltage input to the first terminal (115a) can be higher than the voltage input to the second terminal (115b).

[0066] Figure 2a yes Figure 1a A plan view of the thin-film transistor unit (10a). Figure 2b It is along Figure 2a A cross-sectional view taken from line I-I'. Figure 2c It is along Figure 2a The cross-sectional view taken from line II-II'.

[0067] Reference Figure 2aThe thin film transistor unit (10a) according to the comparative example includes a first terminal (115a) and a second terminal (115b). At this time, the first terminal (115a) is connected to the first drain electrode (162a) of the first thin film transistor (100a) and the second drain electrode (162b) of the second thin film transistor (100b). In addition, the second terminal (115b) is connected to the third source electrode (161c) of the third thin film transistor (100c) and the fourth source electrode (161d) of the fourth thin film transistor (100d).

[0068] According to one embodiment of the present application, when the first terminal (115a) to which a high voltage is input is connected to the drain electrode of the thin film transistor, the thin film transistor can be referred to as a 'Heat Source' according to the present application.

[0069] Reference Figure 2a When the first terminal (115a) to which a high voltage is input is connected to the first drain electrode (162a) of the adjacent first thin film transistor (100a) and the second drain electrode (162b) of the second thin film transistor (100b), the high voltage is applied to the first drain electrode (162a) and the second drain electrode (162b). As a result, deterioration can occur in the first drain electrode (162a) and the second drain electrode (162b) of the first thin film transistor (100a) and the second thin film transistor (100b). The first thin film transistor (100a) and the second thin film transistor (100b) can be referred to as a Heat Source.

[0070] Reference Figure 2a When the first gate electrode (150a) and the second gate electrode (150b) of the first thin film transistor (100a) and the second thin film transistor (100b) that are Heat Sources are connected adjacent to each other and the first thin film transistor (100a) and the second thin film transistor (100b) are disposed adjacent to each other with respect to the first direction (X), a problem of an increase in the heat generation temperature of the thin film transistor unit (10a) including the first thin film transistor (100a) and the second thin film transistor (100b) can occur.

[0071] In the past, in order to prevent an increase in the heat generation temperature of the thin film transistor unit (10a), a method of horizontally or vertically increasing the distance between the first thin film transistor (100a) and the second thin film transistor (100b) that are Heat Sources has been used.

[0072] For example, an increase in the distance horizontal between the first thin-film transistor (100a) and the second thin-film transistor (100b) as a heat source means that the distance between the first thin-film transistor (100a) and the second thin-film transistor (100b) increases in the first direction (X).

[0073] Further, an increase in the distance vertical between the first thin-film transistor (100a) and the second thin-film transistor (100b) as a heat source means that the distance between the first thin-film transistor (100a) and the second thin-film transistor (100b) increases in a direction perpendicular to the first direction (X) and the second direction (Y). Specifically, this means that the distance between the first thin-film transistor (100a) and the second thin-film transistor (100b) increases in the thickness direction of the display device (1000).

[0074] However, in the conventional method, when the distance horizontal or the distance vertical between the first thin-film transistor (100a) and the second thin-film transistor (100b) as a heat source is increased to reduce the heat generation temperature, the heat generation temperature can be reduced by increasing the distance from the heat source, but there is a problem in that the size of the bezel of the display device (1000) increases.

[0075] To solve this problem, the thin-film transistor unit (10b) according to one embodiment of the present application can have heat sources that cross each other in a plan view.

[0076] Reference Figure 1b , the first thin-film transistor (100a) and the second thin-film transistor (100b) connected to the first terminal (115a) can be disposed diagonally to each other.

[0077] Figure 3a is a plan view of the thin-film transistor unit (10b) of Figure 1b Figure 3b is a cross-sectional view taken along line III-III' of Figure 3a Figure 3c is a cross-sectional view taken along line IV-IV' of Figure 3a

[0078] ​​​According to one embodiment of the present application, the first terminal (115a) of the thin film transistor unit (10b) is connected to the first drain electrode (162a) and the second drain electrode (162b), and the second terminal (115b) is connected to the third source electrode (161c) and the fourth source electrode (161d). Further, the third drain electrode (162c) can be connected to the fourth drain electrode (162d) only via the first source electrode (161a), and can be connected to the fourth drain electrode (162d) only via the second source electrode (161b). That is, as shown in Figure 3a

[0079] Referring to Figure 3a , the first terminal (115a) is connected to the first drain electrode (162a) and the second drain electrode (162b) of the first thin film transistor (100a) and the second thin film transistor (100b) which are disposed diagonally to each other.

[0080] As a result, it is possible to prevent the heat generation temperature of the thin film transistor unit (10b) from rising by increasing the distance between the heat sources without increasing the distance in the horizontal or vertical direction between the first thin film transistor (100a) and the second thin film transistor (100b).

[0081] According to one embodiment of the present application, in a plan view, the first thin film transistor (100a) and the fourth thin film transistor (100d) are adjacently disposed along the first direction (X), and the second thin film transistor (100b) and the third thin film transistor (100c) are adjacently disposed along the first direction (X).

[0082] In Figure 3a , the first thin film transistor (100a) connected to the first terminal (115a) and the fourth thin film transistor (100d) connected to the second terminal (115b) are adjacently disposed along the first direction (X) to each other, and the second thin film transistor (100b) connected to the first terminal (115a) and the third thin film transistor (100c) connected to the second terminal (115b) are adjacently disposed along the first direction (X) to each other.

[0083] ​Thus, the first thin film transistor (100a) and the second thin film transistor (100b) connected to the first terminal (115a) to which a high voltage is input are provided in different rows, thereby preventing the heating temperature of the thin film transistor unit (10b) from rising.

[0084] According to one embodiment of the present application, the same gate voltage can be applied to the first gate electrode (150a), the second gate electrode (150b), the third gate electrode (150c), and the fourth gate electrode (150d) at the same time.

[0085] Reference Figure 3a , the gate voltage (VGS) through the gate electrode (Gate) is applied to the first gate electrode (150a), the second gate electrode (150b), the third gate electrode (150c), and the fourth gate electrode (150d) at the same time.

[0086] According to one embodiment of the present application, the first gate electrode (150a) can be connected to the second gate electrode (150b) only through the third gate electrode (150c), and can be connected to the second gate electrode (150b) only through the fourth gate electrode (150d).

[0087] Reference Figure 3a The first gate electrode (150a) is connected to the second gate electrode (150b) only via the third gate electrode (150c). Specifically, no other gate electrode is provided between the first gate electrode (150a) and the third gate electrode (150c), and no other gate electrode is provided between the third gate electrode (150c) and the second gate electrode (150b).

[0088] Further, the first gate electrode (150a) is connected to the second gate electrode (150b) only via the fourth gate electrode (150d). Specifically, no other gate electrode is provided between the first gate electrode (150a) and the fourth gate electrode (150d), and no other gate electrode is provided between the fourth gate electrode (150d) and the second gate electrode (150b).

[0089] According to one embodiment of the present application, in a plan view, the first thin film transistor (100a) and the third thin film transistor (100c) are provided adjacent along a second direction (Y) perpendicular to the first direction (X), and the second thin film transistor (100b) and the fourth thin film transistor (100d) are provided adjacent along the second direction (Y) perpendicular to the first direction (X).

[0090] Reference Figure 3a , Figure 3b and Figure 3cThe first thin film transistor (100a) connected to the first terminal (115a) and the third thin film transistor (100c) connected to the second terminal (115b) are arranged adjacent to each other along the second direction (Y), and the second thin film transistor (100b) connected to the first terminal (115a) and the fourth thin film transistor (100d) connected to the second terminal (115b) are arranged adjacent to each other along the second direction (Y).

[0091] Thus, the first thin film transistor (100a) and the second thin film transistor (100b) connected to the first terminal (115a) to which a high voltage is input are arranged in different columns, thereby preventing the heat generation temperature of the thin film transistor unit (10b) from rising.

[0092] Specifically, the first thin film transistor (100a) and the second thin film transistor (100b) are arranged adjacent to each other in a diagonal direction between the first direction (X) and the second direction (Y) in plan view.

[0093] When the first thin film transistor (100a) and the second thin film transistor (100b) are diagonally arranged in plan view, the heat generation temperature of the thin film transistor unit (10b) can be prevented from rising by increasing the distance between the heat sources (the first thin film transistor (100a) and the second thin film transistor (100b)) without increasing the distance in the horizontal or vertical direction between the heat sources (the first thin film transistor (100a) and the second thin film transistor (100b)) as heat sources.

[0094] According to one embodiment of the present application, the first active layer (130a), the second active layer (130b), the third active layer (130c), and the fourth active layer (130d) form a rectangle in plan view, in which the first active layer (130a), the second active layer (130b), the third active layer (130c), and the fourth active layer (130d) are respectively located at the corners, and the first active layer (130a) and the second active layer (130b) can be located on one diagonal of the rectangle, and the third active layer (130c) and the fourth active layer (130d) can be located on the other diagonal of the rectangle.

[0095] According to one embodiment of the present application, the first active layer (130a), the second active layer (130b), the third active layer (130c), and the fourth active layer (130d) can be arranged spaced apart from each other.

[0096] When the first active layer (130a) of the first thin film transistor (100a) as a heat source is integrally formed with the active layer of an adjacent thin film transistor, a problem can occur in which the heat generation temperature increases in the entire integrally formed active layer.

[0097] For example, when the first active layer (130a) of the first thin film transistor (100a) as a heat source is integrally formed with the third active layer (130c) or the fourth active layer (130d) of the third thin film transistor (100c) or the fourth thin film transistor (100d) in the thin film transistor unit (10b) of FIG. 1A, Figure 3a

[0098] Therefore, in order to reduce the heat generation temperature of the thin film transistor unit (10b) according to one embodiment of the present application, the first active layer (130a), the second active layer (130b), the third active layer (130c), and the fourth active layer (130d) need to be disposed apart from each other.

[0099] According to one embodiment of the present application, the thin film transistor unit (10b) can further include a third terminal (115c).

[0100] According to one embodiment of the present application, the third terminal (115c) can be connected to the first source electrode (161a), the second source electrode (161b), the third drain electrode (162c), and the fourth drain electrode (162d).

[0101] Figure 3a The third terminal (115c) connected to the first source electrode (161a), the second source electrode (161b), the third drain electrode (162c), and the fourth drain electrode (162d) is illustrated. However, one embodiment of the present application is not limited thereto, and the first source electrode (161a), the second source electrode (161b), the third drain electrode (162c), and the fourth drain electrode (162d) can be in a floating state.

[0102] ​According to one embodiment of the present application, the first thin film transistor (100a), the second thin film transistor (100b), the third thin film transistor (100c), and the fourth thin film transistor (100d) each include a base substrate (110), a buffer layer (120) on the base substrate (110), an active layer (130a, 130b, 130c, 130d) on the buffer layer (120), a gate electrode insulating film (140) on the active layer (130a, 130b, 130c, 130d), a gate electrode (150a, 150b, 150c, 150d) on the gate electrode insulating film (140), a source electrode (161a, 161b, 161c, 161d), and a drain electrode (162a, 162b, 162c, 162d).

[0103] The respective configurations of the first thin film transistor (100a), the second thin film transistor (100b), the third thin film transistor (100c), and the fourth thin film transistor (100d) are described in detail below.

[0104] Glass or plastic can be used as the base substrate (110). A transparent plastic (e.g., polyimide) having a flexible property can be used as the plastic. Referring to FIG. 1, the base substrate (110) can be formed of a transparent plastic (e.g., polyimide) having a flexible property. Figure 3b and Figure 3c The base substrate (110) on which the active layer (130a, 130b, 130c, 130d) is disposed can be integrally formed.

[0105] According to one embodiment of the present application, the buffer layer (120) can be disposed on the base substrate (110).

[0106] The buffer layer (120) has an insulating property and protects the active layer (130a, 130b, 130c, 130d). The buffer layer (120) can include at least one of insulating silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide. The buffer layer (120) on which the active layer (130a, 130b, 130c, 130d) is disposed can be integrally formed.

[0107] The active layer (130a, 130b, 130c, 130d) can be disposed on the buffer layer (120).

[0108] The active layers (130a, 130b, 130c, 130d) each include an oxide semiconductor material. According to one embodiment of the present application, the active layers (130a, 130b, 130c, 130d) are oxide semiconductor layers made of an oxide semiconductor material. For example, the active layers (130a, 130b, 130c, 130d) can include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, a GO (GaO)-based oxide semiconductor material, and an ITZO (InSnZnO)-based oxide semiconductor material. However, one embodiment of the present application is not limited to this, and the active layers (130a, 130b, 130c, 130d) can be formed using other oxide semiconductor materials known in the art.

[0109] The gate insulating film (140) is provided over the active layer (130a, 130b, 130c, 130d). The gate insulating film (140) can include at least one of silicon oxide and silicon nitride, and can further include a metal oxide or a metal nitride. The gate insulating film (140) can have a single-film structure or a multi-film structure. The gate insulating film (140) can be provided so as to cover the entire upper surface of the buffer layer (120).

[0110] The gate insulating film (140) can be formed by an atomic layer deposition (ALD) method or a metal organic chemical vapor deposition (MOCVD) method. The gate insulating film (140) can be patterned or can not be patterned. Figure 3b Figure 3c Figure 4b Figure 4c A structure in which the gate insulating film (140) is not patterned is disclosed.

[0111] The gate electrodes (150a, 150b, 150c, 150d) are provided over the gate insulating film (140). The gate electrodes (150a, 150b, 150c, 150d) are each spaced apart from the active layer (130a, 130b, 130c, 130d) and at least partially overlaps with the active layer (130a, 130b, 130c, 130d).

[0112] ​​​The gate electrodes (150a, 150b, 150c, 150d) can include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrodes (150a, 150b, 150c, 150d) can also have a multilayer film structure including at least two conductive films having different physical properties.

[0113] The source electrodes (161a, 161b, 161c, 161d) and the drain electrodes (162a, 162b, 162c, 162d) are disposed on the gate electrode insulating film (140).

[0114] The source electrodes (161a, 161b, 161c, 161d) and the drain electrodes (162a, 162b, 162c, 162d) are spaced apart from each other and connected to the active layers (130a, 130b, 130c, 130d), respectively. The source electrodes (161a, 161b, 161c, 161d) and the drain electrodes (162a, 162b, 162c, 162d) are connected to the active layers (130a, 130b, 130c, 130d) through contact holes formed in the gate electrode insulating film (140), respectively.

[0115] The source electrodes (161a, 161b, 161c, 161d) and the drain electrodes (162a, 162b, 162c, 162d) can each include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy thereof. The source electrodes (161a, 161b, 161c, 161d) and the drain electrodes (162a, 162b, 162c, 162d) can each be formed of a single layer made of a metal or a metal alloy, or can be formed of a multilayer including two or more layers.

[0116] According to one embodiment of the present application, the gate electrodes (150a, 150b, 150c, 150d), the source electrodes (161a, 161b, 161c, 161d), and the drain electrodes (162a, 162b, 162c, 162d) can be formed on the same layer.

[0117] Specifically, Figure 3b , Figure 3c , Figure 4b and Figure 4cA gate electrode (150a, 150b, 150c, 150d), a source electrode (161a, 161b, 161c, 161d), and a drain electrode (162a, 162b, 162c, 162d) formed on a gate electrode insulating film (140) are shown.

[0118] Figure 4a is a plan view of a thin film transistor unit (10c) according to another embodiment of the present application. Figure 4b is a cross-sectional view taken along Figure 4a line V-V' of Figure 4c is a cross-sectional view taken along Figure 4a line VI-VI' of

[0119] compared with the thin film transistor unit (10b) of Figure 3a , Figure 3b and Figure 3c the thin film transistor unit (10c) of Figure 4a , Figure 4b and Figure 4c has different positions of the first thin film transistor (100a), the second thin film transistor (100b), the third thin film transistor (100c), and the fourth thin film transistor (100d).

[0120] Specifically, in the thin film transistor unit (10b) of Figure 3a , Figure 3b and Figure 3c the first thin film transistor (100a) and the second thin film transistor (100b) connected to the first terminal (115a) to which a high voltage is input are respectively provided in the lower left and the upper right in the plane.

[0121] However, specifically, in the thin film transistor unit (10c) of Figure 4a , Figure 4b and Figure 4c the first thin film transistor (100a) and the second thin film transistor (100b) connected to the first terminal (115a) to which a high voltage is input are respectively provided in the upper left and the lower right in the plane.

[0122] According to one embodiment of the present application, the first thin film transistor (100a) and the second thin film transistor (100b) as heat sources must be provided diagonally adjacent to each other, but are not limited to the diagonal direction toward the upper right and the diagonal direction toward the lower right.

[0123] Figure 5 is a schematic view of a display device (1000) according to another embodiment of the present application.

[0124] A display device (1000) according to another embodiment of the present application can include a display panel (310), a gate driving circuit (320), a data driving circuit (330), and a control unit (340), as shown in Figure 5

[0125] The display panel (310) includes gate lines (GL) and data lines (DL), and pixels (P) are disposed at intersections of the gate lines (GL) and the data lines (DL). An image is displayed by driving the pixels (P). The gate lines (GL), the data lines (DL), and the pixels (P) can be disposed on a base substrate (110).

[0126] The control unit (340) controls the gate driving circuit (320) and the data driving circuit (330).

[0127] The control unit (340) outputs a gate control signal (GCS) for controlling the gate driving circuit (320) and a data control signal (DCS) for controlling the data driving circuit (330) using a signal provided from an external system (not shown). In addition, the control unit (340) samples input image data input from the external system, rearranges it, and provides the rearranged digital image data (RGB) to the data driving circuit (330).

[0128] The gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK). In addition, the gate control signal (GCS) can include a control signal for controlling the gate driving circuit (330).

[0129] The data control signal (DCS) includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), and a polarity control signal (POL).

[0130] The data driving circuit (330) provides a data voltage to the data lines (DL) of the display panel (310). Specifically, the data driving circuit (330) converts image data (RGB) input from the control unit (340) into an analog data voltage, and provides the data voltage to the data lines (DL).

[0131] According to one embodiment of the present application, the gate driving circuit (320) can be mounted on the display panel (310). In this way, a structure in which the gate driving circuit (320) is directly mounted on the display panel (310) is referred to as a Gate In Panel (GIP) structure. Specifically, in the GIP structure, the gate driving circuit (320) can be disposed on the base substrate (110).​

[0132] The display device (1000) according to one embodiment of the present application can include the thin film transistor units (10b, 10c) described above. According to one embodiment of the present application, the gate driver circuit (320) can include the thin film transistor units (10b, 10c) described above.

[0133] Figure 6 is a diagram illustrating an example of a display panel (310) in which a gate driver circuit (320) is implemented as a GIP type in a display device (1000).

[0134] Referring to Figure 6 n gate lines (GL(1) to GL(n), where n is a natural number) can be provided in a display region (A / A) in which an image is displayed on the display panel (310) in the display device (1000).

[0135] At this time, the gate driver circuit (320) is constructed and provided in a non-display region corresponding to an outer periphery of the display region (A / A) of the display panel (310), and can include n gate lines (GL(1) to GL(n), where n is a natural number) and n stages (ST1 to STn) corresponding to each other.

[0136] Therefore, the n stages (ST1 to STn) can output a scan signal (SCAN) to the n gate lines (GL(1) to GL(n), where n is a natural number) (see Figure 7 ).

[0137] Referring to Figure 6 The gate driver circuit (320) is formed on the left and right sides, and provides a scan signal (SCAN) to the n gate lines (GL(1) to GL(n), where n is a natural number) formed on the display panel (310).

[0138] Specifically, Figure 6 The case where the n stages (ST1 to STn) are respectively provided on the left and right sides is illustrated.

[0139] Here, the left and right gate driver circuits simultaneously output a scan signal (SCAN) to the same gate line (GL) in a double feeding manner. However, one embodiment of the present application is not limited thereto.

[0140] A plurality of clock signal lines (CL) can be provided in a non-display region corresponding to an outer periphery of a display region (A / A) of a display panel (310) to transmit a gate clock required to generate and output a scan signal (SCAN) to a gate driver circuit (320).

[0141] Figure 7 is a diagram illustrating a schematic configuration of a stage (ST) provided in a gate driving circuit (320) of Figure 5

[0142] Referring to Figure 7 , one stage (ST) in the display device (1000) means any one of n stages (ST1 to STn) of Figure 6 , and one stage (ST) can include a control circuit (122) and a buffer circuit (124).

[0143] The stage (ST) starts operation in response to a gate start pulse (GSP), and outputs a scan signal (SCAN) in response to a gate clock (GCLK). The scan signal (SCAN) output from the stage (ST) is sequentially shifted and sequentially supplied through a gate line (GL).

[0144] The buffer circuit (124) includes two nodes (Q, QB) that are most important in a gate driving state, and can include a pull-up transistor (TU) and a pull-down transistor (TD). Here, a gate node of the pull-up transistor (TU) can correspond to the Q node, and a gate node of the pull-down transistor (TD) can correspond to the QB node.

[0145] The control circuit (122) can be used to generate a scan signal (SCAN) synchronized with a gate clock (GCLK).

[0146] The control circuit (122) can control the Q node and the QB node connected to the buffer circuit (124) so that the buffer circuit (124) can output the scan signal (SCAN), and for this purpose, can include a plurality of transistors.

[0147] The control circuit (122) starts to generate the scan signal (SCAN), and the output of the control circuit (122) is sequentially turned on according to the gate clock (GCLK). That is, by controlling the output time of the control circuit (122) using the gate clock (GCLK), it can be sequentially transmitted to the buffer circuit (124) that determines the on / off of the gate line (GL).

[0148] According to the control circuit (122), the voltage state of each of the Q node and the QB node of the buffer circuit (124) can change. Therefore, the buffer circuit (124) can output a voltage to the corresponding gate line (GL) to turn on the corresponding gate line (GL), or output a voltage to the corresponding gate line (GL) to turn off the corresponding gate line (GL).

[0149] At this time, the control circuit (122) and the buffer circuit (124) constituting one stage (ST) can be connected in various structures. ​

[0150] Figure 8 is a circuit diagram of a stage (ST) provided in a gate drive circuit (320) according to one embodiment Figure 5 is a circuit diagram of a stage (ST) provided in a gate drive circuit (320) according to one embodiment

[0151] With reference to Figure 8 The stage (ST) according to one embodiment of the present application includes an M_o node, a Q_o node, a Q_e node, a Qb_o node, a Qb_e node, and a Qh_o node.

[0152] With reference to Figure 8 The stage (ST) includes a first sensing control block (BK1a), a second sensing control block (BK1b), an input block (BK2), an inverter block (BK3), and an output block (BK4).

[0153] The first sensing control block (BK1a) applies a carry signal C(n-2) to the node M_o according to row sampling signals (LSP1, LSP2) to activate a potential of the node M_o to a high potential power supply voltage GVDD, and activates a potential of the node Q_o to the high potential power supply voltage GVDD according to an activation potential of the node M_o and a global reset signal (RESET).

[0154] To this end, the first sensing control block (BK1a) includes a plurality of transistors (Ta, Tb, Tc, T1b, T1c) and a capacitor (Cst1).

[0155] The transistor Ta includes a gate electrode to which the row sampling signals (LSP1, LSP2) are applied, a drain electrode to which the carry signal C(n-2) is applied, and a source electrode connected to the node N1. The transistor Tb includes a gate electrode to which the row sampling signals (LSP1, LSP2) are applied, a drain electrode connected to the node N1, and a source electrode connected to the node M_o. The transistor Tc includes a gate electrode connected to the node N2, a drain electrode to which the high potential power supply voltage GVDD is applied, and a source electrode connected to the node N1. The transistor T1b includes a gate electrode connected to the node N2, a drain electrode to which the high potential power supply voltage GVDD is applied, and a source electrode connected to a drain electrode of the transistor T1c. The capacitor Cst1 is connected between an input terminal of the high potential power supply voltage GVDD and the node N2 to hold the activation potential of the node M_o. The transistor T1c includes a gate electrode to which the global reset signal (RESET) is applied, a drain electrode connected to the source electrode of the transistor T1b, and a source electrode connected to the node Q_o.

[0156] According to one embodiment of the present application, the transistors Ta, Tb, T1b, and T1c of the first sensing control block (BK1a) can each include a thin film transistor unit (10b, 10c) according to one embodiment of the present application.

[0157] The second sensing control block (BK1b) deactivates the potential of the node Qb_o to the low potential power supply voltage GVSS2 in accordance with the global reset signal (RESET) and the potential of the node M.

[0158] To this end, the second sensing control block (BK1b) includes a plurality of transistors (T5a, T5b, T5c, T5d, T5e). The transistor T5a includes a gate electrode to which the global reset signal (RESET) is applied, a drain electrode connected to the node Qb_o, and a source electrode connected to the node N3. The transistor T5b includes a gate electrode connected to the node M, a drain electrode connected to the node N3, and a source electrode to which the low potential power supply voltage GVSS2 is applied. The transistor T5c includes a gate electrode to which the second global reset signal (RESET2) is applied, a drain electrode connected to the node Q_o, and a source electrode connected to the drain electrode of the transistor T5d. The transistor T5d includes a gate electrode to which the second global reset signal (RESET2) is applied, a drain electrode connected to the source electrode of the transistor T5c, and a source electrode connected to the node Qh_o. The transistor T5e includes a gate electrode to which the second global reset signal (RESET2) is applied, a drain electrode connected to the node Qh_o, and a source electrode connected to the node N3.

[0159] The input block (BK2) applies the carry signal C(n-3) to the node Q_o to activate the potential of the node Qh_o to the high potential power supply voltage GVDD. The second sensing control block (BK1b) deactivates the potential of the node Q_o to the low potential power supply voltage GVSS2 in accordance with the carry signal C(n+3). The second sensing control block (BK1b) deactivates the potential of the node Q_o to the low potential power supply voltage GVSS2 in accordance with the potential of the node Qb_o or Qb_e. The second sensing control block (BK1b) deactivates the potential of the node Q_o to the low potential power supply voltage GVSS2 in accordance with the global start pulse (Vsp).

[0160] To this end, the input block (BK2) comprises a plurality of transistors (T1, T1a, T3q, T3q', T3n, T3na, T3, T3a, T31a, T31b, T3nb, T3nc). The transistor T1 comprises a gate electrode to which the carry signal C(n-3) is applied, a drain electrode and a source electrode connected to the node Qh_o. The transistor T1a comprises a gate electrode to which the carry signal C(n-3) is applied, a drain electrode connected to the node Qh_o and a source electrode connected to the node Q_o. The transistor T3q comprises a gate electrode connected to the node Q_o, a drain electrode to which the high potential power supply voltage GVDD is applied and a source electrode connected to the drain electrode of the transistor T3q'. The transistor T3q' comprises a gate electrode connected to the node Q_o, a drain electrode connected to the source electrode of the transistor T3q and a source electrode connected to the node Qh_o. The transistor T3n comprises a gate electrode to which the carry signal C(n+3) is applied, a drain electrode connected to the node Q_o and a source electrode connected to the node Qh_o. The transistor T3na comprises a gate electrode to which the carry signal C(n+3) is applied, a drain electrode connected to the node Qh_o and a source electrode to which the low potential power supply voltage GVSS2 is applied. The transistor T3 comprises a gate electrode connected to the node Qb_o, a drain electrode connected to the node Q_o and a source electrode connected to the node Qh_o. The transistor T3a comprises a gate electrode connected to the node Qb_o, a drain electrode connected to the node Qh_o and a source electrode to which the low potential power supply voltage GVSS2 is applied. The transistor T31a comprises a gate electrode connected to the node Qb_e, a drain electrode connected to the node Q_o and a source electrode connected to the node Qh_o. The transistor T31b comprises a gate electrode connected to the node Qb_e, a drain electrode connected to the node Qh_o and a source electrode to which the low potential power supply voltage GVSS2 is applied. The transistor T3nb comprises a gate electrode to which the global start pulse (Vsp) is applied, a drain electrode connected to the node Q_o and a source electrode connected to the node Qh_o. The transistor T3nc comprises a gate electrode to which the global start pulse (Vsp) is applied, a drain electrode connected to the node Qh_o and a source electrode connected to the low potential power supply voltage GVSS2.

[0161] According to an embodiment of the present application, the transistors T1, T1a, T3n, T3na, T3, T3a, T3nb and T3nc of the input block (BK2) can each comprise a thin film transistor unit (10b, 10c) according to an embodiment of the present application.

[0162] The inverter block (BK3) deactivates the potential of the node Qb_o to the low potential power supply voltage GVSS2 in accordance with the carry signal C(n-3). The inverter block (BK3) deactivates the potential of the node Qb_o to the low potential power supply voltage GVSS2 in accordance with the activation potential of the node Q_o. The inverter block (BK3) applies the power supply voltage GVDD_o to the node N4 to activate the potential of the node Qb_o to the power supply voltage GVDDo. The inverter block (BK3) deactivates the potential of the node N4 to the low potential power supply voltage GVSS2 in accordance with the activation potential of the node Q_e.

[0163] To this end, the inverter block (BK3) includes a plurality of transistors (T4, T41, T4q, T4q', T5, T5q). The transistor T4 includes a gate electrode connected to the node N4, a drain electrode to which the power supply voltage GVDD_o is applied, and a source electrode connected to the node Qb_o. The transistor T41 includes a gate electrode and a drain electrode to which the power supply voltage GVDD_o is applied, and a source electrode connected to the node N4. The transistor T4q includes a gate electrode connected to the node Q_o, a drain electrode connected to the node N4, and a source electrode connected to the low potential power supply voltage GVSS1. The transistor T4q' includes a gate electrode connected to the node Q_e, a drain electrode connected to the node N4, and a source electrode to which the low potential power supply voltage GVSS1 is applied. The transistor T5 includes a gate electrode to which the carry signal C(n-3) is applied, a drain electrode connected to the node Qb_o, and a source electrode to which the low potential power supply voltage GVSS2 is applied. The transistor T5q includes a gate electrode connected to the node Q_o, a drain electrode connected to the node Qb_o, and a source electrode to which the low potential power supply voltage GVSS2 is applied.

[0164] The output block (BK4) outputs a carry shift clock CRCLK(n) as a carry signal C(n) when the potential of the node Q_o is raised from the voltage level L2 to L3, and outputs a low potential power supply voltage GVSS2 as the carry signal C(n) when the potential of the node Qb_o is activated to the voltage level L2 or when the potential of the node Qb_e is activated to the voltage level L2. The output block (BK4) outputs a scan shift clock SCCLK(n) as a gate pulse SCOUT(n) for image display when the potential of the node Q_o is raised from the level L2 to L3, and outputs a low potential power supply voltage GVSS0 as the gate pulse SCOUT(n) for image display when the potential of the node Qb_o is activated to the voltage level L2 or when the potential of the node Qb_e is activated to the voltage level L2. The output block (BK4) outputs a sense shift clock SECLK(n) to a sense signal SEOUT(n) when the potential of the node Q_o is raised from the level L2 to L3, and outputs a low voltage power supply voltage GVSS0 to the sense signal SEOUT(n) when the potential of the node Qb_o is activated to the voltage level L2 or when the potential of the node Qb_e is activated to the voltage level L2.

[0165] To this end, the output block (BK4) comprises a plurality of pull-up transistors (T6a, T6b, T6c), a plurality of pull-down transistors (T7a, T7a', T7b, T7b', T7c, T7c') and a plurality of capacitors (Cap CR, Cap SC, Cap SE). The pull-up transistor T6a comprises a gate electrode connected to the node Q o, a drain electrode to which the carry shift clock CRCLK(n) is applied, and a source electrode connected to the node N5. The capacitor Cap CR is connected between the node Q o and the node N5. The pull-up transistor T6b comprises a gate electrode connected to the node Q o, a drain electrode to which the scan shift clock SCCLK(n) is applied, and a source electrode connected to the node N6. The capacitor Cap SC is connected between the node Q o and the node N6. The pull-up transistor T6c comprises a gate electrode connected to the node Q o, a drain electrode to which the sense shift clock SECLK(n) is applied, and a source electrode connected to the node N7. The capacitor Cap SE is connected between the node Q o and the node N7. The pull-down transistor T7a comprises a gate electrode connected to the node Qb o, a drain electrode connected to the node N5 and a source electrode connected to the low potential power supply voltage GVSS2. The pull-down transistor T7a' comprises a gate electrode connected to the node Qb e, a drain electrode connected to the node N5 and a source electrode connected to the low potential power supply voltage GVSS2. The pull-down transistor T7b comprises a gate electrode connected to the node Qb o, a drain electrode connected to the node N6 and a source electrode connected to the low potential power supply voltage GVSS0. The pull-down transistor T7b' comprises a gate electrode connected to the node Qb e, a drain electrode connected to the node N6 and a source electrode connected to the low potential power supply voltage GVSS0. The pull-down transistor T7c comprises a gate electrode connected to the node Qb o, a drain electrode connected to the node N7 and a source electrode connected to the low potential power supply voltage GVSS0. The pull-down transistor T7c' comprises a gate electrode connected to the node Qb e, a drain electrode connected to the node N7 and a source electrode connected to the low potential power supply voltage GVSS0.

[0166] According to one embodiment of the present application, the transistors T6a, T6b, T6c, T7b and T7c of the output block (BK4) can each comprise a thin film transistor unit (10b, 10c) according to one embodiment of the present application.

[0167] Figure 9 is a diagram showing the arrangement of stages (ST) within the display panel (310).

[0168] Figure 10 is a diagram showing a structure for sensing and compensating for degradation of the gate driver circuit (320).

[0169] According to one embodiment of the present application, the gate driver circuit (320) includes n stages (ST1 to STn), a front dummy stage (DST1) located in front of the first stage (ST1), and a back dummy stage (DST2) located behind the n-th stage (STn).

[0170] Figure 9 The gate driver circuit (320) disposed at the left and right sides of the display panel (310) is shown to include n stages (ST1 to STn), a front dummy stage (DST1) disposed in front of the first stage (ST1), and a back dummy stage (DST2) disposed behind the n-th stage (STn).

[0171] The front dummy stage (DST1) and the back dummy stage (DST2) are not connected to the gate lines (GL). The front dummy stage (DST1) and the back dummy stage (DST2) do not output the scan signal (SCAN) but only output the carry signal. The front dummy stage (DST1) and the back dummy stage (DST2) are dependently connected to the stages (ST) and have substantially the same circuit configuration as the stages (ST).

[0172] Referring to Figure 9 and Figure 10 , the front dummy stage (DST1) and the back dummy stage (DST2) including the feedback transistor (Tfb) built in a portion of the display panel (310) are included.

[0173] For example, the front dummy stage (DST1) and the back dummy stage (DST2) including the feedback transistor (Tfb) can be located at the upper, lower, left, and right corners of the display panel (310) to compensate for the degradation distribution of the display panel (310).

[0174] Figure 9 The front dummy stage (DST1) and the back dummy stage (DST2) disposed at the upper, lower, left, and right corners of the display panel (310) are shown.

[0175] In this case, the feedback voltage (GVDD_FB) is supplied from the front dummy stage (DST1) and the back dummy stage (DST2) disposed at the upper, lower, left, and right corners of the display panel (310), and can determine the degradation state of the stages (ST) according to the position of the display panel (310).

[0176] As a result, the degradation state of the stages (ST) can be detected according to the position of the display panel (310), and the compensation high potential gate voltage (PGVDD) is generated according to the degradation state reflecting the position of the display panel (310) (see Figure 10 ).

[0177] Meanwhile, the display device (1000) can also check for defects in the feedback transistors (Tfb) built into the front dummy stage (DST1) and the back dummy stage (DST2) by using a high-potential gate voltage (PGVDD) for compensation.

[0178] Figure 10 The arrangement of the dummy stage (DST) is shown as an example of a front dummy stage (DST1) and a rear dummy stage (DST2). The dummy stage (DST) includes a feedback transistor (Tfb).

[0179] The gate electrode of the feedback transistor (Tfb) is connected to the QB node, and its drain electrode is connected to the low-potential supply voltage GVSS2. Furthermore, its source electrode is connected to the feedback line.

[0180] Therefore, the compensation circuit (152) receives the feedback voltage (GVDD_FB) through the feedback transistor (Tfb) configured in the dummy stage (DST) and generates a compensation high-potential gate voltage (PGVDD) applied to the stage (ST).

[0181] Omitted Figure 10 The description of the control circuit (122), gate clock (GCLK), pull-up transistor (TU), and pull-down transistor (TD) shown is as follows: Figure 7 The description is repeated. Furthermore... Figure 10 The transistor T3 shown corresponds to Figure 8 The T3 shown is omitted, and any repeated descriptions are omitted.

[0182] According to one embodiment of the present invention, each feedback transistor (Tfb) of the dummy stage (DST) may include a thin-film transistor unit (10b, 10c) according to one embodiment of the present invention.

[0183] Based on this disclosure, the following beneficial effects can be obtained.

[0184] A thin-film transistor cell according to one embodiment of the present invention can have a reduced heating temperature by using cross heat sources.

[0185] A display device including such a thin-film transistor unit according to one embodiment of the present invention may have a narrow bezel.

[0186] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments described above and the drawings, and various substitutions, modifications and changes can be made in the disclosure without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims are intended to fall within the scope of the disclosure.

Claims

1. A thin-film transistor unit, comprising: First terminal; The first thin-film transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; The second thin-film transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; The third thin-film transistor includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode; The fourth thin-film transistor includes a fourth active layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode; as well as Second terminal, The same gate voltage is configured to be applied simultaneously to the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode. The first terminal is connected to the first drain electrode and the second drain electrode. The second terminal is connected to the third source electrode and the fourth source electrode, and The third drain electrode is connected to the fourth drain electrode only via the first source electrode and only via the second source electrode.

2. The thin-film transistor unit according to claim 1, wherein, The voltage input to the first terminal is higher than the voltage input to the second terminal.

3. The thin-film transistor unit according to claim 1, wherein, The first thin-film transistor and the fourth thin-film transistor are arranged adjacent to each other along a first direction in a plan view, and The second thin-film transistor and the third thin-film transistor are arranged adjacent to each other along the first direction in a plan view.

4. The thin-film transistor unit according to claim 1, wherein, The first gate electrode is connected to the second gate electrode only via the third gate electrode, and is connected to the second gate electrode only via the fourth gate electrode.

5. The thin-film transistor unit according to claim 3, wherein, The first thin-film transistor and the third thin-film transistor are arranged adjacent to each other in a plan view along a second direction perpendicular to the first direction, and The second thin-film transistor and the fourth thin-film transistor are arranged adjacent to each other along the second direction in a plan view.

6. The thin-film transistor unit as claimed in claim 5, wherein, The first thin-film transistor and the second thin-film transistor are arranged adjacent to each other in a plan view along a diagonal direction between the first direction and the second direction.

7. The thin-film transistor unit according to claim 5, wherein, The first active layer, the second active layer, the third active layer, and the fourth active layer form a square, wherein the first active layer, the second active layer, the third active layer, and the fourth active layer are respectively located at the corners of the square in a plan view, and The first active layer and the second active layer are located on opposite diagonals of the square, and the third active layer and the fourth active layer are located on the other diagonal of the square.

8. The thin-film transistor unit according to claim 1, wherein, The first active layer, the second active layer, the third active layer, and the fourth active layer are spaced apart from each other.

9. The thin-film transistor unit according to claim 1, further comprising a third terminal connected to the first source electrode, the second source electrode, the third drain electrode, and the fourth drain electrode.

10. The thin-film transistor unit according to claim 1, wherein, The first source electrode, the second source electrode, the third source electrode, the fourth source electrode, the first drain electrode, the second drain electrode, the third drain electrode, the fourth drain electrode, the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are disposed on the same layer.

11. A display device, comprising: A display panel, wherein multiple pixels are provided in the display panel; as well as A gate driving circuit configured to provide multiple scan signals to the display panel via multiple gate lines. The gate drive circuit includes a stage for providing the scan signal. and The stage includes a thin-film transistor unit according to any one of claims 1 to 10.

12. A display device, comprising: A display panel, wherein multiple pixels are provided in the display panel; as well as A gate driving circuit configured to provide multiple scan signals to the display panel via multiple gate lines. The gate drive circuit includes: The stage used to provide the scan signal; and Dependently connected to the pre-dummy level and post-dummy level of the aforementioned level, Wherein, the pre-dummy stage and the post-dummy stage include feedback transistors, and The feedback transistor includes a thin-film transistor unit according to any one of claims 1 to 10.

13. The display device according to claim 12, wherein, The front dummy level and the rear dummy level are located in the corner area of ​​the display panel.

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