Memory tester and memory testing method

Abstract

The application discloses a memory tester and a memory testing method, and relates to the technical field of memory testing, in particular to a memory tester and a memory testing method. The memory tester comprises a memory testing site circuit board, a voltage and current measuring circuit board, a peripheral management interface board, a switch circuit board and a CRPS power conversion board; the memory testing site circuit board is fixedly connected with the voltage and current measuring circuit board through a first board-to-board connector; the voltage and current measuring circuit board is fixedly connected with the peripheral management interface board through a first crimping connector; the peripheral management interface board is fixedly connected with the switch circuit board through a second crimping connector; and the switch circuit board is fixedly connected with the CRPS power conversion board through a second board-to-board connector. The application can improve the compatibility and hardware flexibility of the memory tester by quickly replacing the memory testing site circuit board.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a memory tester and a memory testing method. BACKGROUND

[0002] At present, the test equipment of LPDDR (Low Power Double Data Rate SDRAM) has the advantages of supporting 64-channel parallel test, covering LPDDR4 / 5 mass production demand, integrating high-speed digital channel (12.8Gbps) and high-precision power module, etc.

[0003] However, the cost of a single LPDDR5 test equipment is high, and the test equipment needs to support LPDDR4 / 5 / 5X at the same time, which leads to low hardware flexibility of the test equipment, and the test equipment mostly adopts a closed architecture of FPGA (Field-Programmable Gate Array) + ARM (Advanced RISC Machines), the protocol parsing capability is limited due to the fixed FPGA logic, and cannot dynamically adapt to the differences of different generations such as LPDDR4 / 5 / 6. The existing LPDDR4 / 5 test equipment only supports SLT (System Level Test) single mode test in the test scheme, but the SLT test mode has the challenges of long test time, production efficiency bottleneck, test consistency and repeatability. The deficiency of STL test mode is essentially because it undertakes the arduous task of "leakage repair" after ATE test. It cannot replace ATE (Automated Test Equipment). Therefore, how to improve the compatibility and hardware flexibility of the test equipment, realize the dual-mode test of ATE and SLT, improve the test efficiency, shorten the test time, and increase the test coverage is a problem to be solved at present.

[0004] The above content is only used to assist in understanding the technical solutions of the present application, and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide a memory tester and a memory testing method, which aims to solve the technical problem of how to improve the compatibility and hardware flexibility of the test equipment.

[0006] To achieve the above purpose, the present application provides a memory tester, which comprises a memory test site circuit board, a voltage and current measurement circuit board, a peripheral management interface board, a switch circuit board and a CRPS power conversion board.

[0007] The memory test site circuit board includes a CPU, a programmable power management chip, a BIOS read-write firmware and a plurality of memory particle test stations; the CPU is in communication connection with the programmable power management chip and the BIOS read-write firmware respectively;

[0008] The voltage and current measurement circuit board includes an analog-to-digital converter ADC, a digital-to-analog converter DAC and a first MCU, and the first MCU is in electrical connection with the analog-to-digital converter ADC and the digital-to-analog converter DAC respectively;

[0009] The peripheral management interface board includes a baseboard management controller BMC and a serial communication module, and the serial communication module is in communication connection with the baseboard management controller BMC;

[0010] The switch circuit board includes a network switch chip and a second MCU, and the second MCU is in electrical connection with the network switch chip;

[0011] The memory test site circuit board is fixedly connected with the voltage and current measurement circuit board through a first board-to-board connector; the voltage and current measurement circuit board is fixedly connected with the peripheral management interface board through a first crimping connector; the peripheral management interface board is fixedly connected with the switch circuit board through a second crimping connector; and the switch circuit board is fixedly connected with the CRPS power conversion board through a second board-to-board connector.

[0012] In an embodiment, the memory test site circuit board includes at least 8, the voltage and current measurement circuit board includes at least 4, and the peripheral management interface board includes at least 4.

[0013] In an embodiment, the CRPS power conversion board supplies power to the switch circuit board through the second board-to-board connector, the switch circuit board supplies power to the peripheral management interface board through the second crimping connector, the peripheral management interface board supplies power to the voltage and current measurement circuit board through the first crimping connector, and the voltage and current measurement circuit board supplies power to the memory test site circuit board through the first board-to-board connector.

[0014] In an embodiment, the memory test site circuit board is fixedly arranged above the corresponding voltage and current measurement circuit board through the first board-to-board connector; the voltage and current measurement circuit board is arranged above the corresponding peripheral management interface board through the first crimping connector and is arranged perpendicularly to the peripheral management interface board; and the peripheral management interface board is arranged above the switch circuit board through the second crimping connector and is arranged perpendicularly to the switch circuit board.

[0015] In an embodiment, the memory test site circuit board is provided with a power button and a reset button.

[0016] The power button is electrically connected with the test machine panel circuit board through the first board-to-board connector, the first crimp connector and the second crimp connector in sequence, and the reset button is electrically connected with the first switch power supply chip in the test machine panel circuit board through the first board-to-board connector, the first crimp connector and the second crimp connector in sequence.

[0017] In an embodiment, the network switch chip is provided with at least 8 first PHY chips, the switch circuit board is provided with a second PHY chip and an RJ45 interface, the first PHY chip is electrically connected with the second PHY chip, and the second PHY chip is electrically connected with the RJ45 interface.

[0018] Each memory test site circuit board sends test data to the voltage and current measurement circuit board through the first board-to-board connector; the voltage and current measurement circuit board sends test data to the external device management interface board through the first crimp connector;

[0019] The external device management interface board sends test data to the corresponding first PHY chip in the network switch chip through the second crimp connector, each first PHY chip forwards the test data to the second PHY chip, and the second PHY chip sends the test data to the corresponding host computer of the memory tester through the RJ45 interface.

[0020] In an embodiment, the first memory test site circuit board in each memory test site circuit board receives a first memory test instruction, and the second memory test site circuit board in each memory test site circuit board receives a second memory test instruction.

[0021] The first memory test site circuit board controls the power-on of the CPU of the first memory test site circuit board, the BIOS of the first memory test site circuit board reads and writes firmware to start a test case corresponding to the first memory test instruction, and performs memory test on the to-be-tested chip corresponding to the first memory test site circuit board based on the test case corresponding to the first memory test instruction.

[0022] The second memory test site circuit board controls the power-on of the CPU of the second memory test site circuit board, the BIOS of the second memory test site circuit board reads and writes firmware to start a test case corresponding to the second memory test instruction, and performs memory test on the to-be-tested chip corresponding to the second memory test site circuit board based on the test case corresponding to the second memory test instruction.

[0023] In an embodiment, the memory test site circuit board sends voltage data to the first MCU of the voltage and current measurement circuit board through the first board-to-board connector, and the first MCU obtains a voltage measurement result based on the voltage data.

[0024] The memory test station circuit board sends current data to an analog-to-digital converter (ADC) through a first board-to-board connector, the ADC samples the current and sends the obtained sampled current to a first MCU, and the first MCU calculates a current measurement result based on the sampled current.

[0025] In an embodiment, the memory test station circuit board is provided with an LED bicolor lamp.

[0026] The BMC obtains a test case result corresponding to the chip to be tested in the BIOS read-write firmware, and controls the corresponding LED bicolor lamp based on the test case result.

[0027] In an embodiment, the BIOS read-write firmware includes a first BIOS flash chip provided with an ATE test mode and a second BIOS flash chip provided with an SLT test mode.

[0028] When the first BIOS flash chip performs chip testing on the chip to be tested, the target BMC corresponding to the chip to be tested monitors BIOS working state data corresponding to the first BIOS flash chip in real time.

[0029] If the BIOS working state data is abnormal, the target BMC controls the target memory test station circuit board corresponding to the chip to be tested to restart.

[0030] When the target memory test station circuit board completes the restart, the target BMC controls the second BIOS flash chip corresponding to the chip to be tested to start, so as to perform chip testing on the chip to be tested.

[0031] In an embodiment, the memory tester is further provided with a second switching power supply chip.

[0032] An input pin of the second switching power supply chip is electrically connected with an input power supply; a positive electrode of a filter capacitor is electrically connected with the input pin, and a negative electrode is grounded.

[0033] One end of a first resistor is electrically connected with an enable input end, and the other end is electrically connected with an enable pin EN of the second switching power supply chip; one end of a second resistor is electrically connected with the enable pin of the second switching power supply chip, and the other end is grounded; a positive electrode of an enable capacitor is electrically connected with the enable pin of the second switching power supply chip, and a negative electrode is grounded.

[0034] A start mode pin of the second switching power supply chip is electrically connected with the input power supply through a first mode resistor; a switching frequency pin of the second switching power supply chip is electrically connected with the input power supply through a first working frequency resistor.

[0035] A positive electrode of a conversion capacitor is electrically connected with a switching control pin of the second switching power supply chip through an inductor, and the positive electrode of the conversion capacitor is electrically connected with a target voltage setting end, and a negative electrode is grounded.

[0036] Further, in order to achieve the above object, the application further provides a memory testing method applied to the memory tester, the memory testing method comprising:

[0037] When the target memory testing site circuit board in each memory testing site circuit board receives the first testing instruction, the target memory testing site circuit board controls the power-on of the corresponding CPU;

[0038] The BIOS read-write firmware corresponding to the target memory testing site circuit board starts the first test case of the ATE test corresponding to the first testing instruction, so as to perform the ATE test on the first to-be-tested chip corresponding to the target memory testing site circuit board based on the first test case;

[0039] If the ATE test of the first to-be-tested chip is passed, the BIOS corresponding to the target memory testing site circuit board starts the second test case of the SLT test, so as to perform the SLT test on the first to-be-tested chip based on the second test case.

[0040] In an embodiment, the BIOS read-write firmware comprises a first BIOS flash memory chip provided with an ATE test mode and a second BIOS flash memory chip provided with an SLT test mode; the memory testing method further comprises:

[0041] When the first to-be-tested chip is tested based on the first BIOS flash memory chip, the target BMC corresponding to the target memory testing site circuit board monitors the BIOS working state data of the first BIOS flash memory chip in real time;

[0042] If the BIOS working state data is abnormal, the target BMC controls the target memory testing site circuit board to restart;

[0043] When the target memory testing site circuit board is restarted, the second BIOS flash memory chip corresponding to the first to-be-tested chip controls the SLT test on the first to-be-tested chip.

[0044] In an embodiment, the memory testing method further comprises:

[0045] When the testing mode switching instruction is received, the target BMC corresponding to the target memory testing site circuit board determines the target BIOS flash memory chip based on the current testing mode of the first to-be-tested chip in the first BIOS flash memory chip and the second BIOS flash memory chip;

[0046] The target BMC controls the target memory testing site circuit board to restart;

[0047] When the target memory test site circuit board restarts is completed, the target BMC controls the target BIOS flash chip to perform chip test on the first to-be-tested chip.

[0048] In an embodiment, the memory test method further includes:

[0049] The first memory test site circuit board in each memory test site circuit board receives a second test instruction, and the second memory test site circuit board in each memory test site circuit board receives a third test instruction;

[0050] The first memory test site circuit board controls the power-on of the CPU of the first memory test site circuit board, and the BIOS read-write firmware of the first memory test site circuit board starts a third test case corresponding to the second test instruction, so as to perform memory test on the second to-be-tested chip corresponding to the first memory test site circuit board based on the third test case;

[0051] The second memory test site circuit board controls the power-on of the CPU of the second memory test site circuit board, and the BIOS read-write firmware of the second memory test site circuit board starts a fourth test case corresponding to the third test instruction, so as to perform memory test on the third to-be-tested chip corresponding to the second memory test site circuit board based on the fourth test case.

[0052] In an embodiment, the memory test method further includes:

[0053] When the ATE test of the first to-be-tested chip is completed, the BMC corresponding to the target memory test site circuit board obtains a test result corresponding to the first test case;

[0054] The BMC corresponding to the target memory test site circuit board controls the corresponding LED double-color lamp based on the test result.

[0055] The one or more technical solutions provided in the present application have at least the following technical effects:

[0056] The memory tester of the application is fixedly connected with the memory test site circuit board, the voltage and current measurement circuit board, the peripheral management interface board, the switch circuit board and the CRPS power conversion board through the connector, the memory test is compatible with at least two generations of LPDDR4 / 5 / 5X through quick replacement of the memory test site circuit board, can support SDP (Single Die Package), DDP (Dual Die Package), QDP (Quad Die Package) and ODP (Octa Die Package) four kinds of packaging, and can support 1-Rank / 2-Rank configuration. By integrating the SoC small system on chip, the test cost of the memory tester is reduced, and the compatibility and hardware flexibility of the memory tester are improved. The memory tester of the application can realize ATE+SLT dual-mode test of LPDDR memory chips. The ATE test mode of the application can cover 95% of memory chip defects, while shortening the test time by 30%-50%, and the SLT test mode as the "check and supplement" of the ATE test can further improve the test coverage by 3-5%. The application realizes independent high-precision measurement of the voltage and current of each independent LPDDR memory chip, and real-time online feedback of the test results. BRIEF DESCRIPTION OF DRAWINGS

[0057] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and serve to explain the principles of the application together with the specification.

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the accompanying drawings required by the embodiments or the prior art description will be briefly introduced. Obviously, those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0059] Figure 1 The structural schematic diagram of an embodiment of the memory tester of the application is provided;

[0060] Figure 2 The circuit structure schematic diagram of an embodiment of the memory tester of the application is provided;

[0061] Figure 3 The circuit structure schematic diagram of another embodiment of the memory tester of the application is provided;

[0062] Figure 4 The circuit structure schematic diagram of another embodiment of the memory tester of the application is provided;

[0063] Figure 5 The test flow schematic diagram of an embodiment of the memory test method of the application is provided;

[0064] Figure 6 The system architecture schematic diagram of the asynchronous test provided by an embodiment of the application is shown in the figure.

[0065] Figure 7 The test flow schematic diagram provided by another embodiment of the memory test method of the application is shown in the figure.

[0066] Figure 8 The experimental data schematic diagram of the current and voltage measurement of the memory tester of the application is shown in the figure.

[0067] Figure 9 The flow schematic diagram provided by an embodiment of the memory test method of the application is shown in the figure.

[0068] The object realization, functional features and advantages of the application will be further explained with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0069] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the application, and are not used to limit the application.

[0070] In order to better understand the technical solutions of the application, the specific embodiments will be described in detail below with reference to the drawings and the specific embodiments.

[0071] The main solution of the embodiment of the application is: a memory test site circuit board, a voltage and current measurement circuit board, a peripheral management interface board, a switch circuit board and a CRPS power conversion board; the memory test site circuit board includes a CPU, a programmable power management chip, a BIOS read-write firmware and a plurality of memory particle test stations; the CPU is in communication connection with the programmable power management chip and the BIOS read-write firmware respectively; the voltage and current measurement circuit board includes an analog-to-digital converter ADC, a digital-to-analog converter DAC and a first MCU, and the first MCU is in electrical connection with the analog-to-digital converter ADC and the digital-to-analog converter DAC respectively; the peripheral management interface board includes a baseboard management controller BMC and a serial communication module, and the serial communication module is in communication connection with the baseboard management controller BMC; the switch circuit board includes a network switch chip and a second MCU, and the network switch chip is in electrical connection with the second MCU; the memory test site circuit board is fixedly connected with the voltage and current measurement circuit board through a first board-to-board connector; the voltage and current measurement circuit board is fixedly connected with the peripheral management interface board through a first pressure connector; the peripheral management interface board is fixedly connected with the switch circuit board through a second pressure connector; and the switch circuit board is fixedly connected with the CRPS power conversion board through a second board-to-board connector.

[0072] At present, the test equipment of LPDDR (Low Power Double Data Rate SDRAM) has the advantages of supporting 64-channel parallel test, covering the mass production demand of LPDDR4 / 5, integrating high-speed digital channels (12.8Gbps) and high-precision power modules, etc.

[0073] However, the cost of a single LPDDR5 test equipment is high, and the test equipment needs to support LPDDR4 / 5 / 5X at the same time, which leads to low hardware flexibility of the test equipment, and the test equipment mostly adopts a closed architecture of FPGA (Field-Programmable Gate Array) + ARM (Advanced RISC Machines), the protocol parsing capability is limited due to the fixed FPGA logic, and cannot dynamically adapt to the differences of different generations such as LPDDR4 / 5 / 6. The new protocol (such as the Partial Array Self-Refresh function of LPDDR5X) needs to redevelop FPGA code, and the development cycle is as long as several months, which is difficult to meet the rapid verification requirements of chip manufacturers.

[0074] Moreover, the existing LPDDR4 / 5 test equipment only supports SLT (System Level Test) single mode test in the test scheme, but the SLT test mode has the challenges of long test time, production efficiency bottleneck, test consistency and repeatability. The deficiency of the STL test mode is essentially because it undertakes the arduous task of "checking and repairing" after ATE test. It cannot replace ATE (Automated Test Equipment).

[0075] Therefore, how to improve the compatibility and hardware flexibility of the test equipment, how to realize the dual-mode test compatible with ATE and STL, and how to improve the test efficiency, shorten the test time, and increase the test coverage are problems that need to be solved at present.

[0076] The application provides a solution, which fixes and connects a memory test site circuit board, a voltage and current measurement circuit board, a peripheral management interface board, a switch circuit board and a CRPS power conversion board through a connector, replaces the memory test site circuit board quickly, so that the memory test can be compatible with at least two generations such as LPDDR4 / 5 / 5X, integrates a SoC small system on chip, reduces the test cost of the memory tester, and improves the compatibility and hardware flexibility of the memory tester.

[0077] Based on this, the embodiment of the application provides a memory tester, which refers to Figure 1 , Figure 1 is a structural schematic diagram of an embodiment of the memory tester of the application.

[0078] The memory tester comprises a memory test station circuit board 5, a voltage and current test circuit board 4, a peripheral management interface board 6, and a switch circuit board 3. The memory tester further comprises a CRPS power conversion board 2 and a host peripheral interface board 1. The memory test station circuit board 5 is a B1 board, the voltage and current test circuit board 4 is a B2 board, the peripheral management interface board 6 is a B3 board, the switch circuit board 3 is a B4 board, the CRPS power conversion board 2 is a B5 board, and the host peripheral interface board 1 is a B6 board.

[0079] The memory test station circuit board 5 comprises a CPU, a programmable power management chip, a BIOS (Basic Input Output System) read-write firmware, and a plurality of memory particle test stations. The CPU is in communication connection with the programmable power management chip and the BIOS read-write firmware.

[0080] The programmable power management chip is electrically connected with the memory circuits corresponding to each memory particle test station, so as to supply power to the memory circuits. The programmable power management chip is in communication connection with the BIOS read-write firmware, so as to obtain voltage information of the BIOS read-write firmware.

[0081] The voltage and current test circuit board 4 comprises an analog-to-digital converter ADC, a digital-to-analog converter DAC, and a first MCU (Microcontroller Unit). The first MCU is electrically connected with the ADC (Analog-to-digital converter) and the DAC (Digital to analog converter), respectively. The ADC and the DAC transmit sampling information to the first MCU through corresponding transmission protocols.

[0082] The peripheral management interface board 6 comprises a baseboard management controller BMC and a serial communication module. The serial communication module is in communication connection with the BMC (Board Management Controller). Specifically, the serial communication module is in communication connection with the BMC through a connector, and the serial communication module and the BMC perform data transmission through a corresponding communication protocol of the connector.

[0083] The switch circuit board 3 comprises a network switch chip and a second MCU. The second MCU is electrically connected with the network switch chip.

[0084] The memory test site circuit board 5 is fixedly connected with the voltage and current test circuit board 4 through the first board-to-board connector; the voltage and current test circuit board 4 is fixedly connected with the peripheral management interface board 6 through the first crimping connector; the peripheral management interface board 6 is fixedly connected with the switch circuit board 3 through the second crimping connector; and the switch circuit board 3 is fixedly connected with the CRPS power conversion board 2 through the second board-to-board connector, wherein the second board-to-board connector is a European board-to-board connector.

[0085] Specifically, one end of the first board-to-board connector is fixedly connected with the memory test site circuit board 5, and the other end is fixedly connected with the voltage and current test circuit board 4; one end of the first crimping connector is fixedly connected with the voltage and current test circuit board 4, and the other end is fixedly connected with the peripheral management interface board 6; one end of the second crimping connector is fixedly connected with the peripheral management interface board 6, and the other end is fixedly connected with the switch circuit board 3; one end of the second board-to-board connector is fixedly connected with the switch circuit board 3, and the other end is fixedly connected with the CRPS power conversion board 2.

[0086] The memory tester is provided with a plurality of memory test site circuit boards 5, a plurality of voltage and current test circuit boards 4 and a plurality of peripheral management interface boards 6. For example, as shown in Figure 1 The memory tester is provided with 8 memory test site circuit boards 5, 4 voltage and current test circuit boards 4 and 4 peripheral management interface boards 6. Through the 8 memory test site circuit boards 5, each memory test site circuit board 5 can be provided with 4 memory particle test stations, thereby realizing parallel test of 32 PCS LPDD4 / 5 memory chips and improving test efficiency.

[0087] As shown in Figure 1 Each voltage and current test circuit board 4 corresponds to 2 memory test site circuit boards 5, the memory tester is provided with 8 first board-to-board connectors, each voltage and current test circuit board 4 is fixedly connected with two first board-to-board connectors, and each memory test site circuit board 5 is fixedly connected with one first board-to-board connector, so that each voltage and current test circuit board 4 is fixedly connected with 2 memory test site circuit boards 5 through two first board-to-board connectors, and each memory test site circuit board 5 can be provided with 4 memory particle test stations.

[0088] As shown in Figure 1As shown, the voltage and current measurement circuit board 4 corresponds to the peripheral management interface board 6 one by one, and the memory tester is provided with four first crimp connectors, and each voltage and current measurement circuit board 4 is fixedly connected to the corresponding peripheral management interface board 6 through a first crimp connector. The memory tester is provided with four second crimp connectors, and the second crimp connector corresponds to the peripheral management interface board 6 one by one, and each second crimp connector is fixedly connected to the switch circuit board 3, and each peripheral management interface board 6 is fixedly connected to the switch circuit board 3 through the corresponding second crimp connector.

[0089] It should be noted that, since each memory test site circuit board 5 corresponds to different voltage and current measurement circuit board 4 and peripheral management interface board 6, 8 memory test site circuit boards 5 can be used to simultaneously test the chip to be tested, or 8 memory test site circuit boards 5 can be used to test different items of the chip to be tested, so that the memory tester can realize asynchronous testing, that is, any one memory test site circuit board 5 completes a round of testing, and the next round of testing can be directly started without waiting for the test results of other memory test site circuit boards 5. After the introduction of automatic sorting, the UPH (Units Per Hour) of automatic sorting can be effectively improved.

[0090] In addition, it should be noted that, since the memory test site circuit board 5 is fixed on the voltage and current measurement circuit board 4 through the first board-to-board connector, different memory test site circuit boards 5 can be set for different generations of memory particles, and different memory test site circuit boards 5 can be selected for memory testing according to different generations of memory particles. For example, when the generation of the memory particles to be tested needs to be updated, only the memory test site circuit board 5 needs to be replaced, that is, the current memory test site circuit board 5 is pulled out and a new memory test site circuit board 5 is inserted, so that the new memory test site circuit board 5 is fixedly connected to the voltage and current measurement circuit board 4 through the first board-to-board connector.

[0091] In this embodiment, the CRPS (Common Redundant Power Supplies) power supply is used to supply power to the memory test site circuit board 5, the voltage and current measurement circuit board 4, the peripheral management interface board 6, and the switch circuit board 3;

[0092] Specifically, the CRPS power conversion board 2 supplies power to the switch circuit board 3 through the second board-to-board connector, the switch circuit board 3 supplies power to the peripheral management interface board 6 through the second crimp connector, the peripheral management interface board 6 supplies power to the voltage and current measurement circuit board 4 through the first crimp connector, and the voltage and current measurement circuit board 4 supplies power to the memory test site circuit board 5 through the first board-to-board connector.

[0093] The host peripheral interface board 1 is fixedly connected with the switch circuit board 3, and is used for providing a peripheral interface for the memory tester.

[0094] In the embodiment, each memory test site circuit board 5 is electrically connected with the corresponding voltage and current test circuit board 4 through the first board-to-board connector, so as to realize data interaction between the memory test site circuit board 5 and the voltage and current test circuit board 4 through the first board-to-board connector; each voltage and current test circuit board 4 is electrically connected with the corresponding peripheral management interface board 6 through the first pressure connector, so as to realize data interaction between the voltage and current test circuit board 4 and the peripheral management interface board 6 through the first pressure connector; and each peripheral management interface board 6 is electrically connected with the switch circuit board 3 through the second pressure connector, so as to realize data interaction between the peripheral management interface board 6 and the switch circuit board 3.

[0095] In a feasible implementation, the memory test site circuit board 5 is fixedly arranged above the corresponding voltage and current test circuit board 4 through the first board-to-board connector; the voltage and current test circuit board 4 is arranged above the corresponding peripheral management interface board 6 through the first pressure connector, and is arranged perpendicularly to the peripheral management interface board 6; and the peripheral management interface board 6 is arranged above the switch circuit board 3 through the second pressure connector, and is arranged perpendicularly to the switch circuit board 3.

[0096] In the embodiment, each peripheral management interface board 6 is arranged below the corresponding voltage and current test circuit board 4, and is uniformly distributed above the switch circuit board 3. The peripheral management interface board 6 can be arranged perpendicularly to the corresponding voltage and current test circuit board 4 and the switch circuit board 3, so that the switch circuit board 3 and the voltage and current test circuit board 4 are parallel, the memory test site circuit board 5 is arranged above the corresponding voltage and current test circuit board 4, each circuit board is fixedly connected through the board-to-board connector and the pressure connector, so that each circuit board of the memory tester forms a module in a "H" shape, and the board-to-board connector and the pressure connector can be 10G+ high-speed connectors, so as to realize wireless cable connection between each circuit board of the memory tester, reduce transmission loss of various signals in the memory tester, and ensure transmission rate requirement of low-power memory chip test.

[0097] The position of the test unit of the memory tester is separated from the base through the "I-shaped" module, and the base includes a voltage and current measurement circuit board 4, a peripheral management interface board 6, a switch circuit board 3, a CRPS power conversion board 2, and a host peripheral interface board 1. The base is specially used to process other circuit functions except for chip testing, such as current and voltage measurement, data aggregation, and transmission. These functions can be reused in different generations of chip testing, and thus only the upper memory test site circuit board 5 needs to be replaced when different generations of chip testing are performed, so that cost intensification and extension of the life cycle of the equipment are achieved.

[0098] In a feasible implementation, the memory test site circuit board 5 sends the voltage data to the first MCU of the voltage and current measurement circuit board 4 through the first board-to-board connector, and the first MCU obtains the voltage measurement result based on the voltage data.

[0099] The memory test site circuit board 5 sends the current data to the analog-to-digital converter ADC through the first board-to-board connector, the analog-to-digital converter ADC performs current sampling and sends the obtained sampling current to the first MCU, and the first MCU calculates the current measurement result based on the sampling current.

[0100] In the embodiment of the application, the first MCU is electrically connected to the memory test site circuit board 5 through the first board-to-board connector, for example, the first MCU is electrically connected to the memory circuit of each memory particle test station in the memory test site circuit board 5 through the first board-to-board connector. The memory circuit sends the voltage data to the first MCU through the first board-to-board connector, and the first MCU obtains the voltage measurement result based on the voltage data. Specifically, the first MCU can directly read the monitored voltage data to obtain the voltage measurement result, and the accuracy of the voltage measurement result is 0.1 mV.

[0101] The analog-to-digital converter ADC is electrically connected to the first MCU, the memory circuit sends the current data to the analog-to-digital converter ADC, the analog-to-digital converter ADC performs current sampling to obtain the sampling current, and sends the obtained sampling current to the first MCU, and the first MCU directly calculates the current measurement result based on the sampling current. The analog-to-digital converter ADC can be an ADC7124 chip, and a 24-bit sigma-delta analog-to-digital converter ADC is used, so that the accuracy of the current measurement result can reach 0.001 mA.

[0102] The first crimp connector, the second crimp connector, and the first board-to-board connector all include a unified signal pin definition from top to bottom, and the voltage measurement result and the current measurement result are transmitted to the BMC on the peripheral management interface board 6 through the signal pins on the connector, and are read and analyzed by the BMC. The voltage and current results are transmitted to the BMC in real time to realize continuous online current and voltage monitoring.

[0103] The embodiment integrates 24-bit high-precision ADC chips and 16-bit DAC chips on the B2 board, collects the current of the current of each to-be-tested chip (a single tester can support 32 chips), and covers the measurement of four groups of currents of LPDDR5 and three groups of currents of LPDDR4 through bidirectional accurate measurement of the voltage and current signals of the LPDDR chip. Figure 8 As shown in the following table, Figure 8 For the four groups of currents of LPDDR5, that is, the experimental data of measuring the currents and voltages of chips 1-4 by using voltages of types VDD1, VDD2H, VDD2L and VDDQ, Figure 8 In the experimental data, whether anchor load 1 or anchor load 2 is used, the error rate of chips 1-4 measured under each voltage type is less than 1.5%, and the error rate of the memory tester in the embodiment is less than or equal to 1.5%, thereby improving the accuracy of current and voltage measurement. % are less than 1.5%, and the error rate of the memory tester in the embodiment is less than or equal to 1.5%, thereby improving the accuracy of current and voltage measurement.

[0104] In a possible implementation, the memory test site circuit board 5 is provided with an LED double-color lamp.

[0105] The BMC obtains the test case result corresponding to the to-be-tested chip and controls the LED double-color lamp based on the test case result.

[0106] In the embodiment, the memory test site circuit board 5 is provided with an LED double-color lamp, the LED double-color lamp is electrically connected to the IO pin of the BMC through a GPIO (General Purpose Input / Output) circuit, the BMC can obtain the test case result corresponding to the to-be-tested chip (memory particle), and control the LED double-color lamp based on the test case result, so as to display the test result of each LPDDR chip in real time through the form of lighting of different colors of the LED, for example, control the LED double-color lamp to light green when the test case result is test passed, and control the LED double-color lamp to light red when the test case result is test failed, so as to realize rapid chip performance chip classification identification.

[0107] In a possible implementation, the network switch chip is provided with at least eight first PHY chips, the switch circuit board 3 is provided with a second PHY chip and an RJ45 interface, the first PHY chip is electrically connected to the second PHY chip, and the second PHY chip is electrically connected to the RJ45 interface.

[0108] Each memory test site circuit board 5 sends test data to the voltage and current measurement circuit board 4 through the first board-to-board connector; and the voltage and current measurement circuit board 4 sends test data to the external device management interface board 6 through the first crimp connector.

[0109] The peripheral management interface board 6 sends the test data to the corresponding first PHY chip in the network switch chip through the second crimp connector, each first PHY chip forwards the test data to the second PHY chip, and the second PHY chip sends the test data to the corresponding host computer of the memory tester through the RJ45 interface.

[0110] In the embodiment, the network switch chip is provided with at least 8 first PHY chips (Physical Layer Chip, physical layer chip). Generally, the first PHY chip corresponds to the memory test site circuit board 5 one by one. When the memory tester is provided with 8 memory test site circuit boards 5, the first PHY chip is 8.

[0111] The switch circuit board 3 is provided with a second PHY chip and an RJ45 interface. The first PHY chip is electrically connected with the second PHY chip, and the second PHY chip is electrically connected with the RJ45 interface, thereby realizing the data exchange mode of 8-in-1-out.

[0112] Specifically, when the 8 memory test site circuit boards 5 are tested at the same time, the 8 memory test site circuit boards 5 send the test data to the corresponding voltage and current test circuit board 4 through the first board-to-board connector; each voltage and current test circuit board 4 sends the test data to the corresponding peripheral management interface board 6 through the first crimp connector; each peripheral management interface board 6 sends the test data to the corresponding first PHY chip in the network switch chip through the second crimp connector. Each first PHY chip forwards the test data to the second PHY chip, thereby realizing the data exchange mode of 8-in-1-out. Then, the second PHY chip sends the test data to the corresponding host computer of the memory tester through the RJ45 interface.

[0113] In a feasible implementation, the memory test site circuit board 5 is provided with a power button PWR_button and a reset button SYS_BUTTON.

[0114] The power button is electrically connected with the test machine panel circuit board in sequence through the first board-to-board connector, the first crimp connector and the second crimp connector, and the reset button is electrically connected with the first switch power supply chip in the test machine panel circuit board in sequence through the first board-to-board connector, the first crimp connector and the second crimp connector.

[0115] The first switching power chip generates corresponding LED instructions and power-on / power-off instructions according to the control signal of the power button, lights up the corresponding power-on / power-off LED indicator in the memory tester based on the LED instructions, and controls the corresponding memory test site circuit board 5 to perform power-on / power-off operation based on the power-on / power-off instructions. The first switching power chip generates corresponding LED instructions and reset instructions according to the control signal of the reset button, lights up the corresponding reset LED indicator in the memory tester based on the LED instructions, and controls the corresponding memory test site circuit board 5 to perform reset operation based on the reset instructions. By electrically connecting the power button and the reset button to the test machine panel circuit board respectively, the test personnel can perform power-on, power-off or reset operation on each memory test site circuit board 5 through the test machine panel circuit board.

[0116] As shown in Figure 2 Figure 2 The current structure diagram corresponding to the power button is shown in FIG. 6. The PWR_BTN can be a power button in any memory test site circuit board 5, that is, the current structure corresponding to the power button in each memory test site circuit board 5 is similar, and the current structure corresponding to the reset button in each memory test site circuit board 5 is similar to the current structure corresponding to the power button. Only the power button needs to be replaced with the reset button.

[0117] The switch circuit board 3 further includes a multi-channel analog switch chip CH444G, and the peripheral management interface board 6 is provided with a liquid crystal digital tube. When receiving the display signal corresponding to the liquid crystal digital tube, the peripheral management interface board 6 sends the display signal to the switch circuit board 3 through the second crimping connector, the second MCU of the switch circuit board 3 generates a control signal corresponding to the display signal, and sends the control signal to the multi-channel analog switch chip CH444G. The multi-channel analog switch chip controls the data channel corresponding to the display signal and the common output end to be conductive based on the control signal, so as to transmit the to-be-displayed data corresponding to the display signal to the corresponding display of the memory tester for display.

[0118] ​In the embodiment of the present application, the peripheral management interface board 6 is provided with a liquid crystal display tube for triggering the display signal (VGA CRT) of each memory test site circuit board 5, and the second MCU of the switch circuit board 3 generates a 2-bit control signal (NI1, NI0). For example, the user presses the button of "2" (corresponding to the second memory test site circuit board 5 VGA CRT2) on the liquid crystal display tube, and the control signal generated by the MCU of the switch circuit board 3 is NI1=0, NI0=1. The MCU of the switch circuit board 3 sends the control signal to the multi-channel analog switch chip CH444G, and at the same time, the three groups (R, G, B) of internal analog switches of the chip are synchronously actuated to connect the input (data channel) of the first channel (corresponding to VGA CRT2) with the common output terminal, so that the analog RGB signal generated by the VGA CRT2 of the second memory test site circuit board 5 is transmitted to the VGA output interface of the common output terminal through the CH444G. Then, the analog RGB signal is matched through a 75-ohm resistor and transmitted to the display through the VGA cable, so that the user can view the data of the memory test site circuit board 5 through the display. Through the multi-channel analog switch chip, the user can conveniently view the test conditions of different memory test site circuit boards 5 and conveniently perform real-time monitoring and site maintenance of SLT testing.

[0119] As shown in Figure 3 , the CRT1-CRT4 in the figure correspond to four memory test site circuit boards 5, the pins 3-7 of the CH444G correspond to one type of data, and the pins 10-13 correspond to another type of data. Then, according to the type of data to be displayed, a plurality of Figure 3 display circuits shown in the figure can be set, and similar display circuits can also be set for the other four memory test site circuit boards 5.

[0120] In a feasible implementation manner, the BIOS read-write firmware includes a first BIOS flash memory chip provided with an ATE test mode and a second BIOS flash memory chip provided with an SLT test mode;

[0121] When the first BIOS flash memory chip performs chip testing on the to-be-tested chip, the target BMC corresponding to the to-be-tested chip monitors the BIOS working state data corresponding to the first BIOS flash memory chip in real time;

[0122] If the BIOS working state data is abnormal, the target BMC controls the target memory test site circuit board 5 corresponding to the to-be-tested chip to restart;

[0123] When the target memory test site circuit board 5 completes the restart, the target BMC controls the second BIOS flash memory chip corresponding to the to-be-tested chip to start, so as to perform chip testing on the to-be-tested chip.

[0124] In this embodiment, the BIOS read-write firmware includes a first BIOS flash chip provided with an ATE (Automatic Test Equipment) test mode and a second BIOS flash chip provided with an SLT (System Level Test) test mode.

[0125] When the first BIOS flash chip performs chip testing on the to-be-tested chip, i.e., the first BIOS flash chip of the target memory test site circuit board 5 to which the to-be-tested chip belongs determines to run, the ATE test is performed on the to-be-tested chip, at this time, the target BMC corresponding to the to-be-tested chip monitors the BIOS working state data corresponding to the first BIOS flash chip in real time, the target BMC is a BMC in communication connection with the target memory test site circuit board 5, the target BMC determines whether there is a BIOS exception according to the BIOS working state data acquired in real time, if there is a BIOS exception, i.e., the BIOS working state data is abnormal, the target BMC performs switching operation of the test mode, the target BMC controls the target memory test site circuit board 5 corresponding to the to-be-tested chip to restart, specifically, the target BMC issues a restart instruction to the target memory test site circuit board 5, the CPU of the target memory test site circuit board 5 is powered off and shut down, and is restarted after being shut down, when the CPU starts and the target memory test site circuit board 5 is restarted, the target BMC performs test mode switching through IIC bus switching, and controls the second BIOS flash chip of the target memory test site circuit board 5 to start, so as to perform chip testing, i.e., SLT test, on the to-be-tested chip.

[0126] It should be noted that when the to-be-tested chip is subjected to SLT test, the target BMC can also monitor the corresponding second BIOS flash chip in real time, so as to perform test mode switching when the second BIOS flash chip is abnormal, the switching process is similar to the above process, and will not be described herein.

[0127] In a feasible implementation, when the test mode switching instruction is received, the target BMC determines the target BIOS flash chip based on the current test mode of the to-be-tested chip, among the first BIOS flash chip and the second BIOS flash chip;

[0128] The target BMC controls the target memory test site circuit board 5 corresponding to the to-be-tested chip to restart;

[0129] When the target memory test site circuit board 5 is restarted, the target BMC controls the target BIOS flash chip to start, so as to perform chip testing on the to-be-tested chip.

[0130] In the embodiments of the present application, the test mode can also be actively switched, for example, a test mode switching instruction is triggered to the target BMC through the corresponding case, when the test mode switching instruction is received, the target BMC determines the target BIOS flash memory chip based on the current test mode of the chip to be tested, for example, if the current test mode is the ATE test mode, the target BIOS flash memory chip is determined as the second BIOS flash memory chip, and if the current test mode is the SLT test mode, the target BIOS flash memory chip is determined as the first BIOS flash memory chip.

[0131] After obtaining the target BIOS flash memory chip, the target BMC controls the target memory test site circuit board 5 corresponding to the chip to be tested to restart, specifically, the target BMC issues a restart instruction to the target memory test site circuit board 5, the CPU of the target memory test site circuit board 5 is powered off and shut down, and is restarted after shutdown, when the CPU startup is completed, that is, the target memory test site circuit board 5 is restarted, the target BMC switches the test mode through the IIC bus, and the target BMC controls the target BIOS flash memory chip to start to test the chip to be tested, thereby actively switching the test mode.

[0132] In a feasible implementation, the memory tester further comprises a second switching power supply chip.

[0133] As shown in Figure 4 , the input pin VIN of the second switching power supply chip is electrically connected with the input power supply; the positive electrode of the filter capacitor is electrically connected with the input pin VIN, and the negative electrode is grounded;

[0134] As shown in Figure 4 , the filter capacitor can include a first filter capacitor C331, a second filter capacitor C332, a third filter capacitor C333, and a fourth filter capacitor C334. The positive electrode of the first filter capacitor C331 is electrically connected with the input pin VIN, and the negative electrode is grounded; the positive electrode of the second filter capacitor C332 is electrically connected with the input pin VIN, and the negative electrode is grounded; the positive electrode of the third filter capacitor C333 is electrically connected with the input pin VIN, and the negative electrode is grounded; the positive electrode of the fourth filter capacitor C334 is electrically connected with the input pin VIN, and the negative electrode is grounded.

[0135] The input power supply is a +5V power supply DDR_+5V, and the corresponding input current Irms can be 1A. The first filter capacitor C331, the second filter capacitor C332, the third filter capacitor C333, and the fourth filter capacitor C334 are all capacitors of 22μF / 10V, which are used to filter the input power supply. The input pin VIN includes the VIN1 pin and the VIN2 pin of the second switching power supply chip.

[0136] As shown in Figure 4As shown in the figure, one end of the first resistor R717 is electrically connected with the enable input end, and the other end is electrically connected with the enable pin EN of the second switching power supply chip; one end of the second resistor R367 is electrically connected with the enable pin EN of the second switching power supply chip, and the other end is grounded; the positive electrode of the enable capacitor is electrically connected with the enable pin EN of the second switching power supply chip, and the negative electrode is grounded, so as to generate the enable signal of the second switching power supply chip through the signal of the enable input end via the first resistor R717 and the second resistor R367 to turn on the second switching power supply chip. The resistance value of the first resistor R717 can be 15KΩ, and the resistance value of the second resistor R367 can be 1MΩ.

[0137] As shown in the figure, Figure 4 the start mode pin MODE of the second switching power supply chip is electrically connected with the input power supply via the first mode resistor R718, one end of the second mode resistor R720 is electrically connected with the start mode pin MODE, and the other end is grounded; the resistance value of the first mode resistor R718 can be 100KΩ, and the resistance value of the second mode resistor R720 can be 100KΩ.

[0138] As shown in the figure, Figure 4 the switch frequency pin FSEL (Frequency Select) of the second switching power supply chip is electrically connected with the input power supply via the first working frequency resistor R722, one end of the second working frequency resistor R724 is electrically connected with the start mode pin MODE, and the other end is grounded; the resistance value of the first working frequency resistor R722 can be 100KΩ, and the resistance value of the second working frequency resistor R724 can be 100KΩ.

[0139] In this embodiment, the second switching power supply chip can enter the forced PWM (Pulse Width Modulation) mode based on the start mode pin MODE, and work at a frequency of 2.25MHz based on the switch frequency pin FSEL.

[0140] The positive electrode of the conversion capacitor is electrically connected with the switch control pin SW of the second switching power supply chip via the inductor L7, and the positive electrode of the conversion capacitor is electrically connected with the target voltage setting end, and the negative electrode is grounded.

[0141] Specifically, as shown in the figure, Figure 4As shown, the conversion capacitors include a first conversion capacitor C336, a second conversion capacitor C337, a third conversion capacitor C338, and a fourth conversion capacitor C339. The positive poles of the first conversion capacitor C336, the second conversion capacitor C337, the third conversion capacitor C338, and the fourth conversion capacitor C339 are electrically connected to the switch control pin SW and the target voltage setting terminal, respectively. The first conversion capacitor C336 is a 0.1 μF / 10 V capacitor, and the second conversion capacitor C337, the third conversion capacitor C338, and the fourth conversion capacitor C339 are all 22 μF / 10 V capacitors.

[0142] As shown in FIG. 6, the voltage detection pin VOSNS of the second switch power supply chip is electrically connected to the positive poles of the first conversion capacitor C336, the second conversion capacitor C337, the third conversion capacitor C338, and the fourth conversion capacitor C339, respectively. Figure 4

[0143] As shown in FIG. 6, the output pin SCL of the second switch power supply chip outputs the output voltage of the second switch power supply chip through the output resistor R370. Figure 4

[0144] As shown in FIG. 6, the output pin SCL is electrically connected to the resistor R371, and the SDA pin of the second switch power supply chip is electrically connected to the resistor R372 and the resistor R373, respectively. Figure 4

[0145] As shown in FIG. 6, the PG pin of the second switch power supply chip is grounded through the resistor R719, and the resistance value of the resistor R719 can be 10 KΩ. Figure 4

[0146] As shown in FIG. 6, the COMP (Compensation) pin of the second switch power supply chip is electrically connected to the feedback loop. Specifically, the positive pole of the first feedback capacitor C340 is electrically connected to the COMP pin, and the negative pole is grounded through the feedback resistor R369. The positive pole of the second feedback capacitor C341 is electrically connected to the COMP pin, and the negative pole is grounded. The first feedback capacitor C340 is a 0.01 μF / 25 V capacitor, and the second feedback capacitor C341 is a 10 pF / 50 V capacitor. Figure 6

[0147] As shown in FIG. 6, the COMP (Compensation) pin of the second switch power supply chip is electrically connected to the feedback loop. Specifically, the positive pole of the first feedback capacitor C340 is electrically connected to the COMP pin, and the negative pole is grounded through the feedback resistor R369. The positive pole of the second feedback capacitor C341 is electrically connected to the COMP pin, and the negative pole is grounded. The first feedback capacitor C340 is a 0.01 μF / 25 V capacitor, and the second feedback capacitor C341 is a 10 pF / 50 V capacitor. Figure 6 ​​​​​As shown, the VSEL (Voltage Select) pin of the second switching power supply chip is connected with the input power supply through the first selection resistor R721, and the VSEL pin is grounded through the second selection resistor R723, wherein the resistance value of the first selection resistor R721 can be 100KΩ, and the resistance value of the second selection resistor R723 can be 6.19KΩ.

[0148] In the embodiment, the main controller of the memory tester sets the required output voltage value of the second switching power supply chip through the I2C bus. The voltage value 0.5V of the JEDEC standard LPDDR5 VDDQ is set as the voltage default value (I2C register address: 0X43), and the I2C register addresses of other different voltages are set as the programmable debug values of the second switching power supply chip. At the same time, the internal error amplifier of the second switching power supply chip compares the output voltage with the target value of the target voltage setting end set by I2C, dynamically adjusts the switching duty cycle, and finally outputs the accurate and stable +VDDQ_PWR. The BMC and the second switching power supply chip are connected through the communication protocol to issue voltage adjustment instructions and receive dynamic feedback power values.

[0149] In the embodiment, the memory tester can support dual memory power supply testing through the second switching power supply chip, wherein a group of chips are provided with 3 groups / 4 groups of standard voltages of LPDDR4 / 5 according to the JEDEC standard, and the standard voltages can be adjusted in the range of ±30%, so as to perform extreme environment stress testing on the chips by adjusting the voltages.

[0150] In a feasible implementation, the test instruction is received, the BMC sends the test instruction to the voltage and current test circuit board 4 through the first crimping connector; the voltage and current test circuit board 4 sends the test instruction to the memory test site circuit board 5 through the first board-to-board connector; the memory test site circuit board 5 starts the CPU based on the test instruction, and the CPU executes the test corresponding to the test instruction based on the control BIOS.

[0151] In the embodiment, the host computer (control PC) corresponding to the memory tester sends a test instruction to the BMC of the B3 board. When receiving the test instruction, the BMC sends the test instruction to the voltage and current measurement circuit board 4 through the first crimp connector. The voltage and current measurement circuit board 4 sends the test instruction to the memory test site circuit board 5 through the first board-to-board connector. At this time, the CPU of the B1 board starts to power on and prepares to perform memory test training on the 4PCS test chip. After the CPU is powered on, the BIOS read-write firmware of the B1 board controls the execution of memory training (memory training) \ RMT Eye Diagram (memory block margin eye diagram diagnosis) \ Function Test (function test). The B1 board sends the test result to the B2 board through the first board-to-board connector. The B2 board sends the test result to the BMC of the B3 board through the first crimp connector. The BMC sends the test result to the host computer through the switch system of the B4 board.

[0152] It should be noted that after the ATE test is completed, the qualified memory particles can be selected for BTT test again, that is, the BMC sends the BTT test instruction to the CPU of the B1 board. The B1 board executes the system-level SLT test process under the operating system platform (such as UEFI Shell) and feeds back the corresponding test result to the BMC. The BMC sends the test result to the host computer through the switch system of the B4 board.

[0153] It can be understood that the memory tester of the embodiment establishes a set of IDD current measurement algorithms based on the JEDEC standard. By integrating into the ATE+SLT test software, the current symbols such as Idd0 / 2 / 3 / 4 / 5 of LPDDR5 / 4 can be measured at the level of milliamperes. The test algorithms of the memory tester are shown in Table 1.

[0154] Table 1: Test algorithm

[0155]

[0156] In the embodiment, each IDD current measurement algorithm based on the JEDEC standard in Table 1 can be used to test the memory particles to be tested, so as to measure the current symbols such as Idd0 / 2 / 3 / 4 / 5 of LPDDR5 / 4 at the level of milliamperes.

[0157] Further, in another possible implementation, the first memory test site circuit board in each memory test site circuit board receives a first memory test instruction, and the second memory test site circuit board in each memory test site circuit board receives a second memory test instruction.

[0158] The first memory test site circuit board controls power-on of a CPU of the first memory test site circuit board, and BIOS read-write firmware of the first memory test site circuit board starts a test case corresponding to the first memory test instruction, so as to perform memory test on a to-be-tested chip corresponding to the first memory test site circuit board based on the test case corresponding to the first memory test instruction.

[0159] The second memory test site circuit board controls power-on of a CPU of the second memory test site circuit board, and BIOS read-write firmware of the second memory test site circuit board starts a test case corresponding to the second memory test instruction, so as to perform memory test on a to-be-tested chip corresponding to the second memory test site circuit board based on the test case corresponding to the second memory test instruction.

[0160] In the embodiment, the host computer can also issue different test instructions to the eight memory test site circuit boards. For example, the first memory test instruction is issued to the first memory test site circuit board in the memory test site circuit boards, and the second memory test site circuit board receives the first memory test instruction. The first memory test site circuit board can include one or more memory test site circuit boards, and the second memory test site circuit board also includes one or more memory test site circuit boards. Of course, as shown in Figure 9 different test instructions can also be issued to each memory test site circuit board respectively, for example, different test instructions are issued to each memory test site circuit board through the test instruction workstation or the host computer.

[0161] The CPU of the first memory test site circuit board is powered on, and the BIOS read-write firmware of the first memory test site circuit board starts a test case corresponding to the first memory test instruction, so as to perform memory test on a to-be-tested chip corresponding to the first memory test site circuit board based on the test case corresponding to the first memory test instruction.

[0162] The CPU of the second memory test site circuit board is powered on, and the BIOS read-write firmware of the second memory test site circuit board starts a test case corresponding to the second memory test instruction, so as to perform memory test on a to-be-tested chip corresponding to the second memory test site circuit board based on the test case corresponding to the second memory test instruction.

[0163] In the embodiment, different test instructions are issued to different memory test site circuit boards, so that asynchronous test can be performed on the to-be-tested chips on the memory test site circuit boards. As shown in Figure 9 The first test site performs test on the four to-be-tested chips thereon through the fifth test case, the second test site performs test on the four to-be-tested chips thereon through the sixth test case, the third to seventh test sites can perform test on the to-be-tested chips through the eighth to twelfth test cases respectively, and the eighth test site performs test on the four to-be-tested chips thereon through the seventh test case. The asynchronous test further improves the memory test efficiency.

[0164] The memory tester of the present application is fixedly connected with the memory test site circuit board 5, the voltage and current test circuit board 4, the peripheral management interface board 6, the switch circuit board 3 and the CRPS power conversion board 2 through the connector. The memory test can be compatible with at least two generations of LPDDR4 / 5 / 5X by quickly replacing the memory test site circuit board 5, can support four kinds of packaging of SDP (Single Die Package), DDP (Dual Die Package), QDP (Quad Die Package) and ODP (Octa Die Package), and can support 1-Rank / 2-Rank configuration. The test cost of the memory tester is reduced by integrating the SoC small system on chip, and the compatibility and hardware flexibility of the memory tester are improved.

[0165] The memory tester of the present embodiment improves the current test precision of LPDDR4 / 5 to 0.001 mA level by using a 24-bit sigma-delta type analog-to-digital converter ADC, and improves the voltage adjustment precision of LPDDR4 / 5 to ±5 mV by using a programmable power management chip.

[0166] The present application also provides a memory test method applied to the memory tester in the above embodiments, which refers to Figure 5 , Figure 5 The flowchart provided by an embodiment of the memory test method of the present application.

[0167] The memory test method comprises steps S110-S130.

[0168] In step S110, when the target memory test site circuit board in each memory test site circuit board receives a first test instruction, the target memory test site circuit board controls the power-on of the corresponding CPU.

[0169] In step S120, the BIOS corresponding to the target memory test site circuit board reads and writes the first test case of the ATE test corresponding to the first test instruction to perform ATE test on the first to-be-tested chip corresponding to the target memory test site circuit board based on the first test case.

[0170] In step S130, if the ATE test of the first to-be-tested chip is passed, the BIOS corresponding to the target memory test site circuit board starts the second test case of the SLT test to perform SLT test on the first to-be-tested chip based on the second test case.

[0171] In the present embodiment, as Figure 6As shown, the eight memory test station circuit boards are designated as the first test station, the second test station, and so on up to the eighth test station. The host computer corresponding to the memory tester can send test commands (IPMI test commands) to each memory test station circuit board, specifically to the BMC corresponding to the memory test station circuit board. For each target memory test station circuit board, the target BMC corresponding to the target memory test station circuit board sends the test command to the voltage and current measurement circuit board corresponding to the target memory test station circuit board through the first crimp connector. The voltage and current measurement circuit board then sends the test command to the target memory test station circuit board through the first board-to-board connector.

[0172] When the target memory test station circuit board receives the first test command, it controls the CPU corresponding to the target memory test station circuit board to power on, and prepares to perform memory testing on the first chip under test. The first chip under test includes four chips under test fixed to four memory chip test stations on the target memory test station circuit board.

[0173] After the CPU powers on, the BIOS read / write firmware corresponding to the target memory test site circuit board initiates the first test instruction corresponding to the first test case of the ATE test. Based on the first test case, the first chip under test corresponding to the target memory test site circuit board is subjected to ATE testing. Specifically, the BIOS read / write firmware executes memory training\RMT Eye Diagram\Function Test to perform ATE testing on the first chip under test. The ATE test specifically includes memory training, eye diagram data analysis, and functional testing.

[0174] When the ATE test is completed, the target memory test station circuit board determines whether the ATE test has passed based on the ATE test results. If the ATE test has passed, the SLT test can continue to be executed. If the test has failed, the target memory test station circuit board sends a test failure feedback message to the host computer. The host computer can then send the test command to the target memory test station circuit board again based on the feedback message.

[0175] like Figure 6 As shown, if the ATE test is passed, the BIOS corresponding to the target memory test station circuit board starts the second test case for the SLT test, and performs the SLT test on the first chip under test based on the second test case. When the SLT test is completed, the target memory test station circuit board determines whether the SLT test has passed based on the SLT test result. If the SLT test has passed, the test ends and the test completion information is fed back to the host computer. If the SLT test has failed, the second test case is executed again to perform the SLT test on the first chip under test.

[0176] It should be noted that after the SLT test is passed, the target memory test site circuit board sends the test result to the corresponding B2 board through the first board-to-board connector, the B2 board sends the test result to the target BMC through the first crimp connector, the target BMC sends the test result to the host computer through the switch system of the B4 board, and the test result includes the ATE test result and the SLT test result.

[0177] In a feasible implementation, the BIOS read-write firmware includes a first BIOS flash memory chip provided with an ATE test mode and a second BIOS flash memory chip provided with an SLT test mode; the memory test method can further include steps A110-A130:

[0178] In step A110, when the first BIOS flash memory chip is used to perform ATE test on the first to-be-tested chip, the target BMC of the target memory test site circuit board is used to monitor the BIOS working state data of the first BIOS flash memory chip in real time.

[0179] In step A120, if the BIOS working state data is abnormal, the target BMC is used to control the target memory test site circuit board to restart.

[0180] In step A130, when the target memory test site circuit board is restarted, the target BMC is used to control the second BIOS flash memory chip corresponding to the first to-be-tested chip to perform SLT test on the first to-be-tested chip.

[0181] In this embodiment, the BIOS read-write firmware includes a first BIOS flash memory chip provided with an ATE test mode and a second BIOS flash memory chip provided with an SLT test mode.

[0182] When the first to-be-tested chip is tested by ATE, the CPU starts the first test case in the first BIOS flash memory chip to perform test, and the target BMC can monitor the BIOS working state data of the first BIOS flash memory chip in real time during the test; whether there is BIOS abnormality is determined according to the BIOS working state data acquired in real time.

[0183] If there is BIOS abnormality, that is, the BIOS working state data is abnormal, the target BMC is used to control the target memory test site circuit board to restart; specifically, the target BMC issues a restart instruction to the target memory test site circuit board 5, the CPU of the target memory test site circuit board is powered off and shut down, and is restarted after being shut down.

[0184] When the CPU startup is completed, i.e., the target memory test site circuit board restart is completed, the target BMC switches the test mode through the IIC bus switching, controls the second BIOS flash chip of the target memory test site circuit board to start, so as to perform chip test, i.e., SLT test, on the chip to be tested. Thus, when the ATE test is abnormal, the SLT test can be switched to, and the efficiency of the memory test is further improved.

[0185] It should be noted that when the SLT test is performed on the chip to be tested, the target BMC can also monitor the corresponding second BIOS flash chip in real time, so as to switch the test mode when the second BIOS flash chip is abnormal. The switching process is similar to the above process, and will not be described here.

[0186] In a feasible implementation, the memory test method can further include steps A140-A160.

[0187] When the test mode switching instruction is received, the target BMC of the target memory test site circuit board determines the target BIOS flash chip based on the current test mode of the first chip to be tested, in the first BIOS flash chip and the second BIOS flash chip.

[0188] The target BMC controls the target memory test site circuit board to restart.

[0189] When the target memory test site circuit board restart is completed, the target BMC controls the target BIOS flash chip to perform chip test on the first chip to be tested.

[0190] In the embodiment of the application, when the ATE test or the SLT test is performed on the first chip to be tested, the test mode can also be actively switched, for example, the test mode switching instruction is triggered to the target BMC through the corresponding key.

[0191] When the test mode switching instruction is received, the target BMC determines the target BIOS flash chip based on the current test mode of the chip to be tested, in the first BIOS flash chip and the second BIOS flash chip. For example, when the current test mode is the ATE test mode, the target BIOS flash chip is determined as the second BIOS flash chip, and when the current test mode is the SLT test mode, the target BIOS flash chip is determined as the first BIOS flash chip.

[0192] After obtaining the target BIOS flash chip, the target BMC controls the target memory test site circuit board corresponding to the to-be-tested chip to restart, specifically, the target BMC issues a restart instruction to the target memory test site circuit board, the CPU of the target memory test site circuit board is powered off and shut down, and is restarted after being shut down, when the CPU starts and the target memory test site circuit board is restarted, the target BMC switches the test mode through the IIC bus, and the target BMC controls the target BIOS flash chip to start, so as to perform chip testing on the to-be-tested chip, thereby actively switching the test mode.

[0193] In a feasible implementation, the memory test method can further include steps B110-B130.

[0194] In step B110, the first memory test site circuit board in each memory test site circuit board receives a second test instruction, and the second memory test site circuit board in each memory test site circuit board receives a third test instruction.

[0195] In step B120, the first memory test site circuit board controls the CPU of the first memory test site circuit board to be powered on, and the BIOS read-write firmware of the first memory test site circuit board starts a third test case corresponding to the second test instruction, so as to perform memory testing on the second to-be-tested chip corresponding to the first memory test site circuit board based on the third test case.

[0196] In step B130, the second memory test site circuit board controls the CPU of the second memory test site circuit board to be powered on, and the BIOS read-write firmware of the second memory test site circuit board starts a fourth test case corresponding to the third test instruction, so as to perform memory testing on the third to-be-tested chip corresponding to the second memory test site circuit board based on the fourth test case.

[0197] In this embodiment, the host computer can also issue different test instructions to the eight memory test site circuit boards, for example, the first memory test site circuit board in the memory test site circuit boards receives a second test instruction, and the second memory test site circuit board receives a third test instruction. The first memory test site circuit board can include one or more memory test site circuit boards, and the second memory test site circuit board also includes one or more memory test site circuit boards. Of course, as shown in the figure, different test instructions can also be issued to each memory test site circuit board, for example, different test instructions are issued to each memory test site circuit board through the test instruction workstation or the host computer. Figure 7

[0198] ​The CPU of the first memory test site circuit board is powered on, the BIOS of the first memory test site circuit board reads and writes firmware to start a third test case corresponding to a second test instruction, and the second test chip corresponding to the first memory test site circuit board is tested based on the third test case.

[0199] The CPU of the second memory test site circuit board is powered on, the BIOS of the second memory test site circuit board reads and writes firmware to start a fourth test case corresponding to a third test instruction, and the third test chip corresponding to the second memory test site circuit board is tested based on the fourth test case.

[0200] In this embodiment, different test instructions are issued to different memory test site circuit boards, so that asynchronous testing of the test chips on the memory test site circuit boards can be realized, for example, ​ As shown in the figure, the first test site tests four test chips on it through a fifth test case, the second test site tests four test chips on it through a sixth test case, the third to seventh test sites can test test chips through an eighth to twelfth test case respectively, and the eighth test site tests four test chips on it through a seventh test case. Through asynchronous testing, the memory test efficiency is further improved.

[0201] In a feasible implementation, the memory test method can further include steps C110-C130:

[0202] When the ATE test of the first test chip is completed, the BMC corresponding to the target memory test site circuit board obtains a test result corresponding to the first test case;

[0203] The BMC corresponding to the target memory test site circuit board controls the LED double-color lamp based on the test result.

[0204] In this embodiment, the memory test site circuit board is provided with an LED double-color lamp, and when the ATE test of the first test chip is completed, the target BMC can obtain a test result (ATE test result) corresponding to the current test chip (memory particle), and control the LED double-color lamp based on the test result, so as to display the test result of each LPDDR chip in real time through different color lighting forms of the LED, for example, ​ As shown in the figure, the test result is controlled to light green when the test is passed, and the test result is controlled to light red when the test is failed, so as to realize rapid chip performance chip classification identification.

[0205] It should be noted that when the SLT test is completed, the BMC can also control the LED double-color lamp according to the corresponding test result.

[0206] The memory test method of the embodiment, when the target memory test site circuit board in each memory test site circuit board receives the first test instruction, the target memory test site circuit board is powered on corresponding to the CPU; then the BIOS read-write firmware corresponding to the target memory test site circuit board starts the first test case of the ATE test corresponding to the first test instruction, to perform ATE test on the first to-be-tested chip corresponding to the target memory test site circuit board based on the first test case; then if the ATE test of the first to-be-tested chip passes, the BIOS corresponding to the target memory test site circuit board starts the second test case of the corresponding SLT test, to perform SLT test on the first to-be-tested chip based on the second test case, to realize ATE and SLT dual-mode test of the test chip, and further improve the memory test efficiency.

[0207] The memory test method of the embodiment can realize ATE+SLT dual-mode test of LPDDR memory chip, and the ATE test mode of the embodiment can cover 95% of memory chip defects, while shortening the test time by 30%-50%. The SLT test mode as "checking and supplementing" of the ATE test can further improve the test coverage by 3-5%, thereby realizing ATE and SLT compatible dual-mode test, improving the test efficiency, shortening the test time, and increasing the test coverage.

[0208] It should be noted that the above examples are only used for understanding the present application and do not constitute a limitation on the memory tester of the present application. More forms of simple transformation based on the technical concept are within the protection scope of the present application.

[0209] The above only describes some embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation based on the technical concept of the present application, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A memory tester, characterized in that, The memory tester includes: a memory test station circuit board, a voltage and current measurement circuit board, a peripheral management interface board, a switch circuit board, and a CRPS power conversion board; The memory test station circuit board includes a CPU, a programmable power management chip, a BIOS read / write firmware, and multiple memory chip test stations; the CPU is communicatively connected to the programmable power management chip and the BIOS read / write firmware, wherein the BIOS read / write firmware includes a first BIOS flash memory chip with ATE test mode and a second BIOS flash memory chip with SLT test mode. The voltage and current measurement circuit board includes an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a first MCU, wherein the first MCU is electrically connected to the ADC and the DAC respectively. The peripheral management interface board includes a baseboard management controller (BMC) and a serial communication module, wherein the serial communication module is communicatively connected to the baseboard management controller (BMC). The switch circuit board includes a network switch chip and a second MCU, and the network switch chip is electrically connected to the second MCU. The memory test station circuit board is fixedly connected to the voltage and current measurement circuit board via the first board-to-board connector; the voltage and current measurement circuit board is fixedly connected to the peripheral management interface board via the first crimp connector; the peripheral management interface board is fixedly connected to the switch circuit board via the second crimp connector; the switch circuit board is fixedly connected to the CRPS power conversion board via the second board-to-board connector. The memory test station circuit board includes at least 8 components, the voltage and current measurement circuit board includes at least 4 components, and the peripheral management interface board includes at least 4 components. When the target memory test station circuit board in each memory test station circuit board receives the first test instruction, it controls the CPU corresponding to the target memory test station circuit board to power on; the BIOS read / write firmware corresponding to the target memory test station circuit board starts the first test case corresponding to the first test instruction for ATE test, so as to perform ATE test on the first chip under test corresponding to the target memory test station circuit board based on the first test case; if the ATE test of the first chip under test passes, the BIOS corresponding to the target memory test station circuit board starts the second test case corresponding to the SLT test, so as to perform SLT test on the first chip under test based on the second test case; Specifically, when performing ATE testing on the first chip under test based on the first BIOS flash memory chip, the target BMC corresponding to the target memory test station circuit board monitors the BIOS operating status data of the first BIOS flash memory chip in real time; if the BIOS operating status data is abnormal, the target BMC controls the target memory test station circuit board to restart; when the target memory test station circuit board has restarted, the target BMC controls the second BIOS flash memory chip corresponding to the first chip under test to perform SLT testing on the first chip under test.

2. The memory tester as described in claim 1, characterized in that, The CRPS power conversion board supplies power to the switch circuit board through the second board-to-board connector. The switch circuit board supplies power to the peripheral management interface board through the second crimp connector. The peripheral management interface board supplies power to the voltage and current measurement circuit board through the first crimp connector. The voltage and current measurement circuit board supplies power to the memory test station circuit board through the first board-to-board connector.

3. The memory tester as described in claim 2, characterized in that, The memory test station circuit board is fixedly mounted above the corresponding voltage and current measurement circuit board via a first board-to-board connector; the voltage and current measurement circuit board is mounted above the corresponding peripheral management interface board via a first crimp connector and is perpendicular to the peripheral management interface board; the peripheral management interface board is mounted above the switch circuit board via a second crimp connector and is perpendicular to the switch circuit board.

4. The memory tester as described in claim 2, characterized in that, The memory test station circuit board is equipped with a power button and a reset button; The power button is electrically connected to the test machine panel circuit board in sequence through the first board-to-board connector, the first crimp connector, and the second crimp connector. The reset button is electrically connected to the first switching power supply chip in the test machine panel circuit board in sequence through the first board-to-board connector, the first crimp connector, and the second crimp connector.

5. The memory tester as described in claim 2, characterized in that, The network switch chip has at least 8 first PHY chips, and the switch circuit board has a second PHY chip and an RJ45 interface. The first PHY chip and the second PHY chip are electrically connected, and the second PHY chip is electrically connected to the RJ45 interface. Each memory test station circuit board sends test data to the voltage and current measurement circuit board via the first board-to-board connector; the voltage and current measurement circuit board sends test data to the peripheral management interface board via the first crimp connector; The peripheral management interface board sends test data to the corresponding first PHY chip in the network switch chip through the second crimp connector. Each first PHY chip forwards the test data to the second PHY chip, and the second PHY chip sends the test data to the host computer corresponding to the memory tester through the RJ45 interface.

6. The memory tester as described in claim 1, characterized in that, The first memory test station circuit board in each memory test station circuit board receives the second test command, and the second memory test station circuit board in each memory test station circuit board receives the third test command; The first memory test station circuit board controls the CPU of the first memory test station circuit board to power on, and the BIOS read / write firmware of the first memory test station circuit board starts the third test case corresponding to the second test instruction, so as to perform memory testing on the second chip under test corresponding to the first memory test station circuit board based on the third test case. The second memory test station circuit board controls the CPU of the second memory test station circuit board to power on, and the BIOS read / write firmware of the second memory test station circuit board starts the fourth test case corresponding to the third test instruction, so as to perform memory testing on the third chip under test corresponding to the second memory test station circuit board based on the fourth test case.

7. The memory tester as described in claim 1, characterized in that, The memory test station circuit board sends voltage data to the first MCU of the voltage and current measurement circuit board through the first board-to-board connector. The first MCU obtains the voltage measurement result based on the voltage data. The memory test station circuit board sends current data to the analog-to-digital converter (ADC) through the first board-to-board connector. The ADC samples the current and sends the sampled current to the first MCU. The first MCU calculates the current measurement result based on the sampled current.

8. The memory tester as described in claim 1, characterized in that, The circuit board of the memory test station is equipped with dual-color LED lights; The BMC obtains the test case results corresponding to the chip under test in the BIOS read / write firmware, and controls the corresponding LED dual-color light based on the test case results.

9. The memory tester as described in any one of claims 1 to 8, characterized in that, The memory tester is also equipped with a second switching power supply chip; The input pin of the second switching power supply chip is electrically connected to the input power supply; the positive terminal of the filter capacitor is electrically connected to the input pin, and the negative terminal is grounded. One end of the first resistor is electrically connected to the enable input terminal, and the other end is electrically connected to the enable pin EN of the second switching power supply chip; one end of the second resistor is electrically connected to the enable pin of the second switching power supply chip, and the other end is grounded; the positive terminal of the enable capacitor is electrically connected to the enable pin of the second switching power supply chip, and the negative terminal is grounded. The startup mode pin of the second switching power supply chip is electrically connected to the input power supply through the first mode resistor; the switching frequency pin of the second switching power supply chip is electrically connected to the input power supply through the first operating frequency resistor. The positive terminal of the conversion capacitor is electrically connected to the switching control pin of the second switching power supply chip through an inductor, and the positive terminal of the conversion capacitor is electrically connected to the target voltage setting terminal, while the negative terminal is grounded.

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