Voltage equalization circuit and energy storage system

Abstract

The invention relates to the technical field of energy storage power supplies, and mainly provides a voltage equalization circuit and an energy storage system, the circuit comprises a driving module, an overvoltage detection module and a CLLC module, the overvoltage detection module and the CLLC module are respectively connected with the driving module, and the overvoltage detection module and the CLLC module are respectively connected with a first bus capacitor and a second bus capacitor. When energy stored in the first bus capacitor and the second bus capacitor rises, in order to avoid the overvoltage risk, the overvoltage detection module detects the first bus voltage and the second bus voltage respectively, and when the voltage difference value between the first bus voltage and the second bus voltage is larger than a voltage threshold value, it is determined that the voltage of the first bus capacitor and the voltage of the second bus capacitor are too high. At the moment, the overvoltage detection module outputs a first control signal to the driving module, so that the driving module drives the CLLC module to start working based on the first control signal, and then the first bus capacitor and the second bus capacitor are controlled to carry out energy transfer, so that the first bus voltage and the second bus voltage are balanced, and the overvoltage condition is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of energy storage power supply, and in particular to a voltage equalization circuit and an energy storage system. BACKGROUND

[0002] In the energy storage power supply, compared with the two-level topology inverter circuit, using the three-level topology inverter circuit to invert the output alternating voltage has many advantages, such as small electromagnetic interference, high input and output compatibility of high and low voltage. However, in practical application, the energy storage power supply may face complex load working conditions, such as driving a load with an RCD absorption circuit, or abnormal situations such as load short circuit, at which time the peak current in the circuit will increase sharply, and if no protection measures are taken, the over-high current will cause damage to the core power devices such as switch tubes and freewheeling tubes, so it is necessary to cut off the driving signal of the power device through the clamp operation to realize the emergency protection of the device. However, when the switch tube and the freewheeling tube in the three-level inverter circuit enter the clamping state, since the inductance current cannot be abruptly changed, the electromagnetic energy stored in the inverter inductance needs to find a release path, at which time the energy will charge the first bus capacitor or the second bus capacitor, thereby causing the voltage across the first bus capacitor or the second bus capacitor to sharply rise, exceeding the rated voltage of the device, resulting in overvoltage of the first bus capacitor or the second bus capacitor. Thus, the service life of the power device is seriously affected, and the device may even be directly damaged, reducing the reliability of the energy storage system. SUMMARY

[0003] The embodiments of the present application provide a voltage equalization circuit and an energy storage system, aiming to solve the problem that in the prior art, when the three-level inverter circuit is clamped, the bus capacitor will be overvoltage, thereby causing the device to be easily damaged, reducing the service life and reliability of the energy storage system.

[0004] To solve the above technical problems, one technical scheme adopted by the embodiments of the present application is to provide a voltage equalization circuit, which comprises an overvoltage detection module, a driving module and a CLLC module. The overvoltage detection module is connected with the driving module, the driving module is connected with the CLLC module, and the overvoltage detection module and the CLLC module are also respectively used to connect the first bus capacitor and the second bus capacitor. The overvoltage detection module is used to detect the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor respectively, and output a first control signal to the driving module when the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold. The drive module is used to output a drive signal to the CLLC module according to the first control signal, so that the CLLC module starts to work based on the drive signal, thereby enabling the CLLC module to automatically balance the first bus voltage and the second bus voltage.

[0005] Optionally, the overvoltage detection module is further configured to output a second control signal to the drive module when the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, so that the drive module stops outputting the drive signal.

[0006] Optionally, the driving module includes a signal generation unit and a driving unit; The signal generation unit is connected to the overvoltage detection module and the drive unit respectively, and the drive unit is connected to the CLLC module; The signal generation unit is configured to, upon receiving the first control signal, output a pulse signal with a preset duty cycle to the driving unit according to the first control signal; and Upon receiving the second control signal, the output of the pulse signal is stopped; The driving unit is configured to, upon receiving a pulse signal with a preset duty cycle, output a corresponding driving signal to the CLLC module according to the duty cycle of the pulse signal, so that the CLLC module starts working based on the driving signal, thereby automatically balancing the first bus voltage and the second bus voltage; and The output drive signal is stopped when the pulse signal is not received, so that the CLLC module stops working.

[0007] Optionally, the signal generation unit includes chip U2, switch Q3, resistor R4, resistor R6 and capacitor C5; The control terminal of the switching transistor Q3 is connected to the overvoltage detection module. The control terminal of the switching transistor Q3 is also grounded through the resistor R6. The first terminal of the switching transistor Q3 is connected to the compensation pin of the chip U2. The second terminal of the switching transistor Q3 is grounded. The reference voltage pin of the chip U2 is connected to the oscillator timing resistor / capacitor pin of the chip U2 through the resistor R4. The oscillator timing resistor / capacitor pin of the chip U2 is grounded through the capacitor C5.

[0008] Optionally, the driving unit includes a half-bridge driving chip U1 and a half-bridge driving chip U4; The input pins of both the half-bridge driver chip U1 and the half-bridge driver chip U4 are connected to the signal generation unit. The output pin of the half-bridge driver chip U1 is connected to the first half-bridge unit of the CLLC module, and the output pin of the half-bridge driver chip U4 is connected to the second half-bridge unit of the CLLC module.

[0009] Optionally, the overvoltage detection module includes a voltage sampling unit and a voltage comparison unit; The voltage sampling unit is connected to the voltage comparison unit, the voltage comparison unit is connected to the driving module, and the voltage sampling unit is also used to connect to the first bus capacitor and the second bus capacitor respectively. The voltage sampling unit is used to collect the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor respectively, and input the collected first bus voltage and second bus voltage to the voltage comparison unit; The voltage comparison unit is used to receive the first bus voltage and the second bus voltage, and outputs a first control signal when the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold; and When the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, a second control signal is output.

[0010] Optionally, the voltage comparison unit includes comparator U5A, comparator U5B, resistor R13, resistor R15, resistor R19, resistor R34 and resistor R36; The first input terminal of comparator U5A is connected to the first output terminal of the voltage sampling unit through resistor R15. The second input terminal of comparator U5A is connected to the second output terminal of the voltage sampling unit through resistor R19. The first input terminal of comparator U5B is connected to the second output terminal of the voltage sampling unit through resistor R34. The second input terminal of comparator U5B is connected to the first output terminal of the voltage sampling unit through resistor R36. The output terminal of comparator U5A is connected to the output terminal of comparator U5B. The output terminal of comparator U5A is also connected to the first power supply through resistor R13. The output terminal of comparator U5A is also connected to the drive module.

[0011] Optionally, the voltage equalization circuit further includes a current detection module; The current detection module is connected to both the CLLC module and the signal generation unit. The current detection module is used to detect the current signal of the CLLC module in real time when the CLLC module is working, and when the current signal is greater than a preset threshold, output a second control signal to the signal generation unit so that the signal generation unit stops outputting the pulse signal.

[0012] Optionally, the current detection module includes a current sampling unit and a current comparison unit; The current sampling unit is connected to the CLLC module and the current comparison unit respectively, and the current comparison unit is connected to the signal generation unit; The current sampling unit is used to collect the current signal of the CLLC module in real time when the CLLC module is working, and output the current signal to the current comparison unit; The current comparison unit is used to receive the current signal and output a second control signal to the signal generation unit when the current signal is greater than a preset threshold, so that the signal generation unit stops outputting the pulse signal.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is to provide an energy storage system, the energy storage system comprising: A three-level inverter circuit, wherein the three-level inverter circuit includes a first bus capacitor and a second bus capacitor; and The voltage equalization circuit described above is connected to the first bus capacitor and the second bus capacitor, respectively.

[0014] Unlike related technologies, this invention provides a voltage balancing circuit and energy storage system. The circuit includes an overvoltage detection module, a drive module, and a CLLC module. The overvoltage detection module is connected to the drive module, and the drive module is connected to the CLLC module. The overvoltage detection module and the CLLC module are also used to connect a first bus capacitor and a second bus capacitor, respectively. When the switching transistor in the three-level inverter circuit is blocked, the energy stored in the first bus capacitor or the second bus capacitor will increase. To avoid the risk of overvoltage in the first bus voltage or the second bus voltage, the overvoltage detection module detects the first bus voltage or the second bus voltage respectively. When the voltage difference between the first bus voltage and the second bus voltage exceeds a voltage threshold, it determines that the voltage of the first bus capacitor or the second bus capacitor is too high. At this time, the overvoltage detection module outputs a first control signal to the drive module, causing the drive module to output a drive signal to the CLLC module based on the first control signal, thereby driving the CLLC module to start working and controlling the energy transfer between the first bus capacitor and the second bus capacitor, thus balancing the voltage of the first bus capacitor and the second bus capacitor. Based on this, by transferring the voltage of one capacitor to another when the voltage of the other capacitor is too high, overvoltage can be avoided, protecting the components in the circuit from damage and thus improving the reliability and safety of the energy storage system. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0016] Figure 1 This is a schematic diagram illustrating an application scenario of an energy storage system provided in an embodiment of the present invention; Figure 2 This is a circuit diagram of a three-level inverter circuit provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a voltage equalization circuit provided in an embodiment of the present invention; Figure 4 This is a circuit diagram of a voltage equalization circuit provided in an embodiment of the present invention; Figure 5 This is a circuit diagram of an overvoltage detection module provided in an embodiment of the present invention; Figure 6 This is a circuit diagram of an overcurrent detection module provided in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] It should be noted that, unless otherwise specified, the various features in the embodiments of the present invention can be combined with each other, and all are within the protection scope of the present invention. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different module division or in a different order than that shown in the device schematic diagram or the flowchart.

[0019] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0020] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of an energy storage system provided in an embodiment of the present invention, such as... Figure 1 As shown, application scenario 1 includes an energy storage system 100, a load 200, and a power supply 300; the energy storage system 100 is connected to both the load 200 and the power supply 300. Wherein, as Figure 1 As shown, the energy storage system 100 further includes a three-level inverter circuit 10, which is connected to the power supply 300 and the load 200 respectively. The three-level inverter circuit 10 is used to receive the power supply voltage output by the power supply 300, and transform the power supply voltage to output a target voltage to the load 200 to supply power to the load 200. In some embodiments, please refer to Figure 2 , Figure 2 This is a circuit diagram of a three-level inverter circuit provided in an embodiment of the present invention, such as... Figure 2As shown, the three-level inverter circuit 10 includes a first bus capacitor CE1, a second bus capacitor CE2, an inverter inductor LD1, a switching bridge arm composed of switching transistors Q1 and Q2, and a freewheeling bridge arm composed of switching transistors Q3 and Q4. When the power supply 300 outputs a power supply voltage, the first bus capacitor CE1 and the second bus capacitor CE2 receive and store the power supply voltage. At this time, the switching bridge arm, the freewheeling bridge arm, and the inverter inductor LD1 start working to transform the voltage stored in the first bus capacitor CE1 (BUS+ to BUSN) and the voltage stored in the second bus capacitor CE2 (BUSN to BUS-), thereby outputting a target voltage to the load 200 (LOAD) to enable the load 200 to start working.

[0021] However, during the power supply to the load 200, if a short circuit or other fault occurs in the load 200, the peak current of the circuit will be large. In this case, to protect the circuit components, the switching bridge arm and the freewheeling bridge arm need to be blocked. Since the current of the inverter inductor LD1 cannot change abruptly, the current of the inverter inductor LD1 will charge the first bus capacitor CE1 or the second bus capacitor CE2 through the body diode of the switching bridge arm. This can lead to overvoltage risks in the bus capacitors, resulting in circuit failure and reduced reliability and safety of the energy storage system 100. For example, taking positive half-cycle blocking as an example, when the peak current in the circuit is large, both the switching bridge arm and the freewheeling bridge arm are blocked. At this time, the energy stored in the inverter inductor LD1 will charge the second bus capacitor CE2 through the body diode of the switching transistor Q2, causing the voltage stored in the second bus capacitor CE2 to rise, which can lead to overvoltage risks in the second bus capacitor CE2.

[0022] Based on this, such as Figure 1 As shown, the energy storage system 100 further includes a voltage equalization circuit 20, which is connected to the three-level inverter circuit 10. The voltage equalization circuit 20 is used to detect the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 in real time. It starts operating when the voltage difference between the first bus voltage and the second bus voltage exceeds a voltage threshold, thereby controlling energy transfer between the first bus capacitor CE1 and the second bus capacitor CE2, and automatically equalizing the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2. Based on this, when the voltage of a certain bus capacitor is too high, the voltage equalization circuit 20 balances the first bus voltage and the second bus voltage, thereby preventing overvoltage in a certain capacitor and improving the reliability and safety of the energy storage system.

[0023] In some embodiments, the power supply 300 may be a photovoltaic input source, power grid, battery, or other power supply device, and there are no restrictions on this.

[0024] In yet another embodiment, please refer to Figure 3 , Figure 3 This is a structural block diagram of a voltage equalization circuit provided in an embodiment of the present invention, such as... Figure 3 As shown, the voltage equalization circuit 20 includes an overvoltage detection module 21, a drive module 22, and a CLLC module 23; The overvoltage detection module 21 is connected to the drive module 22, and the drive module 22 is connected to the CLLC module 23. The overvoltage detection module 21 and the CLLC module 23 are also used to connect the first bus capacitor CE1 and the second bus capacitor CE2, respectively. The overvoltage detection module 21 is used to detect the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 respectively, and outputs a first control signal to the drive module 22 when the voltage difference between the first bus voltage and the second bus voltage is greater than the voltage threshold. The drive module 22 is used to output a drive signal to the CLLC module 23 according to the first control signal, so that the CLLC module 23 starts to work based on the drive signal, thereby enabling the CLLC module 23 to automatically balance the first bus voltage and the second bus voltage.

[0025] During the operation of the energy storage system 100, the overvoltage detection module 21 continuously monitors the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2, and determines whether the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold. If the voltage difference between the first bus voltage and the second bus voltage is greater than the voltage threshold, it is considered that the voltage of one of the first bus capacitors CE1 and the second bus capacitor CE2 is too high. At this time, the overvoltage detection module 21 outputs a first control signal to the drive module 22, so that the drive module 22 outputs a drive signal to the CLLC module 23 based on the first control signal, thereby driving the CLLC module 23 to start working, and thus automatically balancing the first bus voltage and the second bus voltage. It should be noted that after the CLLC module 23 starts working based on the drive signal, the CLLC module 23 will use the bus capacitor with the higher voltage value as the input terminal and the bus capacitor with the lower voltage value as the output terminal, thereby automatically transferring the voltage from the side with the higher bus voltage to the side with the lower bus voltage to achieve automatic bus voltage balancing, thereby avoiding overvoltage and improving the reliability and safety of the energy storage system.

[0026] In some embodiments, the overvoltage detection module 21 is further configured to output a second control signal to the drive module 22 when the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, so that the drive module 22 stops outputting the drive signal.

[0027] If the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, it is considered that the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 are balanced. At this time, the overvoltage detection module 21 will output a second control signal to the drive module 22, so that the drive module 22 stops outputting drive signals based on the second control signal, thereby causing the CLLC module 23 to stop working. Based on this, the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 can be detected in real time. Once a difference in bus voltage is detected, the CLLC module 23 is controlled to start working, thereby automatically balancing the first bus voltage and the second bus voltage, thus avoiding overvoltage in one capacitor.

[0028] In some embodiments, such as Figure 3 As shown, the driving module 22 includes a signal generation unit 221 and a driving unit 222; The signal generation unit 221 is connected to the overvoltage detection module 21 and the drive unit 222 respectively, and the drive unit 222 is connected to the CLLC module 23; The signal generation unit 221 is configured to, upon receiving the first control signal, output a pulse signal with a preset duty cycle to the driving unit 222 according to the first control signal; and Upon receiving the second control signal, the output of the pulse signal is stopped; The driving unit 222, upon receiving a pulse signal with a preset duty cycle, outputs a corresponding driving signal to the CLLC module 23 according to the duty cycle of the pulse signal, so that the CLLC module 23 starts working based on the driving signal, thereby automatically balancing the first bus voltage and the second bus voltage; and The output of the drive signal is stopped when the pulse signal is not received, so that the CLLC module 23 stops working.

[0029] Specifically, when the overvoltage detection module 21 outputs the first control signal, the signal generation unit 221 receives the first control signal and outputs a pulse signal with a preset duty cycle based on the first control signal. At this time, the drive unit 222 outputs a corresponding drive signal to the CLLC module 23 based on the pulse signal with the preset duty cycle, so that the CLLC module 23 starts working based on the drive signal. After the CLLC module 23 starts working, it automatically balances the first bus voltage and the second bus voltage to avoid overvoltage. If the signal generation unit 221 receives the second control signal, it will stop working based on the second control signal, thereby stopping the output of the pulse signal. When the drive unit 222 does not receive the pulse signal, it will stop outputting the drive signal to the CLLC module 23, thereby causing the CLLC module 23 to stop working.

[0030] In some embodiments, please refer to Figure 4 , Figure 4 This is a circuit diagram of a voltage equalization circuit provided in an embodiment of the present invention, such as... Figure 4 As shown, the CLLC module 23 includes a first half-bridge unit composed of switching transistors Q1 and Q2, a second half-bridge unit composed of switching transistors Q4 and Q5, and a resonant unit composed of a transformer T1, inductors L1 and L2, and capacitors C3, C4, C10, and C11. Both the first and second half-bridge units are connected to the drive unit 222, and both are also connected to the resonant unit. The first half-bridge unit is further connected to the first bus capacitor CE1, and the second half-bridge unit is further connected to the second bus capacitor CE2.

[0031] It should be noted that the CLLC module 23 has a symmetrical primary and secondary structure. The switching transistors (the upper or lower transistor in the first half-bridge unit and the second half-bridge unit) on both the primary and secondary sides are driven simultaneously, thereby transferring the voltage from the side with the higher bus capacitor voltage to the side with the lower bus capacitor voltage, thus achieving automatic balancing of the first bus voltage and the second bus voltage. The working principle of the CLLC module 23 is existing technology and will not be described in detail here.

[0032] In some embodiments, such as Figure 4 As shown, the signal generation unit 221 includes chip U2, switch Q3, resistor R4, resistor R6 and capacitor C5; the driving unit 222 includes half-bridge driver chip U1 and half-bridge driver chip U4. The control terminal of the switching transistor Q3 is connected to the overvoltage detection module 21. The control terminal of the switching transistor Q3 is also grounded through the resistor R6. The first terminal of the switching transistor Q3 is connected to the compensation pin of the chip U2. The second terminal of the switching transistor Q3 is used for grounding. The reference voltage pin of the chip U2 is connected to the oscillator timing resistor / capacitor pin of the chip U2 through the resistor R4. The oscillator timing resistor / capacitor pin of the chip U2 is grounded through the capacitor C5.

[0033] The input pins of the half-bridge driver chip U1 and the input pins of the half-bridge driver chip U4 are both connected to the signal generation unit 221. The output pin of the half-bridge driver chip U1 is connected to the first half-bridge unit of the CLLC module 23, and the output pin of the half-bridge driver chip U4 is connected to the second half-bridge unit of the CLLC module.

[0034] It is known that the chip U2 is a PWM controller, and when the compensation pin of the chip U2 receives a low-level signal, the chip U2 will stop outputting pulse signals.

[0035] When the overvoltage detection module 21 outputs a first control signal, the switching transistor Q3 receives the first control signal and turns off based on it. At this time, the compensation pin of chip U2 does not receive a low-level signal, and chip U2 will output a pulse signal normally. When the overvoltage detection module 21 outputs a second control signal, the switching transistor Q3 turns on based on the second control signal. At this time, the compensation pin of chip U2 is pulled low by the switching transistor Q3, thereby causing chip U2 to stop outputting pulse signals.

[0036] It should be noted that the resistor R4 and the capacitor C5 are used to adjust the frequency of the pulse signal. By changing the resistance value of the resistor R4 and the capacitance value of the capacitor C5, the duty cycle of the pulse signal output by the chip U2 can be changed.

[0037] When chip U2 outputs the pulse signal, both half-bridge driver chip U1 and half-bridge driver chip U4 will receive the pulse signal and simultaneously output drive signals of the same phase to the first half-bridge unit and the second half-bridge unit based on the pulse signal, so that the first half-bridge unit and the second half-bridge unit work at the same time, thereby realizing the automatic balancing of the first bus voltage and the second bus voltage.

[0038] In yet another embodiment, such as Figure 3 As shown, the driving module 22 further includes an isolation unit 223; the isolation unit 223 is connected to the signal generation unit 221 and the driving unit 222 respectively.

[0039] The isolation unit 223 is used to isolate the signal generation unit 221 and the driving unit 222 to suppress common-mode interference, thereby improving the stability of the pulse signal.

[0040] In another embodiment, such as Figure 4 As shown, the isolation unit 223 includes an isolation chip U3, a capacitor C7, and a resistor R5; The first input terminal and the second input terminal of the isolation chip U3 are connected. The first input terminal of the isolation chip U3 is also connected to the signal generation unit 221 through the resistor R5. The first power supply terminal of the isolation chip U3 is connected to the first power supply (VCC). The first power supply terminal of the isolation chip U3 is also grounded through the capacitor C7. The second power supply terminal of the isolation chip U3 is connected to the second power supply (VCC2). The first output terminal of the isolation chip U3 is connected to the half-bridge driver chip U1. The second output terminal of the isolation chip U3 is connected to the half-bridge driver chip U4.

[0041] The isolation chip U3 is used to receive the pulse signal with the preset duty cycle, and after isolating the pulse signal, output it to the half-bridge driver chip U1 and the half-bridge driver chip U4 simultaneously, so that the half-bridge driver chip U1 and the half-bridge driver chip U4 can simultaneously drive the first half-bridge unit and the second half-bridge unit to work.

[0042] In yet another embodiment, such as Figure 3 As shown, the overvoltage detection module 21 includes a voltage sampling unit 211 and a voltage comparison unit 212; The voltage sampling unit 211 is connected to the voltage comparison unit 212, the voltage comparison unit 212 is connected to the driving module 22, and the voltage sampling unit 211 is also used to connect to the first bus capacitor CE1 and the second bus capacitor CE2 respectively. The voltage sampling unit 211 is used to collect the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 respectively, and input the collected first bus voltage and second bus voltage to the voltage comparison unit 212. The voltage comparison unit 212 is used to receive the first bus voltage and the second bus voltage, and output a first control signal when the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold; and When the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, a second control signal is output.

[0043] Specifically, during the operation of the energy storage system 100, the voltage sampling unit 211 collects the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2, and inputs the collected first bus voltage and second bus voltage to the voltage comparison unit 212. When the voltage comparison unit 212 receives the first bus voltage and the second bus voltage, it determines whether the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold. When the voltage difference is greater than the voltage threshold, the voltage comparison unit 212 outputs a first control signal; if the voltage difference is less than the voltage threshold, the voltage comparison unit 212 outputs a second control signal.

[0044] In some embodiments, please refer to Figure 5 , Figure 5 This is a circuit diagram of an overvoltage detection module provided in an embodiment of the present invention, such as... Figure 5 As shown, the voltage sampling unit 211 includes differential amplifier U7A and differential amplifier U7B; the voltage comparison unit 212 includes comparator U5A, comparator U5B, resistor R13, resistor R15, resistor R19, resistor R34 and resistor R36. The two input terminals of the differential amplifier U7A are respectively connected to the two ends (BUS+ and BUSN) of the first bus capacitor CE1, and the output terminal of the differential amplifier U7A is connected to the voltage comparator unit 212. The two input terminals of the differential amplifier U7B are respectively connected to the two ends (BUSN and BUS-) of the second bus capacitor CE2, and the output terminal of the differential amplifier U7B is connected to the voltage comparator unit 212.

[0045] The first input terminal of comparator U5A is connected to the first output terminal of voltage sampling unit 211 through resistor R15. The second input terminal of comparator U5A is connected to the second output terminal of voltage sampling unit 211 through resistor R19. The first input terminal of comparator U5B is connected to the second output terminal of voltage sampling unit 211 through resistor R34. The second input terminal of comparator U5B is connected to the first output terminal of voltage sampling unit 211 through resistor R36. The output terminal of comparator U5A is connected to the output terminal of comparator U5B. The output terminal of comparator U5A is also connected to the first power supply (VCC) through resistor R13. The output terminal of comparator U5A is also connected to the drive module 22.

[0046] Here, the differential amplifier refers to a device that amplifies the difference between two input signals. Therefore, the differential amplifier U7A will sample the voltage on the first bus capacitor CE1 in real time, and output the first bus voltage (V_BUS1) to the first input terminal of the comparator U5A and the second input terminal of the comparator U5B; at the same time, the differential amplifier U7B will also sample the second bus voltage (V_BUS2) on the second bus capacitor CE2 in real time, and input the sampled second bus voltage to the second input terminal of the comparator U5A and the first input terminal of the comparator U5B. When both comparator U5A and comparator U5B receive the first bus voltage and the second bus voltage, if the first bus voltage is greater than the sum of the second bus voltage and the voltage threshold, then the first bus capacitor CE1 is considered to have an overvoltage risk, and comparator U5B will output a first control signal (PWM_EN_N). Conversely, if the second bus voltage is greater than the sum of the first bus voltage and the voltage threshold, then the second bus capacitor CE2 is considered to have an overvoltage risk, and comparator U5A will output a first control signal. After either comparator U5A or comparator U5B outputs the first control signal, the drive module 22 receives the first control signal and outputs a drive signal based on it to drive the CLLC module 23 to start working, thereby automatically balancing the first bus voltage and the second bus voltage.

[0047] If the voltage difference between the first bus and the second bus is less than the voltage threshold, then the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 are considered to be balanced. In this case, comparators U5A and U5B will simultaneously output a second control signal to stop the drive module 22 from outputting drive signals, thereby stopping the CLLC module 23 from operating. It should be noted that the voltage threshold is determined based on the resistance value of the resistor connected to comparator U5A or comparator U5B. Different voltage thresholds can be set by adjusting the resistance value. For example, as... Figure 5As shown, the first input terminal of comparator U5A is grounded through resistor R12, and the second input terminal of comparator U5A is grounded through resistor R22. When differential amplifier U7A outputs the first bus voltage and differential amplifier U7B outputs the second bus signal, resistors R15 and R12 divide the first bus voltage and input the divided first bus voltage to the first input terminal of comparator U5A; simultaneously, resistors R22 and R19 divide the second bus voltage and input the divided second bus voltage to the second input terminal of comparator U5A. At this time, a suitable voltage threshold can be set by adjusting the resistance values ​​of resistors R12, R15, R19, and R22.

[0048] In some other embodiments, the voltage threshold can also be set by increasing a bias voltage, for example by increasing a bias voltage (not shown) at the second input terminal of comparator U5A or comparator U5B, and the voltage threshold can be determined based on the bias voltage.

[0049] In some embodiments, such as Figure 3 As shown, the voltage equalization circuit 20 also includes a current detection module 24; The current detection module 24 is connected to the CLLC module 23 and the signal generation unit 221 respectively; The current detection module 24 is used to detect the current signal of the CLLC module 23 in real time when the CLLC module 23 is working, and output a second control signal to the signal generation unit 221 when the current signal is greater than a preset threshold, so that the signal generation unit 221 stops outputting the pulse signal.

[0050] Specifically, during the process of the drive unit 222 outputting a drive signal to control the operation of the CLLC module 23, the current detection module 24 will detect the current signal of the CLLC module 23 in real time, and determine that the CLLC module 23 has an overcurrent condition when the current signal is greater than a preset threshold. At this time, in order to avoid damage to the device, the current detection module 24 will output a second control signal to the signal generation unit 221, so that the signal generation unit 221 stops outputting pulse signals, thereby causing the drive unit 222 to stop outputting drive signals, and the CLLC module 23 to stop working, thus avoiding damage to the circuit due to overcurrent.

[0051] In yet another embodiment, such as Figure 3 As shown, the current detection module 24 includes a current sampling unit 241 and a current comparison unit 242; The current sampling unit 241 is connected to the CLLC module 23 and the current comparison unit 242 respectively, and the current comparison unit 242 is connected to the signal generation unit 221; The current sampling unit 241 is used to collect the current signal of the CLLC module 23 in real time when the CLLC module 23 is working, and output the current signal to the current comparison unit 242. The current comparison unit 242 is used to receive the current signal and output a second control signal to the signal generation unit 221 when the current signal is greater than a preset threshold, so that the signal generation unit 221 stops outputting the pulse signal.

[0052] When the CLLC module 23 is operating, the current sampling unit 241 collects the current signal of the CLLC module 23 in real time and transmits the current signal to the current comparison unit 242, so that the current comparison unit 242 can determine whether the current signal is greater than a preset threshold. If the current signal is greater than the preset threshold, the current comparison unit 242 outputs a second control signal to the signal generation unit 221, so that the signal generation unit 221 stops outputting pulse signals, thereby causing the CLLC module 23 to stop operating. If the current signal is less than the preset threshold, the current comparison unit 242 outputs a first control signal to the signal generation unit 221, so that the signal generation unit 221 operates normally and outputs pulse signals with a preset duty cycle, thereby causing the CLLC module 23 to automatically balance the first bus voltage and the second bus voltage.

[0053] In some embodiments, combined with Figure 4 and Figure 6 The current sampling unit 241 includes a current transformer CT1, a rectifier bridge (diodes D4, D5, D7 and D8), a differential amplifier U6A, resistors R24, R25 and R27; the current comparison unit 242 includes a comparator U6B, resistors R18, R30, R33 and R37. The primary side of the current transformer CT1 is connected to the CLLC module 23. The secondary side of the current transformer CT1 is connected to the resistor R25 and the resistor R27 respectively through the rectifier bridge. The resistor R25 is also connected to the first input terminal of the differential amplifier U6A. The resistor R27 is also connected to the second input terminal of the differential amplifier U6A. The first input terminal of the differential amplifier U6A also receives the midpoint voltage (Vmid) through the resistor R24. The output terminal of the differential amplifier U6A is also connected to the current comparison unit 242.

[0054] The first input terminal of the comparator U6B is connected to the current sampling unit 241 through the resistor R30. The second input terminal of the comparator U6B is connected to the first power supply (VCC) through the resistor R37. The second input terminal of the comparator U6B is grounded through the resistor R33. The output terminal of the comparator U6B is connected to the first power supply through the resistor R18. The output terminal of the comparator U6B is also connected to the drive module 22.

[0055] When the CLLC module 23 is operating, the current transformer CT1 senses the current signal in the CLLC module 23 and rectifies the current signal through the rectifier bridge, outputting it to the two input terminals (I_T1+ and I_T1-) of the differential amplifier U6A. Upon receiving the current signal, the differential amplifier U6A transmits it to the first input terminal of the comparator U6B. Simultaneously, the power supply voltage of the first power source is divided by resistors R33 and R37 and input to the second input terminal of the comparator U6B. If the signal at the first input terminal of the comparator U6B is greater than the signal at the second input terminal, the comparator U6B outputs a second control signal (OCP_P) to the signal generation unit 221 to stop the CLLC module 23 from operating. Conversely, if the signal at the first input terminal of the comparator U6B is less than the signal at the second input terminal, the comparator U6B outputs a first control signal to maintain the CLLC module 23's operating state. Based on this, overcurrent protection can be achieved when the current is too high, thereby improving the reliability of the circuit.

[0056] This invention provides a voltage equalization circuit, which includes an overvoltage detection module, a drive module, and a CLLC module. The overvoltage detection module is connected to the drive module, and the drive module is connected to the CLLC module. The overvoltage detection module and the CLLC module are also used to connect a first bus capacitor and a second bus capacitor, respectively. When the switching transistor in the three-level inverter circuit is blocked, the energy stored in the first bus capacitor or the second bus capacitor will increase. To avoid the risk of overvoltage in the first bus voltage or the second bus voltage, the overvoltage detection module will detect the first bus voltage or the second bus voltage respectively. When the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold, it is determined that the voltage of the first bus capacitor or the second bus capacitor is too high. At this time, the overvoltage detection module will output a first control signal to the drive module, so that the drive module outputs a drive signal to the CLLC module based on the first control signal, thereby driving the CLLC module to start working, and then controlling the first bus capacitor and the second bus capacitor to transfer energy, so that the voltage of the first bus capacitor and the voltage of the second bus capacitor are equalized. Based on this, by transferring the voltage of one capacitor to another when the voltage of the other capacitor is too high, overvoltage can be avoided, protecting the components in the circuit from damage and thus improving the reliability and safety of the energy storage system.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage equalization circuit, characterized in that, The voltage equalization circuit includes an overvoltage detection module, a drive module, and a CLLC module; The overvoltage detection module is connected to the drive module, the drive module is connected to the CLLC module, and the overvoltage detection module and the CLLC module are also used to connect the first bus capacitor and the second bus capacitor, respectively. The overvoltage detection module is used to detect the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor respectively, and outputs a first control signal to the drive module when the voltage difference between the first bus voltage and the second bus voltage is greater than the voltage threshold. The drive module is used to output a drive signal to the CLLC module according to the first control signal, so that the CLLC module starts to work based on the drive signal, thereby enabling the CLLC module to automatically balance the first bus voltage and the second bus voltage.

2. The voltage equalization circuit according to claim 1, characterized in that, The overvoltage detection module is further configured to output a second control signal to the drive module when the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, so that the drive module stops outputting the drive signal.

3. The voltage equalization circuit according to claim 2, characterized in that, The driving module includes a signal generation unit and a driving unit; The signal generation unit is connected to the overvoltage detection module and the drive unit respectively, and the drive unit is connected to the CLLC module; The signal generation unit is used to output a pulse signal with a preset duty cycle to the driving unit after receiving the first control signal; as well as Upon receiving the second control signal, the output of the pulse signal is stopped; The driving unit is used to output a corresponding driving signal to the CLLC module according to the duty cycle of the pulse signal after receiving the pulse signal with the preset duty cycle, so that the CLLC module starts to work based on the driving signal, thereby automatically balancing the first bus voltage and the second bus voltage. as well as The output drive signal is stopped when the pulse signal is not received, so that the CLLC module stops working.

4. The voltage equalization circuit according to claim 3, characterized in that, The signal generation unit includes chip U2, switch Q3, resistor R4, resistor R6 and capacitor C5; The control terminal of the switching transistor Q3 is connected to the overvoltage detection module. The control terminal of the switching transistor Q3 is also grounded through the resistor R6. The first terminal of the switching transistor Q3 is connected to the compensation pin of the chip U2. The second terminal of the switching transistor Q3 is grounded. The reference voltage pin of the chip U2 is connected to the oscillator timing resistor / capacitor pin of the chip U2 through the resistor R4. The oscillator timing resistor / capacitor pin of the chip U2 is grounded through the capacitor C5.

5. The voltage equalization circuit according to claim 3, characterized in that, The driving unit includes a half-bridge driving chip U1 and a half-bridge driving chip U4. The input pins of both the half-bridge driver chip U1 and the half-bridge driver chip U4 are connected to the signal generation unit. The output pin of the half-bridge driver chip U1 is connected to the first half-bridge unit of the CLLC module, and the output pin of the half-bridge driver chip U4 is connected to the second half-bridge unit of the CLLC module.

6. The voltage equalization circuit according to any one of claims 2-5, characterized in that, The overvoltage detection module includes a voltage sampling unit and a voltage comparison unit; The voltage sampling unit is connected to the voltage comparison unit, the voltage comparison unit is connected to the driving module, and the voltage sampling unit is also used to connect to the first bus capacitor and the second bus capacitor respectively. The voltage sampling unit is used to collect the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor respectively, and input the collected first bus voltage and second bus voltage to the voltage comparison unit; The voltage comparison unit is used to receive the first bus voltage and the second bus voltage, and outputs a first control signal when the voltage difference between the first bus voltage and the second bus voltage is greater than a voltage threshold. as well as When the voltage difference between the first bus voltage and the second bus voltage is less than the voltage threshold, a second control signal is output.

7. The voltage equalization circuit according to claim 6, characterized in that, The voltage comparison unit includes comparator U5A, comparator U5B, resistor R13, resistor R15, resistor R19, resistor R34 and resistor R36; The first input terminal of comparator U5A is connected to the first output terminal of the voltage sampling unit through resistor R15. The second input terminal of comparator U5A is connected to the second output terminal of the voltage sampling unit through resistor R19. The first input terminal of comparator U5B is connected to the second output terminal of the voltage sampling unit through resistor R34. The second input terminal of comparator U5B is connected to the first output terminal of the voltage sampling unit through resistor R36. The output terminal of comparator U5A is connected to the output terminal of comparator U5B. The output terminal of comparator U5A is also connected to the first power supply through resistor R13. The output terminal of comparator U5A is also connected to the drive module.

8. The voltage equalization circuit according to claim 3, characterized in that, The voltage equalization circuit also includes a current detection module; The current detection module is connected to both the CLLC module and the signal generation unit. The current detection module is used to detect the current signal of the CLLC module in real time when the CLLC module is working, and when the current signal is greater than a preset threshold, output a second control signal to the signal generation unit so that the signal generation unit stops outputting the pulse signal.

9. The voltage equalization circuit according to claim 8, characterized in that, The current detection module includes a current sampling unit and a current comparison unit; The current sampling unit is connected to the CLLC module and the current comparison unit respectively, and the current comparison unit is connected to the signal generation unit; The current sampling unit is used to collect the current signal of the CLLC module in real time when the CLLC module is working, and output the current signal to the current comparison unit; The current comparison unit is used to receive the current signal and output a second control signal to the signal generation unit when the current signal is greater than a preset threshold, so that the signal generation unit stops outputting the pulse signal.

10. An energy storage system, characterized in that, The energy storage system includes: A three-level inverter circuit, wherein the three-level inverter circuit includes a first bus capacitor and a second bus capacitor; and The voltage equalization circuit according to any one of claims 1-9 is connected to the first bus capacitor and the second bus capacitor respectively.

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