Chip single-wire IIC signal analysis method based on function test

Abstract

The application relates to the technical field of signal analysis, and particularly discloses a chip single-wire IIC signal analysis method based on function testing, which comprises the following steps: step S1: performing dynamic window median filtering on an input signal, effectively eliminating signal jitter and burrs through dynamic expansion of a sliding window and median replacement, and outputting a smooth digital signal; step S2: performing virtual clock generation, obtaining a time interval sequence based on jump edge detection, calculating interval variance by using a sliding window, screening effective intervals according to a variance threshold, and finally equally dividing to generate a virtual clock; and step S3: sampling at the center of a signal steady state interval by using the clock, and analyzing sampling data according to an IIC protocol state machine to complete data decoding; the whole process is realized by a pure software algorithm, the hardware limitation is broken through, and the analysis precision and equipment compatibility are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of signal analysis technology, and more specifically to a chip single-line IIC signal analysis method based on functional testing. Background Technology

[0002] In the field of automated testing of integrated circuits, automated test equipment (ATE) is widely used to perform functional and performance verification on device-under-the-chip (DUT). Among numerous chip communication protocols, the IIC (Inter-Integrated Circuit) bus is widely adopted due to its simple structure and few pins. The traditional IIC bus uses separate serial data lines (SDA) and serial clock lines (SCL) for synchronous communication. However, to further save pin resources, a single-wire IIC protocol was developed, which combines data and clock signals into a single line for transmission, eliminating the need for a separate clock signal.

[0003] This characteristic poses a significant challenge to the signal acquisition mechanisms of existing ATE (Automatic Test Equipment) systems. Traditional ATE systems heavily rely on a stable, independent clock signal as a sampling reference when capturing DUT (Data Under Test) signals. For single-wire IIC (Integrated Circuit) signals, the lack of this reference prevents the ATE from directly and reliably synchronizing and parsing the data signal. Although some high-end ATE systems offer hardware-based pattern matching (MATCH) functions to attempt to capture such signals, this approach is limited by its fixed hardware circuit structure, resulting in inherent drawbacks such as poor flexibility, complex configuration, and inability to adapt to all types of DUTs, leading to low test coverage and efficiency.

[0004] Therefore, there is an urgent need in the existing technology to find a signal analysis method that does not rely on an independent clock signal, can overcome the jitter interference of single-line IIC signals, and has wide applicability, so as to achieve efficient and accurate testing of chips using the single-line IIC protocol. Summary of the Invention

[0005] The purpose of this invention is to provide a chip single-wire IIC signal analysis method based on functional testing, and to solve the following technical problems.

[0006] The objective of this invention can be achieved through the following technical solutions:

[0007] A chip single-wire IIC signal analysis method based on functional testing includes the following steps:

[0008] Step S1: The input single-line IIC signal is filtered using a dynamic extended window mid-range filtering algorithm to eliminate jitter and glitches in the signal and output a smoothed digital signal.

[0009] Step S2: Perform edge detection on the smoothed digital signal to obtain a timestamp sequence and the time interval between consecutive edges; use a sliding window to obtain the variance of the time interval, and filter the time interval based on the variance and a preset variance threshold to remove noise intervals and obtain an effective time interval; generate a virtual clock signal based on the effective time interval.

[0010] Step S3: Using the virtual clock signal, perform center sampling in the steady-state range of the IIC signal to obtain sampled data, and parse the sampled data according to the IIC protocol state machine to output the decoded IIC data.

[0011] As a further aspect of the present invention: the process of the dynamically expanded window mid-value filtering algorithm includes:

[0012] Initialize a dynamically expanding window. If the number of data points within the dynamically expanding window is insufficient for median calculation, then dynamically expand the boundary of the dynamically expanding window. Prioritize expanding the left boundary of the dynamically expanding window to the left. If the left boundary of the dynamically expanding window can no longer be expanded, then expand the right boundary of the dynamically expanding window to the right.

[0013] As a further aspect of the present invention: during the initialization process of the dynamically expanding window, the size of the dynamically expanding window is 3 by default, and the size of the dynamically expanding window is dynamically adjusted based on the signal quality.

[0014] As a further aspect of the present invention: the process of setting the variance threshold includes:

[0015] Obtain the average value T of each time interval within the current sliding window, and set the variance threshold to αT, where α is a preset configurable parameter and α=0.2.

[0016] As a further aspect of the present invention, the process of filtering the time interval includes:

[0017] For any time interval within the sliding window, if the time interval is greater than the sum of the average value and the variance threshold, or less than the difference between the average value and the variance threshold, then the time interval is determined to be noise and is filtered out.

[0018] As a further aspect of the present invention: the process of generating the virtual clock signal includes dividing the effective time interval after noise filtering into equal parts to obtain a virtual clock signal with a constant period.

[0019] As a further aspect of the present invention: the process of performing center sampling in the steady-state region includes:

[0020] Within one clock cycle of the virtual clock signal, the smoothed digital signal is sampled at the center of the clock cycle.

[0021] As a further aspect of the present invention, the process of parsing the sampled data according to the IIC protocol state machine includes the identification and state transition of the start condition, data bits, acknowledgment bits, and stop condition.

[0022] The beneficial effects of this invention are:

[0023] This invention, through an innovative virtual clock generation algorithm, completely eliminates the reliance on independent clock signals and dedicated hardware matching circuits. This allows standard ATE test platforms to be compatible with various single-line IIC devices without hardware modifications, significantly improving test coverage and equipment utilization. Furthermore, it employs dynamic window mid-range filtering technology to intelligently eliminate jitter and glitches during signal transmission, effectively restoring the true signal waveform. Combined with a noise interval filtering mechanism based on variance analysis, the accuracy and stability of the virtual clock extraction are ensured, providing a highly complete signal foundation for subsequent data decoding. Key parameters in this method, such as the filter window size and variance threshold coefficient α, are all configurable in software, enabling flexible adaptation to single-line IIC communication scenarios with different rates and signal qualities, meeting diverse testing needs, and greatly enhancing the method's versatility and application value. Attached Figure Description

[0024] The invention will now be further described with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of the steps of the chip single-line IIC signal analysis method based on functional testing of the present invention;

[0026] Figure 2 This is a flowchart of the signal processing in the chip single-line IIC signal analysis method based on functional testing of the present invention;

[0027] Figure 3 This is a flowchart of the preprocessing process in the chip single-line IIC signal parsing method based on functional testing of the present invention;

[0028] Figure 4 This is a flowchart of the clock extraction process in the chip single-wire IIC signal parsing method based on functional testing of the present invention;

[0029] Figure 5 This is a flowchart of the data decoding process in the chip single-line IIC signal parsing method based on functional testing of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1 As shown, this invention is a chip single-wire IIC signal analysis method based on functional testing, including the following steps:

[0032] Step S1: The input single-line IIC signal is filtered using a dynamic extended window mid-range filtering algorithm to eliminate jitter and glitches in the signal and output a smoothed digital signal.

[0033] In a preferred embodiment of the present invention, the process of the dynamic expanded window mid-value filtering algorithm includes:

[0034] Initialize a dynamically expanding window. If the number of data points in the dynamically expanding window is insufficient for median calculation, then dynamically expand the boundary of the dynamically expanding window. The left boundary of the dynamically expanding window is expanded first. If the left boundary of the dynamically expanding window cannot be expanded, then the right boundary of the dynamically expanding window is expanded to the right.

[0035] During the initialization process of the dynamically expanding window, the size of the dynamically expanding window is 3 by default, and the size of the dynamically expanding window is dynamically adjusted based on the signal quality.

[0036] Specifically, a fixed-size window is initialized for the currently processed data point. When the number of valid data points in the window is insufficient, the window boundary is dynamically expanded. The expansion logic is as follows: the left boundary of the window is expanded to the left first. If there is no data on the left, the right boundary of the window is expanded to the right. The left is the direction of the historical signal that has been processed, and the right is the direction of the new signal to be processed. The expansion logic aims to prioritize the use of confirmed stable signal segments to evaluate the current point, thereby achieving the optimal balance between the real-time performance and accuracy of filtering.

[0037] Sort the level values ​​of all data points in the current dynamic window and take the median value. Use the median value to replace the original current data point. This operation can effectively filter out positive or negative glitches in the form of narrow pulses and pull the unstable level caused by jitter back to the stable dominant level state. Thus, without significantly distorting the edges of the original signal, output a smooth digital signal that eliminates isolated interference points.

[0038] It should be noted that in the ATE test environment, the signal will introduce random jitter and transient glitches, such as ringing. Traditional fixed window filtering or mean filtering is prone to failure near the signal edge due to insufficient data when processing in real time, or it will cause the signal edge to become smooth, that is, the slope will decrease, which is not conducive to subsequent accurate edge detection.

[0039] By using dynamic extended window median filtering, especially the strategy of prioritizing left extension, sufficient window data is ensured for effective filtering even at the first point after a signal transition edge. At the same time, the characteristics of median filtering make it extremely effective in eliminating isolated spikes and glitches, and it can well preserve the step edges of the signal.

[0040] Step S2: Perform edge detection on the smoothed digital signal to obtain a timestamp sequence and the time interval between consecutive edges; use a sliding window to obtain the variance of the time interval, and filter the time interval based on the variance and a preset variance threshold to remove noise intervals and obtain an effective time interval; generate a virtual clock signal based on the effective time interval.

[0041] Specifically, the smoothed digital signal is subjected to edge detection, and the timestamps of each rising and falling edge are accurately recorded to form a sequence. The time interval between consecutive edges is calculated. To solve the core problem of abnormal fluctuations in the interval time caused by residual noise after filtering or non-ideal signal transitions, which makes it impossible to directly and stably reconstruct the clock, an interval filtering mechanism based on statistical characteristics is introduced.

[0042] Define a fixed-size sliding window that slides over the time interval sequence. For N time intervals within the window, calculate their statistical variance to quantify the temporal stability of the signal segment. Set a dynamic variance threshold, which is obtained by multiplying the average of the time intervals within the window by a configurable parameter α. Compare the current time interval with the constructed interval. If the current interval falls outside the interval, it is determined to be an abnormal interval caused by noise and is filtered out, thereby obtaining a clean sequence composed of valid time intervals.

[0043] Based on the effective time interval after noise filtering, a virtual clock signal with a constant period is generated by equally dividing these effective intervals. This virtual clock signal is equivalent to the independent SCL clock in the traditional IIC bus, providing a stable and reliable sampling reference for subsequent data decoding.

[0044] In a preferred embodiment of the present invention, the process of setting the variance threshold includes:

[0045] Obtain the average value T of each time interval within the current sliding window, and set the variance threshold to αT, where α is a preset configurable parameter and α=0.2;

[0046] The process of filtering the time intervals includes:

[0047] For any time interval within the sliding window, if the time interval is greater than the sum of the average value and the variance threshold, or less than the difference between the average value and the variance threshold, then the time interval is determined to be noise and is filtered out.

[0048] In a preferred embodiment of the present invention, the virtual clock signal generation process includes dividing the effective time interval after noise filtering into equal parts to obtain a virtual clock signal with a constant period.

[0049] It should be noted that since single-line IIC has no physical clock line, the core task of this invention is to create one out of thin air. Even after filtering, there may still be slight timing jitter in the actual signal, or intervals of varying lengths due to the protocol itself. If these intervals are directly used as clock cycles, huge timing errors will occur. Therefore, this invention uses variance analysis and dynamic threshold algorithms to intelligently distinguish intervals into valid signal transition intervals, invalid noise, and abnormal intervals. This ensures that the source data used to generate the clock is clean and representative, thereby synthesizing a highly stable virtual clock. It successfully separates clock information from the merged signal with high precision, breaking through the key bottleneck of single-line IIC testing. It can handle communication scenarios with different rates by averaging and different signal qualities by variance, and has strong versatility.

[0050] Step S3: Using the virtual clock signal, perform center sampling in the steady-state range of the IIC signal to obtain sampled data, and parse the sampled data according to the IIC protocol state machine to output the decoded IIC data;

[0051] Specifically, the virtual clock signal generated in step S2 is used to sample and parse the smoothed digital signal output in step S1; this solves the two ultimate problems of how to determine the optimal sampling time to reliably read each bit of data in the absence of hardware clock synchronization, and how to accurately interpret the sampled bit stream into commands and data conforming to the IIC standard.

[0052] In a preferred embodiment of the present invention, the process of performing center sampling in the steady-state region includes:

[0053] Within one clock cycle of the virtual clock signal, the smoothed digital signal is sampled at the center of the clock cycle;

[0054] Specifically, to avoid the problem of insufficient setup and hold time and possible residual jitter near the signal transition edge, the sampling point is set at the center of the steady-state interval of each data bit defined by the virtual clock signal; within one virtual clock cycle, the data signal is sampled once at the time center of the cycle; this ensures that the sampling point is far away from the dangerous area of ​​signal change, thereby capturing stable and error-free data bit level values, i.e., 0 or 1, to obtain the original bit stream sequence;

[0055] In a preferred embodiment of the present invention, the process of parsing the sampled data according to the IIC protocol state machine includes the identification and state transition of the start condition, data bits, acknowledgment bits and the stop condition;

[0056] Specifically, an IIC protocol state machine is constructed to parse the bitstream sequence in real time. The IIC protocol state machine sequentially identifies the IIC standard communication frame format and performs the following processing:

[0057] The initial condition is to detect the falling edge of the SDA line during the SCL high level.

[0058] Address and data bits: In each subsequent virtual clock cycle, one bit of data is read and the byte is assembled.

[0059] The acknowledge bit is used to detect an acknowledgment (ACK) or non-acknowledgment (NACK) signal from the receiver after each byte (8 bits) is transmitted.

[0060] The stop condition is to detect the rising edge of the SDA line during the SCL high level.

[0061] The IIC protocol state machine performs state transitions according to these specific sequences, thereby accurately separating the start signal, slave address, read / write operation bits, valid data bytes, and stop signal from the original bit stream, and finally outputting structured, decoded IIC communication data.

[0062] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the invention.

Claims

1. A chip single-wire IIC signal analysis method based on functional testing, characterized in that, Includes the following steps: Step S1: The input single-line IIC signal is filtered using a dynamic extended window mid-range filtering algorithm to eliminate jitter and glitches in the signal and output a smoothed digital signal. Step S2: Perform edge detection on the smoothed digital signal to obtain a timestamp sequence and the time interval between consecutive edges; use a sliding window to obtain the variance of the time interval, and filter the time interval based on the variance and a preset variance threshold to remove noise intervals and obtain an effective time interval; generate a virtual clock signal based on the effective time interval. Step S3: Using the virtual clock signal, perform center sampling in the steady-state range of the IIC signal to obtain sampled data, and parse the sampled data according to the IIC protocol state machine to output the decoded IIC data.

2. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S1, the process of the dynamic expanded window mid-value filtering algorithm includes: Initialize a dynamically expanding window. If the number of data points within the dynamically expanding window is insufficient for median calculation, then dynamically expand the boundary of the dynamically expanding window. Prioritize expanding the left boundary of the dynamically expanding window to the left. If the left boundary of the dynamically expanding window can no longer be expanded, then expand the right boundary of the dynamically expanding window to the right.

3. The chip single-wire IIC signal analysis method based on functional testing according to claim 2, characterized in that, In step S1, during the initialization of the dynamically expanding window, the size of the dynamically expanding window is 3 by default, and the size of the dynamically expanding window is dynamically adjusted based on the signal quality.

4. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S2, the process of setting the variance threshold includes: Obtain the average value T of each time interval within the current sliding window, and set the variance threshold to αT, where α is a preset configurable parameter and α=0.

2.

5. The chip single-wire IIC signal analysis method based on functional testing according to claim 4, characterized in that, In step S2, the process of filtering the time intervals includes: For any time interval within the sliding window, if the time interval is greater than the sum of the average value and the variance threshold, or less than the difference between the average value and the variance threshold, then the time interval is determined to be noise and is filtered out.

6. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S2, the process of generating the virtual clock signal includes dividing the effective time interval after noise filtering into equal parts to obtain a virtual clock signal with a constant period.

7. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S3, the process of performing center sampling in the steady-state region includes: Within one clock cycle of the virtual clock signal, the smoothed digital signal is sampled at the center of the clock cycle.

8. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S3, the process of parsing the sampled data according to the IIC protocol state machine includes the identification and state transition of the start condition, data bits, response bits, and stop condition.

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