Self-adaptive synchronization method for acquisition time difference among multiple ADC (Analog to Digital Converter) chips

Abstract

The invention provides a self-adaptive synchronization method for acquisition time difference among multiple ADC (Analog to Digital Converter) chips, which comprises the following steps of: S1, triggering a linear feedback shift register to generate a PN sequence signal with a sharp autocorrelation characteristic during initialization or calibration; s2, inputting the PN sequence signal into a multi-ADC chip acquisition channel, and enabling the chip to start analog-to-digital conversion at the same time; s3, performing binarization preprocessing on the acquired data, selecting a reference sequence, performing cyclic shift on other sequences, and calculating an autocorrelation value; s4, detecting a peak point of an autocorrelation function, estimating an acquisition time difference between ADCs, and recording a cyclic shift number as a compensation value; and S5, in a synchronous acquisition mode, inputting multiple paths of sensor signals, performing shift compensation on other ADC data streams according to the compensation value, and outputting synchronous acquisition data. The method provided by the invention can effectively improve the synchronism of data acquisition and the time sequence precision of the system, is high in universality, and is suitable for different types of ADC (Analog to Digital Converter) systems.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of ADC synchronization, in particular, especially relates to a kind of adaptive synchronization method of acquisition time difference between multiple ADC chips. BACKGROUND

[0002] In the multi-ADC data acquisition system, multiple analog-to-digital conversion chips (ADC) are designed to trigger simultaneously to perform data acquisition. However, due to the influence of chip individual differences and different conversion architectures, etc., acquisition time difference may occur between chips, resulting in inconsistency of actual sampling time. This phenomenon can cause phase deviation between multiple signals, and further cause phase distortion and spectrum leakage, etc., which seriously affects the system performance. In the fields of industrial automation, precision instruments and meters, radio communication and radar detection, etc., the strict synchronous acquisition of multiple sensor signals is particularly significant, because only the accurate acquisition of signals at the same time can reflect the true state of the measured object.

[0003] At present, the mainstream methods to realize synchronous acquisition of multiple ADC chips include global clock distribution, hardware trigger synchronization, timestamp marking and FPGA cache resynchronization, etc. These methods mainly focus on solving the synchronization problem of trigger instructions and the phase offset problem of clock, to reduce the timing deviation of the acquisition system, thereby improving the synchronization of sampling to a certain extent.

[0004] However, although the existing methods have made certain progress in the synchronization of trigger instructions and clock phase, they generally ignore the fundamental problem of acquisition time difference between multiple ADC chips. Due to the influence of chip individual differences and different conversion architectures, the existence of acquisition time difference will still cause the misplacement of instantaneous time of acquisition data, affecting the accuracy of synchronous acquisition. Therefore, in the multi-ADC acquisition system, how to accurately estimate and compensate the acquisition time difference introduced by chip individual differences and different conversion architectures is the key to realizing efficient data synchronization. SUMMARY

[0005] Therefore, the purpose of the present application is to provide an adaptive synchronization method of acquisition time difference between multiple ADC chips to solve the technical problem that the existing synchronous acquisition method ignores the acquisition time difference between multiple ADC chips.

[0006] The technical means adopted by the present application is as follows: An adaptive synchronization method of acquisition time difference between multiple ADC chips, comprising the following steps: S1, generating an acquisition time difference measurement signal; In the initialization phase or when recalibration is needed, the hardware timer interrupt of the microcontroller is configured to trigger the linear feedback shift register to update the PN sequence signal in real time; the PN sequence signal is a pseudo-random noise code with sharp autocorrelation characteristics; S2, simultaneously triggering multi-ADC chip analog-to-digital conversion; The PN sequence signal is simultaneously input to the acquisition channels of the multi-ADC chips to be synchronized; the microcontroller is used to control or trigger the multi-ADC chips, so that the multi-ADC chips simultaneously start analog-to-digital conversion on the input same PN sequence signal, and the original acquisition data of the PN sequence of each channel is acquired; S3, estimating the acquisition time difference; The original acquisition data of the PN sequence acquired by the multi-ADC chips is binarized and preprocessed, one of the binarized sequences acquired by the ADC is selected as a reference sequence, the binarized sequences acquired by the other ADCs are cyclically shifted relative to the reference sequence, and the autocorrelation values of the sequences acquired by the other ADCs and the reference sequence are calculated bit by bit; the autocorrelation values under all shift amounts are acquired and recorded, thereby forming a complete autocorrelation function; S4, acquisition time difference compensation value calculation; The peak point position of the autocorrelation function is detected to estimate the acquisition time difference between the ADCs; the peak point position is the state of the best alignment with the reference sequence; the sequence cyclic shift number required to reach the highest autocorrelation peak is recorded, and the sequence cyclic shift number is the acquisition time difference compensation value; S5, acquisition time difference compensation and synchronous acquisition After entering the synchronous acquisition mode, the multi-sensor input signal is used, the acquisition data stream of the reference ADC enters the output buffer, and the acquisition data streams of the other ADCs are shifted and compensated according to the acquisition time difference compensation value, and the multi-ADC chip acquisition data after time difference compensation is output.

[0007] Further, S1 specifically includes the following steps: A pseudo-random code sequence of a specific length is generated as a reference signal for acquisition time difference measurement, a timer hardware interrupt of a microcontroller is configured, each interrupt period corresponds to the duration of one PN chip, a linear feedback shift register is triggered to update in real time to generate a PN sequence with sharp autocorrelation characteristics; PN sequence The expression is as follows: (1) In the formula, is a PN sequence with a length of , and m is the number of stages of the linear feedback shift register; {0,1}, when , the output pulse amplitude is , and when , the output pulse amplitude is 0; is the pulse shape of the PN sequence; is the symbol duration , The clock frequency of the shift register, i.e. the number of output symbols updated per second; The time shift of the pulse waveform, which arranges each symbol in sequence on the time axis; the length of the sequence is usually set according to the maximum expected time difference, which needs to satisfy , The maximum estimated time difference.

[0008] Further, S3 specifically comprises the following steps: Pretreatment of data and adaptive acquisition of time difference estimation; after obtaining the PN sequence data output by different ADCs through analog-to-digital conversion, the acquisition value is converted into a code value by setting a threshold Binarization of original data; select a PN sequence collected by an ADC as a reference chip stream, and perform cyclic shift on the sequence chips collected by the remaining ADCs relative to the reference sequence; after each shift operation, calculate the autocorrelation value of the sequence chips relative to the reference sequence; based on the unique and sharp characteristics of the autocorrelation peak of the PN sequence, detect and locate the position of the significant peak of the autocorrelation function, which corresponds to the best chip alignment position between the two sequences; Autocorrelation function of two sequences The expression is as follows: (2) In the formula, d is the cyclic shift amount, representing the number of sampling points by which the sequence is shifted; N is the actual sampling sequence length, To ensure that the complete PN sequence period is included; The best alignment point at which the autocorrelation function reaches the maximum value; The sampling sequence of the reference ADC for the PN sequence after binarization, which is obtained by Sampling at intervals (3) In the formula, To avoid spectral aliasing of the chip waveform during sampling; The sampling sequence of the ADC to be synchronized for the PN sequence after binarization, which contains the time difference to be estimated, and is obtained by Sampling at intervals (4) In the formula, The time difference to be estimated, which is actually used for periodic extension and cyclic shift calculation during autocorrelation operation.

[0009] ​​​Further, S4 specifically comprises the following steps: The acquisition time difference compensation value calculation; judging whether the significant correlation peak position is detected, if detected, the system determines that the current data is valid, the time difference estimation is feasible, and enters the compensation value calculation; if not detected, the system determines that the current data is invalid, triggers the error handling process, discards the current data, and returns to S2 to regenerate the PN sequence; by finding the global maximum value position of the correlation function , to determine : (5) When the cyclic shift amount d is equal to the acquisition time difference in the number of sampling points, the two sequences reach the best alignment position, and at this time the theoretical maximum value of the autocorrelation function is obtained N .

[0010] The application also provides a multi-ADC chip acquisition time difference synchronization system for realizing the adaptive synchronization method of the acquisition time difference between the multi-ADC chips, comprising: An acquisition time difference measurement signal generation module is configured to generate a pseudo-random noise code sequence with sharp autocorrelation characteristics as a reference signal for acquisition time difference measurement; the acquisition time difference measurement signal generation module triggers a linear feedback shift register to update the PN sequence signal in real time through the hardware timing interrupt of the configuration microcontroller; An ADC chip control and triggering module is configured to input the generated PN sequence signal to the acquisition channels of the multi-ADC chips to be synchronized, and control or trigger the multi-ADC chips to start analog-to-digital conversion on the input same PN sequence signal at the same time, so as to obtain the PN sequence original acquisition data of each channel; An acquisition time difference estimation module is configured to perform binaryzation preprocessing on the PN sequence original acquisition data collected by the multi-ADC chips, select a binaryzation sequence collected by one of the ADCs as a reference sequence, perform cyclic shift on the binaryzation sequences collected by the other ADCs relative to the reference sequence, and calculate the autocorrelation values of the sequences collected by the other ADCs and the reference sequence bit by bit; An acquisition time difference compensation module is configured to adaptively determine the acquisition time difference between the ADCs based on the autocorrelation function by detecting the peak point position of the correlation function; record the sequence cyclic shift number required to reach the highest autocorrelation peak, which is the acquisition time difference compensation value, and calculate the actual time difference according to the acquisition period of the system; A synchronous acquisition module is configured to access external multi-channel sensor signals after the system enters the synchronous acquisition mode, perform shift compensation on the data streams collected by the other ADCs according to the acquisition time difference compensation value, and output the multi-ADC chip acquisition data after time difference compensation.

[0011] The application further provides a storage medium comprising a stored program, wherein the program, when executed, performs any of the adaptive synchronization methods of the time difference of acquisition between multiple ADC chips.

[0012] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor performs any of the adaptive synchronization methods of the time difference of acquisition between multiple ADC chips by executing the computer program.

[0013] Compared with the prior art, the application has the following advantages: The application uses the PN code generated by the system itself as the time difference measurement signal, automatically performs the calibration process in the system initialization stage, accurately determines the time difference of acquisition between multiple ADC chips by using the sharp autocorrelation characteristics of the PN code, and after obtaining the compensation value, the system enters the synchronous acquisition mode, acquires the target signal and applies the calculated time difference compensation to ensure the synchronization of the acquired data.

[0014] The synchronization method provided by the application has excellent versatility. It can be compatible with ADC chips of different conversion architectures and different sampling rates, and improves the flexibility of hardware circuit design. The core algorithm can be efficiently executed by a microcontroller, and has the advantages of low hardware implementation cost and strong system compatibility. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0016] Figure 1 The method flowchart of the application.

[0017] Figure 2 The device module structure diagram related to the embodiment of the application.

[0018] Figure 3 The original PN sequence waveform diagram of different ADC acquisition of the application.

[0019] Figure 4 The PN sequence correlation function analysis diagram of different ADC acquisition of the application.

[0020] Figure 5 The synchronization sequence comparison diagram after acquisition time difference compensation of the application.

[0021] Figure 6 To realize the contrast chart before and after the compensation of the synchronous acquisition data of the application. DETAILED DESCRIPTION

[0022] In order to make the personnel in the art better understand the application scheme, the technical solutions in the embodiments of the application will be clearly and completely described below in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the application.

[0023] It should be noted that the terms "first", "second", and the like in the specification and claims of the application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0024] As shown in Figure 1 The application provides a multi-ADC chip inter-acquisition time difference adaptive synchronization method, comprising the following steps: S1, generating an acquisition time difference measurement signal; In the initialization stage or when re-calibration is needed, the linear feedback shift register is triggered to update the PN sequence signal in real time by configuring the hardware timing interrupt of the microcontroller; the PN sequence signal is a pseudo-random noise code with sharp autocorrelation characteristics; S2, simultaneously triggering multi-ADC chip analog-to-digital conversion; The PN sequence signal is simultaneously input to the acquisition channels of the multi-ADC chips to be synchronized; the microcontroller is used to control or trigger the multi-ADC chips, so that the multi-ADC chips simultaneously start analog-to-digital conversion on the same input PN sequence signal, and obtain the original acquisition data of the PN sequence of each channel; S3, estimating the acquisition time difference; The original acquisition data of the PN sequence collected by the multiple ADC chips is binarized for preprocessing, so as to simplify subsequent calculation and improve processing efficiency. S4, acquisition time difference compensation value calculation Based on the calculation result of the autocorrelation function, the peak position of the correlation function is detected to estimate the acquisition time difference between the ADCs. The peak position is the state of the best alignment (i.e., the time difference is compensated) with the reference sequence, and the autocorrelation function reaches the theoretical maximum value at this time.

[0025] S5, acquisition time difference compensation and synchronous acquisition After entering the synchronous acquisition mode, the input signals of the multiple sensors are used, the acquisition data stream of the reference ADC enters the output buffer, and the acquisition data streams of the other ADCs are shifted and compensated according to the acquisition time difference compensation value.

[0026] The application also provides a synchronous system for acquisition time difference between multiple ADC chips, which is used to realize the adaptive synchronization method for acquisition time difference between multiple ADC chips, and comprises: The acquisition time difference measurement signal generation module is used to generate a pseudo-random noise code sequence with sharp autocorrelation characteristics as a reference signal for acquisition time difference measurement. The ADC chip control and trigger module is used to input the generated PN sequence signal to the acquisition channels of the multiple ADC chips to be synchronized, and control or trigger the multiple ADC chips to start analog-to-digital conversion on the same input PN sequence signal at the same time. The acquisition time difference estimation module is used to binarize the original acquisition data of the PN sequence collected by the multiple ADC chips for preprocessing, select a binarized sequence collected by one of the ADCs as a reference sequence, cyclically shift the binarized sequences collected by the other ADCs relative to the reference sequence, and calculate the autocorrelation values of the sequences collected by the other ADCs and the reference sequence bit by bit. The acquisition time difference compensation module is used for adaptively determining the time difference between ADCs by detecting the peak point position of the correlation function based on the autocorrelation value; the sequence cycle shift number required to reach the highest autocorrelation peak is recorded, and the sequence cycle shift number is the acquisition time difference compensation value, and the actual time difference is calculated according to the acquisition cycle of the system; The synchronous acquisition module is used for accessing external multi-channel sensor signals after the system enters the synchronous acquisition mode, and shifting and compensating the data stream acquired by other ADCs according to the acquisition time difference compensation value, and outputting the multi-ADC chip acquisition data after time difference compensation.

[0027] The application further provides a device for realizing the adaptive synchronization method of acquisition time difference between multi-ADC chips, and a device module structure diagram is shown in the figure, Figure 2 which mainly comprises an MCU master control unit, a sigma-delta type ADC, a SAR-ADC, a PN sequence input module and external multi-channel sensors. The MCU chip module adopts a GD32F407ZGT6 chip with a Cortex-M4 architecture, and realizes the following core functions: controlling acquisition mode conversion, configuring and triggering ADC acquisition, reading ADC conversion data and executing adaptive acquisition time difference estimation and compensation algorithms. The sigma-delta type ADC module adopts an ADS1274 chip, which is a 24-bit 4-channel synchronous ADC, and the internal execution module comprises a sigma-delta modulator and a digital filter, and the key analog acquisition pulse is generated internally and is not directly controlled externally. The architecture results in a long group delay introduced by the modulator and the digital filter, which cannot be ignored. The chip comprises high-speed, high-resolution, low-power and low-speed four modes, and different modes correspond to different acquisition frequencies, and the highest sampling rate is 144KSPS. The SAR-ADC directly uses the built-in 12-bit SAR-ADC resource of the MCU chip, adopts a successive approximation architecture, and the conversion process is accurately started by an external trigger signal, so that nanosecond-level inter-channel synchronization accuracy can be realized, and the highest sampling rate is 2.4MSPS. The PN sequence input module is realized by software programming of the MCU in the system, and is used to generate a PN sequence with sharp autocorrelation characteristics, and the sequence is used as a reference signal for measuring the acquisition time difference. The sensor module is responsible for accessing external multi-channel sensor signals, and the system enters the synchronous acquisition mode after the time difference compensation value is calculated, and the multi-ADC chip module acquires the sensor input signals in the mode.

[0028] Due to the essential difference in sampling mechanism and sampling rate between the sigma-delta ADC and the SAR-ADC, and the completely different timing control modes of the two, if the two chips are directly used for parallel collection, there will be a long collection time difference that cannot achieve synchronous collection. It should be noted that the ADC selection involved in the present system includes but is not limited to the above two chips, and other ADCs that meet the technical requirements are also applicable to the adaptive time difference estimation and collection synchronization method described in the present application under the same technical conditions.

[0029] The flow chart of the collection synchronization system in the present application is shown in Figure 1 , and the main steps are as follows: (1) System initialization and parameter configuration. The microcontroller starts the system, and configures the relevant parameters of the collection according to different ADC selection and mode setting, etc.

[0030] (2) The system generates a pseudo-random (PN) code sequence of a specific length as a reference signal for measuring the collection time difference, configures the timer hardware interrupt of the microcontroller, each interrupt period accurately corresponds to the duration of one PN chip, triggers the linear feedback shift register (LFSR) to update in real time, and generates a PN sequence with sharp autocorrelation characteristics.

[0031] PN sequence The expression is as formula (1): (1) In the formula, is a PN sequence with a length of , n is the number of stages of the linear feedback shift register; m {0,1}, when , the output pulse amplitude is , when , the output pulse amplitude is 0; is the pulse shape of the PN sequence; is the symbol duration , is the clock frequency of the shift register, that is, an output symbol is updated every second; represents the time shift of the pulse waveform, which ensures that each symbol is arranged in order on the time axis; the length of the sequence is usually set according to the maximum expected time difference of the system, and needs to meet , is the maximum estimated time difference. (3) The generated PN sequence signal is input in parallel to different ADC collection channels to be synchronized. The microcontroller controls or triggers the ADC to start analog-to-digital conversion of the input PN sequence signal at the same time, and reads the original collection data of each channel.

[0032] ​

[0033] In the specific implementation of the present application, a PN sequence with a sequence length of 2^19 is generated by a 6-stage LFSR, and a primitive polynomial is used as a feedback polynomial. The sampling frequency of the Σ-Δ ADC is 10547 SPS, and the m-sequence symbol duration is configured as 200 , so that each symbol is collected at least twice. By repeatedly collecting two groups of PN sequences, the data reliability is further enhanced.

[0034] Figure 3 The waveform comparison results of the same PN sequence collected by different ADC chips are shown. The data length is 252 sampling points. It can be observed from the comparison that the two-channel waveforms have the same sequence pattern but have obvious phase shifts, which directly reflects the collection time difference between the ADC chips. The sharp square wave edge verifies the autocorrelation characteristics of the PN sequence, providing an ideal measurement signal for subsequent time difference estimation.

[0035] (4) Preprocessing of data and adaptive collection time difference estimation. After obtaining the PN sequence data output by different ADCs through analog-to-digital conversion, the collection values are converted to code values by setting a threshold. The original data is binarized to simplify the subsequent operation complexity and improve the processing efficiency. The PN sequence collected by the SAR-ADC is taken as the reference chip stream, and the sequence chip collected by the Σ-Δ ADC is cyclically shifted relative to the reference sequence. After each shift operation (step size is one sampling period), the system calculates the autocorrelation value of the reference sequence. Based on the sharp and unique characteristics of the autocorrelation peak of the PN sequence, the significant peak position of the autocorrelation function is detected and located. The peak corresponds to the best chip alignment position between the two sequences.

[0036] Autocorrelation function of two sequences is expressed as formula (2): (2) In the formula, d is the cyclic shift amount, indicating the number of sampling points by which the sequence is shifted. N is the actual sampling sequence length, which needs to satisfy to ensure that the complete PN sequence period is included. is the best alignment point at which the autocorrelation function reaches the maximum value.

[0037] is the sampling sequence of the PN sequence collected by the SAR-ADC and binarized, which is obtained by sampling at intervals : (3) In the formula, it needs to satisfy This condition prevents spectral aliasing of the chip waveform during the sampling process.

[0038] This is a sampled sequence of a Σ-Δ type ADC that has been discretely sampled and binarized from a PN sequence, containing the time difference of the signal to be estimated. It is also composed of... With intervals The sampling yielded: (4) In the formula, To estimate the time difference, periodic extension is used in the actual autocorrelation calculation, and cyclic shift calculation is performed.

[0039] (5) Calculation of time difference compensation value. Determine if a significant correlation peak is detected. If detected, the system determines the current data is valid and the time difference estimation is feasible, proceeding to compensation value calculation; if not detected, the system determines the current measurement may be invalid. In this case, the system adaptively triggers an error handling process, discarding the current data and returning to step (2) to regenerate the PN sequence. This is achieved by finding the correlation function. To determine the location of the global maximum value. : (5) When the cyclic shift amount d When the acquisition time difference is equal to the number of sampling points, the two sequences reach the optimal alignment position. Obtain the theoretical maximum value of the autocorrelation function N .

[0040] (6) Record the cyclic shift amount required for the Σ-Δ ADC acquisition sequence to reach the maximum correlation peak. d According to the collection cycle Calculate the time difference This value is determined by The time difference in acquisition between different ADC chips is caused by the filter processing link and the transmission acquisition circuit.

[0041] In a specific implementation of this invention, the test results of the acquisition time difference estimation and compensation are shown in the appendix. Figure 4 , Figure 5 As shown, the sharp single-peak characteristic verifies the advantages of the autocorrelation properties of the PN sequence, and the peak position is the acquisition time difference between the two ADC chips. Data stream shift compensation based on the fixed compensation value determined by correlation analysis can effectively eliminate the acquisition time difference between the ADC chips, achieving strict synchronization of data at the effective sampling time.

[0042] (7) The system enters the synchronous acquisition mode. The multi-channel sensor input signal is used, the SAR-ADC data stream directly enters the output buffer, the data stream of the sigma-delta type ADC is superimposed with a fixed compensation value, and different ADC data streams after synchronization are continuously output for subsequent signal processing or control system use.

[0043] The specific example of the application can realize adaptive estimation and synchronous acquisition of the acquisition time difference between multiple ADC chips through the above steps. The verification method is as follows: by inputting the same 1KHz sine wave signal into the SAR-ADC and the sigma-delta type ADC, the original asynchronous acquisition data and the acquisition data after synchronous processing of the method are compared, and the implementation effect is shown in the attached Figure 6 The analysis result shows that there is an acquisition time difference of about 39 acquisition cycles in the original asynchronous acquisition data. After applying the adaptive estimation and compensation algorithm of the application, the accurate synchronization of the acquisition data between different ADC chips is successfully realized.

[0044] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A method for adaptive synchronization of inter-chip acquisition time difference of multiple ADCs, comprising: The method comprises the following steps: S1, generating a collection time difference measurement signal; In the initialization stage or when recalibration is required, the linear feedback shift register is triggered to update the PN sequence signal in real time by configuring the hardware timer interrupt of the microcontroller; the PN sequence signal is a pseudo-random noise code with sharp autocorrelation characteristics; S2, simultaneously triggering multi-ADC chip analog-to-digital conversion; The PN sequence signal is simultaneously input to the collection channels of the multi-ADC chips to be synchronized; The microcontroller is used to control or trigger the multi-ADC chips to simultaneously start analog-to-digital conversion on the same PN sequence signal input, so as to obtain the PN sequence original collection data of each channel; S3, estimating the collection time difference; The PN sequence original collection data collected by the multi-ADC chips are subjected to binaryzation preprocessing, one of the binaryzation sequences collected by the ADCs is selected as a reference sequence, the binaryzation sequences collected by the other ADCs are cyclically shifted relative to the reference sequence, and the autocorrelation values of the sequences collected by the other ADCs relative to the reference sequence are calculated bit by bit; the autocorrelation values under all shift amounts are obtained and recorded, so as to form a complete autocorrelation function; S4, collection time difference compensation value calculation; The peak point position of the autocorrelation function is detected to estimate the collection time difference between the ADCs; the peak point position is the state of the best alignment with the reference sequence; The sequence cyclic shift number required to reach the highest autocorrelation peak is recorded, and the sequence cyclic shift number is the collection time difference compensation value; S5, collection time difference compensation and synchronous collection After entering the synchronous collection mode, the collection data stream of the reference ADC is input to the output buffer, and the collection data streams of the other ADCs are shifted and compensated according to the collection time difference compensation value, so as to output the synchronous multi-ADC chip collection data after time difference compensation.

2. The method of adaptive synchronization of inter-chip acquisition time difference of multiple ADCs of claim 1, wherein, S1 specifically comprises the following steps: A pseudo-random code sequence with a specific length is generated as a reference signal for collection time difference measurement, the timer hardware interrupt of the microcontroller is configured, each interrupt period corresponds to the duration of one PN chip, the linear feedback shift register is triggered to update in real time, and a PN sequence with sharp autocorrelation characteristics is generated; PN sequence The expression is as follows: (1) wherein, is a PN sequence of length , m is the number of stages of the linear feedback shift register; {0,1} when , the output pulse amplitude is , when , the output pulse amplitude is 0; is the pulse shape of the PN sequence; is the symbol duration , is the clock frequency of the shift register, i.e. one output symbol is updated every seconds; represents the time shift of the pulse waveform, so that each symbol is sequentially arranged on the time axis; the length of the sequence is usually set according to the maximum expected time difference of the system, and needs to satisfy , is the maximum estimated time difference.

3. The method of adaptive synchronization of inter-chip acquisition time difference of multiple ADCs of claim 1, wherein, S3 specifically comprises the following steps: The data is preprocessed and adaptive acquisition time difference is estimated; after acquiring PN sequence data output by different ADCs, the acquisition value is converted into code value by setting threshold The original data is binarized One of the PN sequences collected by the ADCs is selected as a reference chip stream, the sequence chips collected by the remaining ADCs are cyclically shifted relative to the reference sequence, and the autocorrelation values of the sequence chips relative to the reference sequence are calculated after each shift operation; based on the sharp and unique characteristics of the autocorrelation peak of the PN sequence, the significant peak point position of the autocorrelation function is detected and located, and the peak corresponds to the best chip alignment position between the two sequences; Two sequence autocorrelation functions The expression is as follows: (2) In the formula, d is a cyclic shift amount, representing the number of sample points by which the sequence is shifted; N is the actual sample sequence length, to ensure that the complete PN sequence period is included; to make the optimal alignment point at which the autocorrelation function attains a maximum. The sampling sequence of the PN sequence which is discretely sampled by the reference ADC and is binarized is denoted by At intervals of The sampling sequence is obtained as (3) In the formula, to avoid spectral aliasing of the chip waveform during sampling; The sampling sequence is the discrete sampling of the PN sequence and the binary processing of the sampling sequence to be synchronized with the ADC, containing the signal time difference to be estimated. At intervals The sampling is obtained: (4) In the formula, The time difference to be estimated is denoted by T, and the period extension is used in the actual autocorrelation operation to perform the cyclic shift calculation.

4. The method of adaptive synchronization of inter-chip acquisition time difference of multiple ADCs of claim 1, wherein, S4 specifically comprises the following steps: Acquisition time difference compensation value calculation; determine whether to detect a significant correlation peak position, if detected, the system determines that the current data is valid, the time difference estimation is feasible, and enters the compensation value calculation; if not detected, the system determines that the current data is invalid, triggers an error handling process, discards the current data, and returns to S2 to regenerate the PN sequence; by finding the global maximum position of the correlation function to determine : (5) When the cyclic shift amount d is equal to the acquisition time difference in number of samples, the two sequences reach the optimal alignment position, at which the theoretical maximum of the correlation function is obtained N .

5. A multi-ADC inter-chip acquisition time difference synchronization system for implementing the multi-ADC inter-chip acquisition time difference adaptive synchronization method of any one of claims 1-4, characterized in that, It comprises: A collection time difference measurement signal generation module for generating a pseudo-random noise code sequence with sharp autocorrelation characteristics as a reference signal for collection time difference measurement; The collection time difference measurement signal generation module triggers the linear feedback shift register to update the PN sequence signal in real time by configuring the hardware timer interrupt of the microcontroller; The ADC chip control and trigger module is used for inputting the generated PN sequence signal to the acquisition channels of the multiple ADC chips to be synchronized at the same time, and controlling or triggering the multiple ADC chips to start analog-digital conversion on the input same PN sequence signal at the same time, so as to obtain the PN sequence original acquisition data of respective channels; The acquisition time difference estimation module is used for binarizing the PN sequence original acquisition data collected by the multiple ADC chips, selecting a binarized sequence collected by one of the ADCs as a reference sequence, cyclically shifting the binarized sequences collected by other ADCs relative to the reference sequence, and calculating the autocorrelation values of the sequences collected by other ADCs relative to the reference sequence bit by bit; The acquisition time difference compensation module is used for adaptively determining the acquisition time difference between the ADCs based on the autocorrelation function by detecting the peak point position of the correlation function; The sequence cyclic shift number required to reach the highest autocorrelation peak is recorded, and the sequence cyclic shift number is the acquisition time difference compensation value, and the actual time difference is calculated according to the acquisition period of the system; The synchronous acquisition module is used for accessing external multiple sensor signals after the system enters the synchronous acquisition mode, and shifting and compensating the data streams collected by other ADCs according to the acquisition time difference compensation value, and outputting the multiple ADC chip acquisition data after time difference compensation.

6. A storage medium, characterized by The storage medium includes a stored program, wherein the program runs to execute the adaptive synchronization method of the acquisition time difference between the multiple ADC chips in any one of claims 1 to 4.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the adaptive synchronization method of the acquisition time difference between the multiple ADC chips in any one of claims 1 to 4 by running the computer program.

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