Video time sequence generation method and device, electronic equipment and storage medium

Abstract

The invention provides a video time sequence generation method and device, electronic equipment and a storage medium, and belongs to the technical field of data processing. The method is applied to a main control chip of the display equipment, and comprises the following steps: in response to a received video signal which comprises video data and a video time sequence, judging whether a cache region corresponding to the video data meets a preset condition or not; determining a target value of a vertical total row number according to an input field frequency corresponding to a video time sequence and a display parameter of a display device under the condition that the cache region meets a preset condition, and generating a target row synchronization signal corresponding to a field synchronization signal in the video time sequence according to the target value; and generating a target video time sequence according to the target line synchronization signal and the field synchronization signal, wherein the target video time sequence is used for displaying a video picture by the display device. According to the embodiment of the invention, the compatibility of the main control chip to the display equipment can be improved under the condition that the cache resources of the video data are limited.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data processing, and particularly relates to a video timing generation method and device, electronic equipment and computer readable storage medium. BACKGROUND

[0002] In the process of video display, a chip is arranged in a display to receive a video signal, and the video signal is converted and then sent to a display main control chip of the display screen through a corresponding port such as an LVDS interface.

[0003] In order to reduce the jitter of the output clock, the display main control chip generates the output clock based on the local clock rather than the input clock after receiving the video signal. In this case, if a small cache space is used to cache the received video data, the display main control chip needs to keep the input frame rate consistent with the output frame rate. However, due to the influence of the local clock, in order to ensure the consistency of the input and output frame rates, the video timing output by the display main control chip will have a vertical total line number deviation, that is, the line frequency of some lines is higher than that of other lines. The display screen cannot receive data with higher line frequency, so the display screen cannot effectively receive the video signal, thereby reducing the compatibility of the display main control chip to the display screen. SUMMARY

[0004] Therefore, the present disclosure provides a video timing generation method to solve the problem that the display main control chip generates the output clock based on the local clock in the case of limited cache resources, resulting in a deviation of the generated video timing and poor compatibility to the display screen.

[0005] To achieve the above object, the first aspect of the present disclosure provides a video timing generation method, which is applied to a main control chip of a display device, and the method comprises the following steps: in response to receiving a video signal, the video signal comprising video data and video timing, judging whether a cache area corresponding to the video data meets a preset condition; in the case that the cache area meets the preset condition, determining a target value of a vertical total line number according to an input field frequency corresponding to the video timing and display parameters of the display device, generating a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value; generating a target video timing according to the target line synchronization signal and the field synchronization signal, the target video timing being used for the display device to display a video picture.

[0006] In an optional implementation, the display parameter comprises a clock frequency value of the display device and a horizontal total pixel value of the display device, and the determining of the target value of the vertical total line number according to the input field frequency corresponding to the video timing and the display parameter of the display device comprises: determining a first processing value as a product of the input field frequency and the horizontal total pixel value; determining a second processing value according to a ratio between the clock frequency value and the first processing value; and determining the target value of the vertical total line number according to the second processing value, wherein the target value is an integer value not greater than the second processing value.

[0007] In an optional implementation, the number of the field synchronization signals is multiple, and the generating of the target line synchronization signal corresponding to the field synchronization signal in the video timing according to the target value comprises: for any field synchronization signal, generating the target value of target line synchronization signals corresponding to the field synchronization signal.

[0008] In an optional implementation, the generating of the target value of target line synchronization signals corresponding to the field synchronization signal comprises: generating a first target line synchronization signal corresponding to the field synchronization signal at a starting time point of the field synchronization signal, and generating a target line synchronization signal every preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal are generated.

[0009] In an optional implementation, the number of the generated target line synchronization signals is accumulated by a first counter, and the generating of a target line synchronization signal every preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal are generated comprises: acquiring a count value of the first counter every preset time interval, and in a case that the count value is less than the target value, generating a target line synchronization signal and increasing the count value; and in a case that the count value is equal to the target value, stopping the generation of the target line synchronization signal and resetting the count value of the first counter at a starting time point of a next field synchronization signal.

[0010] In an optional implementation, the judging of whether the buffer area corresponding to the video data satisfies a preset condition comprises: in a case that the buffer area corresponding to the video data belongs to an on-chip memory area or a region size of the buffer area is not greater than a preset region threshold, determining that the buffer area corresponding to the video data satisfies the preset condition.

[0011] In an optional implementation, after the target video timing is generated according to the target line synchronization signal and the field synchronization signal, the method further includes: generating a target video clock matching the clock frequency value of the display device according to the local clock of the master chip; and generating a target video signal according to the target video timing, the video data and the target video clock, so that the display device displays a video picture according to the target video signal.

[0012] In a second aspect, the present disclosure provides a video timing generation apparatus, which is applied to a master chip of a display device, and includes: a judging module configured to, in response to receiving a video signal, judge whether a buffer area corresponding to video data of the video signal satisfies a preset condition, the video signal including the video data and a video timing; a first generation module configured to, in a case where the buffer area satisfies the preset condition, determine a target value of a total number of vertical lines according to an input field frequency corresponding to the video timing and display parameters of the display device, and generate a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value; and a second generation module configured to generate a target video timing according to the target line synchronization signal and the field synchronization signal, the target video timing being used for the display device to display a video picture.

[0013] In a third aspect, the present disclosure provides an electronic device, which includes: one or more processors; a memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the video timing generation method described above; and one or more I / O interfaces connected between the processor and the memory and configured to implement information interaction between the processor and the memory.

[0014] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, the program, when executed by a processor, implements the video timing generation method described above.

[0015] The present disclosure has the following advantages:

[0016] The present disclosure provides a video timing generation method, which first judges whether a buffer area corresponding to video data of a video signal satisfies a preset condition in response to receiving the video signal, the video signal including the video data and a video timing; secondly, in a case where the buffer area satisfies the preset condition, determines a target value of a total number of vertical lines according to an input field frequency corresponding to the video timing and display parameters of a display device, and generates a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value; and finally, generates a target video timing according to the target line synchronization signal and the field synchronization signal, the target video timing being used for the display device to display a video picture.

[0017] It can be seen that in the case that the preset condition of the buffer area corresponding to the video data is met, for example, in the case that the video data is buffered in a smaller buffer interval, the target value of the total number of vertical lines is determined by the input field frequency corresponding to the input video signal and the display parameter of the display device. Correspondingly, the target line synchronization signal is generated according to the target value, and the target video timing is generated according to the target line synchronization signal and the field synchronization signal in the received video timing. Since the target video timing is generated according to the determined target value of the total number of vertical lines, and the target value is dynamically determined according to the input field frequency and the display parameter of the display device, the target video timing generated by the master control chip can enable the display screen to receive and process, and avoid the case that the display screen cannot effectively receive the video signal due to the deviation of the total number of vertical lines in the target video timing. Therefore, the master control chip can generate the video timing that can be received by the display device such as a display screen in the case of using a smaller buffer interval, so that the display screen can normally display the video picture, and the compatibility of the master control chip to the display device is improved.

[0018] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the embodiments of the present disclosure are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of the specific example embodiments, with reference to the accompanying drawings, in which:

[0020] Figure 1 A flowchart of a video timing generation method provided by an embodiment of the present disclosure;

[0021] Figure 2 A flowchart of a video timing generation method provided by an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of the master control chip generating a target line synchronization signal in an embodiment of the present disclosure;

[0023] Figure 4 A flowchart of a video timing generation method provided by an embodiment of the present disclosure;

[0024] Figure 5 A flowchart of a video timing generation method provided by an embodiment of the present disclosure;

[0025] Figure 6A flowchart of a video timing generation method provided by an embodiment of the present disclosure is shown in FIG. 1.

[0026] Figure 7 A block diagram of a video timing generation apparatus provided by an embodiment of the present disclosure is shown in FIG. 2.

[0027] Figure 8 A block diagram of an electronic device provided by an embodiment of the present disclosure is shown in FIG. 3. DETAILED DESCRIPTION

[0028] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to explain and illustrate the present disclosure, and are not intended to limit the present disclosure.

[0029] As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] The terms used in the present disclosure are only used to describe specific embodiments, and are not intended to limit the present disclosure. As used in the present disclosure, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0031] When the terms "comprise" and / or "consist of" are used in the present disclosure, it is specified that the features, integers, steps, operations, elements, and / or components exist, but it does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise defined, all terms used in the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined in the present disclosure.

[0033] In the video display process, a chip is set in the display to receive the video signal, i.e., the video signal transmitted by a video transmission interface such as a VGA, HDMI or DP interface is received by the chip, and the chip transmits the video signal to the display main control chip of the display screen after conversion processing.

[0034] The display master chip of the display screen receives the video signal sent by the above chip based on the LVDS interface, and needs to regenerate the video signal that the display screen can receive according to the received video signal, such as regenerating the video timing, the video clock and the video data. The video data and the video timing correspond to each other, and a relatively large cache resource is needed to process the video data. In the case of limited cache resource, the display master chip may not be able to make the generated video data, video timing and video clock meet the display requirements of the display screen at the same time.

[0035] In actual application, in order to reduce the jitter of the output clock, the display master chip generates the output clock based on the local clock rather than the received input clock when the video clock and the video data meet the receiving requirements of the display screen. In the case of processing the video data with a small cache resource, the input frame rate of the display master chip must be consistent with the output frame rate, and the output frame rate, the output clock frequency, the output horizontal total pixel value and the output vertical total line value need to meet a preset numerical relationship. Therefore, when the frame rate is fixed, the output vertical total line value or the output horizontal total pixel value may be a small value to meet the preset numerical relationship.

[0036] Generally, in the above case, there is a deviation in the vertical total line value in the video timing output by the display master chip, that is, the line frequency of some lines is higher than that of other lines or the horizontal total pixel points of some lines are less than those of other lines. When the line frequency of some lines is much higher than that of other lines, the display screen cannot receive data with too high line frequency, thereby affecting the normal display of the video picture by the display screen and reducing the compatibility of the display master chip to the display screen.

[0037] Therefore, the embodiment of the present disclosure provides a video timing generation method, which can determine a target value of the vertical total line value by using the input field frequency corresponding to the input video signal and the display parameter of the display device when the cache area corresponding to the video data meets a preset condition, for example, when a small cache area is used to cache the video data. Correspondingly, the embodiment of the present disclosure can generate a target line synchronization signal according to the target value, and generate a target video timing according to the target line synchronization signal and the field synchronization signal in the received video timing. Since the target video timing is generated according to the target value of the vertical total line value, and the target value is dynamically determined according to the input field frequency and the display parameter of the display device, the target video timing generated by the master chip can be received and processed by the display screen, avoiding the case that the display screen cannot effectively receive the video signal due to the deviation of the vertical total line value in the target video timing. Therefore, the embodiment of the present disclosure can make the master chip generate the video timing that can be received by the display device such as the display screen when a small cache area is used, so that the display screen can normally display the video picture, and the compatibility of the master chip to the display device is improved.

[0038] In a first aspect, the embodiments of the present disclosure provide a video timing generation method. The method is applied to a master chip of a display device, wherein the display device is used to display a video picture, and the display device can be a display screen. The master chip of the display device is a display master chip that receives and processes a video signal in the display device.

[0039] Figure 1 A flowchart of the video timing generation method provided by the embodiments of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the method comprises the following steps. Figure 1

[0040] In step S110, in response to receiving a video signal, it is determined whether a buffer area corresponding to video data satisfies a preset condition, wherein the video signal comprises the video data and video timing.

[0041] The video signal is an input video signal of the master chip of the display device, for example, an input video signal received through an LDVS interface. Specifically, the video signal can comprise video data, video timing and a video clock.

[0042] The video data is used to represent the content of the video picture, such as the luminance and color data of pixels. The video timing is used to represent the transmission and display order of the data. Specifically, the video timing can comprise a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC. The video clock is used to represent the synchronization reference of data transmission.

[0043] The determination of whether the buffer area corresponding to the video data satisfies the preset condition means the determination of whether the buffer area corresponding to the video data is a buffer area with a small buffer space. Since the master chip generates an output clock based on a local clock, when a small buffer area is used to process the video data, in order to ensure that the input frame rate of the master chip is consistent with the output frame rate, the video timing generated by the master chip will have a vertical total line number deviation, thereby affecting the data reception of the display device such as the display screen.

[0044] Therefore, the embodiments of the present disclosure determine whether the buffer area corresponding to the video data satisfies the preset condition after receiving the video signal, so as to determine the target value of the vertical total line number according to the determination result, for example, in the case where the buffer area satisfies the preset condition. Thus, the generated video timing satisfies the reception requirement of the display screen.

[0045] In an optional implementation, in order to accurately determine whether the buffer area corresponding to the video data is a buffer area with a small buffer space, the condition can be determined according to the area type of the buffer area or the area size of the buffer area.

[0046] Correspondingly, Figure 2 ​A flowchart of a video timing generation method is shown, and the method is provided by an embodiment of the present disclosure. Referring to Figure 2 In step S110, in response to receiving the video signal, the video signal including the video data and the video timing, it is determined whether the buffer area corresponding to the video data meets the preset condition, which can include:

[0047] In step S111, in response to receiving the video signal, the video signal including the video data and the video timing, if the buffer area corresponding to the video data belongs to the on-chip memory area, or the area size of the buffer area does not exceed the preset area threshold, it is determined that the buffer area corresponding to the video data meets the preset condition.

[0048] In the case where the buffer area corresponding to the video data belongs to the on-chip memory area, since the storage space of the on-chip memory area is small, it is impossible to realize frame buffering of the video data, so in this case, it can be determined that the buffer area corresponding to the video data meets the preset condition. In the case where the area size of the buffer area does not exceed the preset area threshold, at this time, it can also be determined that the storage space of the buffer area is small, which is impossible to realize frame buffering of the video data, so in this case, it can be determined that the buffer area corresponding to the video data meets the preset condition.

[0049] It should be noted that the threshold size of the preset area threshold can be adaptively set according to actual needs, and the present disclosure does not limit this.

[0050] In step S120, in the case where the buffer area meets the preset condition, the target value of the total number of vertical lines is determined according to the input field frequency corresponding to the video timing and the display parameters of the display device, and the target line synchronization signal corresponding to the field synchronization signal in the video timing is generated according to the target value.

[0051] The input field frequency corresponding to the video timing refers to the number of times of receiving the field synchronization signal per second when receiving the video signal. Specifically, it can be obtained by counting the field synchronization signal in the received video timing.

[0052] The display parameters of the display device are used to represent the parameter requirements of the display device when displaying the video picture. Specifically, the display parameters can include the clock frequency value of the display device and the total number of horizontal pixels of the display device.

[0053] The total number of vertical lines refers to the total number of scanning lines from the start of a field timing to the start of the next field timing in a frame. Since the input field frequency, the display parameters and the total number of vertical lines have a preset numerical relationship, the target value of the total number of vertical lines can be determined according to the input field frequency and the display parameters of the display device.

[0054] Specifically, the matching value of the total vertical lines can be determined according to a preset numerical relationship among the input field frequency, the display parameter and the total vertical lines. The matching value is generally a decimal value due to the influence of the master control chip generating the output clock based on the local clock. Accordingly, the target value of the total vertical lines is determined according to the matching value, which is an integer value not greater than the matching value.

[0055] Therefore, after the target value of the total vertical lines is determined, the embodiment of the disclosure can generate a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value. That is, the embodiment of the disclosure can limit the number of target line synchronization signals corresponding to the field synchronization signal according to the target value of the total vertical lines, so that the line frequency of the generated target line synchronization signal meets the receiving requirements of the display device.

[0056] Therefore, the master control chip of the display device can generate a target line synchronization signal corresponding to a field synchronization signal in the received video timing according to the target value of the total vertical lines based on the field synchronization signal in the received video timing, so that the line frequency of the target line synchronization signal meets the receiving requirements of the display device.

[0057] In an alternative implementation, in order to accurately determine the target value of the total vertical lines so that the line frequency in the target video timing generated by the master control chip meets the receiving requirements of the display device, a matching value of the total vertical lines can be determined according to a preset numerical relationship among the total vertical lines, the input field frequency and the display parameter, and the target value of the total vertical lines is obtained by performing a downward rounding processing on the matching value of the total vertical lines.

[0058] Specifically, referring to Figure 2 the display parameter includes a clock frequency value of the display device and a total horizontal pixel value of the display device, and the target value of the total vertical lines is determined according to the input field frequency corresponding to the video timing and the display parameter of the display device in the case that the preset condition is met in the cache area, including:

[0059] Step S121: determining a product of the input field frequency corresponding to the video timing and the total horizontal pixel value of the display device to obtain a first processing value in the case that the preset condition is met in the cache area.

[0060] Step S122: obtaining a second processing value according to a ratio between the clock frequency value of the display device and the first processing value.

[0061] Step S123: determining the target value of the total vertical lines according to the second processing value, wherein the target value is an integer value not greater than the second processing value.

[0062] Specifically, the horizontal total pixel value of the display device can also be referred to as the horizontal total pixel number of the display device, which is used to represent the total number of pixels in a single horizontal scanning line from the timing start of a row to the timing start of the next row. The first processing value is the product of the input field frequency f and the horizontal total pixel value HT, that is, the first processing value is HT x f. The second processing value is obtained according to the ratio between the clock frequency value Fclk and the first processing value, that is, the second processing value is Fclk / (HT x f), which is the matching value of the vertical total number of rows.

[0063] In the case where the master control chip generates an output clock using a local clock, the second processing value is generally a non-integer value, and in order to enable the target value of the vertical total number of rows to enable the generated video timing to meet the receiving requirements of the display device, the target value of the vertical total number of rows can be determined to be an integer value not greater than the second processing value. For example, the integer part of the second processing value is directly taken as the target value of the vertical total number of rows.

[0064] Since the target value of the vertical total number of rows is an integer value, and the target value of the vertical total number of rows is not greater than the second processing value, that is, the matching value of the vertical total number of rows, when generating the target row synchronization signal according to the target value of the vertical total number of rows, it will not cause the number of row synchronization signals to be too high, thereby causing the horizontal frequency of some rows to be higher than that of other rows when the field video signal is reset.

[0065] In an optional implementation, the number of field synchronization signals is multiple, and in order to limit the number of signal generation of the target row synchronization signal based on the target value of the vertical total number of rows, continuing to refer to Figure 2 , the step S120 of generating the target row synchronization signal corresponding to the field synchronization signal in the video timing according to the target value can include:

[0066] Step S124: For any field synchronization signal, generate target value target row synchronization signals corresponding to the field synchronization signal.

[0067] Among them, for any field synchronization signal, the first corresponding target row synchronization signal can be generated at the starting time of the field synchronization signal, and one target row synchronization signal is uniformly generated according to a preset time interval, so that the target value target row synchronization signals are finally generated. That is, in the embodiment of the present disclosure, the master control chip can uniformly generate target value target row synchronization signals for any field synchronization signal.

[0068] In order to facilitate understanding, Figure 3 A schematic diagram of the master control chip generating the target row synchronization signal is shown. Referring to Figure 3Wherein, when the video timing is generated without using the target value of the total number of vertical lines, the output frame rate of the master chip needs to be exactly the same as the input frame rate. The video frame rate = clock frequency / (total number of horizontal pixels * total number of vertical lines). In order to satisfy the frame rate, the input clock frequency / (input total number of horizontal pixels * input total number of vertical lines) = output clock frequency / (output total number of horizontal pixels * output total number of vertical lines).

[0069] Since the master chip generates the output clock through the local clock, it is difficult to satisfy the above equation when the output total number of horizontal pixels and the output total number of vertical lines are integers, that is, the output total number of horizontal pixels or the output total number of vertical lines is a decimal value. The above situation usually causes the total number of vertical lines to deviate.

[0070] Referring to the (a) part in Figure 3 , n+1 line synchronization signals HSYNC need to be generated for a certain field synchronization signal VSYNC. Since the output frame rate needs to be exactly the same as the input frame rate, at a certain time, the output field synchronization signal VSYNC needs to be reset according to the input timing, and the line synchronization signal HSYNC needs to correspond to the field synchronization signal VSYNC at this time. In this case, the horizontal frequency of a certain line is greater than that of other lines, that is, the number of horizontal pixels of the line is inconsistent with that of other lines.

[0071] For example, referring to the circled area in the (a) part in Figure 3 , due to the reset of the field synchronization signal VSYNC, the corresponding line synchronization signal HSYNC needs to be generated at the starting time of the field synchronization signal VSYNC, so that the horizontal frequency of the target line is greater than that of other lines.

[0072] The second processing value is determined by the input field frequency, the total number of horizontal pixels of the display device, and the clock frequency value. The second processing value is the matching value of the total number of vertical lines, which is usually a decimal value. The target value of the total number of vertical lines is determined by the second processing value. For example, the integer value of the second processing value is taken as the target value of the total number of vertical lines. Correspondingly, the target value of the total number of vertical lines is not greater than the integer value of the second processing value. Therefore, the target line synchronization signal generated according to the target value will not appear when the field synchronization signal is reset, so that the horizontal frequency of the target line is higher than that of other lines.

[0073] Referring to the circled area in the (b) part in Figure 3 , the master chip is limited by the target value of the total number of vertical lines. n+1 line synchronization signals are generated for each field synchronization signal, which is changed to n line synchronization signals for each field synchronization signal. Therefore, in this case, when the master chip generates the line synchronization signal, the target line with fewer horizontal pixels than other lines can be combined with other lines, so that the horizontal frequency of the target line is lower than that of other lines, and the display device can normally receive.

[0074] Step S130: Generate target video timing based on target line synchronization signal and field synchronization signal. Target video timing is used by the display device to display video images.

[0075] The target video timing sequence consists of a target horizontal synchronization signal and a field synchronization signal from the received video timing sequence. Since the target horizontal synchronization signal is generated based on a predetermined target value for the total number of vertical lines, there will be no situation where the horizontal frequency of some lines is higher than that of others. Accordingly, this target video timing sequence enables the display device to receive and display the video image correctly.

[0076] In one alternative implementation, continue to refer to Figure 2 After generating the target video timing sequence based on the target line synchronization signal and the field synchronization signal in step S130, the method further includes:

[0077] Step S140: Generate a target video clock that matches the clock frequency value of the display device based on the local clock of the main control chip.

[0078] Step S150: Generate a target video signal based on the target video timing, video data, and target video clock, so that the display device displays the video image according to the target video signal.

[0079] The main control chip needs to generate a target video signal for the display device based on the input video signal. The target video signal includes the target video timing sequence, video data, and a target video clock. Therefore, the main control chip generates a target video clock that matches its local clock and the clock frequency of the display device. The target video clock is the time reference signal, used to characterize the time base for pixel transmission. This target video clock enables the display device to accurately receive and display each pixel's data, preventing image misalignment or distortion.

[0080] After generating the target video timing and target video clock, the target video signal can be obtained based on the target video timing, target video clock, and video data. Since the target video timing is generated based on the target value of the total number of vertical lines, and the target video clock is also matched with the clock frequency value of the display device, the display device can display the corresponding video image normally after receiving the target video signal.

[0081] The embodiment of the present disclosure provides a video timing generation method, which can determine a target value of the total number of vertical lines by using the input field frequency corresponding to the input video signal and the display parameter of the display device, in the case that the preset condition of the buffer area corresponding to the video data is met, for example, in the case that a smaller buffer interval is used to buffer the video data. Correspondingly, the embodiment of the present disclosure can generate a target line synchronization signal according to the target value, and generate a target video timing according to the target line synchronization signal and the field synchronization signal in the received video timing. Since the target video timing is generated according to the target value of the total number of vertical lines, and the target value is dynamically determined according to the input field frequency and the display parameter of the display device, the target video timing generated by the master control chip can enable the display screen to receive and process, and avoid the case that the display screen cannot effectively receive the video signal due to the deviation of the total number of vertical lines in the target video timing. Therefore, the embodiment of the present disclosure can enable the master control chip to generate the video timing that can be received by the display device such as a display screen in the case of using a smaller buffer interval, so that the display screen can normally display the video picture, and the compatibility of the master control chip to the display device is improved.

[0082] Figure 4 A flowchart of a video timing generation method provided by the embodiment of the present disclosure is shown, and the method is described in detail with reference to Figure 4 In an optional implementation, the step S124 of generating, for any field synchronization signal, the target value of target line synchronization signals corresponding to the field synchronization signal comprises:

[0083] The step S125 comprises: generating, for any field synchronization signal, a first target line synchronization signal corresponding to the field synchronization signal at a starting time point of the field synchronization signal, generating a target line synchronization signal every preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal is generated.

[0084] The starting time point of the field synchronization signal refers to the time point at which the active edge of the field synchronization signal starts to trigger, and is used to represent the time at which a frame picture starts. For example, in the above embodiment, the time point corresponding to the rising edge of the field synchronization signal VSYNC is the starting time point of the field synchronization signal. Figure 3

[0085] The interval size of the preset time interval can be determined according to the total number of horizontal pixels of the display device. The preset time interval is the line period, and the line period has a correlation with the total number of horizontal pixels of the display device and the clock frequency value, so that the pixel transmission of each line is matched with the scanning rhythm. In actual application, the preset time interval can be adaptively set according to application needs, and the embodiment of the present disclosure does not limit this.

[0086] ​Thus, the embodiment of the present disclosure can generate the first target line synchronization signal at the starting moment of the field synchronization signal, and generate a target line synchronization signal every interval of a line period, so that for each received field synchronization signal, a target value of target line synchronization signals are generated correspondingly.

[0087] It should be noted that, Figure 4 The specific implementation details of the remaining steps in the method can refer to the description above, and will not be repeated here.

[0088] In an optional implementation, in order to make the number of generated target line synchronization signals strictly match the target value, the number of generated target line signals can be accumulated based on the first counter, so as to determine whether to generate a target line synchronization signal according to the comparison relationship between the count value and the target value.

[0089] Correspondingly, Figure 5 A flowchart of a video timing generation method provided by an embodiment of the present disclosure is shown, which will be described with reference to Figure 5 The above step S125, for any field synchronization signal, generates the first target line synchronization signal corresponding to the field synchronization signal at the starting moment corresponding to the field synchronization signal, generates a target line synchronization signal every interval of a preset time interval, and generates the target value of target line synchronization signals corresponding to the field synchronization signal, can include:

[0090] Step S126: for any field synchronization signal, the first target line synchronization signal corresponding to the field synchronization signal is generated at the starting moment corresponding to the field synchronization signal, the count value of the first counter is obtained every interval of a preset time interval, and in the case that the count value is less than the target value, a target line synchronization signal is generated and the count value is increased.

[0091] Step S127: in the case that the count value is equal to the target value, the generation of the target line synchronization signal is stopped, and the count value of the first counter is reset at the starting moment of the next field synchronization signal.

[0092] Specifically, for any field synchronization signal, the count value of the first counter can be 1 when the corresponding first target line synchronization signal is generated, so that after a target line synchronization signal is generated every interval of a preset time interval, the count value of the first counter is increased by 1, until the target value of target line synchronization signals is generated, at which time the count value of the first counter is the target value.

[0093] In this case, the generation of the target line synchronization signal will be stopped, that is, all target line synchronization signals corresponding to the field synchronization signal have been generated. Thus, for the next field synchronization signal, the count value of the first counter is reset at the starting moment, such as being reset to 0, so that it continues to generate the corresponding first target line synchronization signal. And after generating the first target line synchronization signal, the count value of the first counter is increased by 1.

[0094] Therefore, the embodiment of the present disclosure can make the number of generated target line synchronization signals strictly match the target value of the total number of vertical lines for each received field synchronization signal by counting the generated target line synchronization signals through the first counter.

[0095] It should be noted that, Figure 5 The specific implementation details of the remaining steps in the above embodiment can be referred to the description above, and will not be repeated here.

[0096] For ease of understanding, the specific implementation details of the above implementation mode are described below with an example.

[0097] In the related art, in the case of using a very small cache area to process video data, the output frame rate and the input frame rate of the display master control chip need to be exactly the same. In actual application, in order to reduce the jitter of the output clock, the source of the output clock needs to be generated by using a local clock instead of using the input clock. In this case, it will cause the output total number of vertical lines or the output total number of horizontal pixels to have a decimal number to meet the frame rate corresponding relationship, thereby causing the total number of vertical lines to have a deviation, that is, one row of horizontal pixel points is less than other rows or one row of line frequency is higher than the line frequency of other rows. The display screen cannot receive data with too high line frequency, and therefore, the display screen cannot normally display the video picture, resulting in poor compatibility of the display master control chip to the display screen.

[0098] Correspondingly, in order to improve the compatibility of the display master control chip to the display screen, a main implementation is based on the frame buffer mode. This mode can make the video timing of the output display screen completely not affected by the received video timing by using a larger cache space to cache the received video data. In the above mode, the quality of the output video clock can be very good, and the generated video timing can also completely guarantee the periodicity. However, the cache space in the above mode must be able to store at least one frame of image data, which has a high cost and a one-frame delay, resulting in a large application cost.

[0099] Another mode is to generate a video clock by using a phase-locked loop (PLL) with higher adjustment capability to realize the compatibility of the display master control chip to the display screen. In the above mode, the application cost can be increased by a small amount, and the generated video timing can also be within the acceptable timing range of the display screen. However, the above mode uses a PLL with higher adjustment capability to generate a video clock, which will cause the quality of the generated video clock to decrease, for example, the jitter of the video clock output by the display master control chip will increase, and therefore, the above mode cannot better solve the compatibility problem of the display master control chip to the display screen.

[0100] Therefore, the embodiment of the present disclosure provides a video timing generation method, Figure 6A flowchart of a video timing generation method provided by an embodiment of the present disclosure is shown, referring to Figure 6 The method is applied to a master chip of a display device, wherein the display device can be a display screen, and the master chip can be a display master chip in the display screen, used for receiving and processing a video signal. The method comprises the following steps:

[0101] In step S601, in response to receiving a video signal, the video signal comprising video data and a video timing, if a cache region corresponding to the video data belongs to an on-chip memory region, or a region size of the cache region is not more than a preset region threshold, it is determined that the cache region corresponding to the video data satisfies a preset condition.

[0102] In step S602, if the cache region satisfies the preset condition, a product of an input field frequency corresponding to the video timing and a horizontal total pixel value of the display device is determined to obtain a first processing value; a ratio between a clock frequency value of the display device and the first processing value is obtained to obtain a second processing value; and a target value of a vertical total line number is determined according to the second processing value, wherein the target value is an integer value not greater than the second processing value.

[0103] In step S603, for any field synchronization signal in the video timing, at a starting moment corresponding to the field synchronization signal, a first target line synchronization signal corresponding to the field synchronization signal is generated, a counting value of a first counter is obtained every preset time interval, and if the counting value is less than the target value, a target line synchronization signal is generated and the counting value is increased.

[0104] In step S604, if the counting value is equal to the target value, the generation of the target line synchronization signal is stopped, and the counting value of the first counter is reset at a starting moment of a next field synchronization signal.

[0105] In step S605, a target video timing is generated according to the target line synchronization signal and the field synchronization signal.

[0106] In step S606, a target video clock matching the clock frequency value of the display device is generated according to a local clock of the master chip.

[0107] In step S607, a target video signal is generated according to the target video timing, the video data and the target video clock, so that the display device displays a video picture according to the target video signal.

[0108] The specific implementation details of each step in the embodiment of the present disclosure can be referred to the description above, and will not be repeated here.

[0109] The embodiment of the present disclosure can determine the target value of the total number of vertical lines by using the input field frequency corresponding to the video timing, the horizontal total pixel value of the display device, and the clock frequency value, in the case that the buffer area corresponding to the video data meets the preset condition, and the target value is an integer value not greater than the second processing value. Thus, according to the target value of the total number of vertical lines, the number of generated target line synchronization signals can be limited, so that for any received field synchronization signal, the target value of target line synchronization signals can be uniformly generated at a preset time interval. Thus, the target video timing generated by the embodiment of the present disclosure can meet the receiving requirements of the display screen. Correspondingly, the target video clock is generated by the local clock of the master control chip, and the target video signal is generated according to the target video clock, the target video timing, and the received video data, which can enable the display screen to normally display the video picture.

[0110] Therefore, the embodiment of the present disclosure provides a video timing generation method, which can, in the case that the buffer resource for processing video data is limited, make special processing on the video timing in the non-effective data interval according to the characteristics of the display screen, in the case that the video clock and the video data received by the display master control chip meet the display requirements of the display screen. By merging the target line with fewer horizontal total pixels with other lines, the line frequency of the target line is lower than that of other lines, so that the display screen can normally receive data, and the compatibility of the display master control chip to the display screen is effectively improved.

[0111] The step division of the above various methods is only for the purpose of clear description, and in implementation, one step can be combined or some steps can be split and decomposed into multiple steps, as long as the same logical relationship is included, and all are within the protection scope of the present patent; adding insignificant modifications or introducing insignificant designs in the algorithm or flow, but not changing the core design of the algorithm and flow, are within the protection scope of the present patent.

[0112] In a second aspect, the embodiment of the present disclosure provides a video timing generation device. Figure 7 A block diagram of a video timing generation device provided by the embodiment of the present disclosure is referred to Figure 7 The video timing generation device comprises:

[0113] The judgment module 71 is configured to, in response to receiving a video signal, determine whether a buffer area corresponding to video data meets a preset condition, wherein the video signal comprises the video data and video timing.

[0114] The first generation module 72 is configured to, in the case that the buffer area meets the preset condition, determine a target value of the total number of vertical lines according to an input field frequency corresponding to the video timing and display parameters of the display device, and generate a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value.

[0115] The second generating module 73 is configured to generate a target video timing according to the target line synchronization signal and the field synchronization signal, the target video timing being used for the display device to display a video picture.

[0116] In an optional implementation, the display parameter includes a clock frequency value of the display device and a horizontal total pixel value of the display device, and the determining of the target value of the vertical total line number according to the input field frequency corresponding to the video timing and the display parameter of the display device includes: determining a first processing value as a product of the input field frequency and the horizontal total pixel value; determining a second processing value according to a ratio between the clock frequency value and the first processing value; and determining the target value of the vertical total line number according to the second processing value, where the target value is an integer value not greater than the second processing value.

[0117] In an optional implementation, the number of the field synchronization signals is multiple, and the generating of the target line synchronization signal corresponding to the field synchronization signal according to the target value includes: for any field synchronization signal, generating the target value of target line synchronization signals corresponding to the field synchronization signal.

[0118] In an optional implementation, the generating of the target value of target line synchronization signals corresponding to the field synchronization signal includes: generating a first target line synchronization signal corresponding to the field synchronization signal at a starting moment of the field synchronization signal, and generating a target line synchronization signal every preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal are generated.

[0119] In an optional implementation, the number of the target line synchronization signals is accumulated by a first counter, and the generating of a target line synchronization signal every preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal are generated includes: acquiring a count value of the first counter every preset time interval, and in a case where the count value is less than the target value, generating a target line synchronization signal and increasing the count value; and in a case where the count value is equal to the target value, stopping the generation of the target line synchronization signal and resetting the count value of the first counter at a starting moment of a next field synchronization signal.

[0120] In an optional implementation, the judging of whether the buffer area corresponding to the video data satisfies a preset condition includes: in a case where the buffer area corresponding to the video data belongs to an on-chip memory area or a region size of the buffer area is not greater than a preset region threshold, determining that the buffer area corresponding to the video data satisfies the preset condition.

[0121] In an optional implementation, after the target video timing is generated according to the target line synchronization signal and the field synchronization signal, the apparatus is further configured to: generate a target video clock matching the clock frequency value of the display device according to the local clock of the master chip; and generate a target video signal according to the target video timing, the video data and the target video clock, so that the display device displays a video picture according to the target video signal.

[0122] The apparatus provided in the embodiments of the present disclosure has functions or contains modules which can be used to execute the methods described in the embodiments of the first aspect, and the specific implementation and technical effects can refer to the descriptions of the method embodiments. For briefness, they will not be repeated here.

[0123] It should be noted that each module involved in the present embodiment is a logical module. In actual application, one logical unit can be one physical unit, or a part of one physical unit, or realized by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, units not closely related to solving the technical problems proposed in the present disclosure are not introduced in the present embodiment, but this does not mean that there are no other units in the present embodiment.

[0124] With reference to Figure 8 The present disclosure provides an electronic device, which includes:

[0125] one or more processors 801;

[0126] a memory 802, having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the video timing generation method of any one of the above;

[0127] one or more I / O interfaces 803 connected between the processor and the memory, configured to realize the information interaction between the processor and the memory.

[0128] The processor 801 is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory 802 is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FLASH); the I / O interface (read-write interface) 803 is connected between the processor 801 and the memory 802, and can realize the information interaction between the processor 801 and the memory 802, including but not limited to a data bus (Bus) and the like.

[0129] In some embodiments, the processor 801, the memory 802 and the I / O interface 803 are connected with each other through a bus, and further connected with other components of the computing device.

[0130] The embodiment further provides a computer readable medium, which stores a computer program. The computer program is executed by a processor to implement the video timing generation method provided by the embodiment. For the sake of brevity, the specific steps of the video timing generation method are not described herein again.

[0131] The embodiment of the disclosure further provides a computer program product, which includes computer readable code or a non-volatile computer readable storage medium carrying the computer readable code. When the computer readable code is run in a processor of an electronic device, the processor in the electronic device executes the video timing generation method.

[0132] Those skilled in the art can understand that all or some steps of the method, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware or appropriate combination thereof. In the hardware implementation, the division between the function modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those skilled in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery medium.

[0133] It has to be understood that, in the present document, the terms "comprising", "including", or any other variant thereof, are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not limited to those elements, but can include other elements not expressly listed or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0134] Those skilled in the art will appreciate that the features of the different embodiments can be combined with each other in any manner within the scope of the embodiments, and form different embodiments.

[0135] It can be understood that the above implementation is only an exemplary implementation adopted for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A method for video timing generation, the method comprising: A master chip applied to a display device, the method comprises: In response to receiving a video signal, the video signal comprising video data and a video timing, determining whether a buffer area corresponding to the video data satisfies a preset condition; In a case where the buffer area satisfies the preset condition, determining a target value of a total number of vertical lines according to an input field frequency corresponding to the video timing and a display parameter of the display device, and generating a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value; Generating a target video timing according to the target line synchronization signal and the field synchronization signal, the target video timing being used for the display device to display a video picture.

2. The method of claim 1, wherein, The display parameter comprises a clock frequency value of the display device and a total horizontal pixel value of the display device, and the determining of the target value of the total number of vertical lines according to the input field frequency corresponding to the video timing and the display parameter of the display device comprises: Determining a first processing value by multiplying the input field frequency and the total horizontal pixel value; Obtaining a second processing value according to a ratio between the clock frequency value and the first processing value; Determining the target value of the total number of vertical lines according to the second processing value, wherein the target value is an integer value not greater than the second processing value.

3. The method of claim 1, wherein, The number of the field synchronization signals is multiple, and the generating of the target line synchronization signal corresponding to the field synchronization signal in the video timing according to the target value comprises: For any field synchronization signal, generating the target value of target line synchronization signals corresponding to the field synchronization signal.

4. The method of claim 3, wherein, The generating of the target value of target line synchronization signals corresponding to the field synchronization signal comprises: At a starting time corresponding to the field synchronization signal, generating a first target line synchronization signal corresponding to the field synchronization signal, and generating a target line synchronization signal every interval of a preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal is generated.

5. The method of claim 4, wherein, The generation number of the target line synchronization signal is accumulated by a first counter, and the generation of a target line synchronization signal every interval of a preset time interval until the target value of target line synchronization signals corresponding to the field synchronization signal is generated comprises: Every interval of the preset time interval, obtaining a count value of the first counter, in a case where the count value is less than the target value, generating a target line synchronization signal and increasing the count value; In a case where the count value is equal to the target value, stopping generating the target line synchronization signal, and resetting the count value of the first counter at a starting time of a next field synchronization signal.

6. The method of claim 1, wherein, The determining of whether the buffer area corresponding to the video data satisfies the preset condition comprises: In a case where the buffer area corresponding to the video data belongs to an on-chip memory area or a region size of the buffer area does not exceed a preset region threshold, determining that the buffer area corresponding to the video data satisfies the preset condition.

7. The method according to any one of claims 1 to 6, characterized in that, After the generating of the target video timing according to the target line synchronization signal and the field synchronization signal, the method further comprises: According to a local clock of the master chip, a target video clock matching a clock frequency value of the display device is generated; According to the target video timing, the video data and the target video clock, a target video signal is generated, so that the display device displays a video picture according to the target video signal.

8. A video timing generation apparatus, characterized by comprising: A master chip applied to a display device, the device comprises: A judging module, configured to, in response to receiving a video signal, judge whether a buffer area corresponding to video data satisfies a preset condition, the video signal comprising the video data and video timing; A first generating module, configured to, in a case where the buffer area satisfies the preset condition, determine a target value of a total number of vertical lines according to an input field frequency corresponding to the video timing and display parameters of the display device, and generate a target line synchronization signal corresponding to a field synchronization signal in the video timing according to the target value; A second generating module, configured to generate a target video timing according to the target line synchronization signal and the field synchronization signal, the target video timing being used for the display device to display a video picture.

9. An electronic device, comprising: Comprise: One or more processors; A memory, having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the video timing generation method according to any one of claims 1-7; One or more I / O interfaces, connected between the processor and the memory, configured to implement information interaction of the processor and the memory.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the video timing generation method according to any one of claims 1-7.

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