High-voltage lateral double-diffused metal oxide semiconductor structure and manufacturing method thereof

Abstract

The invention provides a high-voltage lateral double-diffused metal oxide semiconductor structure and a manufacturing method thereof. The structure comprises a substrate, a drift region, a source region, a drain region, a gate structure and a shallow trench isolation structure. The method is characterized in that an electrically suspended conductor is embedded in the shallow trench isolation structure between the grid electrode and the drain electrode. When the device bears high voltage, the suspended conductor can induce potential, enhance depletion of a drift region below the suspended conductor and form a new electric field peak, so that overall electric field distribution is optimized, and the problem of electric field concentration in a traditional structure is relieved. On the premise of not increasing the process complexity and the cost, the breakdown voltage and the reliability of the LDMOS device are remarkably improved, and an effective technical scheme is provided for designing an integrated circuit with higher power density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage lateral double-diffused metal-oxide-semiconductor structure and its manufacturing method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in medium and high voltage power integrated circuits such as power management, RF power amplification, automotive electronics, and display drivers due to their advantages such as good compatibility with standard CMOS processes, ease of integration, and low on-resistance.

[0003] A conventional high-voltage NLDMOS structure, the cross-sectional structure of which can be referenced. Figure 1 This structure is typically formed on a P-type substrate 101. To improve latch-up resistance and device performance, an N-type buried layer 102 is selectively formed within the P-type substrate 101. A P-type epitaxial layer 103 is grown on the N-type buried layer 102, and the active region of the device is constructed within this P-type epitaxial layer 103. Specifically, the structure includes a P-well 106 and an N-type drift region 107 formed in the P-type epitaxial layer 103. An N-type heavily doped source region 108b and a P-type heavily doped body contact region 109 are formed within the P-well 106. An N-type heavily doped drain region 108a is formed at the distal end of the N-type drift region 107. A gate 110 is disposed above the channel region between the P-well 106 and the N-type drift region 107. To achieve electrical isolation between devices and to shape the drift region, a shallow trench isolation (STI) structure 104 is typically provided in the N-type drift region 107. In addition, to optimize the surface electric field distribution, a metal field plate 111 may be placed above the source and drain.

[0004] In power applications, breakdown voltage is one of the core parameters for evaluating the performance and reliability of LDMOS devices. For the conventional structure described above, when a high voltage is applied between the drain 108a and source 108b, the space charge region primarily expands within the N-type drift region 107. However, the electric field tends to peak at the edge of the gate 110 or near the junction of the drain 108a. When this peak electric field reaches the critical breakdown field strength of the semiconductor material, avalanche breakdown occurs. For example, for a typical conventional structure, the breakdown voltage is only around 108.6V, which limits its use in higher voltage level applications.

[0005] To improve the breakdown voltage of LDMOS, existing technologies typically employ methods such as optimizing the doping concentration and length of the drift region 107, introducing a field plate 111 structure, or utilizing resistivity-reducing surface field (RESURF) technology to modulate the electric field distribution on the device surface, preventing the local electric field from reaching the critical value prematurely. However, these traditional electric field optimization techniques are gradually encountering bottlenecks in improving breakdown voltage. For example, simply increasing the length of the drift region significantly increases the on-resistance and chip area of ​​the device; and the design of the field plate structure also presents complex potential coupling problems, limiting the optimization window.

[0006] Therefore, the industry continues to seek new structures and methods that can effectively improve the breakdown voltage of LDMOS devices without significantly increasing process complexity and cost, or sacrificing other key electrical parameters (such as on-resistance). Summary of the Invention

[0007] The technical problem to be solved by the present invention is that the electric field distribution in the existing high voltage LDMOS device is uneven, especially near the gate edge and the drain junction region, which easily leads to electric field concentration, resulting in limited breakdown voltage of the device and difficulty in meeting the requirements of higher voltage level applications.

[0008] To address the aforementioned technical problems, this invention provides a high-voltage lateral double-diffused metal-oxide-semiconductor structure, comprising:

[0009] First conductivity type substrate;

[0010] A second conductivity type drift region is disposed on a first conductivity type substrate;

[0011] Source region and drain region;

[0012] Gate structure covering the channel region between the source region and the drift region of the second conductivity type;

[0013] A shallow trench isolation structure disposed within the drift region of the second conductivity type for electrical isolation; and

[0014] Electrically suspended conductors embedded in shallow trench isolation structures.

[0015] Preferably, the first conductivity type is P-type and the second conductivity type is N-type.

[0016] Preferably, the structure further includes a first conductivity type well region; wherein the source region is disposed within the first conductivity type well region.

[0017] Preferably, the structure further includes a first conductivity type body contact region disposed within the first conductivity type well region, the first conductivity type body contact region being disposed adjacent to the source region.

[0018] Preferably, the electrically levitated conductor is polycrystalline silicon.

[0019] Preferably, the shallow trench isolation structure is located between the gate structure and the drain region, and the electrically suspended conductor is correspondingly disposed within the shallow trench isolation structure between the gate structure and the drain region.

[0020] Preferably, the length of the electrically levitated conductor in the direction extending along the drift region of the second conductivity type is less than the total length of the shallow trench isolation structure in that direction.

[0021] Preferably, the structure further includes: a second conductivity type buried layer disposed within a first conductivity type substrate; and a first conductivity type epitaxial layer disposed above the second conductivity type buried layer, wherein the second conductivity type drift region is formed in the first conductivity type epitaxial layer.

[0022] Another aspect of the present invention provides a method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure, comprising the following steps:

[0023] Step 1: Provide a substrate of the first conductivity type;

[0024] Step 2: Form a drift region of the second conductivity type on the substrate of the first conductivity type;

[0025] Step 3: Form a shallow trench isolation structure in the drift region of the second conductivity type, and during the formation of the shallow trench isolation structure, embed the electrically suspended conductor in the shallow trench isolation structure.

[0026] Step 4: Form a gate structure covering the channel region on a substrate of the first conductivity type; and

[0027] Step 5: Form the source and drain regions.

[0028] Preferably, the first conductivity type is P-type and the second conductivity type is N-type.

[0029] Preferably, prior to step two, the method further includes: selectively forming a second conductivity type buried layer in a first conductivity type substrate; and growing a first conductivity type epitaxial layer on the second conductivity type buried layer, wherein a second conductivity type drift region is formed in the first conductivity type epitaxial layer.

[0030] Preferably, in step three, the electrically levitated conductor is embedded in a shallow trench isolation structure between the gate structure and the drain region.

[0031] Preferably, in step three, the electrically levitated conductor is polycrystalline silicon.

[0032] Preferably, in step three, the step of forming a shallow trench isolation structure and embedding an electrically suspended conductor includes: etching a trench in a drift region of a second conductivity type; depositing a conductive material in the trench; patterning the conductive material to form an electrically suspended conductor in a portion of the trench; and filling the remaining portion of the trench with a dielectric material to form a shallow trench isolation structure.

[0033] Preferably, before forming the gate structure in step four, the method further includes the step of forming a first conductivity type well region; and in step five, the step of forming the source region and the drain region includes: forming a source region in the first conductivity type well region, a first conductivity type body contact region adjacent to the source region, and forming a drain region in the second conductivity type drift region.

[0034] Preferably, after step five, the method further includes: forming a metal interconnect structure, the metal interconnect structure including a source electrode electrically connected to the source region and the first conductivity type body contact region, a drain electrode electrically connected to the drain region, a source end metal field plate, and a drain end metal field plate.

[0035] As described above, the high-voltage lateral double-diffused metal-oxide-semiconductor structure and its manufacturing method of the present invention have the following beneficial effects:

[0036] This invention utilizes an electrically levitated conductor embedded within a shallow trench isolation structure to enhance the depletion of the underlying drift region and create a new electric field peak, resulting in a more uniform overall electric field distribution. This significantly improves the device's breakdown voltage without altering its dimensions. Furthermore, the proposed structural improvements and manufacturing method can be integrated into standard CMOS processes without requiring additional photomasks, thus minimizing manufacturing costs and process complexity. Ultimately, the higher breakdown voltage enhances the device's reliability under overvoltage conditions and enables the design of higher power density integrated circuits, contributing to the miniaturization and efficiency of electronic systems. Attached Figure Description

[0037] Figure 1 This is a cross-sectional schematic diagram of a high-voltage NLDMOS structure in the prior art;

[0038] Figure 2 This is a schematic flowchart of a high-voltage NLDMOS structure manufacturing method according to the present invention;

[0039] Figure 3 This is a schematic cross-sectional view of the intermediate structure after the formation of the N-type buried layer in the manufacturing method of the present invention;

[0040] Figure 4 This is a schematic cross-sectional view of the intermediate structure after shallow trench isolation with embedded suspended conductors is formed in the manufacturing method of the present invention.

[0041] Figure 5 This is a schematic cross-sectional view of the intermediate structure after the formation of the P-well and the P-type injection region in the manufacturing method of the present invention.

[0042] Figure 6 This is a schematic cross-sectional view of the intermediate structure after the gate and source, drain and body contact regions are formed in the manufacturing method of the present invention.

[0043] Figure 7 This is a cross-sectional schematic diagram of a high-voltage NLDMOS structure according to the present invention;

[0044] Figure 8 This is a simulation comparison diagram of the depletion region between the structure of the present invention and the structure of the prior art. Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] To better understand this invention, first refer to... Figure 1 , Figure 1 A prior art high-voltage lateral double-diffused metal-oxide-semiconductor (MOS) structure is shown. This structure includes: a P-type substrate 101, an N-type buried layer 102, a P-type epitaxial layer 103, a shallow trench isolation 104, a P-type implantation region 105, a P-well 106, an N-type drift region 107, a heavily doped N-type drain 108a, a heavily doped N-type source 108b, a heavily doped P-type body contact region 109, a gate 110, and a metal field plate 111. However, the breakdown voltage of this structure is limited by the electric field concentration effect at the gate edge and drain junction, resulting in limited upside potential.

[0047] Based on the above, this invention provides a novel high-voltage lateral double-diffused metal-oxide-semiconductor structure, the cross-sectional schematic of which can be found in the following embodiment. Figure 7 (Final structure). With Figure 1 Compared with the prior art, a key difference in the structure of the present invention is that an electrically levitated conductor 112 is additionally embedded in the shallow trench isolation structure 104 disposed in the second conductivity type drift region 107.

[0048] In some embodiments, such as Figure 7As shown, the first conductivity type is P-type, and the second conductivity type is N-type. Of course, those skilled in the art will understand that by reversing the conductivity types of each region, a P-channel high-voltage LDMOS device can also be constructed, which also falls within the scope of this invention.

[0049] In some embodiments, the structure further includes:

[0050] A second conductivity type buried layer 102 disposed within a first conductivity type substrate 101; and

[0051] A first conductivity type epitaxial layer 103 is disposed above the second conductivity type buried layer 102, and a second conductivity type drift region 107 is formed in the first conductivity type epitaxial layer 103.

[0052] The second conductivity type buried layer 102 helps reduce the substrate resistance of the device and improve latch-up resistance. The first conductivity type substrate 101 can be a high-resistivity or low-resistivity silicon substrate, or other semiconductor substrates, such as silicon-on-insulator (SOI) substrates, germanium (Ge) substrates, silicon-germanium (SiGe) substrates, or III-V compound semiconductor substrates. For higher power or higher frequency applications, the substrate can also be a wide bandgap semiconductor material, such as silicon carbide (SiC) or gallium nitride (GaN) based substrates.

[0053] In some embodiments, the structure further includes a first conductivity type well region 106; wherein, a source region 108b is disposed within the first conductivity type well region 106.

[0054] In some embodiments, the structure further includes a first conductivity type body contact region 109 disposed within the first conductivity type well region 106, the first conductivity type body contact region 109 being disposed adjacent to the source region 108b. The first conductivity type body contact region 109 is used to provide a stable potential for the first conductivity type well region 106, prevent body effects, and draw out substrate current.

[0055] The electrically suspended conductor 112, embedded within the shallow trench isolation structure 104, is a core technical concept of this invention. When the device is subjected to reverse high voltage, the high potential of the drain 108a induces a charge and a certain potential on the electrically suspended conductor 112 through electric field coupling. This suspended potential effectively helps the drift region 107 of the second conductivity type below it to be depleted, allowing the space charge region to expand wider.

[0056] Please see Figure 8 , Figure 8 This is a simulation comparison of the depletion region of the structure in this application and the structure in the prior art under the breakdown state. From Figure 8As can be clearly seen, compared to existing structures, the structure of this application, after adding a floating conductor inside the shallow trench isolation region, increases the depletion region below it, confirming the enhancing effect of the floating conductor on the depletion of the drift region. This is equivalent to introducing a new electric field modulation node in the drift region, which can form a new electric field peak below the shallow trench isolation region between the gate and drain. This new electric field peak shares the electric field intensity originally concentrated at the edge of the gate 110 or the junction region of the drain 108a, making the electric field distribution of the entire device more uniform, thereby significantly improving the breakdown voltage of the device without increasing the length of the drift region. According to simulation data, the breakdown voltage of the device using the structure of this invention can be increased from 108.6V in the original structure to 144.8V, an increase of 36.2V, which is significant. This enhances the device's tolerance under overvoltage conditions and improves the operational reliability of the device and the circuit system it is in; on the other hand, the higher breakdown voltage margin also makes it possible to design chips with higher power density, which helps to achieve miniaturization and weight reduction of electronic devices.

[0057] In some embodiments, the electrically levitated conductor 112 is polycrystalline silicon. Polycrystalline silicon is a common conductive material in semiconductor processes, with mature technology and full compatibility with standard CMOS processes. Of course, the electrically levitated conductor 112 can also be made of other suitable conductive materials, such as amorphous silicon, metal silicides (e.g., tungsten silicides, titanium silicides, cobalt silicides, nickel silicides, etc.), or refractory metal materials capable of withstanding the high temperatures of subsequent processes (e.g., tungsten, molybdenum, tantalum, etc.), as long as they can achieve electrical levitation and play a role in electric field modulation. The key to selecting these materials lies in their good conductivity and thermal stability during subsequent heat treatment.

[0058] In some embodiments, a shallow trench isolation structure 104 is located between the gate structure 110 and the drain region 108a, and an electrically levitated conductor 112 is correspondingly disposed within the shallow trench isolation structure 104 between the gate structure 110 and the drain region 108a. This location is one of the areas where the electric field is most concentrated on the device surface, and placing the levitated conductor 112 here can most effectively modulate the electric field. Furthermore, as... Figure 7 As shown, the structure may also include a P-type injection region 105 for further optimizing the electric field distribution in the drift region.

[0059] In some embodiments, the length of the electrically levitated conductor 112 along the extension direction of the drift region 107 of the second conductivity type is less than the total length of the shallow trench isolation structure 104 in that direction. This locally buried design can more precisely modulate the electric field at critical locations, effectively forming new electric field peaks to share the electric field concentration at the gate edge and drain junction, avoiding the undesirable capacitive coupling effect that may result from completely burying the conductor, thereby improving the breakdown voltage while maintaining the excellent switching characteristics of the device.

[0060] Please see Figure 2 and combined Figures 3 to 7 , Figure 2 A flowchart illustrating a method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to an embodiment of the present invention is shown. Figures 3 to 7 This shows a schematic cross-sectional view of the semiconductor intermediate structure corresponding to each step in the flowchart.

[0061] The method includes the following steps:

[0062] Step 1: Provide a substrate of the first conductivity type. For example... Figure 3 As shown, a first conductivity type substrate 101 is provided.

[0063] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0064] Step 2: Form a drift region of the second conductivity type on the substrate of the first conductivity type.

[0065] In some embodiments, prior to this step, the method further includes: selectively forming a second conductivity type buried layer 102 within a first conductivity type substrate 101; and growing a first conductivity type epitaxial layer 103 on the second conductivity type buried layer 102, wherein a second conductivity type drift region 107 is formed in the first conductivity type epitaxial layer 103. The second conductivity type buried layer 102 can be formed by a high-energy ion implantation process, and the implanted N-type dopant is typically a heavy ion with a low diffusion coefficient, such as arsenic (As) or antimony (Sb), to reduce its upward diffusion during subsequent high-temperature epitaxial growth. The first conductivity type epitaxial layer 103 can be formed by epitaxial growth techniques, such as atmospheric pressure chemical vapor deposition (APCVD), reduced pressure chemical vapor deposition (RPCVD), or ultra-high vacuum chemical vapor deposition (UHVCVD) in chemical vapor deposition (CVD). The silicon source gas during the growth process can be silane (SiH4), dichlorosilane (SiH2Cl2), etc., while a P-type dopant gas source such as diborane (B2H6) is introduced.

[0066] Step 3: Form a shallow trench isolation structure in the drift region of the second conductivity type, and during the formation of the shallow trench isolation structure, embed an electrically suspended conductor within the shallow trench isolation structure.

[0067] In some embodiments, the electrically levitated conductor 112 is embedded within a shallow trench isolation structure 104 between the gate structure 110 and the drain region 108a. The advantage of this is that the formation of this structure can be fully integrated into a standard shallow trench isolation process flow without the need for additional photomasks, thus not significantly increasing manufacturing costs or process complexity, resulting in high economic efficiency and process feasibility.

[0068] In some embodiments, the electrically levitated conductor 112 is a polycrystalline silicon body.

[0069] In some embodiments, the steps of forming a shallow trench isolation structure 104 and embedding an electrically suspended conductor 112 include: etching a trench in a drift region of a second conductivity type; depositing a conductive material within the trench; patterning the conductive material to form an electrically suspended conductor 112 within a portion of the trench; and filling the remaining portion of the trench with a dielectric material to form the shallow trench isolation structure 104. Specifically, etching to form the trench preferably employs anisotropic plasma etching, such as reactive ion etching (RIE), to obtain steep and precisely contoured trench sidewalls. The conductive material, such as polysilicon, can be deposited using a low-pressure chemical vapor deposition (LPCVD) process. Patterning the conductive material can be performed using photolithography and etching processes to remove unwanted conductive material, leaving only a small portion at a predetermined location. Finally, the trench is filled with a dielectric material; to achieve void-free filling, high-density plasma chemical vapor deposition (HDP-CVD) is typically used to deposit silicon dioxide. After filling, excess dielectric and conductive materials are removed from the surface using a chemical mechanical planarization (CMP) process to achieve global planarization. The paste used for CMP can be cerium dioxide-based or silicon dioxide-based paste. In addition to silicon dioxide, the filled dielectric material can also be silicon nitride (SiN), silicon oxynitride (SiON), or a stacked structure thereof.

[0070] Step 4: Form a gate structure covering the channel region on a substrate of the first conductivity type.

[0071] In some embodiments, forming the gate structure 110 typically includes sequentially forming a gate dielectric layer and a gate electrode layer. The gate dielectric layer may be silicon dioxide (SiO2) formed by thermal growth, or a high-k material deposited by methods such as atomic layer deposition (ALD), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), and their silicates. The gate electrode layer may be doped polycrystalline silicon, or a metal gate, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or other metal materials or their stacked structures, to improve the gate electrical characteristics.

[0072] In some embodiments, prior to this step, the method further includes the step of forming a first conductivity type well region 106.

[0073] Step 5: Form the source and drain regions.

[0074] In some embodiments, the steps of forming the source and drain regions include: forming a source region 108b and a first conductivity type body contact region 109 adjacent to the source region 108b within a first conductivity type well region 106, and forming a drain region 108a on the side away from the gate structure 110 within a second conductivity type drift region 107. The formation of these doped regions is typically achieved through an ion implantation process, followed by a thermal treatment process to activate impurities and repair electrical damage. This thermal treatment process can be rapid thermal annealing (RTA), which has a fast heating and cooling rate, effectively activating impurities while suppressing their diffusion; or it can be conventional furnace tube annealing or laser annealing.

[0075] In some embodiments, after this step, the method further includes: forming a metal interconnect structure, the metal interconnect structure including a source electrode electrically connected to the source region 108b and the first conductivity type body contact region 109, a drain electrode electrically connected to the drain region 108a, a source metal field plate, and a drain metal field plate 111. This step typically includes: firstly depositing an interlayer dielectric (ILD), such as phosphorus-doped or boron-phosphorus silicate glass (PSG / BPSG), or silicon fluoride glass (FSG), or even a low-k material deposited using plasma-enhanced chemical vapor deposition (PECVD). The thickness of the interlayer dielectric can be from about 0.5 micrometers to 2 micrometers. Then, contact holes are etched on the interlayer dielectric using photolithography and etching techniques. Before depositing the metal, a barrier metal / adhesion layer, such as a titanium / titanium nitride (Ti / TiN) stack, is typically deposited on the inner wall of the contact holes using physical vapor deposition (PVD) to prevent the metal from directly contacting the silicon and causing spike effects and to improve electrical contact. Next, metal layers, such as aluminum (Al), copper (Cu), or their alloys, are deposited using methods such as PVD. Finally, the required electrode interconnects and field patterns are formed again through photolithography and etching. If copper is used as the interconnect metal, damascene or dual damascene processes are typically used for fabrication.

[0076] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage lateral double-diffused metal-oxide-semiconductor structure, comprising: First conductivity type substrate; A second conductivity type drift region disposed on the first conductivity type substrate; Source region and drain region; A gate structure covering the channel region between the source region and the drift region of the second conductivity type; and A shallow trench isolation structure disposed within the drift region of the second conductivity type for electrical isolation; The high-voltage lateral double-diffused metal-oxide-semiconductor structure is characterized by further comprising: Electrically suspended conductors embedded within the shallow trench isolation structure.

2. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 1, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type.

3. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 1, characterized in that: The structure further includes a first conductivity type well region; wherein the source region is disposed within the first conductivity type well region.

4. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 3, characterized in that: The structure further includes a first conductive body contact region disposed within the first conductive type well region, the first conductive type body contact region being disposed adjacent to the source region.

5. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 1, characterized in that: The electrically levitated conductor is polycrystalline silicon.

6. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 1, characterized in that: The shallow trench isolation structure is located between the gate structure and the drain region, and the electrically levitated conductor is correspondingly disposed within the shallow trench isolation structure between the gate structure and the drain region.

7. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 6, characterized in that: The length of the electrically levitated conductor in the direction extending along the drift region of the second conductivity type is less than the total length of the shallow trench isolation structure in that direction.

8. The high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 1, characterized in that: The structure further includes: a second conductivity type buried layer disposed within the first conductivity type substrate; and a first conductivity type epitaxial layer disposed above the second conductivity type buried layer, wherein the second conductivity type drift region is formed in the first conductivity type epitaxial layer.

9. A method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure, characterized in that, include: Step 1: Provide a substrate of the first conductivity type; Step 2: Form a drift region of the second conductivity type on the substrate of the first conductivity type; Step 3: Form a shallow trench isolation structure in the drift region of the second conductivity type, and during the formation of the shallow trench isolation structure, embed an electrically suspended conductor in the shallow trench isolation structure; Step 4: Form a gate structure covering the channel region on the first conductivity type substrate; as well as Step 5: Form the source and drain regions.

10. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 9, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type.

11. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 9, characterized in that: Prior to step two, the method further includes: selectively forming a second conductivity type buried layer within the first conductivity type substrate; and growing a first conductivity type epitaxial layer on the second conductivity type buried layer, wherein the second conductivity type drift region is formed in the first conductivity type epitaxial layer.

12. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 9, characterized in that: In step three, the electrically suspended conductor is embedded in the shallow trench isolation structure between the gate structure and the drain region.

13. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 9 or 12, characterized in that: In step three, the electrically levitated conductor is polycrystalline silicon.

14. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 9 or 12, characterized in that: In step three, the steps of forming the shallow trench isolation structure and embedding the electrically suspended conductor include: etching a trench in a drift region of the second conductivity type; depositing a conductive material in the trench; patterning the conductive material to form the electrically suspended conductor in a portion of the trench; and filling the remaining portion of the trench with a dielectric material to form the shallow trench isolation structure.

15. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 9, characterized in that: Before forming the gate structure in step four, the method further includes the step of forming a well region of a first conductivity type; Furthermore, in step five, the step of forming the source region and the drain region includes: forming a source region and a first conductivity type body contact region adjacent to the source region within the first conductivity type well region.

16. The method for manufacturing a high-voltage lateral double-diffused metal-oxide-semiconductor structure according to claim 15, characterized in that: After step five, the method further includes: forming a metal interconnect structure, the metal interconnect structure including a source electrode electrically connected to the source region and the first conductivity type body contact region, a drain electrode electrically connected to the drain region, a source end metal field plate, and a drain end metal field plate.

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