Driving circuit based on ferroelectric oxide thin film transistor and preparation method thereof

Abstract

The invention discloses a driving circuit based on a ferroelectric oxide thin film transistor and a preparation method of the driving circuit, the driving circuit based on the ferroelectric oxide thin film transistor is designed by utilizing the polarization characteristic of the ferroelectric thin film transistor, the preparation process is optimized, the annealing temperature is reduced, and the production efficiency is improved. Each driving unit comprises a ferroelectric transistor and a common transistor which are connected through wiring, driving matrixes are prepared on the flexible substrate and the rigid substrate, and experimental results show that the ferroelectric capacitor has excellent polarization intensity, the ferroelectric transistor has good ferroelectric performance, and the driving circuit has good maintaining performance.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and particularly relates to a driving circuit based on ferroelectric oxide thin film transistors and its fabrication method. Background Technology

[0002] With the development of display technology, the demand for new display technologies such as flexible displays, wearable devices, and augmented reality is increasing, placing higher expectations and requirements on the driving circuits corresponding to display matrices in terms of size, lifespan, and power consumption. Multi-transistor, multi-capacitor driving circuits, using LTPS or oxide semiconductors (such as IGZO) as materials and composed of switching transistors, driving transistors, and capacitors, rely on high capacitance values ​​to maintain the driving current. However, the area of ​​the capacitors limits the area of ​​the driving circuit, thus reducing the density of the driving units and leading to higher power consumption, becoming one of the main factors limiting the performance of the driving circuit.

[0003] Oxide thin-film transistors (TFTs) based on ferroelectric materials have demonstrated their advantages, such as non-volatility, and have become a hot topic in recent research on memory and driver circuits. Currently, FeMFETs based on HZO materials have shown good compatibility in CMOS technology, but their application in the oxide TFT field is limited. Furthermore, the thermal budget (300–500℃) in back-end processing (BEOL) can lead to metal diffusion or crystallization in oxide semiconductors (such as IGZO), reducing mobility. For example, indium segregation in a-IGZO at high temperatures can cause carrier concentration fluctuations. HZO also suffers from insufficient thermal stability (e.g., <10nm films maintain ferroelectricity at 250℃, but high-temperature annealing easily introduces non-ferroelectric phases, further limiting the process compatibility of oxide TFTs). Summary of the Invention

[0004] Purpose of the invention: In order to solve the problems existing in the prior art, the present invention provides a driving circuit based on ferroelectric oxide thin film transistor and its fabrication method.

[0005] Technical solution: The present invention discloses a driving circuit based on ferroelectric oxide thin film transistors, including a matrix based on ferroelectric oxide thin film transistors, the matrix including multiple 2T driving units arranged in rows and columns.

[0006] Furthermore, the 2T driving unit includes a driving transistor and a switching transistor. The driving transistor is a ferroelectric oxide thin-film transistor, which contains a ferroelectric capacitor structure. The source of the switching transistor is connected to the DATA line, the gate is connected to the SCAN line, the drain is connected to the floating gate electrode of the driving transistor, the source of the driving transistor is connected to the GND line, the drain is connected to one end of the load, and the other end of the load is connected to the VDD signal.

[0007] Furthermore, this includes methods for fabricating the driving transistor and methods for fabricating the switching transistor;

[0008] The specific method for preparing the driving transistor is as follows:

[0009] Step 1: Obtain the substrate and prepare a buffer layer on the substrate;

[0010] Step 2: Perform photoresist homogenization, photolithography, drying, exposure and development on the substrate surface to obtain patterned photoresist. Use a photoresist remover to remove any residual photoresist in the patterned area. Use DC sputtering to form a metal layer on the buffer layer. Then, use a lift-off process to obtain the patterned bottom gate electrode.

[0011] Step 3: Cover the bottom gate electrode with a ferroelectric layer;

[0012] Step 4: Perform homogenization, photolithography, drying, exposure and development on the surface of the ferroelectric layer to obtain patterned photoresist. Use a photoresist remover to remove residual photoresist in the patterned area. Use magnetron sputtering to form a metal layer on the ferroelectric layer. Use a lift-off process to obtain patterned floating gate electrodes.

[0013] Step 5: After the floating gate electrode is formed, annealing is performed to induce the crystallization of the ferroelectric layer. The floating gate electrode, the bottom gate electrode, and the crystallized ferroelectric layer constitute a ferroelectric capacitor.

[0014] Step 6: Cover the annealed floating gate electrode with a gate dielectric layer;

[0015] Step 7: Form an active layer on the gate dielectric layer;

[0016] Step 8: Anneal the active layer in an air environment;

[0017] Step 9: Perform homogenization, photolithography, drying, exposure and development on the surface of the active layer to obtain patterned photoresist. Use a photoresist remover to remove residual photoresist in the patterned area. Use magnetron sputtering to form a metal layer on the active layer. Then use a lift-off process to obtain patterned source and drain electrodes.

[0018] The specific method for fabricating the switching transistor is as follows:

[0019] Step A: Obtain the substrate and cover the substrate surface with a buffer layer;

[0020] Step B: Perform photoresist homogenization, photolithography, drying, exposure and development on the substrate surface to obtain patterned photoresist. Use a photoresist remover to remove any residual photoresist in the patterned area. Use magnetron sputtering to form a molybdenum metal layer on the buffer layer. Use a lift-off process to obtain patterned floating gate electrodes.

[0021] Step C: A gate dielectric layer is deposited on the floating gate electrode using an ALD process. The gate dielectric layer is made of aluminum oxide.

[0022] Step D: An active layer is formed on the gate dielectric layer using an RF magnetron sputtering process;

[0023] Step E: Anneal the active layer in an air environment;

[0024] Step F: Perform homogenization, photolithography, drying, exposure and development on the surface of the active layer to obtain patterned photoresist. Use a photoresist stripper to remove any residual photoresist in the patterned area. Use magnetron sputtering to form a molybdenum metal layer on the active layer. Use a lift-off process to obtain patterned source and drain electrodes.

[0025] Furthermore, the buffer layer in step 1 or step A is made of silicon dioxide. The buffer layer is coated on the substrate surface by a PECVD process. The PECVD process parameters are as follows: first stage working pressure 1500 mTorr, N2O and 5% SiH4 ratio 700:200, power 100W, reaction temperature 300℃, time 6min; second stage working pressure 1130 mTorr, N2O and 5% SiH4 ratio 700:200, power 100W, reaction temperature 300℃, time 2min; the thickness of the buffer layer is 100 nm.

[0026] Furthermore, the bottom gate electrode in step 2 uses a titanium metal layer and a molybdenum metal layer, while the metal layer of the floating gate electrode in steps 4 and B uses molybdenum metal.

[0027] Furthermore, in step 3, an ALD process is used to coat the bottom gate electrode with a ferroelectric layer made of hafnium zirconium oxide. The ALD process parameters are as follows: precursor: hafnium source peak value 50-60 Pa, water source peak value 150-200 Pa, zirconium source peak value 600-800 Pa, cycle number set to 50, temperature 220℃, time 2h14min; ferroelectric layer thickness is 12nm.

[0028] Furthermore, the annealing conditions in step 5 are: temperature of 400℃, annealing atmosphere of N2, and annealing time of 2h.

[0029] Furthermore, in steps 6 and C, an ALD process is used to cover the floating gate electrode with a gate dielectric layer; the gate dielectric layer is made of aluminum oxide and the thickness of the prepared gate dielectric layer is 20 nm.

[0030] Furthermore, in steps 7 and D, an active layer is formed on the gate dielectric layer using an RF magnetron sputtering process. The reaction conditions for the RF magnetron sputtering process are: sputtering pressure 0.5 Pa, Ar to O2 ratio of 44:6, sputtering power 60 W, and sputtering time 400 s. Patterned photoresist is obtained by performing homogenization, photolithography, drying, exposure, and development on the surface of the active layer. After photoresist removal, a patterned active layer with a thickness of 4 nm is obtained.

[0031] Furthermore, the annealing conditions in steps E and 8 are as follows: temperature is 200℃, annealing atmosphere is air, and annealing time is 30 min.

[0032] Beneficial Effects: This invention utilizes the polarization characteristics of ferroelectric thin-film transistors (FTTFTs) to design a driving circuit based on ferroelectric oxide thin-film transistors. Each 2T driving unit contains one ferroelectric transistor and one ordinary transistor, connected by wiring. The driving matrix is ​​fabricated on both flexible and rigid substrates. Compared with the traditional 2T1C driving circuit, this invention reduces the unit area. Through ferroelectric capacitor performance characterization, ferroelectric transistor device performance characterization, and 2T driving unit hold-up tests, it is demonstrated that the ferroelectric capacitor of this invention has high polarization intensity, the ferroelectric transistor has good ferroelectric performance, and the driving circuit has a long hold-up time. This lays the foundation for the application of ferroelectric oxide thin-film transistors in display driving and other fields. Attached Figure Description

[0033] Figure 1 This is a circuit connection diagram of a driving circuit based on a ferroelectric oxide thin film transistor provided by the present invention;

[0034] Figure 2 This is a schematic diagram of a 2T driving unit circuit based on a ferroelectric oxide thin-film transistor provided by the present invention.

[0035] Figure 3 This is a flowchart of the drive transistor manufacturing process;

[0036] Figure 4 This is a cross-sectional view of the drive tube.

[0037] Figure 5 This is a flowchart of the switching transistor manufacturing process;

[0038] Figure 6 This is a cross-sectional view of the switching transistor.

[0039] Figure 7 Figure 1 shows the ferroelectric capacitor and device performance characterization diagrams of the driving circuit based on the ferroelectric oxide thin film transistor of the present invention. Figure 2(a) is the PV curve of the ferroelectric capacitor structure; Figure 3(b) is the transfer characteristic curve of the driving transistor; and Figure 4(c) is the output curve of the driving transistor.

[0040] Figure 8 This is a retention performance diagram of a driving circuit based on a ferroelectric oxide thin-film transistor in an embodiment of the present invention. Detailed Implementation

[0041] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0042] This invention relates to oxide thin-film transistors based on ferroelectric materials, which have demonstrated advantages such as non-volatility, becoming a recent hot topic in memory and driver circuit research. Currently, FeMFETs based on HZO materials have shown good compatibility in CMOS technology, but their application in the oxide thin-film transistor field is limited. Furthermore, the thermal budget (300–500°C) in back-end processing (BEOL) can lead to metal diffusion or crystallization in oxide semiconductors (such as IGZO), reducing mobility. For example, indium segregation in a-IGZO at high temperatures can cause carrier concentration fluctuations. HZO has insufficient thermal stability; for example, <10nm films maintain ferroelectricity at 250°C, but high-temperature annealing easily introduces non-ferroelectric phases, further limiting the process compatibility of oxide TFTs. The advantage of FeMFETs lies in their ability to store polarization states via dipole polarization. In conventional drive circuits, the amount of charge stored in a capacitor decreases continuously with leakage current, requiring a large area to improve its retention performance. However, for ferroelectric capacitor structures, the HZO dipole reduces the impact of leakage current on charge storage and does not exhibit area dependence. This eliminates the need for a significant amount of capacitor area, allowing ferroelectric oxide transistors to replace traditional transistors and capacitors in the drive circuit. Furthermore, the drive circuit can maintain polarization states, achieving extremely low power consumption and refresh rates.

[0043] like Figure 1 As shown, a driving circuit based on a ferroelectric oxide thin-film transistor includes the following technical solution:

[0044] The matrix based on ferroelectric oxide thin film transistors includes GND wiring, DATA wiring, VDD wiring, and open SCAN wiring.

[0045] Figure 1 The ferroelectric oxide thin-film transistor matrix consists of multiple 2T driving units arranged in rows and columns. For example... Figure 2The circuit diagram of the 2T drive unit is shown in the figure.

[0046] The transistor and wiring connections are as follows:

[0047] Figure 2 Facap is a ferroelectric capacitor. The ferroelectric capacitor and transistor F1 together form the driving transistor, which is a ferroelectric oxide thin-film transistor.

[0048] The driving transistor has its source connected to GND, its drain connected to VDD, and its floating gate electrode connected to the source of the switching transistor.

[0049] The source of the switching transistor is connected to DATA, the gate is connected to SCAN, and the drain is connected to the floating gate electrode of the driving transistor.

[0050] A driving circuit based on a ferroelectric oxide thin-film transistor (FET) operates on the principle of controlling the switching of a switching transistor by enabling or disabling the SCAN signal, thereby controlling whether the DATA signal can be written to and transmitted through the switching transistor. The DATA signal controls the polarization switching of the driving transistor, which in turn controls its on / off state. When the driving transistor is on, a loop is formed between the external load, VDD, and GND, generating current and enabling the driving circuit to operate. When the driving transistor is off, one end of the external load is connected to the VDD signal, and the other end is connected to the drain segment of the off driving transistor, resulting in no current flow. This establishes a logic where the SCAN signal controls the switching of the transistor and the DATA signal, the DATA signal controls the polarization, and the polarization controls the switching of the driving transistor.

[0051] This invention also provides a method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor, such as... Figure 3 As shown, this method can be used to prepare Figure 1 The driving circuit based on ferroelectric oxide thin-film transistors shown includes the following steps:

[0052] The fabrication flowchart for the driver transistor is as follows: Figure 3 As shown:

[0053] S10, Obtain the substrate.

[0054] The substrate can be a rigid substrate (e.g., a silicon / silicon oxide substrate) or a flexible substrate known in the art. In one embodiment of the invention, the substrate is a flexible substrate, such as a PI substrate. The substrate is ultrasonically cleaned for four to five minutes each with a power of 100W using deionized water, acetone, ethanol, and then deionized water in that order, to obtain a substrate suitable for subsequent operations. A buffer layer, made of silicon dioxide, is then deposited on the surface of the substrate S10 using a PECVD process. The PECVD process parameters used in this embodiment are as follows: First stage operating pressure 1500 mTorr, N2O and 5% SiH4 in a ratio of 700:200, power 100W, reaction temperature 300°C, and time 6 min. Second stage operating pressure 1130 mTorr, N2O and 5% SiH4 in a ratio of 700:200, power 100W, reaction temperature 300°C, and time 2 min. In this embodiment, the thickness of the prepared buffer layer is 100 nm.

[0055] S20, forming a bottom gate electrode on the substrate.

[0056] In one embodiment of the present invention, the substrate surface is subjected to homogenization, photolithography, drying, exposure, and development to obtain patterned photoresist. Any residual photoresist in the patterned area is removed using a photoresist stripper. A titanium and molybdenum metal layer is formed on a buffer layer (on which the patterned photoresist is present) using a DC sputtering process. A further lift-off process is used to obtain the patterned bottom gate electrode. Other materials / structures known in the art can also be used as the bottom gate electrode. In this embodiment, the thickness of the prepared bottom gate electrode is 100 nm.

[0057] S30, a ferroelectric layer is formed on the bottom gate electrode.

[0058] In this embodiment, a ferroelectric layer is deposited on the bottom gate electrode using an ALD process. The ferroelectric layer material is hafnium zirconium oxide (HZO). The ALD process parameters used in this embodiment are as follows: precursor: hafnium source peak value 50-60 Pa, water source peak value 150-200 Pa, zirconium source peak value 600-800 Pa, cycle number set to 50. Temperature is 220℃, time is 2 h 14 min. In this embodiment, the thickness of the prepared ferroelectric layer is 12 nm.

[0059] S40 forms a floating gate electrode on the ferroelectric layer.

[0060] In this embodiment, the ferroelectric layer surface undergoes homogenization, photolithography, drying, exposure, and development to obtain patterned photoresist. A photoresist stripper is used to remove any residual photoresist in the patterned area. A molybdenum metal layer is formed on the ferroelectric layer (at which point the patterned photoresist is present on the ferroelectric layer surface) using magnetron sputtering. A further lift-off process is used to obtain the patterned floating gate electrode. Alternatively, other materials / structures known in the art can be used as the floating gate electrode, and the prepared floating gate electrode has a thickness of 50 nm.

[0061] S50, annealed after metallization.

[0062] In this embodiment, after the floating gate electrode is formed, an annealing process is performed to induce HZO crystallization. The annealing conditions are as follows: temperature is 400℃, annealing atmosphere is N2, and annealing time is 2h.

[0063] S60, a gate dielectric layer is formed on the floating gate electrode.

[0064] In this embodiment, an ALD (Alternating Discharge) process is used to coat the annealed floating gate electrode with a gate dielectric layer made of aluminum oxide. In this embodiment, the thickness of the prepared gate dielectric layer is 20 nm.

[0065] S70, an active layer is formed on the gate dielectric layer.

[0066] In this embodiment, an active layer is formed on the gate dielectric layer using radio frequency magnetron sputtering. The reaction conditions used in this embodiment are as follows: sputtering pressure 0.5 Pa, Ar to O2 ratio of 44:6, sputtering power 60 W, and sputtering time 400 s. Patterned photoresist is obtained by performing homogenization, photolithography, drying, exposure, and development on the surface of the ITO active layer. After photoresist removal, a patterned ITO active layer is obtained. In this embodiment, the thickness of the prepared ITO active layer is 4 nm.

[0067] S80, active layer activation heat treatment;

[0068] In this embodiment, ITO is activated by annealing the active layer in an air environment. The annealing conditions are as follows: temperature 200°C, annealing atmosphere air, and annealing time 30 minutes.

[0069] S90 forms the source and drain on the active layer.

[0070] In this embodiment, the active layer surface undergoes spin coating, photolithography, drying, exposure, and development to obtain patterned photoresist. A photoresist stripper is used to remove any residual photoresist in the patterned area. A molybdenum metal layer is formed on the active layer (where the patterned photoresist is present) using magnetron sputtering. A further lift-off process is used to obtain patterned source and drain electrodes. In this embodiment, the prepared source and drain electrodes have a thickness of 100 nm.

[0071] Upon completion of step S90, the drive transistor is fully fabricated, and its structure is as follows: Figure 4 As shown, it includes a substrate 110, a bottom gate electrode 120, a ferroelectric layer 130, a floating gate electrode 140, a gate dielectric layer 150, an ITO active layer 160, a source electrode 170, and a drain electrode 171.

[0072] For the fabrication process of the switching transistor, such as Figure 5 As shown:

[0073] S10, Obtain the substrate.

[0074] The substrate can be a rigid substrate (e.g., a silicon / silicon oxide substrate) or a flexible substrate known in the art. In one embodiment of the invention, the substrate is a flexible substrate, such as a PI substrate. The substrate is ultrasonically cleaned for four to five minutes each with deionized water, acetone, and then more deionized water at a power of 100W to obtain a substrate for subsequent operations. A buffer layer, made of silicon dioxide, is then deposited on the surface of the substrate using a PECVD process. The PECVD process parameters used in this embodiment are as follows: First stage operating pressure 1500 mTorr, N2O and 5% SiH4 in a ratio of 700:200, power 100W, reaction temperature 300°C, and time 6 min. Second stage operating pressure 1130 mTorr, N2O and 5% SiH4 in a ratio of 700:200, power 100W, reaction temperature 300°C, and time 2 min. In this embodiment, the thickness of the prepared buffer layer is 100 nm.

[0075] S20, a floating gate electrode is formed on the substrate.

[0076] In one embodiment of the present invention, patterned photoresist is obtained by performing spin coating, photolithography, drying, exposure, and development on the substrate surface. Residual photoresist in the patterned area is removed using a photoresist stripper. A molybdenum metal layer is formed on a buffer layer (on which the patterned photoresist is present) using magnetron sputtering. A further lift-off process is used to obtain a patterned floating gate electrode. Other materials / structures known in the art can also be used as the bottom gate electrode. In this embodiment, the thickness of the prepared floating gate electrode is 50 nm.

[0077] S30, a gate dielectric layer is formed on the floating gate electrode.

[0078] In this embodiment, a gate dielectric layer is deposited on the floating gate electrode using an ALD process. The gate dielectric layer is made of aluminum oxide. In this embodiment, the thickness of the prepared gate dielectric layer is 20 nm.

[0079] S40, an active layer is formed on the gate dielectric layer.

[0080] In this embodiment, an active layer is formed on the gate dielectric layer using radio frequency magnetron sputtering. The reaction conditions used in this embodiment are as follows: sputtering pressure 0.5 Pa, Ar to O2 ratio of 44:6, sputtering power 60 W, and sputtering time 400 s. Patterned photoresist is obtained by performing homogenization, photolithography, drying, exposure, and development on the surface of the ITO active layer. After photoresist removal, the patterned ITO active layer is obtained, followed by annealing. In this embodiment, the thickness of the prepared ITO active layer is 4 nm.

[0081] S50, active layer activated heat treatment.

[0082] In this embodiment, ITO is activated by annealing the active layer in an air environment. The annealing conditions are as follows: temperature 200°C, annealing atmosphere air, and annealing time 30 minutes.

[0083] S60 forms the source and drain on the active layer.

[0084] In this embodiment, the active layer surface undergoes spin coating, photolithography, drying, exposure, and development to obtain patterned photoresist. A photoresist stripper is used to remove any residual photoresist in the patterned area. A molybdenum metal layer is formed on the active layer (where the patterned photoresist is present) using magnetron sputtering. A further lift-off process is used to obtain patterned source and drain electrodes. In this embodiment, the prepared source and drain electrodes have a thickness of 100 nm.

[0085] Upon completion of step S60, the switching transistor is fabricated, and its structure is as follows: Figure 6 As shown, it includes a substrate 210, a bottom gate electrode 220, a gate dielectric layer 230, an active layer 240, a source electrode 250, and a drain electrode 251.

[0086] Figure 7 This is the PV curve of the ferroelectric capacitor structure of the driving circuit in this embodiment of the invention. The horizontal axis represents the bottom gate voltage, and the vertical axis represents the polarization intensity. The calculated 2Pr value is approximately 44.93 μC / cm. 2 The polarization intensity is relatively large. Figure 7 Figures (b) and (c) show the transfer characteristic curve and output curve of the driver transistor, respectively, with a channel width of 50 μm and a length of 15 μm. It can be seen that the driver transistor exhibits excellent ferroelectric properties.

[0087] Figure 8 This is a holding effect diagram of the 2T drive unit in an embodiment of the present invention. When the switching transistor is turned off, the normalized on-state current of the drive unit remains basically unchanged within 50 seconds, maintaining around 0.1 μA / μm. Figure 8 It demonstrates the excellent retention performance of the 2T drive unit.

[0088] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A driving circuit based on a ferroelectric oxide thin-film transistor, characterized in that, It includes a matrix based on ferroelectric oxide thin-film transistors, which comprises multiple 2T drive units arranged in rows and columns.

2. The driving circuit based on a ferroelectric oxide thin-film transistor according to claim 1, characterized in that, The 2T drive unit includes a drive transistor and a switch transistor. The drive transistor is a ferroelectric oxide thin film transistor, which contains a ferroelectric capacitor structure. The source of the switch transistor is connected to the DATA line, the gate is connected to the SCAN line, the drain is connected to the floating gate electrode of the drive transistor, the source of the drive transistor is connected to the GND line, the drain is connected to one end of the load, and the other end of the load is connected to the VDD signal.

3. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor as described in claim 2, characterized in that, This includes methods for fabricating driving transistors and methods for fabricating switching transistors; The specific method for preparing the driving transistor is as follows: Step 1: Obtain the substrate and prepare a buffer layer on the substrate; Step 2: Perform photoresist homogenization, photolithography, drying, exposure and development on the substrate surface to obtain patterned photoresist. Use a photoresist remover to remove any residual photoresist in the patterned area. Use DC sputtering to form a metal layer on the buffer layer. Then, use a lift-off process to obtain the patterned bottom gate electrode. Step 3: Cover the bottom gate electrode with a ferroelectric layer; Step 4: Perform homogenization, photolithography, drying, exposure and development on the surface of the ferroelectric layer to obtain patterned photoresist. Use a photoresist remover to remove residual photoresist in the patterned area. Use magnetron sputtering to form a metal layer on the ferroelectric layer. Use a lift-off process to obtain patterned floating gate electrodes. Step 5: After the floating gate electrode is formed, annealing is performed to induce the crystallization of the ferroelectric layer. The floating gate electrode, the bottom gate electrode, and the crystallized ferroelectric layer constitute a ferroelectric capacitor. Step 6: Cover the annealed floating gate electrode with a gate dielectric layer; Step 7: Form an active layer on the gate dielectric layer; Step 8: Anneal the active layer in an air environment; Step 9: Perform homogenization, photolithography, drying, exposure and development on the surface of the active layer to obtain patterned photoresist. Use a photoresist remover to remove residual photoresist in the patterned area. Use magnetron sputtering to form a metal layer on the active layer. Then use a lift-off process to obtain patterned source and drain electrodes. The specific method for fabricating the switching transistor is as follows: Step A: Obtain the substrate and cover the substrate surface with a buffer layer; Step B: Perform photoresist homogenization, photolithography, drying, exposure and development on the substrate surface to obtain patterned photoresist. Use a photoresist remover to remove any residual photoresist in the patterned area. Use magnetron sputtering to form a molybdenum metal layer on the buffer layer. Use a lift-off process to obtain patterned floating gate electrodes. Step C: A gate dielectric layer is deposited on the floating gate electrode using an ALD process. The gate dielectric layer is made of aluminum oxide. Step D: An active layer is formed on the gate dielectric layer using an RF magnetron sputtering process; Step E: Anneal the active layer in an air environment; Step F: Perform homogenization, photolithography, drying, exposure and development on the surface of the active layer to obtain patterned photoresist. Use a photoresist stripper to remove any residual photoresist in the patterned area. Use magnetron sputtering to form a molybdenum metal layer on the active layer. Use a lift-off process to obtain patterned source and drain electrodes.

4. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, The buffer layer in step 1 or step A is made of silicon dioxide. The buffer layer is coated on the substrate surface by PECVD process. The PECVD process parameters are as follows: first stage working pressure 1500 mTorr, N2O and 5% SiH4 ratio 700:200, power 100W, reaction temperature 300℃, time 6min; second stage working pressure 1130 mTorr, N2O and 5% SiH4 ratio 700:200, power 100W, reaction temperature 300℃, time 2min; the thickness of the buffer layer is 100nm.

5. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, In step 2, the bottom gate electrode uses a titanium metal layer and a molybdenum metal layer, while in steps 4 and B, the floating gate electrode uses a molybdenum metal layer.

6. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, In step 3, an ALD process is used to coat the bottom gate electrode with a ferroelectric layer made of hafnium zirconium oxide. The ALD process parameters are as follows: precursor: hafnium source peak value 50-60 Pa, water source peak value 150-200 Pa, zirconium source peak value 600-800 Pa, cycle number set to 50, temperature 220℃, time 2h14min; ferroelectric layer thickness is 12nm.

7. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, The annealing conditions in step 5 are: temperature 400℃, annealing atmosphere N2, and annealing time 2h.

8. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, In steps 6 and C, an ALD process is used to cover the floating gate electrode with a gate dielectric layer; the gate dielectric layer is made of aluminum oxide and has a thickness of 20 nm.

9. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, In steps 7 and D, an active layer is formed on the gate dielectric layer using an RF magnetron sputtering process. The reaction conditions for the RF magnetron sputtering process are: sputtering pressure 0.5 Pa, Ar to O2 ratio of 44:6, sputtering power of 60 W, and sputtering time of 400 s. Patterned photoresist is obtained by performing homogenization, photolithography, drying, exposure, and development on the surface of the active layer. After photoresist removal, a patterned active layer with a thickness of 4 nm is obtained.

10. The method for fabricating a driving circuit based on a ferroelectric oxide thin-film transistor according to claim 3, characterized in that, The annealing conditions in steps E and 8 are as follows: temperature is 200℃, annealing atmosphere is air, and annealing time is 30 min.

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