Electrostatic protection semiconductor device and integrated circuit

Abstract

The invention discloses an electrostatic protection semiconductor device and an integrated circuit. The electrostatic protection semiconductor device comprises a substrate, a drift region, a first well region and a second well region which are distributed at two end parts of the drift region, a first N + injection region and a first P + injection region which are distributed at the upper part of the first well region at an interval, and a second P + injection region and a second N + injection region which are distributed at the upper part of the second well region at an interval, a gate electrode layer over the drift region between the first well region and the second well region; and an equivalent diode element over the first well region. The first N + injection region and the gate electrode layer are led out to the cathode electrode, the second P + injection region and the second N + injection region are led out to the anode electrode, and the equivalent diode element is connected between the first P + injection region and the cathode electrode. When an electrostatic pulse comes, a PNP triode and an equivalent diode element in the device are conducted before an SCR structure, no hysteresis effect exists, the latch-up effect caused by overvoltage of a pin is prevented while effective electrostatic protection is achieved, the electrostatic protection capacity is high, and robustness is high.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an electrostatic discharge (ESD) protected semiconductor device and integrated circuit. Background Technology

[0002] ESD (Electro-Static Discharge) is an objective, natural phenomenon, not easily perceived by the human body, yet it accompanies products throughout their entire lifecycle and poses a serious threat to integrated circuit products. From chip manufacturing, packaging, and testing to application, the external environment and internal structure accumulate a certain amount of charge, making them susceptible to electrostatic discharge (ESD). Therefore, ESD protection devices need to be placed at each pin in chip design. High-voltage CMOS or high-voltage BCD processes are widely used in the manufacture of integrated circuits for power management, high-voltage drives, and automotive electronics. The pins of these products often use LDMOS (Laterally Diffused Metal Oxide Semiconductor) or SCR (Silicon Controlled Rectifier) ​​structures for ESD protection.

[0003] For traditional LDMOS protection devices, when an electrostatic discharge (ESD) pulse occurs, the uneven turn-on of the parasitic NPN transistors leads to local current accumulation, which easily causes the internal base region expansion effect (kirk), resulting in local overheating and failure. To prevent Kirk, SCR structures are typically used for protection. SCR protection devices have good robustness and efficiency per unit area. However, when an ESD pulse occurs, the parasitic NPN and PNP transistors in the SCR turn on successively, forming an open-circuit positive feedback mechanism. When the SCR is fully turned on, it forms a low-resistance path, clamping the voltage to a very low value. That is, after the SCR structure is triggered, the sustaining voltage is very low and the trigger current is very small. If voltage overshoots or voltage spikes occur at the chip pins during testing or operation, the SCR device will be falsely triggered, causing a latch-up effect and burning out the chip. To ensure the sustaining voltage of ESD protection devices, LDMOS devices are often modified to form PNP structures, discharging current through parasitic PNP transistors. However, its robustness is lower, and achieving a higher HBM (Human Body Model) requires a larger device area. Therefore, currently common ESD protection devices all have some problems, and cannot simultaneously achieve electrostatic protection performance, cost, and area. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide an electrostatic discharge (ESD) protected semiconductor device and integrated circuit to solve the problems in the prior art.

[0005] According to one aspect of the present invention, an electrostatic discharge (ESD) protected semiconductor device is provided, comprising: a drift region located on an upper portion of a substrate; a first well region and a second well region laterally distributed at two ends of the upper portion of the drift region; a first N+ injection region and a first P+ injection region spaced apart on the upper portion of the first well region; a second P+ injection region and a second N+ injection region spaced apart on the upper portion of the second well region, wherein a gate electrode layer is distributed above the drift region between the first P+ injection region and the second P+ injection region; and an equivalent diode element located above the first well region, wherein the anode and cathode of the equivalent diode element are respectively connected to the first P+ injection region and the first N+ injection region, wherein the first N+ injection region is connected to the gate electrode layer and led out to the cathode electrode, and the second P+ injection region is connected to the second N+ injection region and led out to the anode electrode.

[0006] Optionally, when the anode electrode receives an electrostatic pulse, the first transistor structure composed of the second P+ injection region, the second well region, the drift region, the first well region, and the first P+ injection region is connected in series with the equivalent diode element to form a first current discharge path from the anode to the cathode.

[0007] Optionally, when the anode electrode receives an electrostatic pulse, the thyristor structure composed of the second P+ injection region, the second well region, the drift region, the first well region, and the first N+ injection region is turned on to form a second current discharge path from the anode to the cathode.

[0008] Optionally, when the anode electrode receives an electrostatic pulse, the first current discharge path is activated before the second current discharge path.

[0009] Optionally, when the current of the electrostatic pulse is greater than a first current threshold, the first current discharge path is opened; when the current of the electrostatic pulse is greater than a second current threshold, the second current discharge path is opened; and the second current threshold is greater than the first current threshold.

[0010] Optionally, the equivalent diode element includes at least one diode, and the sum of the forward voltage drops of the at least one diode does not exceed the forward voltage drop of the second transistor structure composed of the drift region, the first well region, and the first N+ injection region.

[0011] Optionally, the at least one diode includes at least one of a Schottky diode, a Zener diode, and a conventional diode.

[0012] Optionally, the sum of the forward voltage drops of the at least one diode is negatively correlated with the magnitude of the second current threshold required to open the second current discharge path.

[0013] Optionally, the number of the at least one diode is negatively correlated with the magnitude of the second current threshold required to open the second current discharge path.

[0014] Optionally, the electrostatic discharge (ESD) protected semiconductor device further includes: a plurality of isolation regions located on the substrate surface, which sequentially separate the first N+ injection region, the first P+ injection region, the second P+ injection region, and the second N+ injection region; a gate dielectric layer located below the gate electrode layer and adjacent to the first P+ injection region, wherein the gate electrode layer also covers a portion of the surface of the isolation region connected to the gate dielectric layer.

[0015] According to another aspect of the present invention, an integrated circuit is provided, comprising: a device to be protected; and the above-described electrostatic discharge (ESD) protection semiconductor device, wherein the ESD protection semiconductor device is connected to a pin of the device to be protected for discharging electrostatic pulses from the pin.

[0016] The electrostatic discharge (ESD) protected semiconductor device and integrated circuit provided by this invention interchanges the positions of the first N+ injection region and the first P+ injection region in the source-side P-well of a traditional SCR device, while simultaneously connecting the first P+ injection region to the cathode electrode via an equivalent diode element. This allows the parasitic PNP transistor to turn on first when the anode electrode receives an ESD pulse, with the parasitic PNP transistor and the equivalent diode element conducting in series to form a first current discharge path. As the current continues to increase, the voltage drop across the equivalent diode element increases, raising the potential of the first P+ injection region and the first well region below it. Once the potential reaches the on-state voltage drop of the parasitic NPN transistor, the SCR structure turns on, forming a second current discharge path. Thus, when the ESD pulse is small, the parasitic PNP transistor turns on first, and discharge is carried out through the first current discharge path containing the parasitic PNP transistor and the equivalent diode element. Since the PNP transistor has no hysteresis effect, it provides effective ESD protection while preventing latch-up caused by voltage overshoot or spikes at the pins leading to false triggering of the SCR device. When the current continues to increase, the SCR structure is activated to discharge the current, which has high robustness and can provide extremely high electrostatic protection capability. It can also improve the current discharge efficiency per unit area of ​​semiconductor devices. At the same time, the process is relatively simple to implement, easy to operate, has good electrostatic protection performance, and occupies a small area.

[0017] Preferably, the overall forward voltage drop of the equivalent diode element can be adjusted by regulating the type and number of diodes included in the equivalent diode element, thereby adjusting the turn-on timing of the SCR structure, expanding the application scenarios of the ESD protection device, and improving its adaptability. Specifically, the sum of the forward voltage drops of at least one diode included in the equivalent diode element is negatively correlated with the second current threshold required to turn on the second current discharge path. Therefore, the smaller the sum of the forward voltage drops of at least one diode, the larger the second current threshold, thereby extending the turn-on time of the second current discharge path and further avoiding latch-up effects. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of the cross-sectional structure of a silicon controlled rectifier (SCR) electrostatic discharge (ESD) semiconductor device is shown.

[0020] Figure 2 It shows Figure 1 The equivalent circuit structure diagram of a silicon controlled rectifier (SCR) electrostatic discharge (ESD) semiconductor device;

[0021] Figure 3 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to an embodiment of the present invention is shown.

[0022] Figure 4 It shows according to Figure 3 The equivalent circuit structure diagram of an electrostatic discharge (ESD) protected semiconductor device;

[0023] Figure 5 A current-voltage comparison diagram is shown between the thyristor electrostatic discharge (ESD) protection semiconductor device and the ESD protection semiconductor device of this embodiment during operation. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0025] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0026] Unless otherwise specified below, the individual layers or regions of a semiconductor device may be made of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, and SiC, and group IV semiconductors such as Si and Ge. The term "semiconductor structure" refers to the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "lateral extension" refers to extension along a direction generally perpendicular to the trench depth.

[0027] Figure 1 A schematic diagram of the cross-sectional structure of a silicon controlled rectifier (SCR) electrostatic discharge (ESD) semiconductor device is shown. Figure 2 It shows Figure 1 The equivalent circuit structure diagram of a silicon controlled rectifier electrostatic discharge (SCR) semiconductor device.

[0028] like Figure 1 As shown, the SCR structure electrostatic discharge (ESD) device includes a P-type doped substrate 101, an N-type doped drift region 102 distributed in the upper part of the substrate 101, and mutually spaced P-type well regions 103 and N-type well regions 104 laterally distributed in the upper part of the drift region 102. P+ implantation regions 133 and N+ implantation regions 134 are formed in the N-type well region 104, and P+ implantation regions 131 and N+ implantation regions 132 are formed in the P-type well region 103. A plurality of isolation regions 111 are formed on the surface of the substrate 101. These isolation regions are, for example, field oxide layers, which sequentially separate the P+ implantation regions 131, N+ implantation regions 132, P+ implantation regions 133, and N+ implantation regions 134. The sides of the field oxide layer are all bird-beak structures. On the side of the field oxide layer between the N+ implantation region 132 and the P+ implantation region 133, near the P-type well region 103, a gate dielectric layer 121 and a gate electrode layer 122 are formed. The gate dielectric layer 121 is adjacent to the field oxide layer, and the gate electrode layer 122 covers the gate dielectric layer 121 and partially covers the surface of the field oxide layer. The gate dielectric layer 121 may include silicon dioxide, silicon nitride, other dielectric materials, or any combination thereof. The gate electrode layer 122 is, for example, a polysilicon layer and / or a metal layer, or other conductive material layer. It is connected to the P+ implantation region 131, the N+ implantation region 132, and the gate electrode layer 122, and leads to the cathode electrode of the SCR structure. The P+ implantation region 133 and the N+ implantation region 134 are connected and lead to the anode electrode of the SCR structure.

[0029] This SCR structure can be considered as consisting of parasitic PNP transistors and parasitic NPN transistors between the anode and cathode, such as... Figure 2As shown, from the anode to the cathode, a PNP transistor and a resistor Rp are connected in series. The P+ injection region 133, the N-type well region 104, the drift region 102, and the P-type well region 103 are considered as PNP transistors, and the internal resistance of the P-type well region 103 is the resistor Rp. Additionally, from the anode to the cathode, a resistor Rn and an NPN transistor are connected in series. The base of the PNP transistor is connected between the resistor Rn and the collector of the NPN transistor, and the base of the NPN transistor is connected between the resistor Rp and the collector of the PNP transistor. The N-type drift region 102, the P-type well region 103, and the N+ injection region 132 are considered as NPN transistors, and the internal resistance of the N-type well region 104 is the resistor Rn. When a positive ESD pulse arrives, a positive pulse appears on the anode electrode. The positive voltage causes the PN junction formed by the N-type drift region 102 and the P-type well region 103 in the SCR to reverse bias. As the ESD voltage gradually increases, the PN junction gradually enters the avalanche breakdown state. The holes generated by the avalanche flow from the N-type well region 104 into the P-type well region 103 and are finally collected by the P+ injection region 131 in the P-type well region 103, generating a current I. PW Similarly, the generated electrons flow from the P-type well region 103 into the N-type well region 104 and are finally collected by the N+ injection region 134 of the N-type well region 104, generating a current I. NW Because parasitic resistances Rn and Rp exist in the N-type well region 104 and P-type well region 103 respectively, voltage drops are generated across them. When the voltage drop across either the N-type well region 104 or the P-type well region 103 reaches 0.7 V, one of the parasitic transistors, either NPN or PNP, will turn on. Once one transistor turns on, the voltage drop caused by the current flowing through its collector immediately turns on the other parasitic transistor. Ultimately, the two transistors form an open-circuit positive feedback mechanism, fully turning on the SCR and creating a low-resistance path. The voltage is clamped at a very low value, meaning the trigger voltage is high, while the sustaining voltage is low. Therefore, after electrostatic triggering, the sustaining voltage (Vh) of this SCR structure is very low, and the trigger current is very small. If, during testing or operation, a voltage overshoot or voltage spike occurs at the power supply pin, causing the SCR device to be falsely triggered and maintained at a very low voltage value, a latch-up effect will occur, burning out the chip.

[0030] Therefore, this invention is applicable to Figure 1 The SCR structure is improved by swapping the positions of the N+ and P+ injection regions in the P-type well region 103 at the source end of the SCR structure. Simultaneously, the P+ injection region is connected to the cathode via a diode structure. Under ESD pulses, the parasitic PNP transistor turns on first, preventing latch-up effects caused by pin overvoltage. The following combines... Figures 3-5 Detailed introduction.

[0031] Figure 3A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to an embodiment of the present invention is shown. Figure 4 It shows according to Figure 3 The equivalent circuit structure diagram of the electrostatic protection semiconductor device.

[0032] like Figure 3 As shown, the electrostatic discharge (ESD) protected semiconductor device 200 includes a P-type doped substrate 201, an N-type doped drift region 202 distributed in the upper part of the substrate 201, a first well region 203 and a second well region 204 laterally distributed at two ends in the upper part of the drift region 202, and an equivalent diode element 241. The first well region 203 is, for example, a P-type well region, and the second well region 204 is, for example, an N-type well region. A first N+ implantation region 231 and a first P+ implantation region 232, spaced apart from each other, are distributed in the upper part of the first well region 203. A second P+ implantation region 233 and a second N+ implantation region 234, spaced apart, are distributed in the upper part of the second well region 204. The first N+ implantation region 231 is located in the first well region 203 at one end away from the second well region 204, and the first P+ implantation region 232 is located in the first well region 203 at one end closer to the second well region 204. The second P+ implantation region 233 is distributed within the second well region 204 near one end of the first well region 203, and the second N+ implantation region 234 is distributed within the second well region 204 away from the first well region 203. A gate electrode layer 222 is distributed above the drift region 202 between the first P+ implantation region 232 and the second P+ implantation region 233. An equivalent diode element 241 is located above the first well region 203, and the anode and cathode of the equivalent diode element 241 are connected to the first P+ implantation region 232 and the first N+ implantation region 231, respectively. A plurality of isolation regions 211 are formed on the surface of the substrate 201. The isolation regions are, for example, field oxide layers or shallow trenches; here, a field oxide layer is used as an example. The plurality of field oxide layers sequentially separate the first N+ implantation region 231, the first P+ implantation region 232, the second P+ implantation region 233, and the second N+ implantation region 234. The sides of the field oxide layer are all beak-shaped. A gate dielectric layer 221 is formed on the side of the field oxide layer between the first P+ implantation region 232 and the second P+ implantation region 233, near the first well region 203. The gate dielectric layer 221 is located below the gate electrode layer 222 and adjacent to the first P+ implantation region 232. The gate electrode layer 222 also covers a portion of the surface of the field oxide layer connected to the gate dielectric layer 221. The gate dielectric layer 221 may include silicon dioxide, silicon nitride, other dielectric materials, or any combination thereof. The gate electrode layer 222 is, for example, a polysilicon layer and / or a metal layer, or other conductive material layer. It is connected to the first N+ implantation region 231 and the gate electrode layer 222, leading to the cathode electrode of the SCR structure. The second P+ implantation region 233 and the second N+ implantation region 234 are connected, leading to the anode electrode of the SCR structure.

[0033] like Figure 4As shown, the equivalent circuit of the electrostatic discharge (ESD) protection semiconductor device 200 can be represented as follows: A PNP transistor and an equivalent diode element Di are connected in series from the anode to the cathode. Additionally, a resistor Rn and an NPN transistor are connected in series from the anode to the cathode. The base of the PNP transistor is connected between the resistor Rn and the collector of the NPN transistor, and the base of the NPN transistor is connected between the equivalent diode element Di and the collector of the PNP transistor. That is, the equivalent diode element Di replaces the previous resistor Rp. Combined with... Figure 3 The second P+ injection region 233, the second well region 204, the drift region 202, the first well region 203, and the first P+ injection region 232 are considered as PNP transistors, i.e., the first transistor structure; the N-type drift region 202, the first well region 203, and the first N+ injection region 231 are considered as NPN transistors, i.e., the second transistor structure; the internal resistance of the N-type second well region 204 is resistor Rn. The equivalent diode element 241 includes at least one diode, and the sum of the forward voltage drops Vdi of the at least one diode does not exceed the forward voltage drop of the NPN transistor, which is typically 0.7V. Therefore, when the equivalent diode element 241 includes one diode, the forward voltage drop of that single diode does not exceed 0.7V; when the equivalent diode element 241 includes multiple diodes, these multiple diodes are connected in series, and the sum of the forward voltage drops of the series diodes does not exceed 0.7V.

[0034] See you again Figure 3When an ESD pulse arrives, the anode electrode receives a positive electrostatic current, causing the PN junction formed by the N-type drift region 202 and the first well region 203 to undergo avalanche breakdown due to reverse bias. The holes generated by the PN junction avalanche flow from the N-type drift region 202 into the P-type first well region 203. Since the first P+ injection region 232 is closer to the second well region 204, the holes are directly collected by the first P+ injection region 232 in the first well region 203, and no voltage drop is generated in the first well region 203 below the first N+ injection region 231 on the left, which is equivalent to the resistor Rp being ineffective. At this time, the NPN transistor in the ESD protection semiconductor device 200 cannot be turned on, and only the parasitic PNP transistor is turned on. Therefore, when the anode electrode receives an electrostatic pulse, the first transistor structure (PNP transistor) composed of the second P+ injection region 233, the second well region 204, the drift region 202, the first well region 203, and the first P+ injection region 232 is connected in series with the equivalent diode element 241 to form the first current discharge path P1 from the anode to the cathode, corresponding to the path shown by the solid arrow in the figure. Subsequently, since the PNP transistor has no hysteresis characteristic, the voltage on the electrostatic protection semiconductor device 200 will continuously increase. As the electrostatic current gradually increases, the internal resistance of the equivalent diode element 241 causes its voltage drop to gradually increase, thereby raising the potential of the first P+ injection region 232 and the first well region 203 connected to it. When the potential of the first well region 203 is raised to the on-state voltage drop of the NPN transistor, for example, 0.7V, the parasitic NPN transistor turns on, at which point the SCR structure is fully turned on and begins to discharge ESD current. When the anode electrode receives a larger electrostatic pulse, the thyristor structure composed of the second P+ injection region 233, the second well region 204, the drift region 202, the first well region 203 and the first N+ injection region 231 is turned on to form a second current discharge path P2 from the anode to the cathode, corresponding to the path shown by the dashed arrow in the figure.

[0035] Therefore, when the anode electrode receives an electrostatic pulse, the first current discharge path P1 opens before the second current discharge path P2 because the sum of the forward voltage drops of the equivalent diode elements is relatively small. Furthermore, the first current discharge path P1 opens only when the current of the electrostatic pulse exceeds the first current threshold, and the second current discharge path P2 opens only when the current of the electrostatic pulse exceeds the second current threshold, which is greater than the first current threshold. After the second current discharge path P2 opens, current discharge occurs primarily via the second current discharge path P2.

[0036] Furthermore, at least one diode forming the equivalent diode element includes at least one of a Schottky diode, a Zener diode, and a conventional diode. That is, one or more diodes of any type with a small forward voltage drop can be selected, whether it is a single diode or multiple diodes connected in series, whose sum of forward voltage drops is less than the forward voltage drop of an NPN transistor. In this embodiment, a Schottky diode with a forward voltage drop of approximately 0.3V is preferred to form the equivalent diode element. In addition, the sum of the forward voltage drops of at least one diode is negatively correlated with the magnitude of the second current threshold required to turn on the second current discharge path. Furthermore, the number of at least one diode is negatively correlated with the magnitude of the second current threshold required to turn on the second current discharge path. That is, the fewer the number of diodes, the smaller the sum of the forward voltage drops, the larger the current in the first current discharge path P1, and the later the second current discharge path P2 turns on. Schottky diodes have a lower forward voltage than conventional diodes, requiring a larger current to trigger the SCR structure, resulting in a later SCR structure turn-on, which is beneficial for the stability of the device. By selecting a base diode with a small forward voltage drop, the PNP transistor can be turned on first to discharge current. Furthermore, by adjusting the number of diodes and the forward voltage drop, the timing of the formation of the second current discharge path where the parasitic SCR structure is located can be adjusted, that is, the current discharged by the first current discharge path can be adjusted. This allows for more flexible application of the ESD protection device in different scenarios.

[0037] Therefore, after the chip is powered on and operating normally, when a voltage overshoot or voltage spike occurs at a chip pin or the pin of the device to be protected, the ESD protection semiconductor device receives an ESD pulse, causing the first current discharge path to open first. As long as the ESD pulse current does not exceed the trigger current of the SCR structure after triggering the first current discharge path of the PNP transistor, the second current discharge path cannot be triggered, thus avoiding latch-up caused by pin overvoltage or spikes. Furthermore, when the ESD current is large, both current discharge paths discharge current simultaneously, with the second current discharge path serving as the main discharge path, improving the current discharge capability per unit area. Therefore, this semiconductor device combines the hysteresis-free characteristics of PNP and the high robustness of SCR, effectively providing ESD protection while preventing latch-up caused by pin overvoltage. This embodiment uses field oxide technology as an example to introduce the ESD protection semiconductor device; however, the device structure upon which the above-mentioned current discharge path formation depends can also be applied to shallow trench isolation technology, etc., and will not be detailed here.

[0038] Figure 5 A current-voltage comparison diagram is shown between the thyristor electrostatic discharge (ESD) protection semiconductor device and the ESD protection semiconductor device of this embodiment during operation.

[0039] like Figure 5 As shown, the horizontal axis represents device voltage, and the vertical axis represents device current. The dashed line indicates... Figure 1A schematic diagram of the current-voltage relationship of an SCR structure electrostatic discharge (ESD) semiconductor device during operation. The solid line shows the voltage. Figure 3 The diagram illustrates the current-voltage relationship of an electrostatic discharge (ESD) protection semiconductor device during operation. It can be seen that in an SCR-structured ESD protection device, after the SCR structure is turned on, a discharge path is formed. The device's sustaining voltage Vh is low, and the trigger current is very small. If the device is falsely triggered due to overvoltage or glitches, a latch-up effect can easily occur. Furthermore, the trigger voltage Vt is relatively high, resulting in slow start-up and affecting the ESD protection effect. However, in the ESD protection semiconductor device of this embodiment, the PNP transistor turns on first. At this point, the voltage Vt0 at point A is easily turned on, achieving rapid discharge of the electrostatic current. Since the PNP transistor has no hysteresis, the voltage continues to rise to Vt1, while the electrostatic current gradually increases. Only when it reaches the current I1 corresponding to point B will the second current discharge path containing the SCR structure be activated, thus avoiding a latch-up effect caused by a small glitch. When the pin voltage overshoots or glitches occur, the current can be quickly discharged through the first current discharge path, preventing false triggering of the SCR structure and avoiding a latch-up effect. When the electrostatic current is larger, a second current discharge path can be activated, leveraging its high robustness to achieve superior electrostatic discharge. This not only results in a lower trigger voltage and better current discharge, but also prevents the SCR from entering a latch-up state due to a low trigger voltage. Furthermore, the current at point B can be adjusted by changing the number and type of diodes in the equivalent diode element, thus regulating the conduction timing of the SCR structure and allowing for applications in various device protection scenarios.

[0040] In addition, the present invention also provides an integrated circuit, which includes an electrostatic discharge (ESD) protection semiconductor device and a device to be protected as described in the above embodiments. The ESD protection semiconductor device is connected to the pins of the device to be protected and is used to discharge ESD pulses on the pins.

[0041] In summary, the electrostatic discharge (ESD) protection semiconductor device and integrated circuit of this invention interchange the positions of the first N+ injection region and the first P+ injection region in the source-side P-well of a traditional SCR device, while simultaneously connecting the first P+ injection region to the cathode electrode via an equivalent diode element. This allows the parasitic PNP transistor to turn on first when the anode electrode receives an ESD pulse, with the parasitic PNP transistor and the equivalent diode element conducting in series to form a first current discharge path. As the current continues to increase, the voltage drop across the equivalent diode element increases, raising the potential of the first P+ injection region and the first well region below it. Once the on-state voltage drop of the parasitic NPN transistor is reached, the SCR structure turns on, forming a second current discharge path. Thus, when the ESD pulse is small, the parasitic PNP transistor turns on first, and discharge is carried out through the first current discharge path containing the parasitic PNP transistor and the equivalent diode element. Since the PNP transistor has no hysteresis effect, effective ESD protection is achieved while preventing latch-up caused by voltage overshoot or spikes at the pins leading to false triggering of the SCR device. When the current continues to increase, the SCR structure is activated to discharge the current, which has high robustness and can provide extremely high electrostatic protection capability. It can also improve the current discharge efficiency per unit area of ​​semiconductor devices. At the same time, the process is relatively simple to implement, easy to operate, and has good electrostatic protection performance.

[0042] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An electrostatic discharge protection semiconductor device, comprising: a drift region on a substrate; a first well region and a second well region laterally distributed on two ends of an upper portion of the drift region; a first N+ implant region and a first P+ implant region spacedly distributed on an upper portion of the first well region; a second P+ implant region and a second N+ implant region spacedly distributed on an upper portion of the second well region, a gate electrode layer being distributed above the drift region between the first P+ implant region and the second P+ implant region; and an equivalent diode element above the first well region, an anode and a cathode of the equivalent diode element being connected to the first P+ implant region and the first N+ implant region respectively, wherein the first N+ implant region and the gate electrode layer are connected to lead out to a cathode electrode, and the second P+ implant region and the second N+ implant region are connected to lead out to an anode electrode.

2. The electrostatic discharge protection semiconductor device of claim 1, wherein, Upon receiving an electrostatic pulse at the anode electrode, a first triode structure composed of the second P+ implant region, the second well region, the drift region, the first well region and the first P+ implant region is turned on in series with the equivalent diode element to form a first current discharge path from the anode to the cathode.

3. The electrostatic discharge protection semiconductor device of claim 2, wherein, Upon receiving an electrostatic pulse at the anode electrode, a thyristor structure composed of the second P+ implant region, the second well region, the drift region, the first well region and the first N+ implant region is turned on to form a second current discharge path from the anode to the cathode.

4. The electrostatic discharge protection semiconductor device of claim 3, wherein, Upon receiving an electrostatic pulse at the anode electrode, the first current discharge path is turned on prior to the second current discharge path.

5. The electrostatic discharge protection semiconductor device of claim 3 or 4, wherein, The first current discharge path is turned on when a current of the electrostatic pulse is greater than a first current threshold, and the second current discharge path is turned on when the current of the electrostatic pulse is greater than a second current threshold, the second current threshold being greater than the first current threshold.

6. The electrostatic discharge protection semiconductor device of claim 3, wherein, The equivalent diode element comprises at least one diode, a sum of conduction voltage drops of the at least one diode being no more than a conduction voltage drop of a second triode structure composed of the drift region, the first well region and the first N+ implant region.

7. The electrostatic discharge protection semiconductor device of claim 6, wherein, The at least one diode comprises at least one of a Schottky diode, a Zener diode and a common diode.

8. The electrostatic discharge protection semiconductor device of claim 6, wherein, A magnitude of the sum of the conduction voltage drops of the at least one diode is negatively correlated with a magnitude of the second current threshold required for the second current discharge path to be turned on.

9. The electrostatic discharge protection semiconductor device of claim 6, wherein, A number of the at least one diode is negatively correlated with the magnitude of the second current threshold required for the second current discharge path to be turned on.

10. The electrostatic discharge protection semiconductor device of claim 1, further comprising: a plurality of isolation regions on a surface of the substrate, sequentially separating the first N+ implant region, the first P+ implant region, the second P+ implant region and the second N+ implant region; a gate dielectric layer below the gate electrode layer, adjacent to the first P+ implant region, the gate electrode layer further covering a portion of a surface of an isolation region connected to the gate dielectric layer.

11. An integrated circuit, comprising: a device to be protected; and ​ The electrostatic discharge protection semiconductor device according to any one of claims 1 to 9, which is connected to a pin of the device to be protected for discharging an electrostatic pulse to the pin.

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