Semiconductor structure and method of manufacturing the same, backside illuminated image sensor

Abstract

The application provides a semiconductor structure, a preparation method thereof and a back-illuminated image sensor, and belongs to the field of semiconductors. The semiconductor structure comprises a substrate, an isolation structure formed on the substrate, and the isolation structure separates the substrate into multiple regions; the isolation structure comprises a metal grid, a first semiconductor structure and a second semiconductor structure oppositely formed on the inner and outer sides of the metal grid; the Fermi levels of the first semiconductor structure, the metal grid and the second semiconductor structure are sequentially increased or sequentially decreased. The semiconductor structure can effectively improve the problems of misalignment of the metal grid, optical crosstalk, current crosstalk and the like, thereby improving the performance of the back-illuminated image sensor.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and in particular relates to a semiconductor structure and its fabrication method, and a back-illuminated image sensor. Background Technology

[0002] Back-illuminated CMOS (BSI) image sensors are widely used in consumer electronics, automotive electronics, medical and scientific imaging, security monitoring, and professional imaging technologies due to their high sensitivity and low noise characteristics.

[0003] Please see Figures 1 to 6 This diagram illustrates the fabrication process of a back-illuminated image sensor, providing insights into related technologies. In fabricating the back-illuminated image sensor, a patterned first barrier layer 100a (e.g., a photoresist layer formed by photoresist) is first formed on the surface of a substrate 10a. Then, under the blocking effect of the patterned first barrier layer 100a, the substrate 10a is etched to form a deep trench 110a. After removing the patterned first barrier layer 100a, an oxide layer 20a is deposited. A portion of the oxide layer 20a is located on the surface of the substrate 10a, and another portion is located within the deep trench 110a, forming a deep trench isolation (DTI) structure 11a. A grid material layer 300a and a patterned second barrier layer 100b are sequentially formed on the surface of the oxide layer 12a. Under the blocking effect of the second barrier layer 100b, the grid material layer 300a is etched, and then the second barrier layer 100b is removed to obtain the grid structure 30a.

[0004] However, existing back-illuminated image sensors still have the following problems: (1) In the existing back-illuminated image sensor manufacturing process, when fabricating the deep trench 110a and the grid structure 30a, it is necessary to first fabricate a patterned first barrier layer 100a and a patterned second barrier layer 100b. Two photolithography processes are required when fabricating the first barrier layer 100a and the second barrier layer 100b. Due to process deviations, the two photolithography processes may cause misalignment between the grid structure 30a and the deep trench 110a (see...). Figure 7This results in limited light isolation of the grid structure 30a, with light propagating between adjacent photosensitive units, which is detrimental to the performance of the image sensor. (2) The photosensitive unit (not shown, generally obtained by ion implantation of the substrate between the deep trench isolation structure) usually includes a P-type doped region and an N-type doped region. A potential barrier (i.e., a buried barrier, BB) is formed between the P-type doped region and the N-type doped region to guide photogenerated electrons to move towards the collection region and suppress the lateral diffusion of charge carriers. Film defects (such as oxide pinholes) between BB and the deep trench isolation structure (DTI) can easily lead to photocurrent crosstalk, resulting in increased dark current in the back-illuminated image sensor and mutual interference between photosensitive units (pixels), which will further affect the performance of the back-illuminated image sensor. Summary of the Invention

[0005] In view of this, one of the objectives of this application is to provide a semiconductor structure and a method for preparing the same, in order to solve one or more of the above-mentioned technical problems.

[0006] Another objective of this application is to provide a back-illuminated image sensor that utilizes the aforementioned semiconductor structure and fabrication method, thereby improving the performance of the back-illuminated image sensor.

[0007] In a first aspect, this application provides a semiconductor structure, comprising:

[0008] Substrate;

[0009] An isolation structure formed on a substrate divides the substrate into multiple regions; the isolation structure includes a metal grid, a first semiconductor structure and a second semiconductor structure formed on the inner and outer sides of the metal grid; the Fermi levels of the first semiconductor structure, the metal grid and the second semiconductor structure increase or decrease sequentially.

[0010] Optionally, the first semiconductor structure and the second semiconductor structure are formed by doping a substrate, wherein one of the first semiconductor structure and the second semiconductor structure is N-type doped and the other is P-type doped.

[0011] Optionally, if the first semiconductor structure is an N-type doped substrate, then the N-type doping concentration of the first semiconductor structure is greater than or equal to... .

[0012] Optionally, if the first semiconductor structure is a P-type doped substrate, then the P-type doping concentration of the first semiconductor structure is greater than or equal to... .

[0013] Optionally, if the second semiconductor structure is an N-type doped substrate, then the N-type doping concentration of the second semiconductor structure is greater than or equal to... .

[0014] Optionally, if the second semiconductor structure is a P-type doped substrate, then the P-type doping concentration of the second semiconductor structure is greater than or equal to... .

[0015] Optionally, a SiN layer is further disposed between the top of the first semiconductor structure and the metal grid.

[0016] Optionally, the metal grid is made of any one or more of Al, Cu, W, Ag, and TiN.

[0017] Secondly, this application provides a method for fabricating a semiconductor structure, including:

[0018] Provide substrate;

[0019] An isolation structure is formed on a substrate, which divides the substrate into multiple regions; the isolation structure includes a metal grid, a first semiconductor structure and a second semiconductor structure formed on the inner and outer sides of the metal grid; the Fermi levels of the first semiconductor structure, the metal grid and the second semiconductor structure are sequentially increased or sequentially decreased.

[0020] Optionally, the step of forming an isolation structure on the substrate includes:

[0021] A sacrificial layer is formed on the substrate surface;

[0022] A barrier layer and a barrier layer sacrificial portion are formed on the surface of the sacrificial layer. The barrier layer includes a patterned region corresponding to the fabrication region of the isolation structure. The barrier layer sacrificial portion is located in the patterned region, and the thickness of the barrier layer sacrificial portion is lower than that of the barrier layer.

[0023] The barrier layer, the barrier layer sacrificial portion, the sacrificial layer, and the substrate are etched to form a trench in the substrate. A portion of the substrate corresponding to the barrier layer sacrificial portion is retained in the trench as a first semiconductor structure fabrication area. The sacrificial layer is retained on top of the first semiconductor structure fabrication area.

[0024] Ion implantation is performed on the fabrication region of the first semiconductor structure to form the first semiconductor structure;

[0025] A metal grid is formed within the trench, and the metal grid covers the first semiconductor structure and the sacrificial layer;

[0026] Ion implantation is performed on the substrate surrounding the metal grid to form a second semiconductor structure.

[0027] Optionally, the step of forming a patterned barrier layer on the surface of the sacrificial layer includes:

[0028] A photoresist layer is formed on the surface of the sacrificial layer;

[0029] The photoresist layer is exposed using grayscale photolithography.

[0030] The exposed photoresist layer is developed to obtain a patterned barrier layer, which includes a patterned region corresponding to the isolation structure, and a portion of the photoresist layer corresponding to the first semiconductor structure is retained in the patterned region.

[0031] Optionally, the step of exposing the photoresist layer using grayscale photolithography includes:

[0032] If the photoresist layer is positive resist, when the photoresist layer is exposed, the exposure dose of the photoresist layer corresponding to the barrier layer sacrificial part in the patterned area is lower than the exposure dose of the photoresist layer in other areas of the patterned area.

[0033] If the photoresist layer is a negative resist, then when the photoresist layer is exposed, the exposure dose at the photoresist layer corresponding to the sacrificial part of the barrier layer in the patterned region is higher than the exposure dose at the photoresist layer in other regions of the patterned region.

[0034] Optionally, the step of exposing the photoresist layer using grayscale photolithography includes:

[0035] If the photoresist layer is positive photoresist, when the photoresist layer is exposed, the transmittance of the mask corresponding to the sacrificial part of the barrier layer in the patterned area is lower than the transmittance of the mask corresponding to other areas in the patterned area.

[0036] If the photoresist layer is a negative photoresist, when the photoresist layer is exposed, the transmittance of the mask corresponding to the sacrificial part of the blocking layer in the patterned area is higher than the transmittance of the mask corresponding to other areas in the patterned area.

[0037] Thirdly, this application provides a back-illuminated image sensor, comprising the semiconductor structure described in any of the preceding claims or prepared using the method described in any of the preceding claims.

[0038] The unexpected technical effects of the technical solution provided in this application include:

[0039] This application provides a semiconductor structure including an isolation structure formed on a substrate. The isolation structure includes a metal grid, a first semiconductor structure formed on the inner and outer sides of the metal grid, and a second semiconductor structure. An unexpected technical advantage is that by incorporating the metal grid as part of the isolation structure, both the metal grid and the isolation structure can be formed in a single photolithography process. This effectively avoids the technical problem of misalignment between the metal grid and the isolation structure due to process deviations in photolithography when forming the metal grid and isolation structure separately through multiple photolithography processes. Incorporating the metal grid as part of the isolation structure further enhances the optical isolation effect, preventing light propagation between adjacent photosensitive units and avoiding optical crosstalk. Furthermore, since the metal grid and isolation structure can be formed in a single photolithography process, the use of materials such as photomasks and photoresists in the photolithography process can be effectively reduced, thus lowering manufacturing costs.

[0040] Furthermore, the Fermi levels of the first semiconductor structure, the metal grid, and the second semiconductor structure increase or decrease sequentially. An unexpected technical effect is the formation of a potential barrier between these structures through the difference in Fermi levels. For example, suppose the first semiconductor structure (e.g., an N-type doped structure) is located inside the metal grid, and the second semiconductor structure (e.g., a P-type doped structure) is located outside the metal grid. In this case, the Fermi levels of the first semiconductor structure, the metal grid, and the second semiconductor structure decrease sequentially. Due to the difference in Fermi levels, the work functions of the first semiconductor structure, the metal grid, and the second semiconductor structure will differ (the work function is the minimum energy required for a material to raise an electron from the Fermi level to the vacuum level). Because of this difference in work functions, when the first semiconductor structure, the metal grid, and the second semiconductor structure come into contact, holes in the first semiconductor structure with a relatively higher work function will move to the metal grid with a relatively lower work function, and electrons in the second semiconductor structure with a relatively lower work function will move to the metal grid with a relatively higher work function. This creates a depletion layer and a potential barrier between the first semiconductor structure, the metal grid, and the second semiconductor structure, hindering carrier movement. The propagation of charge carriers between the first semiconductor structure, the metal grid, and the second semiconductor structure is isolated by the effect of potential barriers, thereby avoiding current crosstalk.

[0041] Furthermore, this application does not use an oxide layer as the isolation structure, thus avoiding the increase in dark current caused by film defects. Simultaneously, the dark current at the second semiconductor structure in the isolation structure is attracted by the charge carriers (electrons or holes) of the first semiconductor structure, which helps to further suppress dark current. It also allows skipping the grounding step used in related technologies to suppress dark current, shortening the process flow. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0043] Figure 1 A schematic diagram illustrating the fabrication process of a back-illuminated image sensor, provided for the present technology.

[0044] Figure 2 A schematic diagram illustrating the fabrication process of a back-illuminated image sensor, provided for the present technology.

[0045] Figure 3 A schematic diagram illustrating the fabrication process of a back-illuminated image sensor, provided for the present technology.

[0046] Figure 4 A schematic diagram illustrating the fabrication process of a back-illuminated image sensor, provided for the present technology.

[0047] Figure 5 A schematic diagram illustrating the fabrication process of a back-illuminated image sensor, provided for the present technology.

[0048] Figure 6 A schematic diagram illustrating the fabrication process of a back-illuminated image sensor, provided for the present technology.

[0049] Figure 7 A schematic diagram illustrating the misalignment of a grid structure and a deep trench isolation structure in the prior art;

[0050] Figure 8 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0051] Figure 9 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0052] Figure 10 A flowchart illustrating a method for fabricating a back-illuminated image sensor according to an embodiment of this application;

[0053] Figure 11 A flowchart illustrating a method for fabricating an isolation structure according to an embodiment of this application;

[0054] Figure 12 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0055] Figure 13A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0056] Figure 14 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0057] Figure 15 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0058] Figure 16 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0059] Figure 17 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0060] Figure 18 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0061] Figure 19 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0062] Figure 20 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0063] Figure 21 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0064] Figure 22 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0065] Figure 23 A schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application;

[0066] Figure 24 This is a schematic diagram of the structure of a back-illuminated image sensor during the manufacturing process provided in this application.

[0067] Related technologies provided Figures 1 to 6 The accompanying figure labels are as follows:

[0068] 10a: Substrate; 100a: First barrier layer; 100b: Second barrier layer; 110a: Deep trench; 11a: Deep trench isolation structure;

[0069] 20a: Oxide layer;

[0070] 30a: Grid structure; 300a: Grid material layer.

[0071] This application provides Figures 8 to 24 The accompanying figure labels are as follows:

[0072] 10: Substrate; 11: Isolation structure; 110: Trench; 111: Metal grid; 1111: Grid metal layer; 112: First semiconductor structure; 1121: Fabrication region of the first semiconductor structure; 113: Second semiconductor structure; 114: Sacrificial layer;

[0073] 20: Barrier layer; 200: Photoresist layer; 21: Grayscale mask; 211: Transmitting area; 212: Low grayscale area; 213: High grayscale area; 22: Patterned area; 221: Barrier layer sacrificial part;

[0074] 30: Filter structure; 31: Blue filter structure; 32: Green filter structure; 33: Red filter structure;

[0075] 40: Lens structure. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0077] Figure 8 This is a schematic diagram of a semiconductor structure provided in one embodiment of this application. See also... Figure 8 ,include:

[0078] Substrate 10;

[0079] An isolation structure 11 is formed on the substrate 10, which divides the substrate 10 into multiple regions; the isolation structure 11 includes a metal grid 111, a first semiconductor structure 112 and a second semiconductor structure 113 formed on the inner and outer sides of the metal grid 111; the Fermi levels of the first semiconductor structure 112, the metal grid 111 and the second semiconductor structure 113 are sequentially increased or sequentially decreased.

[0080] As an example provided in this application, a Schottky contact is formed between the first semiconductor structure 112 and the metal grid 111, and a Schottky contact is formed between the metal grid 111 and the second semiconductor structure 113.

[0081] In one example, substrate 10 can be any one of substrates such as Si substrate, SiC substrate, SOI substrate, Ge substrate, GaAs substrate, etc.

[0082] For example, substrate 10 can be a Si substrate.

[0083] In one example, the metal grid 111 is made of any one or more of Al, Cu, W, Ag, and TiN.

[0084] For example, the metal grille 111 is made of W material.

[0085] In one example, a sacrificial layer 114 is further disposed between the top of the first semiconductor structure 112 and the metal grid 111. The sacrificial layer 114 is a SiN layer, and the SiN layer and the metal grid 111 cooperate to form a composite metal grid.

[0086] In one example, the first semiconductor structure 112 and the second semiconductor structure 113 are formed by doping the substrate 10, wherein one of the first semiconductor structure 112 and the second semiconductor structure 113 is N-type doped and the other is P-type doped.

[0087] As an example, the first semiconductor structure 112 is formed by N-type doping of the substrate, and the second semiconductor structure 113 is formed by P-type doping of the substrate.

[0088] This application obtains a first semiconductor structure 112 and a second semiconductor structure 113 by doping a substrate 10. Compared to the traditional method of forming an oxide layer in a deep trench, this application can effectively avoid phenomena such as photocurrent crosstalk caused by film defects in the oxide layer. Furthermore, taking a P-type doped second semiconductor structure as an example and an N-type doped first semiconductor structure as an example, the dark current in the second semiconductor structure 113 is attracted by electrons in the first semiconductor structure 112, thereby effectively suppressing the dark current of the back-illuminated image sensor and improving its performance. Conversely, if the second semiconductor structure is an N-type doped structure and the first semiconductor structure is a P-type doped structure, the generated dark current can also be suppressed. This application can also skip the grounding step used in the fabrication process of traditional back-illuminated image sensors to suppress dark current, shortening the process flow. The unexpected technical effect of this application, by manufacturing the metal grille and the isolation structure simultaneously, is that it not only ensures that the two are highly aligned in principle, avoiding the problem of reduced isolation effect caused by misalignment between the existing grille structure and the deep trench, but also saves a photomask, simplifies the manufacturing process, and reduces manufacturing costs.

[0089] The present invention sets a first semiconductor structure with a Fermi level higher than that of the metal grid inside the metal grid, and sets a second semiconductor structure with a Fermi level lower than that of the metal grid outside the metal grid to form a Schottky barrier. This enables the isolation structure to have an electrical isolation function, preventing current from flowing between photosensitive units and preventing current crosstalk.

[0090] It should be noted that the region isolated by the isolation structure 11 within the substrate 10 is the photosensitive region for forming a photodiode. The photodiode can be formed using epitaxial growth or doping methods in the prior art. The specific timing and method of formation do not affect the technical problem solved by this invention. Therefore, this application will not elaborate further.

[0091] In one example, if the first semiconductor structure 112 is an N-type doped substrate, then the N-type doping concentration of the first semiconductor structure 112 is greater than or equal to... .

[0092] In one example, if the first semiconductor structure 112 is a p-type doped substrate, then the p-type doping concentration of the first semiconductor structure 112 is greater than or equal to... .

[0093] In one example, if the second semiconductor structure 113 is an N-type doped substrate, then the N-type doping concentration of the second semiconductor structure 113 is greater than or equal to... .

[0094] In one example, if the second semiconductor structure 113 is a p-type doped substrate, then the p-type doping concentration of the second semiconductor structure 113 is greater than or equal to... .

[0095] In one example, the doping element for P-type doping may include boron.

[0096] In one example, the doping element for N-type doping may include phosphorus or arsenic.

[0097] Figure 9 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. See also... Figure 9 ,include:

[0098] S101, Provide substrate 10.

[0099] In one example, substrate 10 can be any one of substrates such as Si substrate, SiC substrate, SOI substrate, Ge substrate, GaAs substrate, etc.

[0100] For example, substrate 10 can be a Si substrate.

[0101] S102, An isolation structure 11 is formed on the substrate 10, the isolation structure 11 dividing the substrate 10 into multiple regions; the isolation structure 11 includes a metal grid 111, a first semiconductor structure 112 and a second semiconductor structure 113 formed on the inner and outer sides of the metal grid 111; the Fermi levels of the first semiconductor structure 112, the metal grid 111 and the second semiconductor structure 113 are sequentially increased or sequentially decreased.

[0102] See Figure 11 In one example, step S102 includes:

[0103] Step 1: Form a sacrificial layer 114 on the surface of substrate 10.

[0104] In one example, a SiN layer is formed on the surface of substrate 10 as a sacrificial layer 114.

[0105] As an example, the sacrificial layer 114 can be deposited using chemical vapor deposition (CVD) processes, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0106] See Figure 12 Specifically, the prepared sacrificial layer 114 is shown.

[0107] Step 2: A barrier layer 20 and a barrier layer sacrificial portion 221 are formed on the surface of the sacrificial layer 114. The barrier layer 20 includes a patterned region 22 corresponding to the fabrication area of ​​the isolation structure 11. The barrier layer sacrificial portion 221 is located in the patterned region 22, and the thickness of the barrier layer sacrificial portion 221 is lower than that of the barrier layer 20.

[0108] In one example, step 2 includes:

[0109] Step 1: Form a photoresist layer 200 on the surface of the sacrificial layer 114.

[0110] The photoresist layer 200 can be either positive or negative photoresist, and this application does not impose any restrictions on it.

[0111] See Figure 13 Specifically, the prepared photoresist layer 200 is shown.

[0112] The second step is to expose the photoresist layer 200 using grayscale photolithography.

[0113] In one example, if the photoresist layer 200 is a positive photoresist, when the photoresist layer 200 is exposed, the exposure dose at the photoresist layer 200 corresponding to the barrier layer sacrificial portion 221 in the patterned region 22 is lower than the exposure dose at the photoresist layer 200 in other regions of the patterned region 22.

[0114] If the photoresist layer 200 is a negative photoresist, when the photoresist layer 200 is exposed, the exposure dose at the photoresist layer 200 corresponding to the barrier layer sacrificial portion 221 in the patterned region 22 is higher than the exposure dose at the photoresist layer 200 in other regions of the patterned region 22.

[0115] It should be noted that exposure dose is the product of light intensity and exposure time.

[0116] In another example, if the photoresist layer 200 is a positive photoresist, when the photoresist layer 200 is exposed, the transmittance at the mask (grayscale mask 21) corresponding to the barrier layer sacrificial portion 221 in the patterned region 22 is lower than the transmittance at the masks (grayscale mask 21) corresponding to other regions in the patterned region 22.

[0117] If the photoresist layer 200 is a negative photoresist, when the photoresist layer 200 is exposed, the transmittance at the mask (grayscale mask 21) corresponding to the barrier layer sacrificial part 221 in the patterned region 22 is higher than the transmittance at the mask (grayscale mask 21) corresponding to other regions in the patterned region 22.

[0118] See Figure 14 To facilitate understanding of grayscale lithography technology, provide Figure 14 and Figure 15 Used to explain grayscale lithography technology.

[0119] Grayscale lithography is a micro-nano fabrication technique that creates continuous or multi-level stepped structures on photoresist by adjusting the exposure dose or mask design. Unlike traditional binary lithography, grayscale lithography enables precise control of three-dimensional morphology and has important applications in microelectromechanical systems (MEMS), optical devices, and biochips.

[0120] The core technologies of grayscale lithography include exposure dose modulation and grayscale mask technology.

[0121] Exposure dose modulation: By controlling the exposure intensity of a laser or electron beam, different areas of the photoresist receive different doses of energy, resulting in a structure with gradually varying thickness after development. For example, during electron beam exposure, the dose gradient is achieved by adjusting the beam current or residence time.

[0122] Grayscale mask technology: Halftone masks are used, whose transmittance varies continuously or in steps. The distribution of transmitted light intensity corresponds to the difference in the dissolution rate of the photoresist, ultimately forming a three-dimensional morphology.

[0123] exist Figure 14 In the process, a grayscale mask 21 is used to expose the photoresist layer 200. The grayscale mask 21 has regions with different grayscale values. Figure 14 A photoresist layer 200 is formed using negative resist. A grayscale mask 21 has a light-transmitting region 211, a low-grayscale region 212, and a high-grayscale region 213. The light-transmitting region 211 allows all light to pass through and undergo a photochemical reaction with the photoresist layer 200. The low-grayscale region 212 allows only a portion of the light to pass through and undergo a photochemical reaction with the photoresist layer 200. The high-grayscale region 213 blocks light, preventing the photoresist layer 200 from undergoing a photochemical reaction with light.

[0124] The third step is to develop the exposed photoresist layer 200 to pattern the photoresist layer and form the barrier layer 20 and the barrier layer sacrificial part 221.

[0125] See Figure 15 In adopting Figure 14 The grayscale mask technique shown in the figure exposes the photoresist layer 200, and after developing the photoresist layer 200, the desired result can be obtained. Figure 15 The structure shown is such that by adjusting the grayscale values ​​of different areas of the grayscale mask 21, different areas of the photoresist layer 200 surface receive different light intensities, thereby causing different degrees of dissolution of the photoresist layer 200 surface during the development process. This ultimately forms a structure like... Figure 15 The diagram shows a barrier layer 20 with a patterned region 22, and a barrier layer sacrificial portion 221 is retained in the patterned region 22.

[0126] In subsequent steps, when the trench 110 is formed by etching, the difference in etching rate between the barrier layer sacrificial portion 221 and the sacrificial layer 114 is utilized to retain a portion of the substrate corresponding to the position of the barrier layer sacrificial portion 221 in the trench 110 as the subsequent first semiconductor structure fabrication region 1121.

[0127] Step 3: Etch the barrier layer 20, barrier layer sacrificial portion 221, sacrificial layer 114, and substrate 10 to form a trench 110 in the substrate 10. A portion of the substrate 10 corresponding to the barrier layer sacrificial portion 221 is retained in the trench 110 as a first semiconductor structure fabrication region 1121. The sacrificial layer 114 is retained on the top of the first semiconductor structure fabrication region 1121.

[0128] In one example, a high aspect ratio etching process is used to etch the barrier layer 20, the sacrificial layer 114, and the substrate 10.

[0129] As an example, the etching process used can be high-density plasma etching (HDP Etching).

[0130] See Figure 17 After etching, a portion of the barrier layer 20 is etched away in the thickness direction, while a small portion of the sacrificial layer 114 is retained on top of the first semiconductor structure fabrication region 1121 for subsequent use in conjunction with the metal grid 111 to form a composite metal grid. A trench 110 is formed in the substrate 10, and a portion of the substrate 10 is retained in the trench 110 as the first semiconductor structure fabrication region 1121.

[0131] It should be noted that trench 110 is a deep trench.

[0132] Step 4: Ion implantation is performed on the first semiconductor structure fabrication region 1121 to form the first semiconductor structure 112. During the ion implantation process, the remaining barrier layer 20 and the sacrificial layer 114 at its bottom are used as ion barriers to implant doped ions into the first semiconductor structure fabrication region 1121. Since the sacrificial layer 114 in the trench 110 is relatively thin, the required depth of ion implantation into the first semiconductor structure fabrication region 1121 can be ensured by adjusting the implantation depth and dose in the ion implantation process. Other substrate areas are simultaneously covered by the remaining barrier layer 20 and the sacrificial layer 114 at its bottom, so ions are basically unable to be implanted. A small amount of ion implantation is also performed on the sidewalls of the trench 110, but the ions implanted in the subsequent ion implantation process to form the second semiconductor structure can offset the influence of the ions implanted in this process.

[0133] In one example, the first semiconductor structure 112 may be N-type doped Si or P-type doped Si.

[0134] If the first semiconductor structure 112 can be N-type doped Si, then phosphorus or arsenic can be implanted into the fabrication region 1121 of the first semiconductor structure to form a doping concentration greater than or equal to First semiconductor structure 112.

[0135] If the first semiconductor structure 112 can be P-type doped Si, boron can be implanted into the fabrication region 1121 of the first semiconductor structure to form a doping concentration greater than or equal to First semiconductor structure 112.

[0136] See Figure 18 Specifically, the first semiconductor structure 112 obtained by ion implantation is shown.

[0137] See Figure 19 After the first semiconductor structure 112 is prepared, the barrier layer 20 is removed.

[0138] Step 5: Form a metal grid 111 in the trench 110, the metal grid 111 covering the first semiconductor structure 112 and the sacrificial layer 114 in the trench 110.

[0139] In one example, step 5 includes:

[0140] The first step is to prepare the grid metal layer 1111.

[0141] As an example, the material used for the grid metal layer 1111 can be any one or more of Al, Cu, W, Ag, and TiN.

[0142] For example, the material used for the grid metal layer 1111 is W.

[0143] As an example, the grid metal layer can be deposited using either physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0144] See Figure 20 Specifically, the prepared grid metal layer 1111 is shown.

[0145] The second step is to grind the metal layer 1111 of the grid to obtain the metal grid 111.

[0146] As an example, the metal layer 1111 of the grid can be ground using a chemical mechanical polishing process and left on the sacrificial layer 114 to obtain the metal grid 111.

[0147] See Figure 21 Specifically, the prepared metal grid 111 is shown.

[0148] See Figure 22 After the metal grid 111 is prepared, the sacrificial layer 114 is removed (the sacrificial layer 114 in the metal grid is retained to cooperate with the metal grid 111 to form a composite metal grid). The sacrificial layer 114 can be removed by wet etching process.

[0149] Step 6: Ion implantation is performed on the substrate 10 surrounding the metal grid 111 to form a second semiconductor structure 113 (see [link to documentation] for the implanted second semiconductor structure 113). Figure 8 ).

[0150] In one example, the second semiconductor structure 113 can be N-type doped Si or P-type doped Si.

[0151] If the second semiconductor structure 113 can be N-type doped Si, then phosphorus or arsenic elements can be implanted into the substrate 10 surrounding the metal grid 111 to form a doping concentration greater than or equal to Second semiconductor structure 113.

[0152] If the second semiconductor structure 113 can be P-type doped Si, boron can be implanted into the substrate 10 surrounding the metal grid 111 to form a doping concentration greater than or equal to Second semiconductor structure 113.

[0153] Finally, the second semiconductor structure 113 obtained by ion implantation can be found in [reference needed]. Figure 8 .

[0154] Figure 10 This is a flowchart illustrating a method for fabricating a back-illuminated image sensor according to an embodiment of this application. See also... Figure 10 ,include:

[0155] S201, Provide substrate 10.

[0156] See step S101.

[0157] S202, An isolation structure 11 is formed on the substrate 10, the isolation structure 11 dividing the substrate 10 into multiple regions; the isolation structure 11 includes a metal grid 111, a first semiconductor structure 112 and a second semiconductor structure 113 formed on the inner and outer sides of the metal grid 111; the Fermi levels of the first semiconductor structure 112, the metal grid 111 and the second semiconductor structure 113 are sequentially increased or sequentially decreased.

[0158] See step S102.

[0159] S203, A photosensitive structure 12 is formed between the isolation structures 11.

[0160] Among them, the photosensitive structure 12 is a photodiode structure, which is used to convert optical signals into electrical signals.

[0161] As an example, the photosensitive structure 12 typically includes P-type doped regions and N-type doped regions, and the photosensitive structure 12 can be obtained by ion implantation of the substrate 10.

[0162] In the aforementioned step S102, a second semiconductor structure 113 (e.g., ...) is formed in the substrate on the side of the metal grid by ion implantation. Figure 8 As shown, if the second semiconductor structure 113 is P-type doped, then the second semiconductor structure 113 is further N-type doped to form an N-type doped region. The N-type doped region and the second semiconductor structure 113 cooperate to form the photosensitive structure 12. Conversely, if the second semiconductor structure 113 is N-type doped, then the second semiconductor structure 113 is further P-type doped to form a P-type doped region. The P-type doped region and the second semiconductor structure 113 cooperate to form the photosensitive structure 12.

[0163] See Figure 23 Specifically, the photosensitive structure 12 is shown.

[0164] S204. A filter structure 30 and a lens structure 40 are formed on the photosensitive structure 12.

[0165] Among them, the filter structure 30 can be a three-primary-color filter structure, namely a blue filter structure 31, a green filter structure 32 and a red filter structure 33, and the lens structure 40 can be a microlens.

[0166] See Figure 23 and Figure 24 Specifically, the filter structure 30 and the lens structure 40 are shown.

[0167] The unexpected technical effects of the technical solution provided in this application include:

[0168] This application provides a semiconductor structure including an isolation structure formed on a substrate. The isolation structure includes a metal grid, a first semiconductor structure formed on the inner and outer sides of the metal grid, and a second semiconductor structure. An unexpected technical advantage is that by incorporating the metal grid as part of the isolation structure, both the metal grid and the isolation structure can be formed in a single photolithography process. This effectively avoids the technical problem of misalignment between the metal grid and the isolation structure due to process deviations in photolithography when forming the metal grid and isolation structure separately through multiple photolithography processes. Incorporating the metal grid as part of the isolation structure further enhances the optical isolation effect, preventing light propagation between adjacent photosensitive units and avoiding optical crosstalk. Furthermore, since the metal grid and isolation structure can be formed in a single photolithography process, the use of materials such as photomasks and photoresists in the photolithography process can be effectively reduced, thus lowering manufacturing costs.

[0169] Furthermore, the Fermi levels of the first semiconductor structure, the metal grid, and the second semiconductor structure increase or decrease sequentially. An unexpected technical effect is the formation of a potential barrier between these structures through the difference in Fermi levels. For example, suppose the first semiconductor structure (e.g., an N-type doped structure) is located inside the metal grid, and the second semiconductor structure (e.g., a P-type doped structure) is located outside the metal grid. In this case, the Fermi levels of the first semiconductor structure, the metal grid, and the second semiconductor structure decrease sequentially. Due to the difference in Fermi levels, the work functions of the first semiconductor structure, the metal grid, and the second semiconductor structure will differ (the work function is the minimum energy required for a material to raise an electron from the Fermi level to the vacuum level). Because of this difference in work functions, when the first semiconductor structure, the metal grid, and the second semiconductor structure come into contact, holes in the first semiconductor structure with a relatively higher work function will move to the metal grid with a relatively lower work function, and electrons in the second semiconductor structure with a relatively lower work function will move to the metal grid with a relatively higher work function. This creates a depletion layer and a potential barrier between the first semiconductor structure, the metal grid, and the second semiconductor structure, hindering carrier movement. The propagation of charge carriers between the first semiconductor structure, the metal grid, and the second semiconductor structure is isolated by the effect of potential barriers, thereby avoiding current crosstalk.

[0170] Furthermore, this application does not use an oxide layer as the isolation structure, thus avoiding the increase in dark current caused by film defects. Simultaneously, the dark current at the second semiconductor structure in the isolation structure is attracted by the charge carriers (electrons or holes) of the first semiconductor structure, which helps to further suppress dark current. It also allows skipping the grounding step used in related technologies to suppress dark current, shortening the process flow.

[0171] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An isolation structure formed on a substrate, the isolation structure dividing the substrate into multiple regions; The isolation structure includes a metal grid, a first semiconductor structure formed inside the metal grid, and a second semiconductor structure formed outside the metal grid; the Fermi levels of the first semiconductor structure, the metal grid, and the second semiconductor structure increase or decrease sequentially.

2. The semiconductor structure according to claim 1, characterized in that, The first semiconductor structure and the second semiconductor structure are formed by doping a substrate, wherein one of the first semiconductor structure and the second semiconductor structure is N-type doped and the other is P-type doped.

3. The semiconductor structure according to claim 2, characterized in that, The P-type doping concentration of the P-type doped substrate is greater than or equal to The N-type doping concentration of the N-type doped substrate is greater than or equal to .

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, A SiN layer is also disposed between the top of the first semiconductor structure and the metal grid.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The metal grid is made of any one or more of the following materials: Al, Cu, W, Ag, and TiN.

6. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; An isolation structure is formed on the substrate, the isolation structure dividing the substrate into multiple regions; The isolation structure includes a metal grid, a first semiconductor structure formed inside the metal grid, and a second semiconductor structure formed outside the metal grid; the Fermi levels of the first semiconductor structure, the metal grid, and the second semiconductor structure increase or decrease sequentially.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The steps of forming an isolation structure on a substrate include: A sacrificial layer is formed on the substrate surface; A barrier layer and a barrier layer sacrificial portion are formed on the surface of the sacrificial layer. The barrier layer includes a patterned region corresponding to the fabrication region of the isolation structure. The barrier layer sacrificial portion is located in the patterned region, and the thickness of the barrier layer sacrificial portion is lower than that of the barrier layer. The barrier layer, the barrier layer sacrificial portion, the sacrificial layer, and the substrate are etched to form a trench in the substrate. A portion of the substrate corresponding to the barrier layer sacrificial portion is retained in the trench as a first semiconductor structure fabrication area. The sacrificial layer is retained on top of the first semiconductor structure fabrication area. Ion implantation is performed on the fabrication region of the first semiconductor structure to form the first semiconductor structure; A metal grid is formed within the trench, and the metal grid covers the first semiconductor structure and the sacrificial layer; Ion implantation is performed on the substrate surrounding the metal grid to form a second semiconductor structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The steps of forming a patterned barrier layer on the surface of the sacrificial layer include: A photoresist layer is formed on the surface of the sacrificial layer; The photoresist layer is exposed using grayscale photolithography. The exposed photoresist layer is developed to pattern the photoresist layer, forming a barrier layer and a barrier layer sacrificial part.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The steps for exposing a photoresist layer using grayscale photolithography include: If the photoresist layer is positive resist, when the photoresist layer is exposed, the exposure dose and / or transmittance of the photoresist layer corresponding to the preparation area of ​​the barrier layer sacrificial part in the patterned area is lower than the exposure dose and / or transmittance of the photoresist layer in other areas of the patterned area. If the photoresist layer is a negative resist, then when the photoresist layer is exposed, the exposure dose and / or transmittance of the photoresist layer corresponding to the preparation area of ​​the barrier layer sacrificial part in the patterned area is higher than the exposure dose and / or transmittance of the photoresist layer in other areas of the patterned area.

10. A back-illuminated image sensor, characterized in that, It includes the semiconductor structure as described in any one of claims 1 to 5, or the semiconductor structure prepared by the method described in claims 6 to 9.

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