Method of manufacturing a semiconductor structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-05-20
- Publication Date
- 2026-06-23
Smart Images
Figure CN115394634B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory widely used in computer systems. Its main working principle is to use the amount of charge stored in a capacitor to represent a binary bit.
[0003] DRAM typically comprises a substrate, word lines, and active regions. Currently, self-aligned double patterning (SADP) is commonly used to form the active regions. However, during the formation of the active regions, tilting or collapse can easily occur, leading to structural failure and reducing the yield of the semiconductor structure. Summary of the Invention
[0004] The technical problem solved by the embodiments of the present invention is to provide a method for manufacturing semiconductor structures to improve the yield of semiconductor structures.
[0005] To address the aforementioned problems, embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a plurality of mutually discrete first mask layers and a plurality of mutually discrete second mask layers on the substrate, wherein the first mask layers extend along a first direction, the second mask layers extend along a second direction, and the first direction is different from the second direction, the first mask layers and the second mask layers are intersecting, and each second mask layer spans a plurality of first mask layers; truncating the first mask layers to form a plurality of mutually discrete first sub-mask layers; the second mask layers spanning a plurality of first mask layers... The substrate is formed by etching a first etching process using the first sub-mask layer as a mask to form mutually discrete active regions; an isolation structure is formed between adjacent active regions, and the first sub-mask layers not covered by the second mask layer are removed; after removing a portion of the first sub-mask layer, a third mask layer is formed between adjacent second mask layers, and a first trench is formed between adjacent third mask layers and the second mask layer; the active regions and the isolation structure are etched along the first trench to form word line trenches.
[0006] Additionally, the steps of forming the third mask layer and the first trench include: forming a fourth mask layer on the opposite sidewalls of adjacent second mask layers; forming the third mask layer between adjacent second mask layers, wherein the third mask layer is also in contact with the fourth mask layer; and removing the fourth mask layer to form the first trench.
[0007] Additionally, the fourth mask layer is located on the substrate between adjacent second mask layers, and the fourth mask layer forms a groove; forming the third mask layer includes: forming the third mask layer that fills the groove; removing the fourth mask layer includes: removing the fourth mask layer located on the sidewall of the second mask layer, retaining the fourth mask layer located on the substrate, and the remaining fourth mask layer and the third mask layer form a stacked structure; forming the word line trench includes: etching the active region and the substrate using the second mask layer and the stacked structure as masks.
[0008] Additionally, the steps of forming the first mask layer and the second mask layer include: forming an initial first mask layer on the substrate; forming a mutually discrete seventh mask layer on the initial first mask layer, the seventh mask layer extending along a first direction; forming a first sidewall layer on the sidewall of the seventh mask layer; removing the seventh mask layer and forming a second sidewall layer on the sidewall of the first sidewall layer; removing the first sidewall layer and etching the initial first mask layer using the second sidewall layer as a mask to form the first mask layer; forming an initial second mask layer located between adjacent first mask layers; and patterning the initial second mask layer using a second etching process to form the second mask layer.
[0009] In addition, the etching gas in the second etching process includes O2 and Ar.
[0010] In addition, the initial second mask layer is also located on the first mask layer; in a direction perpendicular to the top surface of the substrate, the top surface of the second mask layer is higher than the top surface of the first mask layer.
[0011] Additionally, the steps of forming the first mask layer and the second mask layer include: forming an initial second mask layer on the substrate; patterning the initial second mask layer to form mutually discrete second mask layers; forming an initial first mask layer located between adjacent second mask layers; forming a mutually discrete seventh mask layer on the initial first mask layer, the seventh mask layer extending along the first direction; forming a first sidewall layer on the sidewall of the seventh mask layer; removing the seventh mask layer and forming a second sidewall layer on the sidewall of the first sidewall layer; removing the first sidewall layer and etching the initial first mask layer using the second sidewall layer as a mask to form the first mask layer.
[0012] In addition, the initial first mask layer is also located on the second mask layer; in a direction perpendicular to the top surface of the substrate, the top surface of the first mask layer is higher than the top surface of the second mask layer.
[0013] In addition, the step of forming the first sub-mask layer includes: forming a fifth mask layer on the first mask layer; patterning the fifth mask layer to form mutually independent cut-off holes, the cut-off holes exposing the first mask layer; and etching the first mask layer along the cut-off holes to form the first sub-mask layer.
[0014] Additionally, the cut-off aperture includes a first cut-off aperture and a second cut-off aperture; for each of the first mask layers, the first cut-off aperture and the second cut-off aperture are alternately arranged in orthographic projections on the top surface of the first mask layer; the step of forming the cut-off aperture includes: performing a first patterning process on the fifth mask layer to form the first cut-off aperture; after forming the first cut-off aperture, forming a sixth mask layer on the fifth mask layer, and performing a patterning process on the sixth mask layer; using the patterned sixth mask layer as a mask, performing a second patterning process on the fifth mask layer to form the second cut-off aperture.
[0015] In addition, the step of forming the first sub-mask layer includes: forming a fifth mask layer on the first mask layer; performing patterning processing on the fifth mask layer to form a second trench exposing the first mask layer and the second mask layer; and using the fifth mask layer as a mask, etching the first mask layer to form the first sub-mask layer.
[0016] In addition, the first etching process includes plasma etching; the plasma etching removes a portion of the substrate by means of an ion beam; the ion beam is tilted at 0° to 30° toward the bottom of the substrate along the first direction to remove a portion of the substrate located directly below the second mask layer.
[0017] In addition, the etching selectivity ratio of the first etching process for the substrate and the second mask layer is greater than 10.
[0018] In addition, the first mask layer is a hard mask layer, and the second mask layer is a hard mask layer.
[0019] In addition, after forming the character line groove, the process also includes forming character lines that fill the character line groove.
[0020] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:
[0021] In this embodiment of the invention, since the second mask layer spans multiple first mask layers, it can support and fix the first mask layers, thereby preventing displacement or tilting of the first sub-mask layers. Furthermore, since the first sub-mask layers are in contact with the active region, the second mask layer can also fix and support the active region through the first sub-mask layers, thus preventing displacement or collapse of the active region. In addition, after removing a portion of the first sub-mask layer, a third mask layer is formed between adjacent second mask layers, and a first trench exists between adjacent third mask layers and the second mask layers. The active region and isolation structure are etched along the first trench to form word line trenches; that is, the second mask layer also serves as the mask layer for forming the word line trenches, thus simplifying the manufacturing process.
[0022] Furthermore, the steps of forming the third mask layer and the first trench include: forming a fourth mask layer on the opposite sidewalls of adjacent second mask layers; forming a third mask layer between adjacent second mask layers; and removing the fourth mask layer to form the first trench. That is, the third mask layer is formed through a self-aligned double patterning process, which reduces the number of photolithography steps and lowers the process complexity. Attached Figure Description
[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0024] Figures 1-2 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure manufacturing method.
[0025] Figures 3-26 This is a schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to an embodiment of the present invention.
[0026] Figures 27-32 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of a semiconductor structure provided in another embodiment of the present invention. Detailed Implementation
[0027] As can be seen from the background technology, the yield of semiconductor structures needs to be further improved. Figures 1-2 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure manufacturing method, for reference. Figure 1 A substrate 30 is provided, and a strip-shaped first mask layer 31 is formed on the substrate 30. (Reference) Figure 2 For the first mask layer 31 (reference) Figure 1The process involves truncation to form multiple independent first sub-mask layers 311, which serve as masks for the subsequent formation of the active region. Because the first sub-mask layers 311 are several independent structures without any other structure to fix or support them, they are prone to displacement and tilting during etching. (Continue to refer to...) Figure 2 The substrate 30 is etched using the first sub-mask layer 311 as a mask to form the active region. Since there is no supporting structure to fix the first sub-mask layer 311 and the active region, and the etching depth is relatively large, the first sub-mask layer 311 and the active region may collapse and tilt, thereby reducing the yield of the semiconductor structure.
[0028] To address the aforementioned problems, embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: forming a plurality of mutually discrete first mask layers and a plurality of mutually discrete second mask layers on a substrate, wherein the first mask layers and second mask layers are intersecting and each second mask layer spans the plurality of first mask layers; truncating the first mask layers to form a plurality of mutually discrete first sub-mask layers; since the second mask layers span the plurality of first mask layers, the second mask layers can support and fix the first mask layers, thereby preventing the first sub-mask layers from shifting or tilting; using the first sub-mask layers as masks, etching the substrate to form mutually discrete active regions; since the second mask layers can fix and support the first sub-mask layers, the first sub-mask layers will not collapse or shift during the etching of the active regions; furthermore, since the first sub-mask layers are in contact with the active regions, the second mask layers can also fix and support the active regions through the first sub-mask layers, thereby preventing the active regions from shifting or collapsing. After removing part of the first sub-mask layer, a third mask layer is formed between adjacent second mask layers, and a first trench is formed between adjacent third mask layers and second mask layers; the active region and isolation structure are etched along the first trench to form word line trenches; that is, the second mask layer also serves as a mask layer for forming word line trenches, thus simplifying the production process.
[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0030] One embodiment of the present invention provides a semiconductor structure, Figures 3-26 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure manufacturing process. The following will provide a detailed explanation in conjunction with the accompanying drawings.
[0031] refer to Figures 3-12 A substrate 10 is provided, on which a plurality of mutually discrete first mask layers 11 and a plurality of mutually discrete second mask layers 12 are formed. The first mask layers 11 extend along a first direction X, and the second mask layers 12 extend along a second direction Y. The first direction X and the second direction Y are different. The first mask layers 11 and the second mask layers 12 are intersecting and each second mask layer 12 spans the plurality of first mask layers 11.
[0032] The substrate 10 can be made of semiconductor material. Specifically, the substrate 10 can be made of elemental semiconductor material or crystalline inorganic compound semiconductor material. Elemental semiconductor material can be silicon or germanium; crystalline inorganic compound semiconductor material can be silicon germanide, gallium arsenide, or indium gallium dihydrogen phosphate, etc.
[0033] The angle between the first direction X and the second direction Y is 60° to 70°, and the first direction X is the extension direction of the subsequently formed active region, while the second direction Y is the extension direction of the subsequently formed word line.
[0034] Since the second mask layer 12 spans multiple first mask layers 11, meaning that the second mask layer 12 is in contact with at least the sidewalls of the first mask layer 11, each second mask layer 12 can support multiple first mask layers 11 through the adhesive force of the contact surfaces between them. During the subsequent etching of the first mask layer 11 to form the first sub-mask layer, the second mask layer 12 can fix the first sub-mask layer and prevent it from tilting or shifting. During the subsequent etching of the substrate 10 to form the active region, the second mask layer 12 can also fix and support the active region and prevent it from tilting or collapsing.
[0035] The steps for forming the first mask layer 11 and the second mask layer 12 will be described in detail below.
[0036] It is worth noting that in this embodiment, the first mask layer 11 is formed before the second mask layer 12. In other embodiments, the second mask layer may also be formed before the first mask layer.
[0037] refer to Figures 3-8 A first mask layer 11 is formed on the substrate 10.
[0038] Specifically, refer to Figure 3 , Figure 3 (a) is Figure 3 (b) Cross-sectional view in the Y direction. Figure 3(b) is a top view of the semiconductor structure, showing an initial first mask layer 111 formed on the substrate 10. Further, the initial first mask layer 111 covers the entire upper surface of the substrate 10. The initial first mask layer 111 is a hard mask. In this embodiment, the material of the initial first mask layer 111 is polycrystalline silicon. In other embodiments, the material of the initial first mask layer may also be silicon oxide, silicon nitride, or silicon carbide. In this embodiment, the initial first mask layer 111 can be formed by chemical vapor deposition.
[0039] A seventh mask layer 117, which is mutually discrete, is formed on the initial first mask layer 111 and extends along the first direction X. In this embodiment, the seventh mask layer 117 is a single-layer structure; in other embodiments, the seventh mask layer may also be a double-layer structure to improve the accuracy of pattern transfer. The seventh mask layer 117 is a hard mask, and its material may be polysilicon, silicon oxide, silicon nitride, or silicon carbide. In this embodiment, the step of forming the seventh mask layer 117 includes: forming an initial seventh mask layer covering the upper surface of the initial first mask layer 111; and patterning the initial seventh mask layer to form the seventh mask layer 117 extending along the first direction X. In this embodiment, the initial seventh mask layer can be formed by chemical vapor deposition, and the initial seventh mask layer can be patterned by dry etching.
[0040] It is worth noting that in other embodiments, an initial eighth mask layer covering the initial first mask layer can be formed before forming the seventh mask layer. The initial eighth mask layer can improve the accuracy of pattern transfer. The initial eighth mask layer can be a double-layer structure or a single-layer structure, and the material of the initial eighth mask layer can be silicon nitride, silicon carbide, or silicon oxynitride.
[0041] refer to Figure 4 , Figure 4 (a) is Figure 4 (b) Cross-sectional view in the Y direction. Figure 4 (b) is a top view of the semiconductor structure, showing a first sidewall layer 112 formed on the sidewall of the seventh mask layer 117. In this embodiment, the width of the seventh mask layer 117 is greater than the width of the first sidewall layer 112 in the direction perpendicular to the first direction X. The first sidewall layer 112 is a hard mask, and its material is different from that of the seventh mask layer 117; its material can be polysilicon, silicon oxide, silicon nitride, or silicon carbide. The first sidewall layer 112 can be formed by atomic layer deposition or chemical vapor deposition.
[0042] refer to Figure 5 , Figure 5 (a) is Figure 5 (b) Cross-sectional view in the Y direction. Figure 5 (b) is a top view of the semiconductor structure, with the seventh mask layer 117 removed (see reference). Figure 4 The first sidewall layer 112 is retained. In this embodiment, the seventh mask layer 117 can be removed by wet etching. In other embodiments, the seventh mask layer can also be removed by dry etching.
[0043] refer to Figure 6 , Figure 6 (a) is Figure 6 (b) Cross-sectional view in the Y direction. Figure 6 (b) is a top view of the semiconductor structure, in which a second sidewall layer 113 is formed on the sidewall of the first sidewall layer 112. The second sidewall layer 113 is a hard mask, and its material is different from that of the first sidewall layer 112. Its material can be polysilicon, silicon oxide, silicon nitride, or silicon carbide. The second sidewall layer 113 can be formed by atomic layer deposition or chemical vapor deposition.
[0044] It is worth noting that in other embodiments, since an initial eighth mask layer can be formed on the initial first mask layer, correspondingly, after removing the seventh mask layer, the initial eighth mask layer can be etched using the first sidewall layer as a mask to form multiple mutually independent eighth mask layers, thereby transferring the pattern of the first sidewall layer to the eighth mask layer; furthermore, a second sidewall layer can be formed on the sidewall of the eighth mask layer.
[0045] refer to Figure 7 , Figure 7 (a) is Figure 7 (b) Cross-sectional view in the Y direction. Figure 7 (b) is a top view of the semiconductor structure, with the first sidewall layer 112 removed (see reference). Figure 6 The first sidewall layer 112 is removed by wet etching, while the second sidewall layer 113 is retained. In this embodiment, the first sidewall layer 112 can be removed by wet etching. In other embodiments, the first sidewall layer can also be removed by dry etching.
[0046] It is worth noting that in other embodiments, since multiple mutually independent eighth mask layers can be formed, and a second sidewall layer is formed on the sidewall of the eighth mask layer; accordingly, after the second sidewall layer is formed, the eighth mask layer can be removed.
[0047] refer to Figure 8 , Figure 8 (a) is Figure 8 (b) Cross-sectional view in the Y direction. Figure 8 (b) is a top view of the semiconductor structure, with the second sidewall layer 113 (reference) Figure 7 ) is the initial first mask layer 111 for mask etching (reference) Figure 7A first mask layer 11 is formed by a process called induction. The first mask layer 11 is a strip-shaped mask extending along a first direction X, and the first mask layer 11 also exposes a portion of the upper surface of the substrate 10. The first mask layer 11 is a hard mask layer. In this embodiment, the material of the first mask layer 11 is polycrystalline silicon; in other embodiments, the material of the first mask layer 11 may also be silicon oxide, silicon nitride, or silicon carbide. Because the hard mask layer has greater hardness and strength, it can improve the support and fixation effect of the subsequently formed second mask layer on the first mask layer.
[0048] refer to Figures 9-12 The following will describe in detail the steps for forming the second mask layer 12.
[0049] refer to Figure 9 , Figure 9 (a) is Figure 9 (b) Cross-sectional view in the Y direction. Figure 9 (b) is a top view of the semiconductor structure, forming an initial second mask layer 121 located between adjacent first mask layers 11.
[0050] In this embodiment, the initial second mask layer 121 is also located above the first mask layer 11, that is, the top surface of the initial second mask layer 121 is higher than the top surface of the first mask layer 11. It is understood that when the initial second mask layer 121 is still located above the first mask layer 11, the initial second mask layer 121 is still in contact with the top surface of the first mask layer 11. This increases the contact area between the two, thereby increasing the adhesion of the first mask layer 11 to the contact surface, and thus improving the supporting effect of the subsequently formed second mask layer on the first mask layer 11. In other embodiments, the initial second mask layer may only be located between adjacent first mask layers, that is, the top surface of the initial second mask layer is flush with the top surface of the first mask layer, or the top surface of the initial second mask layer is lower than the top surface of the first mask layer.
[0051] The initial second mask layer 121 is made of a hard mask layer, and the material of the initial second mask layer 121 is different from that of the first mask layer 11. In this embodiment, the material of the initial second mask layer 121 can be silicon carbide. In other embodiments, the material of the initial second mask layer can also be silicon nitride, silicon oxide, or silicon carbonitride, etc.
[0052] refer to Figures 10-12 , Figure 11 for Figure 10 Cross-sectional view along the A-A1 direction. Figure 12 for Figure 10 A cross-sectional view along the B-B1 direction, showing the initial second mask layer 121 (reference) etched using the second etching process. Figure 9 The image is then processed to form a second mask layer 12.
[0053] In this embodiment, the second etching process has a large etching selectivity between the initial second mask layer 121 and the first mask layer 11. Therefore, during the etching of the initial second mask layer 121, the second etching process causes less damage to the first mask layer 11, thus maintaining the original morphology of the first mask layer 11 and ensuring the accuracy of the subsequently formed active region pattern. In this embodiment, the material of the initial second mask layer 121 is silicon carbide, and correspondingly, the etching gases in the second etching process include O2 and Ar.
[0054] As mentioned above, the initial second mask layer 121 (reference) Figure 9 It is also located on the first mask layer 11. Correspondingly, in the direction perpendicular to the top surface of the substrate 10, the top surface of the second mask layer 12 is higher than the top surface of the first mask layer 11. It is understandable that when the top surface of the second mask layer 12 is higher than the top surface of the first mask layer 11, several separate second mask layers 12 located between adjacent first mask layers 11 are connected into a whole through the second mask layer 12 that is higher than the top surface of the first mask layer 11. The second mask layer 12 is in contact not only with the sidewall of the first mask layer 11, but also with the top surface of the first mask layer 11. That is, the second mask layer 12 can play a traction and fixing role on the first mask layer 11 through the sidewall and top surface of the first mask layer 11, thereby preventing the subsequent first sub-mask layer from shifting or tilting during the formation process. Since the first sub-mask layer is also in contact with the substrate 10, the second mask layer 12 can also play a fixing and supporting role on the active region through the first sub-mask layer during the subsequent etching of the substrate 10 to form the active region, thereby preventing the active region from collapsing or tilting.
[0055] In other embodiments, the second mask layer may be located only between adjacent first mask layers, that is, the second mask layer is a block structure that is independent of each other and only contacts the sidewall of the first mask layer. In other words, the second mask layer can support and fix the first mask layer through the sidewall of the first mask layer.
[0056] In addition, the second mask layer 12 is a hard mask, which can further improve the support strength of the second mask layer 12 to the first mask layer 11, thereby avoiding the problem of tilting or collapse of the first mask layer 11 and the subsequent active area.
[0057] refer to Figures 13-18 The first mask layer 11 is truncated to form a plurality of mutually independent first sub-mask layers 118; the second mask layer 12 spans the plurality of first sub-mask layers 118, and a portion of the sidewall of each first sub-mask layer 118 is covered by the second mask layer 12.
[0058] In this embodiment, the second mask layer 12 is in contact with the middle region or two edge regions of the first sub-mask layer 118. Since the second mask layer 12 intersects with multiple first sub-mask layers 118, during the formation of the first sub-mask layers 118, the second mask layer 12 can fix and support the multiple first sub-mask layers 118 to prevent the first sub-mask layers 118 from tilting or shifting.
[0059] The first sub-mask layer 118, which is independent of each other, serves as the mask layer for the subsequent formation of the active region. Since the first sub-mask layer 118 is fixed by the second mask layer 12, the accuracy of the subsequently formed active region can be improved; and since the first sub-mask layer 118 is also in contact with the active region, the second mask layer 12 can also support and fix the active region through the first sub-mask layer 118, thereby preventing the active region from tilting or collapsing.
[0060] The following will describe in detail the steps for forming the first sub-mask layer 118.
[0061] Continue to refer to Figures 13-18 A fifth mask layer 191 is formed on the first mask layer 11. The fifth mask layer 191 is patterned to form mutually independent cut-off holes, which expose the first mask layer 11. The first mask layer 11 is etched along the cut-off holes to form a first sub-mask layer 118.
[0062] Specifically, the cut-off holes include a first cut-off hole 193 and a second cut-off hole 194; for each first mask layer 11, the first cut-off hole 193 and the second cut-off hole 194 are alternately arranged in the orthographic projection of the top surface of the first mask layer 11.
[0063] Furthermore, the steps for forming the cut-off hole include: (Refer to...) Figure 13 The fifth mask layer 191 is first patterned to form a first cut-off hole 193. Specifically, a first photoresist layer is formed on the fifth mask layer 191, and the first photoresist layer is exposed and developed to form a patterned first photoresist layer. The fifth mask layer 191 is etched using the patterned first photoresist layer as a mask to form the first cut-off hole 193. After the first cut-off hole 193 is formed, the patterned first photoresist layer is removed.
[0064] refer to Figure 14After forming the first cut-off hole 193, a sixth mask layer 192 is formed on the fifth mask layer 191. The sixth mask layer 192 is patterned to form the initial second cut-off hole. Specifically, a second photoresist layer is formed on the sixth mask layer 192. The second photoresist layer is exposed and developed to form a patterned second photoresist layer. The patterned second photoresist layer is used as a mask to etch the sixth mask layer 192 to form the patterned sixth mask layer 192. After forming the patterned sixth mask layer 192, the second photoresist layer is removed.
[0065] refer to Figure 15 Using the patterned sixth mask layer 192 as a mask, the fifth mask layer 191 is subjected to a second patterning process to form a second cut-off hole 194. After forming the second cut-off hole 194, the sixth mask layer 192 is removed (see reference). Figure 14 Thus, alternating first cut-off holes 193 and second cut-off holes 194 are formed on the fifth mask layer 191.
[0066] refer to Figures 16-18 , Figure 17 for Figure 16 Cross-sectional view along the A-A1 direction. Figure 18 for Figure 16 In the cross-sectional view along the B-B1 direction, the first mask layer 11 is etched along the cut-off hole to form the first sub-mask layer 118.
[0067] It is understandable that during the formation of the first sub-mask layer 118, the second mask layer 12 can play a role in pulling and fixing the first sub-mask layer 118, thus preventing the first sub-mask layer 118 from shifting or displacing, which is beneficial to improving the accuracy of the pattern of the active region formed subsequently.
[0068] It is worth noting that in this embodiment, the first cut-off hole 193 and the second cut-off hole 194 are formed in the fifth mask layer 191 through two photolithography processes, and the first mask layer 11 is etched along the cut-off holes to form the first sub-mask layer 118. In other embodiments, the step of forming the first sub-mask layer may further include: forming a fifth mask layer on the first mask layer, and performing patterning processing on the fifth mask layer to form a second trench exposing the first mask layer and the second mask layer; that is, the patterned fifth mask layer can be formed by only one photolithography process. The patterned fifth mask layer is a strip structure that spans multiple first mask layers, and the second trench exposes the cut-off areas of multiple first mask layers; using the fifth mask layer as a mask, the first mask layer is etched to form the first sub-mask layer.
[0069] In this embodiment, the first mask layer 11 is cut off by dry etching. In this embodiment, the material of the first mask layer 11 is polycrystalline silicon, and correspondingly, the etching gas can be SF6, CF4 or Cl2.
[0070] refer to Figure 16 , Figure 19 and Figure 20 , Figure 19 for Figure 16 Cross-sectional view along the A-A1 direction. Figure 20 for Figure 16 In the cross-sectional view along the B-B1 direction, it is worth noting that the top view of the semiconductor structure in this step is the same as the top view of the semiconductor structure in the previous step. Using the first sub-mask layer 118 as a mask, the substrate 10 is etched using the first etching process to form mutually discrete active regions 119.
[0071] In this embodiment, the first etching process is plasma etching, which removes a portion of the substrate 10 using an ion beam. Specifically, the first etching process can be divided into two stages. In the first stage, the direction of the ion beam is perpendicular to the top surface of the substrate 10, that is, the ion beam is tilted 90° towards the bottom of the substrate along the first direction X to remove the portion of the substrate 10 not covered by the first sub-mask layer 118 and the second mask layer 12. In the second stage, the ion beam is tilted 0° to 30° towards the bottom of the substrate along the first direction X to remove a portion of the substrate 10 located directly below the second mask layer 12, while retaining the substrate 10 located directly below the first sub-mask layer 118, thereby forming several independent active regions 119. It is understood that in the second stage, the ion beam may etch the sidewalls of the active regions 119 along the first direction X. To ensure that the actual pattern of the active regions 119 is consistent with the target pattern, the thickness of the first sub-mask layer 118 can be appropriately increased, that is, a loss margin can be reserved for the active regions 119 in advance. The plasma etching in the second stage can remove the loss margin reserved in the aforementioned steps. In other embodiments, the order of the first stage and the second stage may be interchanged, or only the second stage may be used.
[0072] It is understandable that since the second mask layer 12 can pull and fix the active region 119 through the first sub-mask layer 118, the active region 119 can be prevented from tilting or collapsing during the formation of the active region 119, thereby improving the yield of the semiconductor structure.
[0073] The first etching process has an etching selectivity ratio of more than 10 for the substrate 10 and the second mask layer 12, such as 12, 20, or 50. When the etching selectivity ratio is greater than 10, the first etching process can easily remove part of the substrate 10 to form mutually discrete active regions 119, and can also avoid causing excessive damage to the second mask layer 12, thereby improving the support effect of the second mask layer 12 on the active region 119.
[0074] The etching gas in the first etching process can be SF6, CF4, Cl2, CHF3, O2, Ar, or a mixture of the above gases.
[0075] refer to Figures 21-23 , Figure 22 for Figure 21 Cross-sectional view along the A-A1 direction. Figure 23 for Figure 21 In the cross-sectional view along the B-B1 direction, an isolation structure 13 is formed between adjacent active regions 119, and the first sub-mask layer 118 not covered by the second mask layer 12 is removed.
[0076] In this embodiment, the isolation structure 13 can be formed by chemical vapor deposition. In other embodiments, the isolation structure can also be formed by physical vapor deposition. The material of the isolation structure 13 can be silicon oxide, silicon nitride, or silicon oxynitride.
[0077] In this embodiment, the first sub-mask layer 118 not covered by the second mask layer 12 is removed; that is, the first sub-mask layer 118 located within the second mask layer 12 is retained. In this embodiment, dry etching can be used to remove part of the first sub-mask layer 118.
[0078] refer to Figures 24-26 After removing part of the first sub-mask layer 118, a third mask layer 15 is formed between adjacent second mask layers 12, and a first trench 16 is formed between adjacent third mask layers 15 and second mask layers 12. The first trench 16 is directly opposite to the word line trenches formed subsequently, that is, the second mask layer 12 also serves as a mask for forming word line trenches, which simplifies the production process.
[0079] It is worth noting that in this embodiment, the third mask layer 15 is formed through a self-aligned dual patterning process, which reduces the complexity of the process. In other embodiments, the position of the third mask layer 15 can also be defined in a single photolithography step.
[0080] The following will describe in detail the steps for forming the third mask layer 15 and the first trench 16.
[0081] refer to Figure 24 , Figure 24 (b) is a top view of the semiconductor structure. Figure 24 (a) is Figure 24 (b) A partial cross-sectional view along the C-C1 direction shows a fourth mask layer 14 formed on the opposite sidewalls of adjacent second mask layers 12. In this embodiment, the fourth mask layer 14 is also located on the substrate 10 between adjacent second mask layers 12, and the fourth mask layer 14 forms a groove 142. In other embodiments, the fourth mask layer may also be located only on the sidewalls of the second mask layers; specifically, a conformal fourth mask layer is formed, the fourth mask layer is located on the surface of the second mask layer and on the substrate between adjacent second mask layers, the fourth mask layer located on the top surface of the second mask layer and on the substrate between adjacent second mask layers is removed, and the fourth mask layer located on the sidewalls of the second mask layer is retained.
[0082] In this embodiment, the fourth mask layer 14 can be formed by chemical vapor deposition or atomic layer deposition.
[0083] The material of the fourth mask layer 14 is different from that of the second mask layer 12. The material of the fourth mask layer 14 can be silicon oxide, silicon nitride, or silicon oxynitride.
[0084] refer to Figure 25 , Figure 25 (b) is a top view of the semiconductor structure. Figure 25 (a) is Figure 25 (b) A partial cross-sectional view along the C-C1 direction, showing a third mask layer 15 formed between adjacent second mask layers 12, the third mask layer 15 also contacting the fourth mask layer 14, i.e. forming a filling groove 142 (see reference). Figure 24 The third mask layer 15. It is understood that, in other embodiments, since the fourth mask layer is not located on the substrate but only on the sidewall of the second mask layer, the third mask layer may also be in contact only with the sidewall of the fourth mask layer.
[0085] In this embodiment, the third mask layer 15 can be formed by chemical vapor deposition or atomic layer deposition.
[0086] In this embodiment, the material of the third mask layer 15 is different from the material of the fourth mask layer 14. The material of the third mask layer 15 can also be the same as the material of the second mask layer 12. The material of the third mask layer 15 can be silicon oxide, silicon nitride, or silicon oxynitride.
[0087] refer to Figure 26 , Figure 26 (b) is a top view of the semiconductor structure. Figure 26 (a) is Figure 26(b) A partial cross-sectional view along the C-C1 direction, showing the removal of the fourth mask layer 14 to form a first trench 16 located between adjacent second mask layers 12 and third mask layers 15. Specifically, the fourth mask layer 14 located on the sidewall of the second mask layer 12 is removed, as is the fourth mask layer 14 located on the top surface of the second mask layer 12, leaving the fourth mask layer 14 on the substrate 10. The remaining fourth mask layer 14 and the third mask layer 15 form a stacked structure 141. It is understood that in other embodiments, since the fourth mask layer may only be located on the sidewall of the second mask layer, the entire fourth mask layer may be removed.
[0088] In this embodiment, wet etching is used to remove the fourth mask layer 14. In other embodiments, dry etching can also be used to remove the fourth mask layer.
[0089] Continue to refer to Figure 26 The active region 119 and the isolation structure 13 are etched along the first trench 16 to form the word line trench 17. That is, in this embodiment, the active region 119 and the isolation structure 13 are etched using the second mask layer 12 and the stacked structure 141 as masks to form the word line trench 17. It is understood that in other embodiments, since the fourth mask layer can be completely removed, the active region and the isolation structure are etched using the second mask layer and the third mask layer as masks to form the word line trench.
[0090] After forming the character line groove 17, it also includes forming character lines that fill the character line groove 17.
[0091] In summary, in this embodiment, the first mask layer 11 and the second mask layer 12 are intersecting. Therefore, during the truncation process of the first mask layer 11, the second mask layer 12 can support and fix the first mask layer 11, thereby preventing the first sub-mask layer 118 from shifting or tilting. Furthermore, since the first sub-mask layer 118 is in contact with the active region 119, the second mask layer 12 can also fix and support the active region 119 through the first sub-mask layer 118, thereby preventing the active region from shifting or collapsing, and thus improving the yield of the semiconductor structure. The second mask layer 12 also serves as a mask layer for forming the word line trench 17, thus simplifying the manufacturing process.
[0092] Another embodiment of the present invention provides a method for manufacturing a semiconductor structure. This embodiment is largely the same as the previous embodiment, except that in this embodiment, the second mask layer is formed before the first mask layer. For the parts of this embodiment that are the same as or similar to the previous embodiment, please refer to the detailed description of the previous embodiment, which will not be repeated here. Figures 27-32 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure manufacturing method provided in this embodiment.
[0093] The following will provide a detailed explanation in conjunction with the accompanying drawings.
[0094] refer to Figures 27-29 , Figure 28 for Figure 27 Cross-sectional view along the A-A1 direction. Figure 29 for Figure 27 In a cross-sectional view along the B-B1 direction, a substrate 20 is provided, on which a plurality of mutually discrete first mask layers 21 and a plurality of mutually discrete second mask layers 22 are formed. The first mask layers 21 extend along a first direction X, and the second mask layers 22 extend along a second direction Y, wherein the first direction X and the second direction Y are different. The first mask layers 21 and the second mask layers 22 are intersecting each other, and each second mask layer 22 spans the plurality of first mask layers 21.
[0095] Specifically, the step of forming the second mask layer 22 includes: forming an initial second mask layer on the substrate 20, wherein the initial second mask layer is a full-coverage film layer covering the substrate; and performing patterning processing on the initial second mask layer to form mutually discrete second mask layers. For details regarding the steps of forming the second mask layer, please refer to the detailed description in the foregoing embodiments.
[0096] The step of forming the first mask layer 21 includes: forming an initial first mask layer located between adjacent second mask layers 22; forming a mutually discrete seventh mask layer on the initial first mask layer, the seventh mask layer extending along a first direction; forming a first sidewall layer on the sidewall of the seventh mask layer; removing the seventh mask layer and forming a second sidewall layer on the sidewall of the first sidewall layer; removing the first sidewall layer and etching the initial first mask layer using the second sidewall layer as a mask to form the first mask layer. The steps for forming the first mask layer can be found in the detailed description in the foregoing embodiments.
[0097] In this embodiment, the initial first mask layer is also located on the second mask layer 22. Correspondingly, the first mask layer 21 is also located on the second mask layer 22, that is, the top surface of the first mask layer 21 is higher than the top surface of the second mask layer 22. The first mask layer 21 is in contact with the sidewalls and top surface of the second mask layer 22. Therefore, the second mask layer 22 can support multiple first mask layers 21 through its sidewalls and top surface. In the subsequent etching of the first mask layer 21 to form the first sub-mask layer, the second mask layer 21 can fix the first sub-mask layer and prevent it from tilting or shifting. In the subsequent etching of the substrate to form the active region, the second mask layer 22 can also fix and support the active region and prevent it from tilting or collapsing.
[0098] In other embodiments, the initial first mask layer may be located only between two adjacent second mask layers. Correspondingly, the first mask layer is located only on the two opposite sidewalls of the second mask layer, that is, the top surface of the first mask layer is flush with or lower than the top surface of the second mask layer. Since the sidewalls of the first mask layer and the second mask layer in contact also have adhesive force, the second mask layer can support and fix the first mask layer through the sidewalls.
[0099] refer to Figures 30-32 , Figure 31 for Figure 30 Cross-sectional view along the A-A1 direction. Figure 32 for Figure 30 A cross-sectional view along the B-B1 direction, showing the first mask layer 21 (reference). Figure 27 The first sub-mask layer 218 is truncated to form multiple independent first sub-mask layers 218; the second mask layer 22 spans the multiple first sub-mask layers 218, and a portion of the sidewall of each first sub-mask layer 218 is covered by the second mask layer 22.
[0100] As can be seen from the foregoing, the top surface and sidewalls of the first mask layer 21 are in contact with the second mask layer 22. Therefore, the second mask layer 22 can fix and support the first mask layer 21, thereby preventing the first sub-mask layer 218 from shifting or tilting.
[0101] Furthermore, using the first sub-mask layer 218 as a mask, the substrate is etched using the first etching process to form mutually independent active regions. During the formation of the active regions, the second mask layer 22 can support and fix the active regions through the first sub-mask layer 218 to prevent the active regions from collapsing or tilting.
[0102] An isolation structure is formed between adjacent active regions, and the first sub-mask layer 218 not covered by the second mask layer 22 is removed. After removing part of the first sub-mask layer 218, a third mask layer is formed between adjacent second mask layers 22, and a first trench is formed between the adjacent third mask layer and the second mask layer 22. The active regions and the isolation structure are etched along the first trench to form word line trenches. For a detailed description of the above steps, please refer to the previous embodiment, which will not be repeated here.
[0103] In summary, in this embodiment, the second mask layer 22 is formed first, followed by the first mask layer 21. The first mask layer 21 intersects with the second mask layer 22, so the second mask layer 22 can fix and support the subsequently formed first sub-mask layer 218 and the subsequently formed active region, thereby preventing the first sub-mask layer 218 and the active region from collapsing or tilting. This can improve the yield of the semiconductor structure. In addition, the second mask layer 22 is also used to form word line trenches, thus simplifying the manufacturing process.
[0104] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; Multiple mutually independent first mask layers and multiple mutually independent second mask layers are formed on the substrate. The first mask layer is a hard mask layer, the second mask layer is a hard mask layer, the first mask layer extends along a first direction, the second mask layer extends along a second direction, and the first direction and the second direction are different. The first mask layer and the second mask layer are intersecting and each second mask layer spans multiple first mask layers. The first mask layer is truncated to form multiple independent first sub-mask layers; The second mask layer spans multiple first sub-mask layers, and a portion of the sidewall of each first sub-mask layer is covered by the second mask layer; Using the first sub-mask layer as a mask, the substrate is etched using the first etching process to form mutually discrete active regions; An isolation structure is formed between adjacent active regions, and the first sub-mask layer not covered by the second mask layer is removed; After removing part of the first sub-mask layer, a third mask layer is formed between adjacent second mask layers, and a first trench is formed between adjacent third mask layers and the second mask layer; The active region and the isolation structure are etched along the first trench to form a word line trench.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps of forming the third mask layer and the first trench include: A fourth mask layer is formed on the opposite sidewall of the adjacent second mask layer; The third mask layer is formed between adjacent second mask layers, and the third mask layer is also in contact with the fourth mask layer; Remove the fourth mask layer to form the first trench.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The fourth mask layer is also located on the substrate between adjacent second mask layers, and the fourth mask layer forms a groove; The formation of the third mask layer includes: forming the third mask layer that fills the groove; The removal of the fourth mask layer includes: removing the fourth mask layer located on the sidewall of the second mask layer, retaining the fourth mask layer located on the substrate, and the remaining fourth mask layer and the third mask layer forming a stacked structure; Forming the word line trench includes: etching the active region and the substrate using the second mask layer and the stacked structure as a mask.
4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps of forming the first mask layer and the second mask layer include: An initial first mask layer is formed on the substrate; A seventh mask layer, which is independent of each other, is formed on the initial first mask layer and extends along the first direction; A first sidewall layer is formed on the sidewall of the seventh mask layer; Remove the seventh mask layer and form a second sidewall layer on the sidewall of the first sidewall layer; Remove the first sidewall layer and etch the initial first mask layer using the second sidewall layer as a mask to form the first mask layer; An initial second mask layer is formed between adjacent first mask layers; The initial second mask layer is patterned using a second etching process to form the second mask layer.
5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The etching gas in the second etching process includes O2 and Ar.
6. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The initial second mask layer is also located on the first mask layer; In a direction perpendicular to the top surface of the substrate, the top surface of the second mask layer is higher than the top surface of the first mask layer.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps of forming the first mask layer and the second mask layer include: An initial second mask layer is formed on the substrate; The initial second mask layer is patterned to form mutually discrete second mask layers; An initial first mask layer is formed between adjacent second mask layers; A seventh mask layer, which is independent of each other, is formed on the initial first mask layer and extends along the first direction; A first sidewall layer is formed on the sidewall of the seventh mask layer; Remove the seventh mask layer and form a second sidewall layer on the sidewall of the first sidewall layer; The first sidewall layer is removed, and the initial first mask layer is etched using the second sidewall layer as a mask to form the first mask layer.
8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The initial first mask layer is also located on the second mask layer; In a direction perpendicular to the top surface of the substrate, the top surface of the first mask layer is higher than the top surface of the second mask layer.
9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the first sub-mask layer includes: forming a fifth mask layer on the first mask layer; patterning the fifth mask layer to form mutually independent cut-off holes, the cut-off holes exposing the first mask layer; and etching the first mask layer along the cut-off holes to form the first sub-mask layer.
10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The cut-off holes include a first cut-off hole and a second cut-off hole; for each of the first mask layers, the first cut-off holes and the second cut-off holes are alternately arranged in the orthographic projections on the top surface of the first mask layer; The steps for forming the cut-off hole include: performing a first patterning process on the fifth mask layer to form the first cut-off hole; after forming the first cut-off hole, forming a sixth mask layer on the fifth mask layer, and performing a patterning process on the sixth mask layer; using the patterned sixth mask layer as a mask, performing a second patterning process on the fifth mask layer to form the second cut-off hole.
11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the first sub-mask layer includes: forming a fifth mask layer on the first mask layer; performing patterning processing on the fifth mask layer to form a second trench exposing the first mask layer and the second mask layer; and using the fifth mask layer as a mask, etching the first mask layer to form the first sub-mask layer.
12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first etching process includes plasma etching; the plasma etching removes a portion of the substrate by means of an ion beam; the ion beam is tilted at 0°~30° toward the bottom of the substrate along the first direction to remove a portion of the substrate located directly below the second mask layer.
13. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The etching process has an etching selectivity ratio of more than 10 for the substrate and the second mask layer.
14. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the character line groove, the method further includes: forming character lines that fill the character line groove.
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