Method of manufacturing a photosensor
By depositing silicon dioxide in the silicon waveguide groove during the optical sensor manufacturing process to provide polishing support, the problem of silicon waveguide collapse caused by CMP was solved, and the structural stability of the optical sensor was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XPHOR LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-06-19
AI Technical Summary
In the manufacturing process of optical sensors, chemical mechanical polishing (CMP) can easily lead to the collapse of silicon waveguides.
Before manufacturing the optical sensor, silicon dioxide is deposited in the grooves of the silicon waveguide to fill the grooves and provide support during polishing. The silicon dioxide is then removed and germanium waveguides, metal interconnect vias, metal wires, and pin areas are fabricated.
This reduces the risk of silicon waveguides collapsing during polishing, ensuring the structural integrity and reliability of the optical sensor.
Smart Images
Figure CN121487381B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip manufacturing technology, and more specifically, to a method for manufacturing an optical sensor. Background Technology
[0002] Silicon-based optoelectronics, with its advantages of compatibility, low cost, and high performance, has become key to the large-scale application of optical sensing technology, driving the development of optical sensing towards miniaturization, integration, and low cost. As a key device in optical sensing, the detector is fabricated from Ge (germanium) on a polarization-insensitive SOI (Silicon-on-Insulator) platform. Other devices, such as end-face couplers, multimode interference couplers, thermally modulated phase shifters, and tunable optical attenuators, are fabricated based on Si (silicon) waveguides. In these processes, Ge needs to be epitaxially grown on the SOI wafer, and after etching the waveguide morphology, ion implantation is performed to form a PN junction (P-type-N-type semiconductor junction).
[0003] Currently, in the manufacturing process of optical sensors, after etching silicon (Si) waveguides and directionally growing Ge single crystals, chemical mechanical polishing (CMP) is required on the wafer. In actual process operations, because the waveguide etching depth of the 3μm SOI platform is >2μm, the waveguide aspect ratio is large, and CMP can easily cause the silicon waveguide to collapse. Summary of the Invention
[0004] This application provides a method for manufacturing an optical sensor to solve the problem that CMP (Chemical Motion Processing) can easily cause silicon waveguides to collapse in existing processes.
[0005] In a first aspect, this application provides a method for manufacturing an optical sensor, comprising: depositing silicon dioxide on a substrate surface, wherein the substrate has a first silicon waveguide and a germanium epitaxial structure, the deposited silicon dioxide being used to fill the grooves of the first silicon waveguide; polishing the side of the substrate where the germanium epitaxial structure is disposed; removing the silicon dioxide deposited on the substrate surface; fabricating a germanium waveguide, metal interconnect vias, metal wires, and a pin area on the substrate where the silicon dioxide has been removed, thereby obtaining an optical sensor; each metal wire being connected to a corresponding target waveguide through a metal interconnect via, and each metal wire being electrically connected to an external circuit through a pin area; the target waveguide being either the first silicon waveguide or the germanium waveguide.
[0006] In this embodiment of the application, by filling the groove of the first silicon waveguide with silicon dioxide before polishing, the first silicon waveguide can be supported by silicon dioxide during polishing, thereby reducing the occurrence of silicon waveguide collapse during polishing.
[0007] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, a photosensitive sensor is obtained by fabricating a germanium waveguide, metal interconnect vias, metal wires, and pin regions on a substrate where the silicon dioxide has been removed. This includes: fabricating the germanium waveguide on the germanium epitaxial structure on the substrate where the silicon dioxide has been removed; performing ion implantation on the germanium waveguide; and fabricating the metal interconnect vias, metal wires, and pin regions in the regions where the first silicon waveguide and the germanium waveguide are located, respectively, to obtain the photosensitive sensor.
[0008] In this embodiment, after removing silicon dioxide, germanium waveguides are first fabricated and ion implanted, and then metal interconnect vias, metal wires, and pinning areas are fabricated, thereby completing the fabrication of the optical sensor.
[0009] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the first silicon waveguide is not connected to the germanium waveguide; after manufacturing the germanium waveguide, the method further includes: manufacturing a second silicon waveguide on the substrate; wherein the first silicon waveguide is connected to the germanium waveguide through the second silicon waveguide.
[0010] In this embodiment, since silicon dioxide is deposited in the first silicon waveguide, removing the deposited silicon dioxide may damage the germanium epitaxial structure. Therefore, the silicon waveguide required for the optical sensor is divided into two segments, and the second silicon waveguide structure is fabricated after the germanium waveguide is fabricated, thus avoiding damage to the germanium epitaxial structure.
[0011] In conjunction with the technical solution provided in the first aspect above, in some possible embodiments, before depositing silicon dioxide on the substrate surface, the method further includes: fabricating the first silicon waveguide on the substrate; and fabricating the germanium epitaxial structure on the substrate.
[0012] In this embodiment, since the annealing temperature of germanium is lower than that of silicon ion implantation (i.e., doping), the conflict between the annealing temperatures of germanium and silicon can be reduced by first fabricating a first silicon waveguide on the substrate and then fabricating a germanium epitaxial structure on the substrate.
[0013] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, fabricating a first silicon waveguide on a substrate includes: etching the substrate to obtain a preset waveguide morphology; and doping the region where the waveguide morphology is located to obtain the first silicon waveguide.
[0014] In conjunction with the technical solution provided in the first aspect above, in some possible embodiments, etching is performed on the substrate to obtain a waveguide morphology, including: etching on the substrate to obtain a first groove and a second groove that are parallel to each other; wherein, the first groove and the second groove are spaced apart by a first preset distance; etching the side of the bottom of the first groove near the second groove to obtain a third groove; etching the side of the bottom of the second groove near the first groove to obtain a fourth groove; wherein, after etching to obtain the fourth groove and the third groove, the waveguide morphology is obtained.
[0015] In this embodiment, by first etching the first and second grooves, and then etching the third and fourth grooves in the first and second grooves respectively, the waveguide morphology of the first silicon waveguide can be manufactured conveniently and quickly.
[0016] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, doping is performed on the region where the waveguide morphology is located to obtain the first silicon waveguide, including: performing N-type heavy doping on the third and fourth grooves in the region of the waveguide morphology used to manufacture a thermally modulated phase shifter; performing N-type heavy doping on the third groove in the region of the waveguide morphology used to manufacture a tunable optical attenuator, and performing P-type heavy doping on the fourth groove in the region of the waveguide morphology used to manufacture a tunable optical attenuator; wherein, the waveguide morphology after doping is the first silicon waveguide.
[0017] In this embodiment, by heavily doping the third and fourth grooves with N-type doping, this portion of the first silicon waveguide can function as a thermally modulated phase shifter. Furthermore, by heavily doping the third groove with N-type doping and the fourth groove with P-type doping, this section of the first silicon waveguide can function as a tunable optical attenuator, thus achieving the complete effect of the first silicon waveguide.
[0018] In conjunction with the technical solution provided in the first aspect above, in some possible embodiments, fabricating a second silicon waveguide on the substrate includes: etching on the substrate to obtain parallel fifth and sixth grooves; wherein the fifth groove and the sixth groove are spaced apart by a second preset distance; etching the side of the bottom of the fifth groove near the sixth groove to obtain a seventh groove; etching the side of the bottom of the sixth groove near the fifth groove to obtain an eighth groove; wherein, after etching to obtain the seventh and eighth grooves, the second silicon waveguide is obtained.
[0019] In this embodiment, by first etching the fifth and sixth grooves, and then etching the seventh and eighth grooves in the fifth and sixth grooves respectively, the waveguide morphology of the second silicon waveguide can be manufactured conveniently and quickly.
[0020] In conjunction with the technical solution provided in the first aspect above, in some possible embodiments, fabricating a germanium epitaxial structure on the substrate includes: etching the substrate to obtain an epitaxial trench; wherein the epitaxial trench and the first silicon waveguide on the substrate do not overlap; epitaxially growing germanium in the epitaxial trench to obtain the germanium epitaxial structure.
[0021] In this embodiment, by etching epitaxial trenches on the substrate and then epitaxially growing germanium inside and outside the trenches, the fabrication of germanium epitaxial structures can be achieved conveniently and quickly.
[0022] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, fabricating the germanium waveguide on the germanium epitaxial structure on the substrate where the silicon dioxide has been removed includes: depositing a silicon dioxide thin film on the surface of the substrate where the deposited silicon dioxide has been removed; and etching the region where the germanium epitaxial structure is located to obtain the germanium waveguide.
[0023] In this embodiment, a silicon dioxide thin film is used to protect areas that do not need to be etched, thereby reducing the possibility of damage to the structure of other areas.
[0024] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, manufacturing the metal interconnect vias includes: depositing a silicon dioxide thin film on the germanium waveguide and the first silicon waveguide; etching the silicon dioxide thin film at a first designated position in the region where the germanium waveguide and the first silicon waveguide are located to obtain a plurality of metal interconnect vias.
[0025] In this embodiment, the locations where metal interconnect vias do not need to be manufactured are protected by the redeposited silicon dioxide film, while isolating the first silicon waveguide, germanium waveguide, and other regions from the metal lines that need to be manufactured subsequently.
[0026] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, manufacturing the metal wire includes: manufacturing the metal wire on the surface of the silicon dioxide thin film, with different metal wires respectively connected to the corresponding target waveguide through a metal interconnect via.
[0027] In this embodiment, metal wires are manufactured to connect different structures and serve as paths for subsequent signal transmission.
[0028] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, manufacturing the needle-piercing region includes: depositing another layer of silicon dioxide thin film on the substrate surface to cover the metal line; etching the silicon dioxide thin film at a second designated position in the region of each metal line to obtain a plurality of needle-piercing regions.
[0029] In this embodiment, a needle-piercing area is manufactured as an interface for the optical sensor to interact with the outside world. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic flowchart illustrating a method for manufacturing an optical sensor according to an embodiment of this application;
[0032] Figure 2 This is a structural schematic diagram of the waveguide morphology of a first silicon waveguide as shown in an embodiment of this application;
[0033] Figure 3 This is a schematic diagram of the structure of a substrate after the first and second grooves have been fabricated, as shown in an embodiment of this application.
[0034] Figure 4 This is a schematic diagram of the structure of a substrate after the third and fourth grooves have been fabricated, as shown in an embodiment of this application;
[0035] Figure 5 This is a schematic diagram illustrating doping of a first silicon waveguide according to an embodiment of this application;
[0036] Figure 6 This is a schematic diagram of the structure of a substrate after an epitaxial trench has been fabricated, as shown in an embodiment of this application;
[0037] Figure 7 This is a schematic diagram of the structure of a substrate after a germanium epitaxial structure has been fabricated, as shown in an embodiment of this application.
[0038] Figure 8 This is a schematic diagram of the structure of a substrate after silicon dioxide has been deposited in a first silicon waveguide, as shown in an embodiment of this application.
[0039] Figure 9 This is a schematic diagram of the structure of a substrate after removing the silicon dioxide deposited in the first silicon waveguide, as shown in an embodiment of this application.
[0040] Figure 10 This is a schematic diagram of the structure of a substrate after a germanium waveguide has been fabricated, as shown in an embodiment of this application;
[0041] Figure 11 This is a schematic diagram of the structure of a substrate after metal interconnect vias have been fabricated, as shown in an embodiment of this application;
[0042] Figure 12 This is a schematic diagram of the structure of a substrate after metal lines have been fabricated, as shown in an embodiment of this application;
[0043] Figure 13 This is a schematic diagram of the structure of a substrate after the needle-piercing region has been fabricated, as shown in an embodiment of this application;
[0044] Figure 14 This is a schematic diagram illustrating a structure in which a first silicon waveguide and a germanium waveguide are directly connected, as shown in an embodiment of this application.
[0045] Figure 15 This is a schematic diagram illustrating a structure in which a first silicon waveguide and a germanium waveguide are not directly connected, according to an embodiment of this application.
[0046] Figure 16 This is a schematic diagram illustrating a structure in which a first silicon waveguide and a germanium waveguide are connected via a second silicon waveguide, as shown in an embodiment of this application.
[0047] Reference numerals: 111-First groove; 112-Second groove; 121-Third groove; 122-Fourth groove; 131-Epipolar groove; 132-Germanium epitaxial structure; 133-Germanium waveguide; 141-Metal interconnect via; 142-Metal wire; 143-Needle insertion area. Detailed Implementation
[0048] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0049] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0050] The technical solution of this application will now be described in detail with reference to the accompanying drawings.
[0051] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for manufacturing an optical sensor according to an embodiment of this application. The following will be combined with... Figure 1 The steps involved are explained.
[0052] S100: Deposit silicon dioxide on the substrate surface.
[0053] The substrate has a first silicon waveguide and a germanium epitaxial structure prefabricated on it, and the deposited silicon dioxide is used to fill the grooves of the first silicon waveguide.
[0054] Silica is used to fill the grooves in the first silicon waveguide, which allows the first silicon waveguide to be supported by silica during polishing, thereby reducing the possibility of silicon waveguide collapse in step S200.
[0055] In one embodiment, silicon dioxide can be deposited on the substrate surface using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or solution deposition. The specific method of silicon dioxide deposition can be selected according to actual needs. There are no restrictions on the method of silicon dioxide deposition here, as long as it can fill the groove of the first silicon waveguide without damaging the structure of the first silicon waveguide.
[0056] In one embodiment, a first silicon waveguide can be fabricated on the substrate before silicon dioxide is deposited on the substrate surface, and then a germanium epitaxial structure can be fabricated on the substrate.
[0057] Since the annealing temperature of germanium is lower than that of silicon ion implantation (i.e., doping), fabricating the first silicon waveguide on the substrate first, and then fabricating the germanium epitaxial structure on the substrate, can reduce the conflict between the annealing temperatures of germanium and silicon.
[0058] Optionally, the first silicon waveguide can be fabricated on the substrate by first etching the substrate to obtain a predetermined waveguide morphology. Then, the region containing the waveguide morphology is doped to obtain the first silicon waveguide.
[0059] The method of fabricating the first silicon waveguide on the substrate can be any existing method that can realize the fabrication of the first silicon waveguide, and is not limited to the method exemplified here.
[0060] For a better understanding of the waveguide morphology of the first silicon waveguide described above, please refer to [link / reference]. Figure 2 , Figure 2 This is a cross-sectional view of the waveguide topography.
[0061] like Figure 2 As shown, the waveguide morphology of the first silicon waveguide consists of two relatively shallow grooves (i.e., Figure 2 The first groove 111, the second groove 112 shown, and two deeper grooves (i.e., Figure 2The third groove 121 and the fourth groove 122 shown are formed. Two shallower grooves are arranged in parallel, and a deeper groove is provided on the side of the bottom of each shallower groove near the other shallower groove.
[0062] In one embodiment, etching on a substrate to obtain a waveguide morphology can be performed by first etching on the substrate to obtain parallel first grooves 111 and second grooves 112. The first groove 111 and the second groove 112 are spaced apart by a first predetermined distance (…). Figure 3 (as shown in h), such as Figure 3 As shown. Then, the bottom of the first groove 111 near the second groove 112 is etched to obtain the third groove 121. And the bottom of the second groove 112 near the first groove 111 is etched to obtain the fourth groove 122, as shown. Figure 4 As shown. The waveguide morphology is obtained after etching to form the fourth groove 122 and the third groove 121. Figure 3 Region 1 is silicon (Si), and region 2 is silicon dioxide (SiO2).
[0063] The first preset spacing can be set according to actual needs, and its specific value is not limited here.
[0064] It should be noted that the adjustable optical attenuator region and the thermally adjustable phase shifter region shown in the figure are only cross-sectional views for ease of understanding. Figure 3 This does not represent the actual positional relationship between the tunable optical attenuator region and the thermally tuned phase shifter region. The tunable optical attenuator region and the thermally tuned phase shifter region are different regions of the first silicon waveguide.
[0065] Optionally, the process of etching the side of the bottom of the first groove 111 near the second groove 112 to obtain the third groove 121, and etching the side of the bottom of the second groove 112 near the first groove 111 to obtain the fourth groove 122, can be carried out simultaneously in the same etching process.
[0066] In other words, the method of etching on the substrate to obtain the waveguide morphology can be divided into two steps. The first step is to perform shallow etching to prepare the first groove 111 and the second groove 112. The second step is to perform deep etching to prepare the third groove 121 and the fourth groove 122.
[0067] Alternatively, the first groove 111, the second groove 112, the third groove 121, and the fourth groove 122 can be etched in four separate steps.
[0068] The methods for etching on the substrate to obtain waveguide morphology are not limited to those listed above.
[0069] Optionally, the method of doping the region containing the waveguide morphology to obtain the first silicon waveguide can be as follows: N-type heavy doping (NPP) is performed on the third groove 121 and the fourth groove 122 in the region of the waveguide morphology used to fabricate the thermally modulated phase shifter. N-type heavy doping is performed on the third groove 121 in the region of the waveguide morphology used to fabricate the tunable optical attenuator, and P-type heavy doping (PPP) is performed on the fourth groove 122 in the region of the waveguide morphology used to fabricate the tunable optical attenuator. The waveguide morphology after doping is the first silicon waveguide. For easier understanding, please refer to [link to relevant documentation]. Figure 5 It is important to note that... Figure 5 The regions of the adjustable optical attenuator and the thermally modulated phase shifter shown should belong to the same waveguide. Figure 5 This is a schematic diagram for ease of understanding only and does not represent the actual positional relationship between the areas of the tunable attenuator and the thermally modulated phase shifter.
[0070] By heavily doping the third groove 121 and the fourth groove 122 with N-type doping, this portion of the first silicon waveguide can function as a thermally modulated phase shifter. Furthermore, by heavily doping the third groove 121 with N-type doping and the fourth groove 122 with P-type doping, this section of the first silicon waveguide can function as a tunable optical attenuator, thus achieving the complete effect of the first silicon waveguide.
[0071] Optionally, in the process of doping the region containing the waveguide morphology to obtain the first silicon waveguide, the third groove 121 and the fourth groove 122 in the region of the waveguide morphology used to manufacture the thermally modulated phase shifter can be heavily N-type doped. The third groove 121 in the region used to manufacture the tunable optical attenuator can also be heavily N-type doped. Then, the fourth groove 122 in the region used to manufacture the tunable optical attenuator can be heavily P-type doped. Thus, the doping operation of the first silicon waveguide is completed through two doping steps.
[0072] The specific implementation methods for N-type heavy doping and P-type heavy doping are well known to those skilled in the art, and will not be elaborated here for the sake of brevity.
[0073] In one embodiment, the method for fabricating a germanium epitaxial structure on a substrate may be: first, etching the substrate to obtain an epitaxial trench 131, such as... Figure 6 As shown. The epitaxial trench 131 does not overlap with the position of the first silicon waveguide on the substrate. Then, germanium is epitaxially grown in the epitaxial trench 131 to obtain a germanium epitaxial structure 132, as shown. Figure 7 As shown.
[0074] The depth, width, and length of the epitaxial groove 131 can be set according to actual needs, and their specific values are not limited here.
[0075] Germanium is epitaxially grown in epitaxial tank 131 to obtain germanium epitaxial structure 132. This can be done by epitaxial methods such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and solid phase epitaxy (SPE), without any restrictions on the specific type.
[0076] After germanium is epitaxially grown in epitaxial trench 131 to obtain germanium epitaxial structure 132, step S100 is executed. The substrate structure after silicon dioxide deposition is as follows. Figure 8 As shown.
[0077] S200: Polish the side of the substrate where the germanium epitaxial structure is located.
[0078] Optionally, the side of the substrate with the germanium epitaxial structure 132 can be polished using chemical mechanical polishing (CMP).
[0079] Alternatively, other polishing methods can be used; no specific polishing method is restricted here.
[0080] S300: Removes silicon dioxide deposited on the substrate surface.
[0081] Among them, the substrate with the silicon dioxide deposited on the substrate surface removed, such as Figure 9 As shown.
[0082] In one embodiment, the silicon dioxide deposited on the substrate surface can be removed by using BOE (a buffer oxide etchant formed by mixing ammonium fluoride and hydrofluoric acid in a certain proportion) to strip the silicon dioxide. During silicon dioxide removal, photoresist is used to protect the germanium epitaxial region.
[0083] Alternatively, other methods can be used, such as dry etching or physical stripping, as long as they can remove the silicon dioxide deposited on the substrate surface.
[0084] S400: A germanium waveguide, metal interconnect vias, metal wires, and pin areas are fabricated on a substrate where silicon dioxide has been removed to obtain an optical sensor.
[0085] Each metal wire is connected to the corresponding target waveguide through a metal interconnect via, and each metal wire is electrically connected to the external circuit through a pinning area; the target waveguide is either a first silicon waveguide or a germanium waveguide.
[0086] In one embodiment, a photosensitive sensor is obtained by fabricating a germanium waveguide, metal interconnect vias, metal wires, and a pinned region on a substrate with silicon dioxide removed. First, a germanium waveguide 133 is fabricated on a germanium epitaxial structure 132 on a substrate with silicon dioxide removed. Then, ion implantation is performed on the germanium waveguide 133. Subsequently, metal interconnect vias 141, metal wires 142, and a pinned region 143 are fabricated in the regions where the first silicon waveguide and the germanium waveguide 133 are located, respectively, to obtain the photosensitive sensor.
[0087] After removing the silicon dioxide, the germanium waveguide 133 is first fabricated and ion implanted, and then the metal interconnect vias, metal wires and pin areas are fabricated, thus completing the fabrication of the optical sensor.
[0088] Optionally, the germanium waveguide 133 can be fabricated on the germanium epitaxial structure 132 on a substrate with the silicon dioxide removed by depositing a thin film of silicon dioxide on the substrate surface. Then, the region containing the germanium epitaxial structure 132 is etched to obtain the germanium waveguide 133. For easier understanding, please refer to [link to relevant documentation]. Figure 10 .
[0089] By depositing a thin film of silicon dioxide to protect areas that do not require etching, the possibility of structural damage to other areas is reduced.
[0090] The specific method for depositing the silica thin film can be selected according to actual needs. For example, any one of the following methods can be selected: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), solution deposition, etc. There are no restrictions on the specific method here.
[0091] Optionally, the germanium waveguide 133 can be obtained by etching the region containing the germanium epitaxial structure 132. This can be achieved by etching the germanium epitaxial structure 132 to obtain parallel ninth and tenth grooves. The bottom of the ninth and tenth grooves is germanium. The side of the ninth groove furthest from the tenth groove is connected to the substrate (i.e., silicon), and the side of the tenth groove furthest from the ninth groove is also connected to the substrate (i.e., silicon). A third predetermined spacing of germanium is placed between the ninth and tenth grooves.
[0092] In one embodiment, the specific method for manufacturing metal interconnect vias may be as follows: First, a silicon dioxide thin film is deposited on the surfaces of the germanium waveguide 133 and the first silicon waveguide. Then, the silicon dioxide thin film at a first designated location in the region where the germanium waveguide 133 and the first silicon waveguide are located is etched to obtain a plurality of metal interconnect vias 141. Figure 11 As shown.
[0093] The re-deposited silicon dioxide film protects the locations where metal interconnect vias 141 do not need to be manufactured, while isolating areas such as the first silicon waveguide, germanium waveguide 133, etc., from the metal lines 142, etc., that need to be manufactured subsequently.
[0094] Optional, the first specified position is as follows Figure 11 As shown, the first designated location may include the N-type heavily doped location (such as the fourth groove 122) in the region of the first silicon waveguide belonging to the thermally modulated phase shifter. It may also include the N-type heavily doped and P-type heavily doped locations in the region of the first silicon waveguide belonging to the tunable optical attenuator. Furthermore, it may include the bottom of the grooves on both sides of the germanium waveguide 133 (i.e., the ninth and tenth grooves) in the region of the germanium waveguide 133.
[0095] Optionally, the specific method for manufacturing metal lines can be: manufacturing metal lines on the surface of a silicon dioxide thin film, with different metal lines connected to the corresponding target waveguides through a metal interconnect via.
[0096] Metal wires are manufactured to connect different structures and serve as paths for subsequent signal transmission.
[0097] The specific location of metal wire 142 is as follows Figure 12 As shown, the first end of each metal line 142 is connected to a metal interconnect via 141, and the second end extends to the surface of the uppermost silicon dioxide film of the substrate.
[0098] Optionally, the pinned regions can be fabricated by first depositing another layer of silicon dioxide film on the substrate surface to cover the metal lines. Then, the silicon dioxide film at a second designated location within the area of each metal line is etched to obtain multiple pinned regions. These pinned regions serve as the interface for the photosensor to interact with the outside world.
[0099] like Figure 13 As shown, a portion of the silicon dioxide film on the surface of each metal wire 142 away from the metal interconnect via 141 is etched away, exposing the metal wire 142 and facilitating subsequent needle insertion operations.
[0100] It is important to note that Figures 3-13 This is a schematic diagram created to facilitate understanding of the process flow and does not represent the actual positional relationship between the tunable attenuator region, the thermally modulated phase shifter region, and the germanium waveguide region.
[0101] In one implementation, the first silicon waveguide and the germanium waveguide can be connected, such as... Figure 14 As shown.
[0102] The third groove of the first silicon waveguide is connected to the ninth groove of the germanium waveguide, and the fourth groove of the first silicon waveguide is connected to the tenth groove of the germanium waveguide.
[0103] In another implementation, the first silicon waveguide may not be connected to the germanium waveguide, such as... Figure 15 As shown, the first silicon waveguide and the germanium waveguide are separated by a silicon substrate.
[0104] In this method, after the germanium waveguide is fabricated on the substrate, a second silicon waveguide needs to be fabricated to connect the germanium waveguide and the first silicon waveguide, and then the germanium waveguide is implanted with ions.
[0105] Because silicon dioxide is deposited in the first silicon waveguide, removing the deposited silicon dioxide may damage the germanium epitaxial structure. Therefore, the silicon waveguide required for the optical sensor is divided into two segments. The second silicon waveguide structure is fabricated after the germanium waveguide is completed, thus avoiding damage to the germanium epitaxial structure.
[0106] Optionally, the second silicon waveguide can be fabricated on the substrate by: firstly etching a fifth and a sixth parallel groove on the substrate, wherein the fifth and sixth grooves are spaced apart by a second predetermined spacing; then etching the bottom of the fifth groove near the sixth groove to obtain a seventh groove; and etching the bottom of the sixth groove near the fifth groove to obtain an eighth groove. The second silicon waveguide is obtained after etching the seventh and eighth grooves.
[0107] By first etching the fifth and sixth grooves, and then etching the seventh and eighth grooves in the fifth and sixth grooves respectively, the waveguide morphology of the second silicon waveguide can be manufactured conveniently and quickly.
[0108] The second preset spacing can be the same as the first preset spacing.
[0109] Optionally, in this embodiment, the specific method for manufacturing the metal interconnect vias can be as follows: First, a silicon dioxide thin film is deposited on the surfaces of the germanium waveguide, the first silicon waveguide, and the second silicon waveguide. Then, the silicon dioxide thin film at a first designated location in the region where the germanium waveguide, the first silicon waveguide, and the second silicon waveguide are located is etched to obtain multiple metal interconnect vias. The method of etching the silicon dioxide thin film at the first designated location in the region where the germanium waveguide, the first silicon waveguide, and the second silicon waveguide are located to obtain multiple metal interconnect vias is the same as the aforementioned method of etching the silicon dioxide thin film at the first designated location in the region where the germanium waveguide and the first silicon waveguide are located to obtain multiple metal interconnect vias; for the sake of brevity, it will not be elaborated here.
[0110] like Figure 16 As shown, the fifth groove is connected to the first groove, the sixth groove is connected to the second groove, the third groove is connected to the ninth groove through the seventh groove, and the fourth groove is connected to the tenth groove through the eighth groove.
[0111] Optionally, the width of the fifth groove can be the same as that of the first groove, the width of the sixth groove can be the same as that of the second groove, the width of the third, seventh, and ninth grooves can be the same, and the width of the fourth, eighth, and tenth grooves can be the same.
[0112] To facilitate understanding of the above-described optical sensor manufacturing method, examples will be provided below.
[0113] First, etching is performed on the substrate to obtain the predetermined waveguide morphology. The region containing the waveguide morphology is then doped to obtain the first silicon waveguide.
[0114] The substrate is then etched to obtain epitaxial trenches. Germanium is then epitaxially grown in the epitaxial trenches to obtain a germanium epitaxial structure.
[0115] Next, silicon dioxide is deposited on the substrate surface to fill the grooves in the first silicon waveguide. Then, the side of the substrate with the germanium epitaxial structure is polished.
[0116] After polishing, the silicon dioxide deposited on the substrate surface is removed. A germanium waveguide is then fabricated on the germanium epitaxial structure on the substrate where the silicon dioxide has been removed. Next, a second silicon waveguide is fabricated on the substrate, with the first silicon waveguide connected to the germanium waveguide via the second silicon waveguide. Ion implantation is then performed on the germanium waveguide. Finally, metal interconnect vias, metal wires, and pin areas are fabricated in the regions containing the first silicon waveguide and the germanium waveguide, respectively, to obtain the optical sensor.
[0117] The specific implementation methods of each step in the above example have been clearly described above, and will not be repeated here for the sake of brevity. The example here is only one implementation of the optical sensor manufacturing method provided in this application, and the optical sensor manufacturing method provided in this application is not limited to the example shown here.
[0118] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method of manufacturing a photosensor, characterized by, include: Silicon dioxide is deposited on the surface of a substrate on which a first silicon waveguide and a germanium epitaxial structure are present. The deposited silicon dioxide is used to fill the grooves of the first silicon waveguide to support the first silicon waveguide during polishing and reduce the collapse of the first silicon waveguide due to polishing. Polish the side of the substrate where the germanium epitaxial structure is located; Remove the silicon dioxide deposited on the substrate surface; A germanium waveguide, metal interconnect vias, metal wires, and a pin area are fabricated on a substrate on which the silicon dioxide has been removed to obtain an optical sensor; each metal wire is connected to a corresponding target waveguide through a metal interconnect via, and each metal wire is electrically connected to an external circuit through a pin area; the target waveguide is either the first silicon waveguide or the germanium waveguide. Specifically, a germanium waveguide, metal interconnect vias, metal wires, and pin areas are fabricated on a substrate where the silicon dioxide has been removed to obtain an optical sensor, comprising: The germanium waveguide is fabricated on the germanium epitaxial structure on the substrate where the silicon dioxide has been removed; the first silicon waveguide is not connected to the germanium waveguide. A second silicon waveguide is fabricated on the substrate; wherein the first silicon waveguide is connected to the germanium waveguide through the second silicon waveguide; Ion implantation is performed on the germanium waveguide; The optical sensor is obtained by fabricating the metal interconnect vias, the metal wires, and the pin areas in the regions where the first silicon waveguide and the germanium waveguide are located.
2. The method of claim 1, wherein, Before depositing silicon dioxide on the substrate surface, the method further includes: The first silicon waveguide is fabricated on the substrate; The germanium epitaxial structure is fabricated on the substrate.
3. The method of claim 2, wherein, Fabricating a first silicon waveguide on a substrate includes: Etching is performed on the substrate to obtain a predetermined waveguide morphology; The region containing the waveguide morphology is doped to obtain the first silicon waveguide.
4. The method of claim 3, wherein, Etching is performed on the substrate to obtain a predetermined waveguide morphology, including: Etching is performed on the substrate to obtain a parallel first groove and a second groove; wherein the first groove and the second groove are spaced apart by a first preset distance. The bottom of the first groove is etched on the side closest to the second groove to obtain the third groove; The bottom of the second groove is etched on the side closest to the first groove to obtain the fourth groove; The waveguide morphology is obtained by etching the fourth and third grooves.
5. The method of claim 4, wherein, The first silicon waveguide is obtained by doping the region containing the waveguide morphology, comprising: The third and fourth grooves in the region used to manufacture the thermally modulated phase shifter in the waveguide morphology are heavily N-type doped. In the waveguide morphology, the third groove in the region used to manufacture the tunable optical attenuator is heavily doped with N-type, and the fourth groove in the region used to manufacture the tunable optical attenuator is heavily doped with P-type. The waveguide morphology after doping is the first silicon waveguide.
6. The method of claim 2, wherein, Fabricating a germanium epitaxial structure on the substrate includes: The substrate is etched to obtain an epitaxial trench; wherein the epitaxial trench does not overlap with the position of the first silicon waveguide on the substrate; Germanium is epitaxially grown in the epitaxial trench to obtain the germanium epitaxial structure.
7. The method of claim 1, wherein, Fabricating the germanium waveguide on the germanium epitaxial structure on a substrate where the silicon dioxide has been removed includes: A thin film of silicon dioxide is deposited on the surface of a substrate after the deposited silicon dioxide has been removed; The region containing the germanium epitaxial structure is etched to obtain the germanium waveguide.
8. The method of claim 1, wherein, Manufacturing the aforementioned metal interconnect vias includes: A silicon dioxide thin film is deposited on the surfaces of the germanium waveguide and the first silicon waveguide; The silicon dioxide thin film at a first designated position in the region where the germanium waveguide and the first silicon waveguide are located is etched to obtain multiple metal interconnect vias.
9. The method of claim 8, wherein, Manufacturing the metal wire includes: Metal lines are fabricated on the surface of the silicon dioxide thin film, and different metal lines are connected to the corresponding target waveguide through a metal interconnect via.
10. The method of claim 9, wherein, Creating the needle insertion area includes: A silicon dioxide thin film is deposited again on the substrate surface to cover the metal lines; A silicon dioxide film is etched at a second designated location in the region of each of the metal lines to obtain multiple needle-piercing regions.
11. The method of claim 1, wherein, Fabricating a second silicon waveguide on the substrate includes: Etching is performed on the substrate to obtain a parallel fifth groove and a sixth groove; wherein the fifth groove and the sixth groove are spaced apart by a second predetermined distance; The bottom of the fifth groove is etched on the side near the sixth groove to obtain the seventh groove; The bottom of the sixth groove is etched on the side closest to the fifth groove to obtain the eighth groove; The second silicon waveguide is obtained by etching the seventh and eighth grooves.