Light emitting diode for improving brightness, preparation method thereof and display panel

Abstract

The invention provides a light emitting diode for improving brightness, a preparation method thereof and a display panel, and belongs to the technical field of photoelectron manufacturing. The light emitting diode comprises a substrate, a first epitaxial layer, a second epitaxial layer, a first flat layer, a first electrode, a second electrode and a third electrode, the first electrode and the first epitaxial layer are sequentially stacked on the substrate, the orthographic projection of the first electrode on the substrate is located in the orthographic projection of the first epitaxial layer on the substrate, and the first flat layer is located on the substrate; the second electrode and the second epitaxial layer are sequentially stacked on the surface, away from the substrate, of the first epitaxial layer, and the orthographic projection of the second electrode on the substrate is located in the orthographic projection of the second epitaxial layer on the substrate; a first through hole penetrating to the substrate is formed in the surface of the first flat layer, at least part of the third electrode is electrically connected with the second epitaxial layer, and the third electrode further extends into the first through hole. According to the embodiment of the invention, more current can be injected, so that the peak brightness is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and in particular, to a light emitting diode with improved brightness, a preparation method thereof and a display panel. BACKGROUND

[0002] A light emitting diode (LED) is a new product with great influence in the optoelectronic industry, which has the characteristics of small size, long service life, rich color, low energy consumption, etc., and is widely used in lighting, display screen, signal lamp, backlight, toy and other fields.

[0003] In the related art, a light emitting diode generally includes a substrate, an epitaxial layer and two electrodes. The epitaxial layer is located on the substrate, and the two electrodes are electrically connected to different conductive semiconductor layers of the epitaxial layer. After the electrodes are powered on, the current is expanded to each area on the surface of the epitaxial layer, so that the light emitting diode emits light.

[0004] However, after a long time of work, the light emitting brightness of the light emitting diode will decrease, thereby causing the display effect or the lighting effect of the light emitting diode to become poor. SUMMARY

[0005] Embodiments of the present disclosure provide a light emitting diode with improved brightness, a preparation method thereof and a display panel, which can improve the problem of poor brightness of the light emitting diode and decrease in brightness after a long time of use. The technical solution is as follows:

[0006] In one aspect, the present disclosure provides a light emitting diode, which includes a substrate, a first epitaxial layer, a second epitaxial layer, a first planar layer, a first electrode, a second electrode and a third electrode, the first epitaxial layer and the second epitaxial layer have the same light emitting color; the first electrode and the first epitaxial layer are sequentially stacked on the substrate, a projection of the first electrode on the substrate is located within a projection of the first epitaxial layer on the substrate, the first planar layer is located on the substrate and surrounds the sidewall of the first electrode and the sidewall of the first epitaxial layer; the second electrode and the second epitaxial layer are sequentially stacked on a surface of the first epitaxial layer away from the substrate, a projection of the second electrode on the substrate is located within a projection of the second epitaxial layer on the substrate; a surface of the first planar layer has a first through hole penetrating to the substrate, at least part of the third electrode is electrically connected to the second epitaxial layer, and the third electrode further extends into the first through hole.

[0007] Optionally, the light emitting diode further comprises a second planar layer, a third epitaxial layer and a fourth electrode; the second planar layer is located on the first planar layer and surrounds the sidewall of the second electrode and the sidewall of the second epitaxial layer, the fourth electrode and the third epitaxial layer are sequentially stacked on the surface of the second epitaxial layer away from the substrate, the orthogonal projection of the fourth electrode on the substrate is located in the orthogonal projection of the third epitaxial layer on the substrate; the surface of the second planar layer has a second through hole in communication with the first through hole, the third electrode is located on the surface of the third epitaxial layer away from the substrate, and the third electrode further extends to the substrate through the second through hole and the first through hole in sequence.

[0008] Optionally, the outer contour of the orthogonal projection of the first electrode on the substrate coincides with the outer contour of the orthogonal projection of the first epitaxial layer on the substrate; the outer contour of the orthogonal projection of the second electrode on the substrate coincides with the outer contour of the orthogonal projection of the first epitaxial layer on the substrate; the outer contour of the orthogonal projection of the second electrode on the substrate coincides with the outer contour of the orthogonal projection of the second epitaxial layer on the substrate; the outer contour of the orthogonal projection of the fourth electrode on the substrate coincides with the outer contour of the orthogonal projection of the second epitaxial layer on the substrate; the outer contour of the orthogonal projection of the fourth electrode on the substrate coincides with the outer contour of the orthogonal projection of the third epitaxial layer on the substrate.

[0009] Optionally, the distance from the hole wall of the first through hole to the sidewall of the first epitaxial layer is not less than 0.5 μm; the distance from the hole wall of the second through hole to the sidewall of the second epitaxial layer is not less than 0.5 μm.

[0010] Optionally, the overlapping area of the orthogonal projection of the first epitaxial layer and the first electrode on the substrate is not greater than the area of the orthogonal projection of the first epitaxial layer; the overlapping area of the orthogonal projection of the second epitaxial layer and the second electrode on the substrate is not greater than the area of the orthogonal projection of the second epitaxial layer; the overlapping area of the orthogonal projection of the third epitaxial layer and the fourth electrode on the substrate is not greater than the area of the orthogonal projection of the third epitaxial layer.

[0011] Optionally, the first planar layer comprises at least one of a silicon oxide layer, a titanium oxide layer and an aluminum oxide layer.

[0012] In another aspect, the present disclosure also provides a method for manufacturing a light emitting diode, the method comprising: providing a substrate; forming a first electrode and a first epitaxial layer in sequence on the substrate, a footprint of the first electrode on the substrate being located within a footprint of the first epitaxial layer on the substrate; forming a first planar layer on the substrate, the first planar layer surrounding sidewalls of the first electrode and sidewalls of the first epitaxial layer, a surface of the first planar layer having a first through hole penetrating to the substrate; forming a second electrode and a second epitaxial layer in sequence on a surface of the first epitaxial layer away from the substrate, a footprint of the second electrode on the substrate being located within a footprint of the second epitaxial layer on the substrate; and forming a third electrode on the first planar layer, at least a portion of the third electrode being electrically connected to the second epitaxial layer, and the third electrode further extending into the first through hole.

[0013] Optionally, before forming the third electrode on the first planar layer, the method further comprises: forming a second planar layer on the first planar layer, the second planar layer surrounding sidewalls of the second electrode and sidewalls of the second epitaxial layer, a surface of the second planar layer having a second through hole communicating with the first through hole; forming a fourth electrode and a third epitaxial layer in sequence on a surface of the second epitaxial layer away from the substrate, a footprint of the fourth electrode on the substrate being located within a footprint of the third epitaxial layer on the substrate; and forming the third electrode on the first planar layer comprises: forming the third electrode on a surface of the third epitaxial layer away from the substrate, the third electrode extending to the substrate through the second through hole and the first through hole in sequence.

[0014] Optionally, an outer contour of the footprint of the first electrode on the substrate coincides with an outer contour of the footprint of the first epitaxial layer on the substrate; an outer contour of the footprint of the second electrode on the substrate coincides with an outer contour of the footprint of the first epitaxial layer on the substrate; an outer contour of the footprint of the second electrode on the substrate coincides with an outer contour of the footprint of the second epitaxial layer on the substrate; an outer contour of the footprint of the fourth electrode on the substrate coincides with an outer contour of the footprint of the second epitaxial layer on the substrate; and an outer contour of the footprint of the fourth electrode on the substrate coincides with an outer contour of the footprint of the third epitaxial layer on the substrate.

[0015] In yet another aspect, the present disclosure provides a display panel, the display panel comprising a driving substrate and a plurality of light emitting diodes as described above, each of the light emitting diodes being arranged on the driving substrate.

[0016] The technical solutions provided by the embodiments of the present disclosure have at least the following beneficial effects:

[0017] The first epitaxial layer and the second epitaxial layer are stacked on the same substrate and have the same light-emitting color to form a double-layer light-emitting unit. The current can drive the two epitaxial layers simultaneously through the third electrode and the first electrode, so that the photon emission amount is superimposed, and double light output is achieved under the same driving current.

[0018] Moreover, the first epitaxial layer completely covers the first electrode, and the second epitaxial layer completely covers the second electrode, so as to avoid that the light-shielding area of the electrode is too large, and also avoid that the first electrode or the second electrode protrudes from the epitaxial layer to cause short circuit between the electrode and other film layers. The first planar layer surrounds and covers the electrode and the epitaxial layer sidewall, which not only protects the device from environmental erosion, but also prevents short circuit through insulation isolation, and ensures that the current is injected into the two epitaxial layers in a directional manner. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 is a top view of a light-emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 2 is Figure 1 is an AA cross-sectional view provided by the present disclosure;

[0022] Figure 3 is a structural schematic diagram of another light-emitting diode provided by an embodiment of the present disclosure;

[0023] Figure 4 is a flowchart of a preparation method of a light-emitting diode provided by an embodiment of the present disclosure;

[0024] Figure 5 is a preparation state diagram of a light-emitting diode provided by an embodiment of the present disclosure;

[0025] Figure 6 is a preparation state diagram of a light-emitting diode provided by an embodiment of the present disclosure;

[0026] Figure 7 is a structural schematic diagram of another light-emitting diode provided by an embodiment of the present disclosure;

[0027] Figure 8 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0028] The various signs in the drawings are explained as follows:

[0029] 10, substrate;

[0030] 21, first epitaxial layer; 22, second epitaxial layer; 23, third epitaxial layer;

[0031] 31, first flat layer; 311, first via hole;

[0032] 32, second flat layer; 321, second via hole;

[0033] 41, first electrode; 42, second electrode; 43, third electrode; 44, fourth electrode;

[0034] 50, driving substrate. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the drawings.

[0036] Unless otherwise defined, technical terms or scientific terms used herein should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third" and similar terms used in the specification and claims of the present patent application do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one" or "a" or similar terms do not denote a quantity limitation, but mean that at least one exists. The terms "include" or "contain" or similar terms mean that the elements or objects appearing before the terms "include" or "contain" cover the elements or objects listed after the terms "include" or "contain" and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", "top", "bottom", etc. are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0037] Figure 1 is a top view of a light-emitting diode provided by an embodiment of the present disclosure. Figure 2 is Figure 1 is an AA cross-sectional view provided. Figure 2 is a cross-sectional view taken from the AA cross-sectional line in Figure 1 is a cross-sectional view taken from the AA cross-sectional line in Figure 1 , 2 As shown in FIG. 1, the light-emitting diode includes a substrate 10, a first epitaxial layer 21, a second epitaxial layer 22, a first flat layer 31, a first electrode 41, a second electrode 42, and a third electrode 43, and the first epitaxial layer 21 and the second epitaxial layer 22 have the same light-emitting color.

[0038] AsFigure 2 As shown in FIG. 1, the first electrode 41 and the first epitaxial layer 21 are sequentially stacked on the substrate 10, the orthographic projection of the first electrode 41 on the substrate 10 is located within the orthographic projection of the first epitaxial layer 21 on the substrate 10, and the first planar layer 31 is located on the substrate 10 and surrounds the sidewalls of the first electrode 41 and the sidewalls of the first epitaxial layer 21.

[0039] As shown in FIG. 1, the first electrode 41 and the first epitaxial layer 21 are sequentially stacked on the substrate 10, the orthographic projection of the first electrode 41 on the substrate 10 is located within the orthographic projection of the first epitaxial layer 21 on the substrate 10, and the first planar layer 31 is located on the substrate 10 and surrounds the sidewalls of the first electrode 41 and the sidewalls of the first epitaxial layer 21. Figure 2 As shown in FIG. 1, the second electrode 42 and the second epitaxial layer 22 are sequentially stacked on the surface of the first epitaxial layer 21 away from the substrate 10, and the orthographic projection of the second electrode 42 on the substrate 10 is located within the orthographic projection of the second epitaxial layer 22 on the substrate 10.

[0040] As shown in FIG. 1, the first electrode 41 and the first epitaxial layer 21 are sequentially stacked on the substrate 10, the orthographic projection of the first electrode 41 on the substrate 10 is located within the orthographic projection of the first epitaxial layer 21 on the substrate 10, and the first planar layer 31 is located on the substrate 10 and surrounds the sidewalls of the first electrode 41 and the sidewalls of the first epitaxial layer 21. Figure 2 As shown in FIG. 1, the first electrode 41 and the first epitaxial layer 21 are sequentially stacked on the substrate 10, the orthographic projection of the first electrode 41 on the substrate 10 is located within the orthographic projection of the first epitaxial layer 21 on the substrate 10, and the first planar layer 31 is located on the substrate 10 and surrounds the sidewalls of the first electrode 41 and the sidewalls of the first epitaxial layer 21.

[0041] The light-emitting diode provided by the embodiment of the present disclosure has the first epitaxial layer 21 and the second epitaxial layer 22 stacked on the same substrate 10, and the light-emitting colors are the same, forming a double-layer light-emitting unit. The current can drive the two epitaxial layers at the same time through the third electrode 43 and the first electrode 41, so that the photon emission amount is superimposed, and double light output is realized under the same driving current.

[0042] Moreover, the first epitaxial layer 21 completely covers the first electrode 41, and the second epitaxial layer 22 completely covers the second electrode 42, so as to avoid that the light-shielding area of the electrode is too large, and also avoid that the first electrode 41 or the second electrode 42 protrudes from the epitaxial layer and causes short circuit of the electrode and other film layers. The first planar layer 31 surrounds and covers the sidewalls of the electrode and the epitaxial layer, which not only protects the device from environmental erosion, but also prevents short circuit through insulation isolation, and ensures that the current is injected into the two epitaxial layers in a directional manner.

[0043] Optionally, the substrate 10 is a sapphire substrate. The sapphire substrate has relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. Moreover, the sapphire material is relatively hard and has stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0044] In the embodiment of the present disclosure, the first epitaxial layer 21 and the second epitaxial layer 22 can each include a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked.

[0045] Exemplarily, in the first epitaxial layer 21, the first semiconductor layer is connected with the first sub-electrode layer of the first electrode 41, and the second semiconductor layer is connected with the first electrode layer of the second electrode 42.

[0046] For example, in the second epitaxial layer 22, the first semiconductor layer is connected to the second sub-electrode layer of the first electrode 41, and the second semiconductor layer is connected to the second electrode layer of the second electrode 42.

[0047] For example, such as Figure 1 As shown, the first epitaxial layer 21 and the second epitaxial layer 22 are circular in shape.

[0048] The circular structure possesses inherent symmetry, allowing current injected into the epitaxial layer to diffuse uniformly along its radial direction. This symmetrical current path avoids excessively high local current density caused by irregular electrode shapes, thereby reducing local overheating and efficiency losses. This ensures more uniform light emission from both epitaxial layers, further enhancing overall luminous efficacy. Furthermore, the smooth, edgeless edges of the circular epitaxial layer effectively reduce light scattering losses during emission.

[0049] In this embodiment of the disclosure, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0050] For example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.

[0051] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0052] Optionally, the multi-quantum-well layer includes alternating InGaN quantum-well layers and GaN quantum-barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0053] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0054] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0055] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0056] For example, the first planarization layer 31 may include at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0057] For example, the first flattening layer 31 may be a distributed Bragg reflection (DBR layer), which comprises multiple periodically alternating layers of SiO2 and TiO2. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0058] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0059] Optionally, the first electrode 41, the second electrode 42, and the third electrode 43 can all be Al layers, Ti layers, Al layers, Ti layers, and Au layers stacked sequentially.

[0060] Figure 3 This is a schematic diagram of another light-emitting diode structure provided in an embodiment of this disclosure. For example... Figure 3 As shown, the light-emitting diode further includes: a second planarization layer 32, a third epitaxial layer 23, and a fourth electrode 44; the second planarization layer 32 is located on the first planarization layer 31 and surrounds the sidewalls of the second electrode 42 and the second epitaxial layer 22; the fourth electrode 44 and the third epitaxial layer 23 are sequentially stacked on the surface of the second epitaxial layer 22 away from the substrate 10; the orthographic projection of the fourth electrode 44 on the substrate 10 is located within the orthographic projection of the third epitaxial layer 23 on the substrate 10.

[0061] like Figure 3 As shown, the surface of the second planarization layer 32 has a second through hole 321 communicating with the first through hole 311, the third electrode 43 is located on the surface of the third epitaxial layer 23 away from the substrate 10, and the third electrode 43 also extends to the substrate 10 in sequence through the second through hole 321 and the first through hole 311.

[0062] In the above implementation, the third epitaxial layer 23 is stacked with the first epitaxial layer 21 and the second epitaxial layer 22 to form a three-level series light-emitting unit. The third electrode 43 spans the three epitaxial layers and is connected to the substrate 10 through the second via 321 and the first via 311, enabling current to drive the three layers to emit light simultaneously, increasing the photon emission to three times and significantly enhancing the optical power density. Furthermore, the second planarization layer 32 surrounds the sidewalls of the second electrode 42 and the third epitaxial layer 23, forming a double-layer insulating barrier with the first planarization layer 31, further isolating the risk of interlayer short circuits and improving device stability; at the same time, it protects the sidewalls to reduce non-radiative recombination and enhance light extraction efficiency. The third electrode 43 is directly connected to the substrate 10 through a vertical path penetrating the second planarization layer 32 and the first planarization layer 31, forming a low-impedance current path, reducing series resistance, resulting in a more uniform current distribution and reducing efficiency decay caused by heat accumulation.

[0063] Compared to two epitaxial layers, three epitaxial layers improve the brightness of light-emitting diodes, meeting the requirements of high-brightness scenarios; in addition, multiple planarization layers can reduce interface defects, delay current leakage and material degradation, and extend device life.

[0064] For example, the diameter of the end of the first through hole 311 near the substrate 10 is larger than the diameter of the end of the second through hole 321 away from the substrate 10. For example, the first through hole 311 and the second through hole 321 together form a tapered hole, and the axial cross-section of the first through hole 311 and the second through hole 321 is trapezoidal.

[0065] The large opening at the bottom of the first through-hole 311 is used to inject external current, which increases the contact area between the third electrode 43 and the external power supply, thus reducing the contact resistance. The narrow opening at the top of the second through-hole 321 allows for more concentrated current injection into the epitaxial layer.

[0066] In this embodiment of the disclosure, the third epitaxial layer 23 and the first epitaxial layer 21 have the same structure. The third epitaxial layer 23 may include a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked sequentially.

[0067] For example, the second planarization layer 32 may include at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0068] Optionally, the fourth electrode 44 may be an Al layer, a Ti layer, an Al layer, a Ti layer and an Au layer stacked sequentially.

[0069] Optionally, such as Figure 3 As shown, the outer contour of the orthographic projection of the first electrode 41 on the substrate 10 coincides with the outer contour of the orthographic projection of the first epitaxial layer 21 on the substrate 10; the outer contour of the orthographic projection of the second electrode 42 on the substrate 10 coincides with the outer contour of the orthographic projection of the first epitaxial layer 21 on the substrate 10; the outer contour of the orthographic projection of the second electrode 42 on the substrate 10 coincides with the outer contour of the orthographic projection of the second epitaxial layer 22 on the substrate 10; the outer contour of the orthographic projection of the fourth electrode 44 on the substrate 10 coincides with the outer contour of the orthographic projection of the second epitaxial layer 22 on the substrate 10; and the outer contour of the orthographic projection of the fourth electrode 44 on the substrate 10 coincides with the outer contour of the orthographic projection of the third epitaxial layer 23 on the substrate 10.

[0070] In the above implementation, the electrodes are completely enclosed within the epitaxial layer. The outer contours of the first electrode 41, the second electrode 42, and the fourth electrode 44 all coincide with the first epitaxial layer 21, forming an embedded electrode structure. This design eliminates the risk of electrode edges protruding from the surface of the epitaxial layer, preventing short circuits between the electrode metal and adjacent layers. At the same time, the sidewalls of the epitaxial layer are completely covered by a planarization layer, further isolating the electrodes from the external environment and improving the electrical safety of the device.

[0071] Meanwhile, all electrodes and epitaxial layers are strictly aligned with their outer contours. Using a uniform outer contour reduces the complexity of the photolithography layout, lowers the risk of alignment errors, and improves mass production yield. The electrodes and epitaxial layer boundaries are perfectly matched to ensure that the current diffuses uniformly along the edge of the epitaxial layer when injected from the electrodes, avoiding local current accumulation or voids caused by contour misalignment and enhancing light emission uniformity. During epitaxial layer growth, the uniform contour design makes the stress distribution of each layer more balanced, reduces lattice defects caused by edge stress concentration, and improves device reliability and lifespan.

[0072] For example, the first electrode 41, the second electrode 42, and the fourth electrode 44 may be hollow structures.

[0073] For example, the first electrode 41, the second electrode 42, and the fourth electrode 44 are all ring structures.

[0074] In particular, after the electrodes are hollowed out, the surface area of ​​the epitaxial layer is reduced, allowing more photons to be emitted directly, reducing metal absorption loss, and significantly improving the overall optical power density.

[0075] For example, the first electrode 41, the second electrode 42, and the fourth electrode 44 can also be layers of transparent conductive material, such as ITO or IZO. Replacing part of the metal electrodes with transparent conductive material can reduce the shading of the light-emitting area by the electrodes, further improving the light extraction efficiency. At the same time, it maintains low contact resistance to ensure uniform current injection.

[0076] Optionally, a thermally conductive material layer may also be provided on the surface of the first electrode 41, the second electrode 42 and the fourth electrode 44.

[0077] For example, the thermally conductive material layer is also a graphene layer. Adding a graphene layer can accelerate heat conduction, reduce operating temperature, delay material aging, and improve device stability and lifespan.

[0078] Optionally, multiple arrayed conical protrusions can be fabricated on the surfaces of the first electrode 41, the second electrode 42, and the fourth electrode 44 using photolithography. This structure can disrupt total internal reflection at the interface between the metal and the epitaxial layer, allowing more photons to be refracted at an oblique angle.

[0079] For example, the height of the conical nanostructure is 100 nm to 500 nm, and the base diameter is 200 nm to 800 nm.

[0080] Optionally, the distance from the wall of the first through hole 311 to the sidewall of the first epitaxial layer 21 is not less than 0.5 μm.

[0081] The lateral over-etching depth is typically 0.3 μm. By ensuring that the distance between the wall of the first via 311 and the sidewall of the first epitaxial layer 21 is greater than 0.5 μm, exceeding the lateral over-etching depth, most process variations can be covered. Even if the over-etching depth reaches 0.3 μm, a safety margin of 0.2 μm is still maintained to prevent short circuits between the via wall and the epitaxial layer sidewall due to process deviations, significantly improving chip yield.

[0082] For example, the distance from the wall of the first through hole 311 to the sidewall of the first epitaxial layer 21 is 0.8 μm.

[0083] Optionally, the distance from the wall of the second through hole 321 to the sidewall of the second epitaxial layer 22 is not less than 0.5 μm.

[0084] The lateral over-etching depth is typically 0.3 μm. By ensuring that the distance between the wall of the second via 321 and the sidewall of the second epitaxial layer 22 is greater than 0.5 μm, exceeding the lateral over-etching depth, most process variations can be covered. Even if the over-etching depth reaches 0.3 μm, a safety margin of 0.2 μm is still maintained to prevent short circuits between the via wall and the epitaxial layer sidewall due to process deviations, significantly improving chip yield.

[0085] Optionally, the overlapping area of ​​the orthographic projections of the first epitaxial layer 21 and the first electrode 41 onto the substrate 10 is not greater than the orthographic projection area of ​​the first epitaxial layer 21.

[0086] For example, the overlapping area of ​​the orthographic projections of the first epitaxial layer 21 and the first electrode 41 on the substrate 10 is no greater than 1 / 5 of the orthographic projection of the first epitaxial layer 21.

[0087] The first electrode 41 is used for current injection. If its projected area is too large, such as exceeding 1 / 5 of the projected area of ​​the epitaxial layer, it will directly block the light emitted by the epitaxial layer, resulting in light energy loss. Limiting the overlap area to within 1 / 5 can minimize the physical obstruction of the light path by the electrode.

[0088] Optionally, the overlapping area of ​​the orthographic projections of the second epitaxial layer 22 and the second electrode 42 onto the substrate 10 is not greater than the orthographic projection area of ​​the second epitaxial layer 22.

[0089] For example, the overlapping area of ​​the orthographic projections of the second epitaxial layer 22 and the second electrode 42 on the substrate 10 is no greater than 1 / 5 of the orthographic projection of the second epitaxial layer 22.

[0090] If the projected area of ​​the second electrode 42 is too large, exceeding 1 / 5 of the projected area of ​​the epitaxial layer, it will directly block the light emitted by the epitaxial layer, resulting in light energy loss. Limiting the overlap area to within 1 / 5 can minimize the physical obstruction of the light path by the electrode.

[0091] Optionally, the overlapping area of ​​the orthographic projections of the third epitaxial layer 23 and the fourth electrode 44 onto the substrate 10 is not greater than the orthographic projection area of ​​the third epitaxial layer 23.

[0092] For example, the overlapping area of ​​the orthographic projections of the third epitaxial layer 23 and the fourth electrode 44 on the substrate 10 is no greater than 1 / 5 of the orthographic projection of the third epitaxial layer 23.

[0093] If the projected area of ​​the fourth electrode 44 is too large, exceeding 1 / 5 of the projected area of ​​the epitaxial layer, it will directly block the light emitted by the epitaxial layer, resulting in light energy loss. Limiting the overlap area to within 1 / 5 can minimize the physical obstruction of the light path by the electrodes.

[0094] Figure 4 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 4 As shown, the preparation method includes:

[0095] S11: Provide a substrate 10.

[0096] S12: A first electrode 41 and a first epitaxial layer 21 are sequentially formed on the substrate 10.

[0097] The orthogonal projection of the first electrode 41 on the substrate 10 is located within the orthogonal projection of the first epitaxial layer 21 on the substrate 10.

[0098] S13: Form a first planarization layer 31 on the substrate 10.

[0099] The first planarization layer 31 surrounds the sidewall of the first electrode 41 and the sidewall of the first epitaxial layer 21, and the surface of the first planarization layer 31 has a first through hole 311 extending to the substrate 10.

[0100] S14: A second electrode 42 and a second epitaxial layer 22 are formed sequentially on the surface of the first epitaxial layer 21 away from the substrate 10.

[0101] The orthogonal projection of the second electrode 42 on the substrate 10 is located within the orthogonal projection of the second epitaxial layer 22 on the substrate 10.

[0102] S15: A third electrode 43 is formed on the first planarization layer 31.

[0103] The third electrode 43 is electrically connected to at least a portion of the second epitaxial layer 22, and the third electrode 43 also extends into the first through hole 311.

[0104] In this fabrication method, the first and second epitaxial layers of the light-emitting diode are stacked on the same substrate and emit the same color, forming a bilayer light-emitting unit. Current flowing through the third and first electrodes simultaneously drives both epitaxial layers, resulting in superimposed photon emissions and achieving double the light output under the same driving current.

[0105] Furthermore, the first epitaxial layer completely covers the first electrode, and the second epitaxial layer completely covers the second electrode, avoiding excessively large light-shielding areas on the electrodes and preventing the first or second electrode from protruding from the epitaxial layer and causing short circuits between the electrodes and other film layers. The first planarization layer surrounds and covers the electrode and the sidewalls of the epitaxial layer, protecting the device from environmental corrosion and preventing short circuits through insulation, ensuring directional current injection into the two epitaxial layers.

[0106] In step S11, the substrate 10 is a sapphire substrate, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0107] As an example, in this embodiment of the disclosure, the substrate 10 is a sapphire substrate. Sapphire substrates are a commonly used substrate 10, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate 10.

[0108] The sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment, the sapphire substrate is baked for 15 minutes.

[0109] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.

[0110] The growth of the first epitaxial layer 21 in step S12 may include: sequentially forming a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer on a sapphire substrate using MOCVD technology.

[0111] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0112] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0113] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.

[0114] Optionally, the multi-quantum-well layer includes alternating InGaN quantum-well layers and GaN quantum-barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0115] When growing multiple quantum well layers, the MOCVD reaction chamber pressure is controlled at 200 torr. When growing InGaN quantum well layers, the reaction chamber temperature is 760℃ to 780℃. When growing GaN quantum barrier layers, the reaction chamber temperature is 860℃ to 890℃.

[0116] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0117] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0118] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0119] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.

[0120] like Figure 5 As shown, the process of fabricating the first electrode 41 on the substrate 10 in step S12 may include: photolithography to define the pattern, electroplating or vapor deposition of a filling metal layer to obtain the first electrode 41.

[0121] For example, the first electrode 41 may be an Al layer, a Ti layer, an Al layer, a Ti layer and an Au layer stacked sequentially.

[0122] like Figure 5 As shown, step S13 may include: depositing a silicon oxide or titanium oxide thin film on the substrate 10 to cover the first epitaxial layer 21 and the first electrode 41, and then forming a first planarization layer 31 that exposes the first epitaxial layer 21 by photolithography etching.

[0123] like Figure 6 As shown, the fabrication of the second electrode 42 in step S14 may include: photolithography to define the pattern, electroplating or vapor deposition of a filling metal layer to obtain the second electrode 42.

[0124] For example, the second electrode 42 may be an Al layer, a Ti layer, an Al layer, a Ti layer and an Au layer stacked sequentially.

[0125] The process of fabricating the second epitaxial layer 22 in step S14 is the same as the process of fabricating the first epitaxial layer 21, and will not be described in detail in this embodiment.

[0126] The following steps may also be included before step S15:

[0127] First step, such as Figure 6 As shown, a second planarization layer 32 is formed on the first planarization layer 31.

[0128] The second planarization layer 32 surrounds the sidewall of the second electrode and the sidewall of the second epitaxial layer, and the surface of the second planarization layer 32 has a second through hole 321 communicating with the first through hole 311.

[0129] Specifically, it may include: depositing a silicon oxide or titanium oxide thin film on the substrate 10 to cover the second epitaxial layer 22 and the second electrode 42, and then forming a second planarization layer 32 that exposes the second epitaxial layer 22 by photolithography and etching.

[0130] The second step, as Figure 6 As shown, a fourth electrode 44 and a third epitaxial layer 23 are sequentially formed on the surface of the second epitaxial layer 22 away from the substrate 10.

[0131] The orthogonal projection of the fourth electrode 44 onto the substrate 10 lies within the orthogonal projection of the third epitaxial layer 23 onto the substrate 10.

[0132] Fabricating the fourth electrode 44 may include: photolithographically defining the pattern, electroplating or vapor-depositing a filling metal layer to obtain the second electrode 42.

[0133] For example, the fourth electrode 44 may be an Al layer, a Ti layer, an Al layer, a Ti layer and an Au layer stacked sequentially.

[0134] The process of fabricating the third epitaxial layer 23 is the same as the process of fabricating the first epitaxial layer 21, and will not be described in detail in this embodiment.

[0135] like Figure 3 As shown, step S15 may include: forming a third electrode 43 on the surface of the third epitaxial layer 23 away from the substrate 10, wherein the third electrode 43 extends to the substrate 10 through the second via 321 and the first via 311 in sequence.

[0136] Specifically, this may include: photolithography to define the pattern, electroplating or vapor deposition of a filling metal layer to obtain the third electrode 43.

[0137] For example, the third electrode 43 may be an Al layer, a Ti layer, an Al layer, a Ti layer and an Au layer stacked sequentially.

[0138] Optionally, the outer contour of the orthographic projection of the first electrode 41 on the substrate 10 coincides with the outer contour of the orthographic projection of the first epitaxial layer 21 on the substrate 10; the outer contour of the orthographic projection of the second electrode 42 on the substrate 10 coincides with the outer contour of the orthographic projection of the first epitaxial layer 21 on the substrate 10; the outer contour of the orthographic projection of the second electrode 42 on the substrate 10 coincides with the outer contour of the orthographic projection of the second epitaxial layer 22 on the substrate 10; the outer contour of the orthographic projection of the fourth electrode 44 on the substrate 10 coincides with the outer contour of the orthographic projection of the second epitaxial layer 22 on the substrate 10; and the outer contour of the orthographic projection of the fourth electrode 44 on the substrate 10 coincides with the outer contour of the orthographic projection of the third epitaxial layer 23 on the substrate 10.

[0139] In the above implementation, the electrodes are completely enclosed within the epitaxial layer. The outer contours of the first electrode 41, the second electrode 42, and the fourth electrode 44 all coincide with the first epitaxial layer 21, forming an embedded electrode structure. This design eliminates the risk of electrode edges protruding from the surface of the epitaxial layer and avoids short circuits between the electrode metal and adjacent layers. Simultaneously, the outer contours of all electrodes and the epitaxial layer are strictly aligned. Using a uniform outer contour reduces the complexity of the photolithography pattern, lowers the risk of alignment errors, and improves mass production yield.

[0140] Figure 7 This is a schematic diagram of another light-emitting diode structure provided in an embodiment of this disclosure. For example... Figure 7 As shown, the light-emitting diode includes a substrate 10, a first electrode 41, a first epitaxial layer 21, a second electrode 42, a second epitaxial layer 22, a fourth electrode 44, a third epitaxial layer 23, and a third electrode 43 stacked sequentially.

[0141] like Figure 7 As shown, the first electrode 41, the first epitaxial layer 21, the second electrode 42, the second epitaxial layer 22, the fourth electrode 44, and the third epitaxial layer 23 are stacked to form a trapezoidal structure.

[0142] The trapezoidal tilted sidewalls can reduce total internal reflection losses between layers. When light travels from a high-refractive-index epitaxial layer to a low-refractive-index medium (such as air), the tilted interface increases the emission critical angle, allowing more photons to escape at a grazing angle, significantly improving optical power density, especially for vertically emitting devices. Furthermore, during epitaxial layer growth, the trapezoidal tilted sidewalls can disperse the stress caused by lattice mismatch, reduce dislocation density, and suppress defect propagation.

[0143] Figure 8 This is a schematic diagram of a display panel provided in an embodiment of this disclosure. For example... Figure 8 As shown, the display panel includes a driving substrate 50 and light-emitting diodes X as described above, with each light-emitting diode X array arranged on the driving substrate 50.

[0144] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes: a substrate (10), a first epitaxial layer (21), a second epitaxial layer (22), a first planarization layer (31), a first electrode (41), a second electrode (42), and a third electrode (43), wherein the first epitaxial layer (21) and the second epitaxial layer (22) emit the same color. The first electrode (41) and the first epitaxial layer (21) are stacked sequentially on the substrate (10). The orthographic projection of the first electrode (41) on the substrate (10) is located within the orthographic projection of the first epitaxial layer (21) on the substrate (10). The first planarization layer (31) is located on the substrate (10) and surrounds and covers the sidewalls of the first electrode (41) and the sidewalls of the first epitaxial layer (21). The second electrode (42) and the second epitaxial layer (22) are sequentially stacked on the surface of the first epitaxial layer (21) away from the substrate (10), and the orthographic projection of the second electrode (42) on the substrate (10) is located within the orthographic projection of the second epitaxial layer (22) on the substrate (10); The surface of the first planarization layer (31) has a first via (311) extending through to the substrate (10), at least a portion of the third electrode (43) is electrically connected to the second epitaxial layer (22), and the third electrode (43) also extends into the first via (311).

2. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode further includes: a second planarization layer (32), a third epitaxial layer (23), and a fourth electrode (44); The second planarization layer (32) is located on the first planarization layer (31) and surrounds the sidewall of the second electrode (42) and the sidewall of the second epitaxial layer (22). The fourth electrode (44) and the third epitaxial layer (23) are stacked sequentially on the surface of the second epitaxial layer (22) away from the substrate (10). The orthographic projection of the fourth electrode (44) on the substrate (10) is located within the orthographic projection of the third epitaxial layer (23) on the substrate (10). The surface of the second planarization layer (32) has a second through hole (321) communicating with the first through hole (311), the third electrode (43) is located on the surface of the third epitaxial layer (23) away from the substrate (10), and the third electrode (43) also extends to the substrate (10) in sequence through the second through hole (321) and the first through hole (311).

3. The light-emitting diode according to claim 2, characterized in that, The outer contour of the orthographic projection of the first electrode (41) on the substrate (10) coincides with the outer contour of the orthographic projection of the first epitaxial layer (21) on the substrate (10); The outer contour of the orthographic projection of the second electrode (42) on the substrate (10) coincides with the outer contour of the orthographic projection of the first epitaxial layer (21) on the substrate (10); The outer contour of the orthographic projection of the second electrode (42) on the substrate (10) coincides with the outer contour of the orthographic projection of the second epitaxial layer (22) on the substrate (10); The outer contour of the orthographic projection of the fourth electrode (44) on the substrate (10) coincides with the outer contour of the orthographic projection of the second epitaxial layer (22) on the substrate (10); The outer contour of the orthographic projection of the fourth electrode (44) on the substrate (10) coincides with the outer contour of the orthographic projection of the third epitaxial layer (23) on the substrate (10).

4. The light-emitting diode according to claim 2, characterized in that, The distance from the wall of the first through hole (311) to the sidewall of the first epitaxial layer (21) is not less than 0.5 μm; The distance from the wall of the second through hole (321) to the sidewall of the second epitaxial layer (22) is not less than 0.5 μm.

5. The light-emitting diode according to any one of claims 2 to 4, characterized in that, The overlapping area of ​​the orthographic projections of the first epitaxial layer (21) and the first electrode (41) on the substrate (10) is not greater than the orthographic projection area of ​​the first epitaxial layer (21); The overlapping area of ​​the orthographic projections of the second epitaxial layer (22) and the second electrode (42) onto the substrate (10) is not greater than the orthographic projection area of ​​the second epitaxial layer (22); The overlapping area of ​​the orthographic projections of the third epitaxial layer (23) and the fourth electrode (44) onto the substrate (10) is not greater than the orthographic projection area of ​​the third epitaxial layer (23).

6. The light-emitting diode according to any one of claims 1 to 4, characterized in that, The first planarization layer (31) includes at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

7. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: Provide a substrate (10); A first electrode (41) and a first epitaxial layer (21) are sequentially formed on the substrate (10), wherein the orthographic projection of the first electrode (41) on the substrate (10) is located within the orthographic projection of the first epitaxial layer (21) on the substrate (10); A first planarization layer (31) is formed on the substrate (10). The first planarization layer (31) surrounds the sidewall of the first electrode (41) and the sidewall of the first epitaxial layer (21). The surface of the first planarization layer (31) has a first through hole (311) extending to the substrate (10). A second electrode (42) and a second epitaxial layer (22) are formed sequentially on the surface of the first epitaxial layer (21) away from the substrate (10), wherein the orthographic projection of the second electrode (42) on the substrate (10) is located within the orthographic projection of the second epitaxial layer (22) on the substrate (10); A third electrode (43) is formed on the first planarization layer (31), at least a portion of the third electrode (43) is electrically connected to the second epitaxial layer (22), and the third electrode (43) also extends into the first via (311).

8. The preparation method according to claim 7, characterized in that, Before forming the third electrode (43) on the first planarization layer (31), the method further includes: A second planarization layer (32) is formed on the first planarization layer (31). The second planarization layer (32) surrounds and covers the sidewall of the second electrode (42) and the sidewall of the second epitaxial layer (22). The surface of the second planarization layer (32) has a second through hole (321) communicating with the first through hole (311). A fourth electrode (44) and a third epitaxial layer (23) are sequentially formed on the surface of the second epitaxial layer (22) away from the substrate (10), wherein the orthographic projection of the fourth electrode (44) on the substrate (10) is located within the orthographic projection of the third epitaxial layer (23) on the substrate (10); Forming a third electrode (43) on the first planarization layer (31) includes: The third electrode (43) is formed on the surface of the third epitaxial layer (23) away from the substrate (10), and the third electrode (43) extends to the substrate (10) through the second via (321) and the first via (311) in sequence.

9. The preparation method according to claim 8, characterized in that, The outer contour of the orthographic projection of the first electrode (41) on the substrate (10) coincides with the outer contour of the orthographic projection of the first epitaxial layer (21) on the substrate (10); the outer contour of the orthographic projection of the second electrode (42) on the substrate (10) coincides with the outer contour of the orthographic projection of the first epitaxial layer (21) on the substrate (10); the outer contour of the orthographic projection of the second electrode (42) on the substrate (10) coincides with the outer contour of the orthographic projection of the second epitaxial layer (22) on the substrate (10); the outer contour of the orthographic projection of the fourth electrode (44) on the substrate (10) coincides with the outer contour of the orthographic projection of the second epitaxial layer (22) on the substrate (10); the outer contour of the orthographic projection of the fourth electrode (44) on the substrate (10) coincides with the outer contour of the orthographic projection of the third epitaxial layer (23) on the substrate (10).

10. A display panel, characterized in that, The display panel includes a driving substrate (50) and light-emitting diodes as described in any one of claims 1 to 6, wherein each of the light-emitting diode arrays is arranged on the driving substrate (50).

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