Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. A semiconductor package may include a package substrate and a first package component over the package substrate. The first package assembly may include a first semiconductor die and a heat dissipation substrate over the first semiconductor die. The heat dissipation substrate may include a base portion and a first coated portion on a first surface of the base portion. The first coated portion may be between the first semiconductor die and the base portion. The base portion may include a first material having a first thermal conductivity, and the first coated portion may include a second material different from the first material. The second material may have a second thermal conductivity less than the first thermal conductivity.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to semiconductor packages and methods of manufacturing the same. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to the improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, the improvement in integration density is due to iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. As the demand for smaller electronic devices increases, there is a need for smaller and more creative packaging technologies for semiconductor dies. An example of such a packaging system is a package-on-package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and small footprint on a printed circuit board (PCB). SUMMARY

[0003] Some embodiments of the present disclosure provide a semiconductor package comprising: a package substrate; and a first package component located above the package substrate, the first package component comprising: a first semiconductor die; and a heat spreading substrate located above the first semiconductor die, the heat spreading substrate comprising: a base portion, wherein the base portion comprises a first material having a first thermal conductivity; and a first coating portion located on a first surface of the base portion, wherein the first coating portion is located between the first semiconductor die and the base portion, wherein the first coating portion comprises a second material different from the first material, and wherein the second material has a second thermal conductivity less than the first thermal conductivity.

[0004] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor package, the method comprising: forming a carrier substrate, forming the carrier substrate comprising: depositing a coating portion on a base portion, wherein the coating portion and the base portion comprise different materials, and wherein the base portion has a higher thermal conductivity than the coating portion; and planarizing a first surface of the coating portion; bonding the carrier substrate above a first semiconductor die, wherein the first surface of the coating portion faces the first semiconductor die; and attaching a lid to the carrier substrate, wherein the carrier substrate is located between the first semiconductor die and the lid.

[0005] Yet another embodiment of the present disclosure provides a method of manufacturing a semiconductor package, the method comprising: depositing a first coating portion on a first surface of a base portion to form a carrier substrate, wherein the base portion comprises a first material having a first thermal conductivity greater than 170 W / mK; bonding the carrier substrate over a first semiconductor die, wherein the first surface of the first coating portion faces the first semiconductor die; and bonding the first semiconductor die over a package substrate, wherein the first semiconductor die is electrically connected to the package substrate. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various components were not necessarily drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 and Figure 2A Cross-sectional views showing intermediate steps during the manufacture of a carrier substrate according to some embodiments are shown.

[0008] Figure 2B Cross-sectional views showing a carrier substrate according to some embodiments are shown.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15A Cross-sectional views showing intermediate steps during the manufacture of a semiconductor package using a carrier substrate according to some embodiments are shown.

[0010] Figure 15B Cross-sectional views showing a semiconductor package according to some embodiments are shown.

[0011] Figure 16 , Figure 17 , Figure 18 and Figure 19 Cross-sectional views showing intermediate steps during the manufacture of a semiconductor package using a carrier substrate according to some embodiments are shown. DETAILED DESCRIPTION

[0012] The following disclosure provides a number of different embodiments or examples for implementing different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, the formation of a first component over or on a second component can include embodiments where the first component and second component are formed directly on one another, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component are not directly in contact. Additionally, the present disclosure can refer to reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatial or directional terms, such as "below", "under", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as drawn in the figures. The spatial and directional terms should be interpreted in view of the orientation of a device as shown in the figures and as can be understood by a person of ordinary skill in the art. The device can be positioned in other ways (rotated 90 degrees or at other orientations) and the spatial or directional descriptors used herein should be interpreted accordingly.

[0014] Semiconductor packages and methods of forming the same are provided. According to some embodiments, a semiconductor package can include a semiconductor die that can generate heat during operation of the semiconductor package. The semiconductor die can be bonded over a package substrate, and a lid can be attached to the package substrate. A carrier substrate can be disposed between the lid and the semiconductor die. Because the carrier substrate includes a material having a high thermal conductivity, and has a low roughness on its top and bottom surfaces, heat generated by the semiconductor die can be more effectively transferred to the carrier substrate, and then to the lid, where the heat can be dissipated away. As a result, performance and reliability of the semiconductor package can be improved.

[0015] Figure 1 and Figure 2A Cross-sectional views showing intermediate steps during fabrication of a carrier substrate according to some embodiments are shown. In Figure 1In some embodiments, a wafer 312 is provided. The material of the wafer 312 can be polycrystalline and have a first thermal conductivity greater than about 170 W / mK, which can be a high thermal conductivity having advantages as described in more detail below. In some embodiments, the wafer 312 includes a semiconductor material, such as silicon carbide or the like, and the first thermal conductivity is in a range of about 230 W / mK to about 500 W / mK. In some embodiments, the wafer 312 includes a dielectric material, such as aluminum nitride or the like, and the first thermal conductivity is in a range of about 170 W / mK to about 250 W / mK. The wafer 312 can be formed by a suitable process, such as chemical vapor deposition (CVD), sintering, or the like. The wafer 312 can have a thickness Tl in a range of about 620 pm to about 800 pm. The surfaces of the wafer 312 (including the top and bottom surfaces) can have a first roughness (e.g., average roughness (Ra)) in a range of about 0.3 nm to about 30 nm. The wafer 312 can have a diameter of about 12 inches.

[0016] In some embodiments, a coating 313 is formed on the surfaces of the wafer 312 and planarized (e.g., polished) the bottom surface (downward-facing surface) of the coating 313. The top surface (upward-facing surface) of the coating 313 can be planarized in a subsequent process, as described in more detail later, such as in Figure 2A In some embodiments, a coating 313 is formed on the surfaces of the wafer 312 and planarized (e.g., polished) the bottom surface (downward-facing surface) of the coating 313. The top surface (upward-facing surface) of the coating 313 can be planarized in a subsequent process, as described in more detail later, such as in Figure 2A In some embodiments, a coating 313 is formed on the surfaces of the wafer 312 and planarized (e.g., polished) the bottom surface (downward-facing surface) of the coating 313. The top surface (upward-facing surface) of the coating 313 can be planarized in a subsequent process, as described in more detail later, such as in Figure 2A In some embodiments, a coating 313 is formed on the surfaces of the wafer 312 and planarized (e.g., polished) the bottom surface (downward-facing surface) of the coating 313. The top surface (upward-facing surface) of the coating 313 can be planarized in a subsequent process, as described in more detail later, such as in Figure 13 In some embodiments, a coating 313 is formed on the surfaces of the wafer 312 and planarized (e.g., polished) the bottom surface (downward-facing surface) of the coating 313. The top surface (upward-facing surface) of the coating 313 can be planarized in a subsequent process, as described in more detail later, such as in

[0017] The bottom surface of the coating 313 can be planarized by a chemical mechanical polishing (CMP) process or the like. After the planarization process, the bottom surface of the coating 313 can have a second roughness (e.g., average roughness (Ra)) of less than about 0.3 nm, and a bottom portion of the coating 313 adjacent to the bottom surface can have a thickness T2 in a range of about 1 nm to about 1 um. The second roughness can be less than the first roughness, and the thickness T2 can be less than the thickness Tl. A ratio of the thickness T2 to the thickness Tl can be less than 0.0002. The wafer 312 and the coating 313 can be collectively referred to as a second carrier substrate 315, where the wafer 312 can be referred to as a base portion of the second carrier substrate 315, and the coating 313 can be referred to as a coated portion of the second carrier substrate 315.

[0018] The second carrier substrate 315 can be used to fabricate a semiconductor package in which the second carrier substrate 315 can be bonded to a structure including heat-generating devices, as described in more detail below. Because the bottom surface of the coating 313 has a low roughness as described above, the bonding between the second carrier substrate 315 and the structure can be more effective. When the bottom surface of the coating 313 has a surface roughness of less than 0.3 nm, an improved bonding strength can be achieved between the second carrier substrate 315 and the structure. Due to the high thermal conductivity (e.g., greater than 170 W / mK) of the wafer 312 material as described above, and the improved bonding strength between the second carrier substrate 315 and the structure, the second carrier substrate 315 can more effectively dissipate heat generated in the structure, as described in more detail below. Because the second thermal conductivity of the coating 313 material can be less than the first thermal conductivity of the wafer 312 material, the smaller ratio of the thickness T2 to the thickness Tl (e.g., less than 0.0002) can improve the heat dissipation capability of the second carrier substrate 315.

[0019] Figure 2B A second carrier substrate 315 according to some alternative embodiments is shown, similar to the embodiment of the second carrier substrate 315 shown in FIG. 1, where like reference numbers indicate like parts formed of like materials and by like processes. In this embodiment, a coating 313 is selectively formed on a bottom surface of a wafer 312 by a suitable process, such as CVD, PECVD, or the like, while other surfaces of the wafer 312 remain exposed after the coating 313 is formed. Figure 2A In this embodiment, the bottom surface of the wafer 312 faces downward, and the bottom surface of the coating 313 faces upward. The wafer 312 can be referred to as a base portion of the second carrier substrate 315, and the coating 313 can be referred to as a coated portion of the second carrier substrate 315. Figure 2B In this embodiment, the coating 313 is selectively formed on the bottom surface of the wafer 312 (downward-facing surface in FIG. 1) by a suitable process, such as CVD, PECVD, or the like, while other surfaces of the wafer 312 remain exposed after the coating 313 is formed. Figure 2B In this embodiment, the bottom surface of the wafer 312 faces downward, and the bottom surface of the coating 313 faces upward. The wafer 312 can be referred to as a base portion of the second carrier substrate 315, and the coating 313 can be referred to as a coated portion of the second carrier substrate 315. Figure 2Bdownward-facing surface), and the bottom surface of the coating 313 can have a second roughness that is less than the first roughness. The top surface of the wafer 312 can be planarized (e.g., to have a flat top surface) in a subsequent process. Figure 2B upward-facing surface), and later, such as in a subsequent process, Figure 18 will be described in more detail.

[0020] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15A shows cross-sectional views of intermediate steps during fabrication of a semiconductor package using a carrier substrate, according to some embodiments. Reference is made to Figure 3 , a bottom semiconductor die 100 is attached to a first carrier substrate 119. The bottom semiconductor die 100 can be a bare semiconductor die (e.g., an un-packaged semiconductor die) that is formed as part of a larger wafer. For example, the bottom semiconductor die 100 can be a logic die (e.g., an application processor (AP), a central processing unit (CPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide I / O) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), a biomedical die, etc. The bottom semiconductor die 100 can be a package that includes one or more bare semiconductor dies.

[0021] The bottom semiconductor die 100 can be processed according to applicable manufacturing processes to form an integrated circuit within it. The bottom semiconductor die 100 can be formed together with other semiconductor dies as a portion of a larger wafer, and subsequently diced from the wafer to form the bottom semiconductor die 100. The bottom semiconductor die 100 may include a substrate 102, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 102 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used.

[0022] Electronic devices 104 (i.e., active and / or passive devices), such as transistors, diodes, capacitors, resistors, etc., may be formed within and / or on substrate 102. Electronic devices 104 may generate relatively high levels of heat during operation, creating hot spots. Electronic devices 104 may be interconnected via interconnect structures 106, which include metallization patterns 108 located in one or more dielectric layers 109 on substrate 102. Interconnect structures 106 electrically connect electronic devices 104 on substrate 102 to form one or more integrated circuits. Metallization patterns 108 may include conductive materials such as copper, aluminum, etc. One or more dielectric layers 109 may include low-k dielectric materials such as silicon oxide, etc. A sealing ring 107 may be formed in interconnect structures 106 and may extend through one or more dielectric layers 109 of interconnect structures 106. In a top view, sealing ring 107 may surround electronic devices 104. In some embodiments, sealing ring 107 is formed of the same material as metallization patterns 108.

[0023] The bottom semiconductor die 100 may also include a through-hole 105, which can be electrically connected to the metallization pattern 108 in the interconnect structure 106. The through-hole 105 may include a conductive material, such as copper, aluminum, etc., and may extend from the interconnect structure 106 into the substrate 102. One or more insulating barrier layers (not shown) may be formed around at least a portion of the through-hole 105 in the substrate 102. In a subsequent processing step, the substrate 102 may be thinned to expose the through-hole 105. After the through-hole 105 is exposed, it can provide an electrical connection from the back side of the substrate 102 to the front side of the substrate 102. In some embodiments, the back side of the substrate 102 may refer to the side of the substrate 102 opposite to the electronics 104 and the interconnect structure 106, while the front side of the substrate 102 may refer to the side of the substrate 102 on which the electronics 104 and the interconnect structure 106 are disposed.

[0024] The bottom semiconductor die 100 may further include one or more passivation layers 110 located on the interconnect structure 106 and conductive vias 112 extending through the one or more passivation layers 110. The conductive vias 112 may be electrically connected to the metallization pattern 108. The one or more passivation layers 110 may include a dielectric material, such as silicon nitride, silicon oxycarbide, etc. The conductive vias 112 may include a conductive material, such as copper, aluminum, etc. A dielectric layer 114 is disposed on the one or more passivation layers 110, and contact pads 116 are embedded in the dielectric layer 114. The contact pads 116 may be electrically connected to the conductive vias 112. In subsequent processing steps, openings may be formed in the dielectric layer 114 to expose the contact pads 116. After exposing the contact pads 116, the contact pads 116 provide electrical connections to the electronic device 104 and the interconnect structure 106. The dielectric layer 114 may include a dielectric material, such as silicon oxide, silicon nitride, etc. The contact pads 116 may include conductive materials such as copper or aluminum. A dielectric layer 118 is disposed on the dielectric layer 114. The dielectric layer 118 may include dielectric materials such as silicon oxide or silicon oxynitride.

[0025] The first carrier substrate 119 can be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The first carrier substrate 119 can be a wafer with a similar size to the second carrier substrate 315. Figure 3 An example is shown of a bottom semiconductor die 100 bonded to a first carrier substrate 119. Two or more bottom semiconductor dies 100 may be bonded to the first carrier substrate 119 and processed together during subsequent manufacturing steps until they are diced into individual semiconductor packages. A bonding layer 120 may be disposed on the first carrier substrate 119. In some embodiments, the bonding layer 120 includes a first bonding layer 121 on the first carrier substrate 119 and a second bonding layer 123 on the first bonding layer 121. The first bonding layer 121 may include a dielectric material, such as silicon oxynitride, and the second bonding layer 123 may include a dielectric material, such as silicon oxide.

[0026] The bottom semiconductor die 100 can be attached to the first carrier substrate 119 by bonding a dielectric layer 118 and a bonding layer 120. The bonding process may include pre-bonding and annealing. During pre-bonding, a small pressure may be applied to press the bottom semiconductor die 100 against the bonding layer 120. Pre-bonding may be performed at a low temperature (such as room temperature), and after pre-bonding, the dielectric layer 118 is bonded to the bonding layer 120. The dielectric layer 118 and the bonding layer 120 may then be annealed in a subsequent annealing step to improve the bond strength. After annealing, dielectric-to-dielectric bonds, such as covalent bonds, may be formed to bond the dielectric layer 118 to the bonding layer 120.

[0027] exist Figure 4 In this process, a bottom sealant 125 is formed over a first carrier substrate 119, and the substrate 102 and the bottom sealant 125 are thinned to expose the through-hole 105. The bottom sealant 125 may extend along the sidewall of the bottom semiconductor die 100 and surround the bottom semiconductor die 100 in a top view. In some embodiments, the bottom sealant 125 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, undoped silicate glass (USG), etc., and may be formed using suitable deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. In some embodiments, the bottom sealant 125 may include molding compound, epoxy resin, resin, etc., and may be formed by applying processes such as compression molding or transfer molding before curing.

[0028] The substrate 102 is thinned to expose the through-hole 105. A portion of the bottom sealant 125 may also be removed by the thinning process. The thinning process may be a chemical mechanical polishing (CMP) process, a grinding process, an etch-back process, or a combination thereof. In some embodiments, the substrate 102 is further recessed to expose the sidewalls of the through-hole 105. The recessing process may be a selective etching process, such as dry etching, wet etching, or a combination thereof. After the recessing process, the through-hole 105 may protrude from the back side of the substrate 102.

[0029] exist Figure 5 In this process, a bonding layer 126 is formed over a substrate 102, a bottom sealant 125, and a through-hole 105, and bonding pads 128 are formed in the bonding layer 126. The bonding layer 126 can be used to bond to another device in subsequent processes. The bonding layer 126 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, silicon carbon oxynitride, USG, etc., and can be formed using suitable deposition processes (such as CVD, PVD, ALD, etc.).

[0030] Bonding pads 128 are formed in bonding layer 126 using techniques such as damascene or dual damascene processes. Bonding pads 128 can be embedded in bonding layer 126, with their top surfaces exposed and their sidewalls and bottom surfaces in contact with bonding layer 126. Some bonding pads 128 can be electrically connected to vias 105 and can be electrically connected to electronic devices 104 of the underlying semiconductor die 100 through vias 105. Thus, bonding pads 128 can provide external devices with access to electronic devices 104. Some bonding pads 128 can be dummy bonding pads and can be electrically isolated from the circuitry of the underlying semiconductor die 100.

[0031] As an example of forming bonding pad 128, an opening can be formed in bonding layer 126, and the opening can expose the underlying through-hole 105. Forming the opening may include forming a patterned mask, such as photoresist or one or more layers of dielectric material, over bonding layer 126, and performing a selective etching process, such as wet etching or dry etching, to remove the exposed portion of bonding layer 126 and expose the top surface of through-hole 105. After the etching process, the patterned mask can be removed. Bonding pad 128 can be formed in the opening. Bonding pad 128 may include a conductive material, such as copper, aluminum, etc., and can be formed by electrochemical plating, chemical plating, CVD, ALD, PVD, etc., or combinations thereof. Planarization processes, such as CMP, can be performed to remove excess conductive material. Thus, the top surfaces of bonding layer 126 and bonding pad 128 can be substantially coplanar or flush.

[0032] exist Figure 6 In the middle, the top semiconductor die 200 is bonded to the bonding layer 126 and the bonding pad 128, and two dummy dies 300 are bonded to the bonding layer 126. Figure 6 The diagram illustrates a top semiconductor die 200 and two dummy dies 300 bonded above a bottom semiconductor die 100 as an example. In some embodiments, other numbers of top semiconductor dies 200 and dummy dies 300 may be bonded above the bottom semiconductor die 100. The top semiconductor die 200 may be a bare semiconductor die (e.g., an unpackaged semiconductor die) formed as a portion of a larger wafer, or formed as a package including one or more bare semiconductor dies, similar to the bottom semiconductor die 100. The top semiconductor die 200 may be processed according to applicable manufacturing processes to form an integrated circuit in the top semiconductor die 200. The materials and manufacturing processes of components in the top semiconductor die 200 can be found by referring to similar components in the bottom semiconductor die 100, wherein similar components in the bottom semiconductor die 100 with reference numbers beginning with the number "1" correspond to components in the top semiconductor die 200 with reference numbers beginning with the number "2".

[0033] The top semiconductor die 200 includes a substrate 202 and electronic devices 204 (i.e., active and / or passive devices) such as transistors, diodes, capacitors, resistors, etc. formed in and / or on the substrate 202. The electronic devices 204 can generate relatively high levels of heat during operation, creating hot spots. An interconnect structure 206 is located on the substrate 202. The interconnect structure 206 can include metallization patterns 208 located in one or more dielectric layers 209 and electrically connect the electronic devices 204 on the substrate 202 to form one or more integrated circuits. A seal ring 207 can extend through one or more of the dielectric layers 209 of the interconnect structure 206 and, in a top view, encircle the electronic devices 204. In some embodiments, a backside of the substrate 202 can refer to a side of the substrate 202 opposite the electronic devices 204 and the interconnect structure 206, while a front side of the substrate 202 can refer to a side of the substrate 202 on which the electronic devices 204 and the interconnect structure 206 are disposed.

[0034] The top semiconductor die 200 can also include one or more passivation layers 210 located on the interconnect structure 206 and conductive vias 212 extending through the one or more passivation layers 210. The conductive vias 212 can be electrically connected with the metallization patterns 208. A dielectric layer 214 is located on the one or more passivation layers 210 and contact pads 216 are embedded in the dielectric layer 214. The contact pads 216 can be electrically connected with the conductive vias 212. A dielectric layer 218 is located on the dielectric layer 214 and conductive vias 220 extend through the dielectric layer 218 and into the dielectric layer 214. The conductive vias 212 can be electrically connected with the contact pads 216. The conductive vias 220 can include the same or similar materials as the conductive vias 212.

[0035] The bonding layer 222 is located on the dielectric layer 218, and the bonding pads 224 extend through the bonding layer 222. Some of the bonding pads 224 can be electrically connected to the conductive vias 220, and can be electrically connected to the electronic devices 204 of the top semiconductor die 200. As such, the bonding pads 224 can provide external devices with access to the electronic devices 204. Some of the bonding pads 224 can be dummy bonding pads, and can be electrically isolated from the circuitry of the top semiconductor die 200. The bottom surfaces of the bonding layer 222 and the bonding pads 224 can be substantially coplanar or flush. The bonding layer 222 can be formed of the same or similar material as the bonding layer 126, and by the same or similar method as the bonding layer 126. The bonding pads 224 can be formed of the same or similar material as the bonding pads 128, and by the same or similar method as the bonding pads 128. The materials of the bonding layer 126 and the bonding layer 222 can be selected such that a dielectric-to-dielectric bond can be formed between the bonding layer 126 and the bonding layer 222, and the materials of the bonding pads 128 and the bonding pads 224 can be selected such that a metal-to-metal bond can be formed between the bonding pads 128 and the bonding pads 224, as discussed below.

[0036] The top semiconductor die 200 can be bonded to the bonding layer 126 and the bonding pads 128 on the bottom semiconductor die 100 using a bonding process, where the bonding layer 222 of the top semiconductor die 200 can be directly bonded to the bonding layer 126 on the bottom semiconductor die 100, and the bonding pads 224 of the top semiconductor die 200 can be directly bonded to the bonding pads 128 on the bottom semiconductor die 100. The top semiconductor die 200 can be disposed facing down such that the front side of the substrate 202 faces the back side of the substrate 102, which can be referred to as a front-to-back package configuration. In some embodiments, the bond between the bonding layer 222 and the bonding layer 126 is a dielectric-to-dielectric bond, or the like, and the bond between the bonding pads 224 and the bonding pads 128 is a metal-to-metal bond. As such, the bottom semiconductor die 100 and the top semiconductor die 200 can be electrically connected.

[0037] As an example, the bonding process can begin with surface treatment of the bonding layer 126 and the bonding layer 222. The surface treatment can include plasma treatment in a vacuum environment. The surface treatment can also include a cleaning process, such as rinsing with deionized water, etc. The bonding process can then proceed to align the bonding pads 224 with the bonding pads 128, such that the bonding pads 224 overlap the corresponding bonding pads 128. Next, the top semiconductor die 200 is brought into contact with the bonding layer 126 and the bonding pads 128 at room temperature (e.g., between about 21 °C and about 25 °C). A small pressure can be applied to press the top semiconductor die 200 against the bottom semiconductor die 100. The bonding process can continue with an anneal, such that the metal in the bonding pads 224 and the metal in the bonding pads 128 interdiffuse across the interface between the bonding pads 224 and the bonding pads 128, which forms a metal-to-metal bond, and the materials of the bonding layer 126 and the bonding layer 222 react to form a dielectric-to-dielectric bond.

[0038] Each dummy die 300 can include a substrate 302 and a dielectric layer 308 on the substrate 302. The dielectric layer 308 can be a bonding layer that can bond the dummy die 300 to the bonding layer 126. During the bonding process, the dielectric layer 308 of each dummy die 300 can be bonded to the bonding layer 126 by a dielectric-to-dielectric bond, similar to the bond between the bonding layer 222 and the bonding layer 126. After the bonding process, the side of the substrate 302 facing the bonding layer 126 can be referred to as the front side of the substrate 302, and the side of the substrate 302 opposite the front side of the substrate 302 can be referred to as the back side of the substrate 302. The substrate 302 can include the same or similar material as the substrate 102. The dielectric layer 308 can include silicon oxide, silicon oxynitride, silicon oxycarbide, etc.

[0039] The manufacturing process described above corresponds to a front-to-back package configuration between the top semiconductor die 200 and the bottom semiconductor die 100 as an example. In the front-to-back package configuration, the top semiconductor die 200 and the bottom semiconductor die 100 are oriented such that the front side of the substrate 202 of the top semiconductor die 200 faces the back side of the substrate 102 of the bottom semiconductor die 100. Other bonding configurations, such as a front-to-front package configuration, can also be considered. In the front-to-front package configuration, the top semiconductor die 200 and the bottom semiconductor die 100 are oriented such that the front side of the substrate 202 of the top semiconductor die 200 faces the front side of the substrate 102 of the bottom semiconductor die 100.

[0040] In Figure 7In this configuration, a top sealant 310 is formed over the remainder of the bonding layer 126, and a dielectric layer 316 is formed on the top sealant 310, the top semiconductor die 200, and the dummy die 300. The top sealant 310 may extend along the sidewalls of the top semiconductor die 200 and the dummy die 300, and in a top view, the top sealant 310 surrounds the top semiconductor die 200 and the dummy die 300. The top sealant 310 may be formed of the same or similar material as the bottom sealant 125, and may be formed by the same or similar methods as the bottom sealant 125. A thinning process may be applied to expose the substrates 202 and 302. The thinning process may include performing CMP processes, polishing processes, etch-back processes, combinations thereof, etc. Thus, the back side of the substrate 202, the back side of the substrate 302, and the top surface of the top sealant 310 may be substantially coplanar or flush. The dielectric layer 316 may be formed of the same or similar material as the bonding layer 126, and may be formed by the same or similar methods as the bonding layer 126. The dielectric layer 316 may serve as a bonding layer in subsequent processes.

[0041] exist Figure 8 In the middle, the first carrier substrate 119 (e.g. Figure 7 The structure above the first carrier substrate 119 is bonded to the second carrier substrate 315, and the first carrier substrate 119 and bonding layer 120 are removed. Prior to the bonding process, a bonding layer 314 can be formed on the bottom surface of the second carrier substrate 315. The bonding layer 314 can be formed of the same or similar material as the bonding layer 126 and can be formed by the same or similar methods as the bonding layer 126. The dielectric layer 316 and the bonding layer 314 can be bonded using the same or similar process as that used to bond the bonding layers 126 and 222 to bond the structure above the first carrier substrate 119 to the second carrier substrate 315. Because the bottom surface of the second carrier substrate 315 has the low roughness described above, the bottom surface of the bonding layer 314 facing the dielectric layer 316 can also have low roughness. This improves the bonding strength between the dielectric layer 316 and the bonding layer 314. The first carrier substrate 119 and the bonding layer 120 can be removed by a thinning process. The thinning process can be a CMP process, a polishing process, an etch-back process, a combination thereof, etc. After the thinning process, the bottom surfaces of the dielectric layer 118 and the bottom sealant 125 can be substantially coplanar or flush.

[0042] exist Figure 9In this case, the opening is formed through the dielectric layer 118 and the dielectric layer 114 to expose the contact pad 116, and the protective layer 318 is formed on the dielectric layer 118 and the bottom surface of the bottom encapsulant 125. Further, an under bump metallization layer (UBM) 320 is formed in the opening, and electrical connections 322 are formed on the UBM 320. The opening can be formed by the same or similar method as the opening in which the bond pad 128 is formed. The opening can expose the contact pad 116 as well as the sidewalls of the dielectric layer 118 and the dielectric layer 114. The protective layer 318 can be formed of an insulating material such as polyimide, and the protective layer 318 can be formed by a coating method such as spin coating. The protective layer 318 can cover the exposed portion of the contact pad 116, and the sidewalls of the dielectric layer 118 and the dielectric layer 114, as well as the dielectric layer 118 and the bottom surface of the bottom encapsulant 125. Then, the portion of the protective layer 318 covering the exposed portion of the contact pad 116 can be removed to re-expose the contact pad 116.

[0043] The UBM 320 has a bump portion on and extending along the surface of the protective layer 318, and a via portion extending through the opening to connect to the contact pad 116. In this way, the UBM 320 is electrically connected to the bottom semiconductor die 100. As an example of forming the UBM 320, a seed layer can be formed on the protective layer 318 and the exposed portion of the contact pad 116. The seed layer can be a metal layer, which can be a single layer, or a composite layer including multiple sub-layers formed of different materials, formed using a deposition process such as PVD. Then, a photoresist can be formed on the seed layer and patterned. The pattern of the photoresist can have an opening through the photoresist to expose the seed layer, and the pattern of the photoresist can correspond to the UBM 320. A conductive material can be formed in the opening of the photoresist and on the exposed portion of the seed layer by plating such as electroless plating, electroplating, or the like. The conductive material can include a metal or a metal alloy such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed can be removed by an acceptable ashing or stripping process such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer can be removed by using an acceptable etching process such as wet etching or dry etching. The conductive material and the remaining portion of the seed layer can be collectively referred to as the UBM 320.

[0044] Electrical connections 322 are formed on the UBM 320. The UBM 320 and the electrical connections 322 can be used to provide input / output connections to external electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc. The electrical connections 322 can be ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, etc. The electrical connections 322 can include electrically conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the electrical connections 322 can be formed by first forming a layer of solder via evaporation, electroplating, printing, solder transfer, ball placement, etc., and then reflowing the layer of solder to shape the material into the desired bump shape. In some embodiments, the electrical connections 322 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The electrical connections 322 can be formed on the UBM 320 prior to the formation of the coating 313. In some embodiments, the electrical connections 322 are formed on the UBM 320 after the formation of the coating 313. In some embodiments, the electrical connections 322 are formed on the UBM 320 after the formation of the coating 313 and prior to the singulation of the wafer structure 400’. Figure 9 The structure shown is referred to as a wafer structure 400’.

[0045] In Figure 10 the wafer structure 400’ is singulated into individual semiconductor package assemblies 400. The wafer structure 400’ can be placed on a tape 324 supported by a frame 326. The wafer structure 400’ can then be singulated along the scribe lines 328, thereby separating the wafer structure 400’ into individual semiconductor package assemblies 400. The singulation process can include a sawing process, a laser cutting process, etc. A cleaning process or a rinsing process can be performed after the singulation process. Each semiconductor package assembly 400 can then be removed from the tape 324, as shown. Figure 11 In the semiconductor package assembly 400, the singulated second carrier substrate 315 can include a singulated wafer 312 (hereinafter referred to as a base portion 312) and a singulated coating 313. The singulated coating 313 can include a first coated portion 313 on a top surface (facing upward in Figure 11 the base portion 312 and a second coated portion 313 on a bottom surface (facing downward in Figure 11 the base portion 312. The sidewalls of the base portion 312 can be exposed.

[0046] In Figure 12In some embodiments, semiconductor package assembly 400 is bonded to semiconductor package assembly 600, and underfill 614 is formed between semiconductor package assembly 400 and semiconductor package assembly 600. In addition, semiconductor package assembly 500 is bonded to semiconductor package assembly 600, and underfill 616 is formed between semiconductor package assembly 500 and semiconductor package assembly 600. Semiconductor package assembly 600 can include a substrate 602, one or more dielectric layers 604 on a first side of substrate 602, conductive features 606 in dielectric layers 604, and conductive features 610 on a second side of substrate 602. Conductive features 606 can include wires, conductive vias, and conductive pads. Substrate vias 608 can extend through substrate 602 and can interconnect conductive features 606 to conductive features 610. Electrical connections 612 can be on conductive features 610. Semiconductor package assembly 600 can be referred to as a middle layer.

[0047] During a bonding process between semiconductor package assembly 400 and semiconductor package assembly 600, electrical connections 322 can be reflowed to bond semiconductor package assembly 400 to conductive features 606. Electrical connections 322 can electrically connect semiconductor package assembly 600 to semiconductor package assembly 400. Underfill 614 can surround electrical connections 322 and protect the joints resulting from the reflow soldering of electrical connections 322. In a top view, underfill 614 can encircle semiconductor package assembly 400. Underfill 614 can be formed from a mold compound, an epoxy, or the like, and can be formed by a capillary flow process after bonding semiconductor package assembly 400. Underfill 614 can then be cured.

[0048] Semiconductor package assembly 500 can include one or more integrated circuit dies in an active region 502 of semiconductor package assembly 500. In some embodiments, active region 502 includes a stack of interconnected memory dies, and semiconductor package assembly 500 can be referred to as a high bandwidth memory (HBM) device. One or more dielectric layers 504 can be on a first side of active region 502, and conductive features 506 can be in and on dielectric layers 504. Conductive features 506 can include wires, conductive vias, and conductive pads. Electrical connections 508 can be on conductive features 506.

[0049] During a bonding process between semiconductor package assembly 500 and semiconductor package assembly 600, electrical connections 508 can be reflowed to bond semiconductor package assembly 500 to conductive features 606. Electrical connections 508 can electrically connect semiconductor package assembly 600 to semiconductor package assembly 500. Underfill 616 can surround electrical connections 508 and protect joints resulting from reflow of electrical connections 508. In a top view, underfill 616 can encircle semiconductor package assembly 500. Underfill 616 can be formed of the same or similar material as underfill 614 and can be formed by the same or similar process as underfill 614.

[0050] In Figure 13 sealant 618 is formed over semiconductor package assembly 600. Electrical connections 508 can be reflowed to bond semiconductor package assembly 600 to semiconductor package assembly 400. In a top view, underfill 616 can encircle semiconductor package assembly 400. Underfill 616 can be formed of the same or similar material as underfill 614 and can be formed by the same or similar process as underfill 614. Figure 13 The structure shown in FIG. 6B is referred to as semiconductor package assembly 650. Sealant 618 can extend along sidewalls of semiconductor package assembly 400 and semiconductor package assembly 500, and in a top view, sealant 618 can encircle semiconductor package assembly 400 and semiconductor package assembly 500. Sealant 618 can be formed of the same or similar material as underfill 125 and can be formed by the same or similar method as underfill 125. A planarization process can be applied to expose second carrier substrate 315 and active region 502. The planarization process can be CMP, lapping, or the like. After the planarization process, the top surface of second carrier substrate 315, active region 502, and the top surface of sealant 618 can be substantially coplanar or flush.

[0051] As a result of the planarization process, the top surface of first coated portion 313 of second carrier substrate 315 (e.g., the top surface of second carrier substrate 315) can have a third roughness (e.g., average roughness (Ra)) of less than about 10 nm. The third roughness can be less than the first roughness of the surface of base portion 312 and greater than or equal to the second roughness of the bottom surface of second coated portion 313 (e.g., the bottom surface of second carrier substrate 315). Second carrier substrate 315 can be attached to a lid, as described in more detail below. Because the top surface of second carrier substrate 315 has a low roughness as described above, the lid can be more effectively attached to second carrier substrate 315. When the top surface of coating 313 has a surface roughness of less than 10 nm, improved attachment strength between second carrier substrate 315 and the lid can be achieved.

[0052] In Figure 14In this process, a semiconductor package assembly 650 is bonded to a package substrate 700, and an underfill 707 is formed between the semiconductor package assembly 650 and the package substrate 700. The package substrate 700 may include a substrate core 702, conductive contacts 704 on a first side of the substrate core 702, and conductive contacts 706 on a second side of the substrate core 702. Conductive contacts 704 can be electrically connected to conductive contacts 706 via conductive components (not shown) within the substrate core 702. Electrical connectors 708 may be located on conductive contacts 706. During the bonding process between the semiconductor package assembly 650 and the package substrate 700, electrical connectors 612 may be reflowed to bond the semiconductor package assembly 650 to the package substrate 700. Electrical connectors 612 electrically connect the semiconductor package assembly 650 to the package substrate 700. The underfill 707 may surround the electrical connectors 612 and protect the joints created by the reflow of the electrical connectors 612. In a top view, underfill 707 may surround semiconductor package assembly 650. Underfill 707 may be formed of the same or similar material as underfill 614 and by the same or similar process as underfill 614.

[0053] exist Figure 15A In the middle, the cover 712 is attached to the packaging substrate 700 and the semiconductor packaging assembly 650. It can be... Figure 15A The structure shown is referred to as semiconductor package 800. A cap 712 protects the structural integrity of the semiconductor package assembly 650 and dissipates heat generated by the semiconductor package assembly 650 during operation. The cap 712 can be formed of metal or metal alloy, such as copper, stainless steel, etc. The cap 712 can be attached to the package substrate 700 via an adhesive layer 714, which may include epoxy resin, glue, etc. The cap 712 can also be attached to the semiconductor package assembly 650 via an adhesive layer 710, which may include a thermal interface material (TIM) with high thermal conductivity, such as thermal paste, gel-based thermal adhesive, graphite, graphene, etc., or combinations thereof. The top surface of the first coated portion 313 of the second carrier substrate 315 (e.g., the top surface of the second carrier substrate 315) can contact the adhesive layer 710. Because the top surface of the second carrier substrate 315 has the low roughness described above, the cap 712 can be attached to the second carrier substrate 315 more effectively.

[0054] Because of the low roughness of the bottom surface of the second carrier substrate 315, the second carrier substrate 315 is more effectively bonded over the top semiconductor die 200 and the bottom semiconductor die 100, so heat generated by the top semiconductor die 200 can be more effectively transferred directly to the second carrier substrate 315 and heat generated by the bottom semiconductor die 100 can be more effectively transferred to the second carrier substrate 315 through the dummy die 300 during operation of the semiconductor package 800. Because the material of the base portion 312 of the second carrier substrate 315 has high thermal conductivity and because of the low roughness of the top surface of the second carrier substrate 315, the second carrier substrate 315 is more effectively bonded to the lid 712, so heat generated by the top semiconductor die 200 and the bottom semiconductor die 100 can be more effectively transferred from the second carrier substrate 315 to the lid 712, where it can be dissipated away. As a result, the performance and reliability of the semiconductor package 800 can be improved.

[0055] Figure 15B A semiconductor package 800 according to some optional embodiments is shown, which is similar to the embodiment of the semiconductor package 800 shown in Figure 15A , where like reference numbers indicate like parts formed from like materials and by like processes. Figure 15B The semiconductor package 800 in Figure 9 may include a wafer structure 400' as shown in Figure 2A , which is subsequently singulated. As a result, the second carrier substrate 315 can include a wafer 312 and a coating 313 on the top surface, the bottom surface, and the sidewalls of the wafer 312. The top surface and the bottom surface of the wafer 312 can have a first roughness (e.g., average roughness (Ra)) in a range from about 0.3 nm to about 30 nm. The bottom surface of the coating 313 (e.g., the bottom surface of the second carrier substrate 315) can be planarized by the processes described with respect to Figure 13 , and the bottom surface of the coating 313 can have a second roughness (e.g., average roughness (Ra)) of less than about 0.3 nm. The top surface of the coating 313 (e.g., the top surface of the second carrier substrate 315) can be planarized by the processes described with respect to

[0056] Figure 16 , Figure 17 , Figure 18 and Figure 19 Cross-sectional views showing intermediate steps during the fabrication of a semiconductor package using a carrier substrate according to some embodiments are shown. Figure 16 A structure according to some optional embodiments is shown, which is similar to the structure shown in Figure 8Embodiments of the structure shown in FIG. 1 1 1, wherein like reference numbers refer to like parts formed of like materials and by like processes. Figure 16 The structure in FIG. 1 1 1 includes Figure 2B Embodiments of the second carrier substrate 315 shown in FIG. 1 1 1, wherein the coating 313 is formed on a bottom surface of the wafer 312, and other surfaces of the wafer 312 are exposed.

[0057] Figure 17 A semiconductor package assembly 400 is shown according to some optional embodiments, similar to Figure 11 Embodiments of the semiconductor package assembly 400 shown in FIG. 1 1 1, wherein like reference numbers refer to like parts formed of like materials and by like processes. Figure 17 The semiconductor package assembly 400 in FIG. 1 1 1 can be to Figure 16 The structure shown in FIG. 1 1 1 can be subjected to processes described with respect to Figure 9 to Figure 11 The resulting structure after the processes described. In the semiconductor package assembly 400, the singulated second carrier substrate 315 can include a singulated wafer 312 (referred to as a base portion 312) and a singulated coating 313. The singulated coating 313 can be referred to as a coated portion 313 on a bottom surface of the base portion 312 (facing down in FIG. 1 1 1 ). A top surface of the base portion 312 (facing up in FIG. 1 1 1 ) and sidewalls can be exposed. Figure 17 Figure 17

[0058] Figure 18 A semiconductor package assembly 650 is shown according to some optional embodiments, similar to Figure 13 Embodiments of the semiconductor package assembly 650 shown in FIG. 1 1 1, wherein like reference numbers refer to like parts formed of like materials and by like processes. Figure 18 The semiconductor package assembly 650 in FIG. 1 1 1 can be to Figure 16 The semiconductor package assembly 400 shown in FIG. 1 1 1 can be subjected to processes described with respect to Figure 12 to Figure 13 The resulting structure after the processes described. As a result of the planarization process, a top surface of the base portion 312 of the second carrier substrate 315 (e.g., a top surface of the second carrier substrate 315) can have a fourth roughness (e.g., an average roughness (Ra)) in a range from about 0.5 nm to about 10 nm. The fourth roughness can be less than the first roughness of the bottom surface of the base portion 312, and greater than the second roughness of the bottom surface of the coated portion 313 (e.g., a bottom surface of the second carrier substrate 315). The second carrier substrate 315 can be attached to a lid, as described in more detail below. Because the top surface of the second carrier substrate 315 has a low roughness as described above, the lid can be more effectively attached to the second carrier substrate 315. When the top surface of the base portion 312 has a surface roughness in a range from about 0.5 nm to about 10 nm, improved attachment strength between the second carrier substrate 315 and the lid can be achieved.​​

[0059] Figure 19 A semiconductor package 800 is shown in accordance with some optional embodiments, similar to Figure 15A the embodiment of the semiconductor package 800 shown in FIG. 8, where like reference numerals indicate like parts formed of similar materials and by similar processes. Figure 19 The semiconductor package 800 in FIG. 8 can be the resulting structure after performing the processes described with respect to Figure 18 the semiconductor package assembly 650 shown in FIG. 6. The top surface of the base portion 312 of the second carrier substrate 315 (e.g., the top surface of the second carrier substrate 315) can be in contact with the adhesive layer 710. Because the top surface of the second carrier substrate 315 has a low roughness as described above, the lid 712 can be attached to the second carrier substrate 315 more effectively. Figure 14 to Figure 15A Because of the low roughness of the bottom surface of the second carrier substrate 315, the second carrier substrate 315 is more effectively bonded over the top semiconductor die 200 and the bottom semiconductor die 100, so heat generated by the top semiconductor die 200 can be more effectively transferred directly to the second carrier substrate 315, and heat generated by the bottom semiconductor die 100 can be more effectively transferred to the second carrier substrate 315 through the dummy die 300 during operation of the semiconductor package 800. Because the material of the base portion 312 of the second carrier substrate 315 has a high thermal conductivity, and because of the low roughness of the top surface of the second carrier substrate 315, the second carrier substrate 315 is more effectively bonded to the lid 712, so heat generated by the top semiconductor die 200 and the bottom semiconductor die 100 can be more effectively transferred from the second carrier substrate 315 to the lid 712, where the heat can be dissipated away. As a result, the performance and reliability of the semiconductor package 800 can be improved.

[0060] Embodiments of the present disclosure can have some advantageous features. By utilizing the second carrier substrate 315, heat generated by the top semiconductor die 200 and the bottom semiconductor die 100 in the semiconductor package 800 can be more effectively transferred to the second carrier substrate 315, and then to the lid 712, where the heat can be dissipated away. As a result, the performance and reliability of the semiconductor package 800 can be improved.

[0061]

[0062] ​In an embodiment, a semiconductor package includes a package substrate; and a first package assembly located above the package substrate, the first package assembly including: a first semiconductor die; and a heat spreading substrate located above the first semiconductor die, the heat spreading substrate including: a base portion, wherein the base portion includes a first material having a first thermal conductivity; and a first coated portion located on a first surface of the base portion, wherein the first coated portion is located between the first semiconductor die and the base portion, wherein the first coated portion includes a second material different from the first material, and wherein the second material has a second thermal conductivity less than the first thermal conductivity. In an embodiment, the first thermal conductivity is greater than 170 W / mK. In an embodiment, the first material is silicon carbide or aluminum nitride. In an embodiment, the second material is silicon, silicon nitride, or aluminum oxide. In an embodiment, the first surface of the first coated portion faces the first semiconductor die, and wherein an average roughness of the first surface of the first coated portion is less than 0.3 nm. In an embodiment, the heat spreading substrate further includes a second coated portion located on a second surface of the base portion, wherein the second surface of the base portion is opposite the first surface of the base portion, and wherein the second coated portion includes the second material. In an embodiment, the semiconductor package further includes: a lid located above the package substrate and the first package assembly; and a first adhesive layer, wherein the lid is attached to the heat spreading substrate of the first package assembly by the first adhesive layer. In an embodiment, the base portion has a first thickness, and the first coated portion has a second thickness, and wherein a ratio of the second thickness to the first thickness is less than 0.0002.

[0063] In an embodiment, a method of manufacturing a semiconductor package includes forming a carrier substrate, forming the carrier substrate including: depositing a coated portion on a base portion, wherein the coated portion and the base portion include different materials, and wherein the base portion has a higher thermal conductivity than the coated portion; and planarizing a first surface of the coated portion; bonding the carrier substrate over a first semiconductor die, wherein the first surface of the coated portion faces the first semiconductor die; and attaching a lid to the carrier substrate, wherein the carrier substrate is located between the first semiconductor die and the lid. In an embodiment, the lid is attached to the coated portion of the carrier substrate by a first adhesive layer. In an embodiment, the method further includes, prior to attaching the lid, planarizing a second surface of the coated portion, wherein the second surface of the coated portion faces the lid. In an embodiment, the lid is attached to the base portion of the carrier substrate by the first adhesive layer. In an embodiment, the method further includes, prior to attaching the lid, planarizing the base portion. In an embodiment, the base portion has a thermal conductivity greater than 170 W / mK.

[0064] In an embodiment, a method of manufacturing a semiconductor package includes depositing a first coated portion on a first surface of a base portion to form a carrier substrate, wherein the base portion includes a first material having a first thermal conductivity greater than 170 W / mK; bonding the carrier substrate over a first semiconductor die, wherein the first surface of the first coated portion faces the first semiconductor die; and bonding the first semiconductor die over a package substrate, wherein the first semiconductor die is electrically connected to the package substrate. In an embodiment, the first material is a polycrystalline semiconductor material or a polycrystalline dielectric material. In an embodiment, the first coated portion includes a second material different from the first material, and wherein the second material is a polycrystalline semiconductor material or a polycrystalline dielectric material. In an embodiment, the method further includes planarizing the first surface of the first coated portion prior to bonding the carrier substrate over the first semiconductor die, wherein, after planarizing the first surface of the first coated portion, an average roughness of the first surface of the first coated portion is less than 0.3 nm. In an embodiment, the method further includes depositing a second coated portion on a second surface of the base portion opposite the first surface, wherein the first coated portion and the second coated portion include the same material. In an embodiment, the method further includes planarizing the first surface of the second coated portion, wherein, after planarizing the first surface of the second coated portion, an average roughness of the first surface of the second coated portion is less than 10 nm.

[0065] According to one aspect of the present application, a semiconductor package is provided, the semiconductor package comprising: a package substrate; and a first package assembly located above the package substrate, the first package assembly comprising: a first semiconductor die; and a heat spreading substrate located above the first semiconductor die, the heat spreading substrate comprising: a base portion, wherein the base portion comprises a first material having a first thermal conductivity; and a first coating portion located on a first surface of the base portion, wherein the first coating portion is located between the first semiconductor die and the base portion, wherein the first coating portion comprises a second material different from the first material, and wherein the second material has a second thermal conductivity less than the first thermal conductivity. In some embodiments, the first thermal conductivity is greater than 170 W / mK. In some embodiments, the first material is silicon carbide or aluminum nitride. In some embodiments, the second material is silicon, silicon nitride, or aluminum oxide. In some embodiments, the first surface of the first coating portion faces the first semiconductor die, and wherein an average roughness of the first surface of the first coating portion is less than 0.3 nm. In some embodiments, the heat spreading substrate further comprises a second coating portion located on a second surface of the base portion, wherein the second surface of the base portion is opposite the first surface of the base portion, and wherein the second coating portion comprises the second material. In some embodiments, the semiconductor package further comprises: a lid located above the package substrate and the first package assembly; and a first adhesive layer, wherein the lid is attached to the heat spreading substrate of the first package assembly by the first adhesive layer. In some embodiments, the base portion has a first thickness, and the first coating portion has a second thickness, and wherein a ratio of the second thickness to the first thickness is less than 0.0002.

[0066] According to another aspect of the present application, a method of manufacturing a semiconductor package is provided, the method comprising: forming a carrier substrate, forming the carrier substrate comprising: depositing a coating portion on a base portion, wherein the coating portion and the base portion comprise different materials, and wherein the base portion has a higher thermal conductivity than the coating portion; and planarizing a first surface of the coating portion; bonding the carrier substrate over a first semiconductor die, wherein the first surface of the coating portion faces the first semiconductor die; and attaching a lid to the carrier substrate, wherein the carrier substrate is located between the first semiconductor die and the lid. In some embodiments, the lid is attached to the coating portion of the carrier substrate by a first adhesive layer. In some embodiments, the method of manufacturing a semiconductor package further comprises, prior to attaching the lid, planarizing a second surface of the coating portion, wherein the second surface of the coating portion faces the lid. In some embodiments, the lid is attached to the base portion of the carrier substrate by a first adhesive layer. In some embodiments, the method of manufacturing a semiconductor package further comprises, prior to attaching the lid, planarizing the base portion. In some embodiments, the base portion has a thermal conductivity greater than 170 W / mK.

[0067] According to yet another aspect of the present application, a method of manufacturing a semiconductor package is provided, the method comprising: depositing a first coated portion on a first surface of a base portion to form a carrier substrate, wherein the base portion comprises a first material having a first thermal conductivity greater than 170 W / mK; bonding the carrier substrate over a first semiconductor die, wherein the first surface of the first coated portion faces the first semiconductor die; and bonding the first semiconductor die over a package substrate, wherein the first semiconductor die is electrically connected to the package substrate. In some embodiments, the first material is a polycrystalline semiconductor material or a polycrystalline dielectric material. In some embodiments, the first coated portion comprises a second material different from the first material, and wherein the second material is a polycrystalline semiconductor material or a polycrystalline dielectric material. In some embodiments, the method of manufacturing a semiconductor package further comprises planarizing the first surface of the first coated portion prior to bonding the carrier substrate over the first semiconductor die, wherein an average roughness of the first surface of the first coated portion is less than 0.3 nm after planarizing the first surface of the first coated portion. In some embodiments, the method of manufacturing a semiconductor package further comprises depositing a second coated portion on a second surface of the base portion opposite the first surface, wherein the first coated portion and the second coated portion comprise the same material. In some embodiments, the method of manufacturing a semiconductor package further comprises planarizing the first surface of the second coated portion, wherein an average roughness of the first surface of the second coated portion is less than 10 nm after planarizing the first surface of the second coated portion.

[0068] The foregoing summary of features of several embodiments has been presented for the purposes of illustration so that one skilled in the art can better understand the aspects of the present disclosure. It will be appreciated that those skilled in the art will be able to devise numerous other processes and structures that, although not explicitly described herein, embody the principles of the same and achieve the same results. It will be appreciated that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor package, comprising: Packaging substrate; as well as A first packaging component, located above the packaging substrate, includes: First Semiconductor Die; and A heat dissipation substrate, located above the first semiconductor die, comprises: The base portion, wherein the base portion comprises a first material having a first thermal conductivity; and A first coating portion is located on a first surface of the base portion, wherein the first coating portion is located between the first semiconductor die and the base portion, wherein the first coating portion comprises a second material different from the first material, and wherein the second material has a second thermal conductivity lower than the first thermal conductivity.

2. The semiconductor package according to claim 1, wherein, The first thermal conductivity is greater than 170 W / mK.

3. The semiconductor package according to claim 1, wherein, The first material is silicon carbide or aluminum nitride.

4. The semiconductor package according to claim 1, wherein, The second material is silicon, silicon nitride, or aluminum oxide.

5. The semiconductor package according to claim 1, wherein, The first surface of the first coated portion faces the first semiconductor die, and wherein the average roughness of the first surface of the first coated portion is less than 0.3 nm.

6. The semiconductor package according to claim 1, wherein, The heat dissipation substrate further includes a second coating portion located on a second surface of the base portion, wherein the second surface of the base portion is opposite to the first surface of the base portion, and wherein the second coating portion comprises the second material.

7. The semiconductor package according to claim 1, further comprising: The cover is located above the encapsulation substrate and the first encapsulation assembly; as well as A first adhesive layer, wherein the cover is attached to the heat dissipation substrate of the first encapsulation assembly via the first adhesive layer.

8. The semiconductor package according to claim 1, wherein, The base portion has a first thickness, and the first coated portion has a second thickness, wherein the ratio of the second thickness to the first thickness is less than 0.0002.

9. A method for manufacturing a semiconductor package, the method comprising: Forming a carrier substrate, wherein forming the carrier substrate includes: A coating portion is deposited on a base portion, wherein the coating portion and the base portion comprise different materials, and wherein the base portion has a higher thermal conductivity than the coating portion; and Planarize the first surface of the coated portion; The carrier substrate is bonded over a first semiconductor die, wherein the first surface of the coated portion faces the first semiconductor die; and The cap is attached to the carrier substrate, wherein the carrier substrate is located between the first semiconductor die and the cap.

10. A method for manufacturing a semiconductor package, the method comprising: A first coating portion is deposited on a first surface of the base portion to form a carrier substrate, wherein the base portion comprises a first material having a first thermal conductivity greater than 170 W / mK; The carrier substrate is bonded over the first semiconductor die, wherein the first surface of the first coated portion faces the first semiconductor die; and The first semiconductor die is bonded over the packaging substrate, wherein the first semiconductor die is electrically connected to the packaging substrate.

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