Chip packaging structure and chip packaging method

Abstract

The invention provides a chip packaging structure and a chip packaging method, and relates to the technical field of semiconductor packaging. The packaging structure comprises a substrate, a concave bonding pad and a convex bonding pad are formed on the surface of the substrate, the concave bonding pad is concave downwards relative to the surface of the substrate, and the convex bonding pad is convex upwards relative to the surface of the substrate; the first chip is electrically connected with the board through the convex bonding pad; and the second chip is electrically connected with the substrate through the concave bonding pad. Through the differential design of the concave and convex bonding pads and the double-layer peelable structure, the reflow soldering temperature of 200-220 DEG C is supported, compared with 180-200 DEG C of a traditional PS carrier tape, the reflow soldering temperature of 180-200 DEG C is remarkably improved, the connection stability and reliability in a high-temperature process are remarkably improved, a temporary carrier tape which needs to be independently used in the traditional process is omitted, the manufacturing cost is reduced, and the production efficiency is improved. And the method is suitable for complex packaging application requiring multiple welding.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a chip packaging method. BACKGROUND

[0002] With the development of electronic products towards miniaturization and high performance, chip packaging technology is facing higher and higher requirements. In the traditional chip packaging process, the packaging tape is a common component, but its price is relatively high, which will increase the cost. SUMMARY

[0003] The purpose of the present application is to provide a chip packaging structure and a chip packaging method for reducing cost and improving the reliability of chip packaging.

[0004] In order to achieve the above-mentioned purpose of the application, the present application provides a chip packaging structure, comprising: a substrate, a concave pad and a convex pad are formed on the upper surface of the substrate, the concave pad is recessed downward relative to the upper surface of the substrate, and the convex pad is protruded upward relative to the upper surface of the substrate; a first chip electrically connected to the substrate through the convex pad; a second chip electrically connected to the substrate through the concave pad.

[0005] Optionally, the recessed depth of the concave pad is 50-200 microns, and the protruding height of the convex pad is 30-150 microns.

[0006] Optionally, the concave pad is located in the outer region of the substrate, and the convex pad is located in the central region of the substrate.

[0007] Optionally, the second chip, the first chip and the substrate are arranged in sequence.

[0008] Optionally, it further comprises a third chip, the third chip is arranged on the second chip, and the third chip is electrically connected to the substrate through the concave pad.

[0009] The present application also provides a chip packaging method, comprising: providing a substrate; forming a concave pad and a convex pad on the upper surface of the substrate, the concave pad is recessed downward relative to the upper surface of the substrate, and the convex pad is protruded upward relative to the upper surface of the substrate; attaching a first chip to the substrate and realizing electrical connection through the convex pad; attaching a second chip to the first chip and realizing electrical connection through the concave pad; packaging.

[0010] Optionally, the substrate comprises: The upper metal plate, the lower metal plate, and the intermediate layer between the upper metal plate and the lower metal plate, wherein the intermediate layer comprises a titanium layer and a tin layer.

[0011] Optionally, the step of forming the concave pads and the convex pads on the surface of the substrate comprises: punching the substrate from the opposite upper and lower surfaces, respectively; performing photoetching on the upper surface of the punched substrate and etching the upper metal plate to expose the central pad area and the surrounding pad area; removing the photoresist, wherein the central pad area forms a plurality of convex pads, and the surrounding pad area forms a plurality of concave pads.

[0012] Optionally, after the packaging is completed, the method further comprises the steps of: cutting, wherein the connection of the lower metal plate is kept intact or is only partially cut into the lower metal plate but not completely cut off; peeling the intermediate layer and the lower metal plate from the upper metal plate.

[0013] Optionally, the temperature during the packaging process is 200-220°C.

[0014] The chip packaging structure and the packaging method provided by the application form a differentiated pad structure of concave pads and convex pads on the upper surface of the substrate, wherein the concave pads are recessed downward to form physical constraints on the solder, which can effectively prevent the lateral flow and collapse of the solder during high-temperature soldering, maintain the stability of the solder joint shape, and improve the soldering reliability. The convex pads are protruded upward and are suitable for electrical connection with the bottom of the chip, and cooperate with the concave pads to realize multi-chip stacked packaging. The structure is used at a soldering temperature of 200-220°C, which can ensure that the previously formed solder joint is not affected, and the stability of the solder joint is improved.

[0015] The double-layer metal plate structure of the application uses the lower metal plate as a process carrier tape, simplifies the packaging process flow, eliminates the temporary carrier tape that needs to be used separately in the traditional process, and reduces the manufacturing cost. The titanium layer provided in the intermediate layer can effectively prevent the metallurgical combination of the upper and lower metal plates during the high-temperature process, so that the lower metal plate can be peeled off smoothly after the packaging is completed, realizing the carrier tape function while not affecting the performance of the final packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 FIG. 1 is a schematic diagram of a chip packaging structure in an embodiment of the application; Figure 2 FIG. 2 is a top view of a chip packaging structure in an embodiment of the application; Figure 3A side view of a chip packaging structure in an embodiment of the present application; Figure 4 A top view of a substrate of a chip packaging structure in an embodiment of the present application; Figure 5 An exploded view of a chip packaging structure in an embodiment of the present application; Figure 6 A flow chart of a chip packaging method in an embodiment of the present application; Figure 7 A schematic view of a stamping process to form a concave-convex structure in an embodiment of the present application; Figure 8 A schematic view of coating photoresist on a top surface of a substrate in an embodiment of the present application; Figure 9 A schematic view of a photoresist after being patterned in an embodiment of the present application; Figure 10 A schematic view of performing lithography and etching on a top surface of a substrate in an embodiment of the present application; Figure 11 A schematic view of removing photoresist in an embodiment of the present application.

[0017] In the figure, 1 is a substrate; 11 is an upper metal plate; 12 is a lower metal plate; 2 is a concave pad; 3 is a convex pad; 4 is a chip; 41 is a first chip; 42 is a second chip; and 5 is photoresist. DETAILED DESCRIPTION

[0018] The present application will now be described with reference to the accompanying drawings. In the description, common numbers will be used to indicate common parts. The following description of the preferred embodiments is merely illustrative of the present application and is not intended to limit the scope of the application as disclosed.

[0019] In this document, the serial numbers for components, such as “first”, “second”, etc., are used only to distinguish the described objects, and do not have any sequential or technical meaning. In this application, “connection” and “coupling” include direct and indirect connections (couplings) unless otherwise specified. In the description of the present application, it should be understood that the terms “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise”, etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0020] In the present application, unless otherwise explicitly specified and limited, a first feature is "on" or "under" a second feature can mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature is "over", "above" and "on top of" the second feature can mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. The first feature is "under", "below" and "underneath" the second feature can mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is horizontally lower than the second feature.

[0021] The present application will be described in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present application will become more apparent from the following description in conjunction with the accompanying drawings. It should be noted that the drawings are in a highly simplified form and are not drawn to precise scale, and are used only to facilitate, clarify and aid understanding of the embodiments of the present application.

[0022] Embodiment One An embodiment of the present application provides a chip packaging structure, as shown in the accompanying drawings, comprising a substrate 1, a concave pad 2, a convex pad 3 and at least one chip 4. The substrate 1 is the bearing body of the packaging structure, used to provide mechanical support and electrical interconnection functions. The surface of the substrate 1 is formed with the concave pad 2 and the convex pad 3. The chip 4 comprises a first chip 41 and a second chip 42. The first chip 41 is electrically connected to the substrate 1 through the convex pad 3. The second chip 42 is electrically connected to the substrate 1 through the concave pad 2. Figure 1 Figure 3 Specifically, the concave pad 2 is recessed downward relative to the upper surface of the substrate 1, forming a recessed structure.

[0023] In this embodiment, the recessed structure forms a physical constraint on the solder, which can effectively prevent the solder from flowing sideways, collapsing or bridging during high-temperature soldering. The concave pad 2 of the present application forms a constraint on the molten solder through the side wall of its groove, limiting the flow range of the solder, so that the solder joint can still maintain a stable shape and position under high temperature. This structure is particularly suitable for complex packaging processes that require multiple soldering. In subsequent soldering processes, the previously formed solder joint will not change its shape due to the high temperature again, ensuring the reliability of the packaging.

[0024] In this embodiment, the recessed structure forms a physical constraint on the solder, which can effectively prevent the solder from flowing sideways, collapsing or bridging during high-temperature soldering. The concave pad 2 of the present application forms a constraint on the molten solder through the side wall of its groove, limiting the flow range of the solder, so that the solder joint can still maintain a stable shape and position under high temperature. This structure is particularly suitable for complex packaging processes that require multiple soldering. In subsequent soldering processes, the previously formed solder joint will not change its shape due to the high temperature again, ensuring the reliability of the packaging.

[0025] ​It should be noted that in the conventional packaging process, polystyrene (PS) plastic tape is often used as a process carrier. Due to the heat resistance temperature limit of PS material, the reflow soldering temperature is usually limited to the range of 180-200℃. In this temperature range, the solder is in a partially molten state, and the soldering quality and reliability are affected to a certain extent. The recessed pad 2 structure of the present application can withstand a reflow soldering temperature of 200-220℃. At this temperature, the solder can be fully melted and wetted to form a more reliable solder joint. At the same time, the constraint effect of the recessed structure of the recessed pad 2 on the solder is more critical at higher temperatures, which can effectively prevent the solder from collapsing or bridging due to the increase in flowability, thereby improving the stability of the solder joint.

[0026] In addition, the recessed structure of the recessed pad 2 also increases the contact area of the solder with the substrate 1. The inner wall of the groove provides additional metallized surface, so that the solder can achieve metallurgical bonding on a larger interface, thereby improving the shear strength and fatigue resistance of the solder joint. The recessed structure is also beneficial to the discharge of gas during the soldering process, reducing the formation of internal voids in the solder joint and further improving the connection quality.

[0027] In a specific example, the connection between the second chip 42 and the recessed pad 2 adopts a wire bonding method. The wire bonding process includes hot pressing, ultrasonic welding or thermal ultrasonic welding, etc., which is a common means for those skilled in the art and will not be described here.

[0028] The recessed structure of the recessed pad 2 provides a protection space for the bottom connection point of the bonding wire, preventing the bonding point from being damaged by mechanical stress in subsequent packaging processes (such as plastic packaging). At the same time, the recessed structure increases the metallized area of the pad, providing a larger bonding area, which is beneficial to the reliable connection of the bonding wire and the substrate 1, and improves the bonding strength. During the high-temperature process, the recessed structure provides physical protection for the bonding point, preventing the bonding interface from falling off or cracking under thermal stress.

[0029] Specifically, the convex pad 3 is upwardly convex relative to the upper surface of the substrate 1, forming a convex structure. The convex pad 3 is mainly used for the connection of flip-chip. Specifically, the convex pad 3 is upwardly convex from the upper surface of the substrate 1, which can form a butt joint with the solder bumps or solder balls at the bottom of the flip-chip, and realize electrical and mechanical connection through soldering. The convex height of the convex pad 3 enables it to extend into the space between the chip 4 and the substrate 1, adapting to the connection requirements of flip-chip. This convex structure provides a differentiated connection scheme for chips using different connection processes in multi-chip stacked packaging.

[0030] In one specific example, the recessed depth of the recessed pad 2 is 50-200 microns. The specific recessed depth can be selected according to the height of the chip bump, the volume of the solder, the connection mode of the bonding wire, and the required height of the solder joint. Preferably, the recessed depth is 80-150 microns, which can balance the solder constraint effect, the bonding point protection, and the process realizability.

[0031] In one specific example, the protruding height of the protruded pad 3 is 30-150 microns. The selection of the protruding height needs to consider the spacing between chips, the volume of the solder, and the overall height requirement after packaging. Preferably, the protruding height is 50-100 microns.

[0032] In one specific example, as shown in Figure 4 The recessed pad 2 is located in the outer region of the substrate 1, and the protruded pad 3 is located in the central region of the substrate 1. This layout design takes into account the functional positioning and connection requirements of different chips in multi-chip packaging.

[0033] Further, as shown in Figure 5 The second chip 42, the first chip 41, and the substrate 1 are arranged in sequence.

[0034] Specifically, the second chip 42 is connected to the substrate 1 by wire bonding. The active surface of the second chip 42 faces upwards, and the pads at the edge of the chip are connected to the recessed pads 2 in the outer region of the substrate 1 by bonding wires. The recessed structure of the recessed pad 2 provides protection for the bottom connection point of the bonding wire, improving the bonding quality. The pads of the second chip 42 and the recessed pads 2 form a stable electrical connection through the bonding wire.

[0035] The first chip 41 can be arranged in a flip-chip manner, with its active surface facing the substrate 1, and its bottom solder bumps or solder balls being connected to the protruded pads 3 in the central region of the substrate 1. The protruded pads 3 protrude upwards from the upper surface of the substrate 1, extending into the gap between the first chip 41 and the substrate 1, and achieving electrical connection with the first chip 41.

[0036] In one specific example, the chip packaging structure further includes a third chip, which is arranged on the second chip 42 and connected to the recessed pad 2 by wire bonding. Preferably, the third chip has a smaller size than the second chip 42. The bonding wire is drawn from the pad of the third chip, across the second chip 42, and connected to the recessed pad 2 in the outer region of the substrate 1.

[0037] The stacked layout realizes high-density three-dimensional packaging. The first chip 41, the second chip 42 and the third chip can be chips with different functions, for example, the first chip 41 is a logic processing chip, the second chip 42 is a storage chip, and the third chip is a sensor chip or a communication chip. Through the differential design of the concave pad 2 and the convex pad 3, the three chips can realize multi-layer stacking and reliable electrical connection in a limited packaging area. The concave structure of the concave pad 2 provides a unified connection point for wire bonding from different level chips, while protecting the connection stability of the chips in multiple reflow processes. This multi-chip stacked packaging method is particularly suitable for system-in-package (SiP) applications, which can integrate multiple functions in a single package, significantly reducing the package size and improving system integration and performance.

[0038] Further, the concave pad 2 and the convex pad 3 are formed by a stamping process. Specifically, a stamping die is used to stamp the substrate 1, causing plastic deformation at the predetermined pad positions, forming a concave or convex structure.

[0039] The stamping process can simultaneously form multiple concave pads 2 and convex pads 3 in one stamping action, with much higher production efficiency than etching process performed on individual regions, making it particularly suitable for mass production.

[0040] The precision of the stamping die can reach microns, allowing accurate control of the depth of the concave and the height of the convex, ensuring the consistency of the pad size.

[0041] The side walls of the concave pad 2 and the convex pad 3 formed by stamping are smooth and flat, without the side etching or rough surface that may occur in etching process, which is beneficial to the wetting and bonding of solder, and also facilitates the reliable connection of the bonding wire and the pad during wire bonding.

[0042] In summary, the chip packaging structure provided by the present application has the following advantages: the concave structure of the concave pad provides a protection space for the wire bonding connection point, and at the same time, it restricts the solder of flip-chip bonding, effectively preventing the bonding point from falling off and the solder from flowing in the high-temperature process of 200-220℃, improving the soldering reliability; through the differential design of the concave and convex pads, wire bonding and flip-chip bonding coexist in the same structure, supporting high-density three-dimensional packaging; the concave structure increases the metallization area, improving the bonding strength and the shear strength of the solder joint; the concave and convex pads formed by stamping process have high precision, good surface quality and high processing efficiency, suitable for mass production. The present application simplifies the process while improving the packaging reliability, and is suitable for high-density and high-reliability chip packaging applications.

[0043] Embodiment Two The present embodiment provides a chip packaging method, please refer to Figure 6 , comprising the following steps: S1: providing a substrate 1; S2: forming a concave pad 2 and a convex pad 3 on the upper surface of the substrate 1, the concave pad 2 being recessed downward relative to the upper surface of the substrate 1, and the convex pad 3 being protruded upward relative to the upper surface of the substrate 1; S3: mounting a first chip 41 on the substrate 1 and realizing electrical connection through the convex pad 3; S4: mounting a second chip 42 on the first chip 41 and realizing electrical connection through the concave pad 2; S5: packaging.

[0044] In step S1, a substrate 1 for packaging is provided.

[0045] In one specific example, the substrate 1 comprises a double-layer metal plate structure, specifically comprising an upper metal plate 11, a lower metal plate 12 and an intermediate layer between the upper metal plate 11 and the lower metal plate 12. The concave pad 2 and the convex pad 3 are formed on the surface of the upper metal plate 11 away from the lower metal plate 12.

[0046] The upper metal plate 11 serves as the final packaging substrate and provides pad and electrical interconnection functions. The thickness of the upper metal plate 11 can be selected as 0.1-1.0 mm, preferably 0.2-0.5 mm, according to packaging requirements. The material of the upper metal plate 11 can be selected as copper, aluminum or other conductive metal materials, and copper is preferred because it has excellent electrical conductivity, thermal conductivity and processability.

[0047] The lower metal plate 12 serves as a process carrier during the packaging process and provides mechanical support functions. The thickness of the lower metal plate 12 can be selected as 0.2-2.0 mm, preferably 0.5-1.0 mm, to provide sufficient rigidity. The material of the lower metal plate 12 is also preferably copper. During the entire packaging process, the lower metal plate 12 remains connected to the upper metal plate 11 to provide a stable carrier for chip mounting, welding, plastic packaging and other processes.

[0048] The intermediate layer is located between the upper metal plate 11 and the lower metal plate 12 and serves as a temporary connection and anti-adhesion function. The intermediate layer comprises a titanium layer, which is used to prevent the upper metal plate 11 and the lower metal plate 12 from being metallurgically combined during high-temperature processes.

[0049] The mechanism of the titanium layer is as follows: Titanium has a melting point as high as 1668℃, far exceeding the temperature range used in packaging processes. During high-temperature processes such as soldering, although temperatures reach 200-220℃ or even higher, they are far below titanium's melting point. Simultaneously, titanium exhibits low reactivity with metals such as copper and tin within this temperature range, making it difficult to form intermetallic compounds. Therefore, the titanium layer forms an effective barrier between the upper metal plate 11 and the lower metal plate 12, preventing metallurgical bonding between the two copper plates at high temperatures through solid-phase diffusion or the formation of intermetallic compounds. Without the titanium layer, Cu-Cu metallurgical bonds may form at the contact interface after multiple high-temperature processes, leading to the lower metal plate 12 being unable to be peeled off after packaging or damaging the structure of the upper metal plate 11 during peeling.

[0050] In one specific example, the intermediate layer further includes a tin layer. The tin layer acts as an adhesive layer, ensuring a reliable mechanical connection between the upper metal plate 11 and the lower metal plate 12 during the process, while preventing excessive bonding force during peeling. Tin has a melting point of 232°C and is solid at room temperature, providing sufficient mechanical strength; at temperatures close to its melting point, tin's plastic deformation ability increases, which is beneficial for the peeling operation. The thickness of the tin layer can be selected from 0.5-5 micrometers, preferably 1-3 micrometers.

[0051] The intermediate layer can have a titanium layer between the upper metal plate 11 and the tin layer, and a tin layer between the titanium layer and the lower metal plate 12; or a tin layer between the upper metal plate 11 and the titanium layer, and a titanium layer between the tin layer and the lower metal plate 12; or titanium layers can be placed on both the upper and lower sides, forming a three-layer structure of titanium-tin-titanium. The specific layer sequence can be optimized according to process requirements and peel performance.

[0052] The intermediate layer can be prepared using thin film deposition techniques such as sputtering, vapor deposition, electroplating, or electroless plating, which are common practices for those skilled in the art and will not be elaborated further.

[0053] The lower metal plate 12 serves as a process carrier and can be peeled off from the upper metal plate 11 after packaging. The peeling operation can be performed after all packaging process steps are completed. The peeling method can be mechanical peeling, i.e., applying shear or tensile force to separate the lower metal plate 12 from the upper metal plate 11 at the interlayer. Due to the blocking effect of the titanium layer, the upper and lower metal plates are connected only through physical contact in the interlayer, rather than by metal bonding; therefore, the peeling process will not damage the upper metal plate 11 or its pads and chip connections.

[0054] In one specific example, the stripping operation can be performed under heating conditions. When the temperature approaches the melting point of tin, the adhesion of the tin layer decreases, which facilitates stripping. The stripped lower metal plate 12 can be cleaned and reused, achieving material recycling and further reducing costs.

[0055] In the present embodiment, the lower metal plate 12 integrates the carrier tape function, without the need for additional dedicated carrier tape material, reducing the carrier tape attachment and stripping steps, and simplifying the process flow. The lower metal plate 12 uses conventional copper plate material, which is lower in cost than dedicated carrier tape; and the lower metal plate 12 can be recycled after stripping, further reducing costs. The lower metal plate 12 provides continuous rigid support throughout the packaging process, avoiding the alignment errors and mechanical stress that can be caused by multiple carrier tape changes, improving process stability and yield.

[0056] In the cutting process, the conventional process usually needs to attach a cutting protection tape on the front surface to fix and protect the packaging unit. In the present embodiment, since the lower metal plate 12 remains connected during cutting, it provides bottom support for the packaging unit, so that the front protection tape can be omitted, simplifying the process, while avoiding the pollution problem that can be caused by tape residues.

[0057] Further, step S1 specifically comprises: S11: providing an upper metal plate 11 and a lower metal plate 12. The upper metal plate 11 and the lower metal plate 12 can use copper plate, aluminum plate or other metal plate material, preferably copper plate. The thickness and size of the metal plate are selected according to the packaging requirements.

[0058] S12: preparing an intermediate layer. On the lower surface of the upper metal plate 11 or the upper surface of the lower metal plate 12, an intermediate layer is deposited by sputtering, evaporation, electroplating or chemical plating process. The intermediate layer includes a titanium layer, which is used to prevent the upper metal plate 11 and the lower metal plate 12 from metallurgical bonding during high-temperature processes.

[0059] S13: attaching the upper metal plate 11 and the lower metal plate 12.

[0060] Further, in step S2, concave pads 2 and convex pads 3 are formed on the upper surface of the substrate 1. The concave pads 2 are recessed downward relative to the upper surface of the substrate 1, and the convex pads 3 are raised upward relative to the upper surface of the substrate 1.

[0061] The formation of the concave pads 2 and the convex pads 3 can use a stamping process to form the recessed and raised structures.

[0062] Step S2 specifically comprises the following processes: S21: stamping the substrate 1 from the opposite upper and lower surfaces, respectively; S22: performing photolithography on the upper surface of the stamped substrate 1 and etching the upper metal plate 11 to expose the central pad area and the surrounding pad area; S23: removing the photoresist 5, the central pad area forms a plurality of convex pads 3, and the surrounding pad area forms a plurality of concave pads 2.

[0063] In detail, please refer to Figure 7 First, the substrate 1 is punched from both opposite upper and lower surfaces. In this embodiment, the substrate 1 is a double-layer metal plate structure, and the punching is performed from the upper surface of the upper metal plate 11 and the lower surface of the lower metal plate 12 respectively. The peripheral pad area is punched from the upper surface of the upper metal plate 11 using a first punching die, and a structure recessed downward relative to the upper surface is formed on the upper surface of the upper metal plate 11 in the peripheral pad area; at the same time or subsequently, the central pad area is punched from the lower surface of the lower metal plate 12 using a second punching die, and a structure protruded upward relative to the upper surface is formed on the upper surface of the upper metal plate 11 in the central pad area. Through the punching in the upper and lower directions, the pad structure with different heights is formed on the upper surface of the upper metal plate 11: the central area is protruded relative to the upper surface, and the peripheral area is recessed relative to the upper surface. The punching depth and position need to be accurately controlled during the punching process, so that the recess depth and the protrusion height meet the design requirements. It should be noted that only the structure of the concave-convex structure on the upper surface of the upper metal plate 11 and the lower surface of the lower metal plate 12 is schematically shown in the figure, and the internal structure of the substrate 1 is not shown because of the structural changes caused by the punching.

[0064] Secondly, photoetching and etching are performed on the upper surface of the punched substrate 1. In detail, please refer to Figure 8 Figure 9 The photoresist 5 is coated on the upper surface of the upper metal plate 11, and the photoresist 5 is patterned, so that the photoresist 5 remains as a protective layer in the central pad area and the peripheral pad area, and the photoresist 5 in the non-pad area is removed to expose the non-pad area. Please refer to Figure 10 Figure 11 Then, the exposed non-pad area is etched to remove the metal layer in the non-pad area, while the pad area retains the metal due to the protection of the photoresist 5. The etching method can use wet etching or dry etching, and the etching stops at the intermediate layer. Finally, the photoresist 5 in the pad area is removed, and the metal pads in the central pad area and the peripheral pad area are exposed. The central pad area forms a plurality of convex pads 3 which are protruded upward relative to the upper surface of the upper metal plate 11; the peripheral pad area forms a plurality of concave pads 2 which are recessed downward relative to the upper surface of the upper metal plate 11.

[0065] Further, in steps S3-S4, the first chip 41 is mounted on the substrate 1 and electrically connected through the convex pads 3; and the second chip 42 is mounted on the first chip 41 and electrically connected through the concave pads 2.

[0066] In another specific example, a third chip is further mounted on the second chip 42 and electrically connected through the concave pads 2.

[0067] ​​During the mounting process, the lower metal plate 12 provides rigid support as a process carrier tape, preventing the substrate 1 from bending and deforming, improving mounting precision and wire bonding quality.

[0068] Further, in step S5, subsequent packaging processes are performed, including but not limited to: underfill, molding, marking, cutting, etc. In the cutting process, in the double-layer metal plate structure, the lower metal plate 12 remains connected during the cutting process, providing bottom support for the packaging units. Cutting can only cut the upper metal plate 11 and the packaging body, without cutting the lower metal plate 12; or partially cutting into the lower metal plate 12 but not completely cutting off. In this way, the cut packaging units are still connected together by the lower metal plate 12, without the need for fixing by attaching protective tape (DAF tape) on the front surface. This simplifies the process, reduces costs, and at the same time avoids the possibility of tape residues contaminating the surface of the packaging units.

[0069] Further, in step S6, after completing the packaging process, the intermediate layer and the lower metal plate 12 are peeled off from the upper metal plate 11.

[0070] The peeling operation can be performed after the cutting process. The peeling method can use mechanical peeling, using a peeling device to apply a shearing force or a stretching force to separate the intermediate layer and the lower metal plate 12 from the upper metal plate 11. Due to the blocking effect of the titanium layer, no metallurgical bonding is formed between the upper and lower metal plates, and the peeling process only needs to overcome the physical bonding force of the intermediate layer, so the peeling force is small and will not damage the upper metal plate 11 and the pads and circuits thereon.

[0071] In one specific example, peeling can be performed under heating conditions, with the temperature controlled in the range close to the melting point of the tin layer (e.g. 180-230°C), so that the tin layer softens, reducing the bonding force and making it easier to peel. After peeling, the lower metal plate 12 surface may have some residual intermediate layer material, which can be reused after cleaning.

[0072] After peeling, the chip packaging structure is separated from the intermediate layer and the lower metal plate 12, and can be subjected to subsequent testing, packaging, etc.

[0073] Compared with the traditional packaging process using polystyrene (PS) plastic carrier tape, whose reflow temperature is limited to 180-200°C, in this embodiment, the soldering temperature is raised to 200-220°C. At this temperature, the solder is relatively more fully melted, with better flowability and wettability, forming a more uniform and reliable solder connection.

[0074] In summary, the beneficial effects of the present application are that the recessed structure of the recessed pad provides a physical protection space for the connection point of wire bonding, preventing the bonding interface from falling off or being damaged due to thermal stress during welding or other high-temperature processes at 200-220 DEG C. This structure is particularly suitable for hybrid packaging processes. When flip-chip welding is performed, the previously completed wire bonding connection can remain stable in a high-temperature environment, improving the reliability and yield of packaging. Through the differential design of the recessed pad and the convex pad, multi-chip stacked packaging is achieved. High-density interconnection is achieved in a limited packaging area, improving the integration level. A double-layer metal plate structure is used, and the lower metal plate integrates the process carrier tape function, eliminating the need for additional special carrier tapes and reducing the carrier tape attachment and stripping steps. In the cutting process, the lower metal plate provides bottom support, eliminating the need for front protective tape, further simplifying the process. The lower metal plate uses conventional copper plate materials, which are lower in cost than special carrier tapes, and can be recycled and reused after stripping, achieving material recycling and significantly reducing packaging costs. The lower metal plate provides continuous rigid support throughout the packaging process, avoiding alignment errors caused by substrate deformation and multiple carrier tape changes, improving process stability. The barrier effect of the titanium layer allows the upper and lower metal plates to be reliably stripped after multiple high-temperature processes without damaging the packaging structure. The present application simplifies the process and reduces costs, providing an excellent technical solution for high-density, high-reliability chip packaging, and has a wide application prospect and significant economic benefits.

[0075] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A chip packaging structure, characterized in that, include: A substrate, wherein concave pads and convex pads are formed on the upper surface of the substrate, the concave pads being recessed downward relative to the upper surface of the substrate, and the convex pads being convex upward relative to the upper surface of the substrate; The first chip is electrically connected to the substrate via the solder pads; The second chip is electrically connected to the substrate via the concave pad.

2. The chip packaging structure according to claim 1, characterized in that, The recessed pad has a depth of 50-200 micrometers, and the raised pad has a height of 30-150 micrometers.

3. The chip packaging structure according to claim 1, characterized in that, The concave pads are located in the outer region of the substrate, and the convex pads are located in the central region of the substrate.

4. The chip packaging structure according to claim 1 or 3, characterized in that, The second chip, the first chip, and the substrate are stacked in sequence.

5. The chip packaging structure according to claim 4, characterized in that, It also includes a third chip, which is disposed on the second chip and is electrically connected to the substrate through the concave pad.

6. A chip packaging method, characterized in that, include: Provide substrate; Concave pads and convex pads are formed on the upper surface of the substrate. The concave pads are recessed downward relative to the upper surface of the substrate, and the convex pads are convex upward relative to the upper surface of the substrate. The first chip is mounted onto the substrate and electrically connected via the solder pads. The second chip is attached to the first chip and electrically connected through the concave pad. Package it.

7. The chip packaging method according to claim 6, characterized in that, The substrate includes: An upper metal plate, a lower metal plate, and an intermediate layer located between the upper metal plate and the lower metal plate, the intermediate layer comprising a titanium layer and a tin layer.

8. The chip packaging method according to claim 7, characterized in that, The step of forming concave pads and convex pads on the surface of the substrate, wherein the concave pads are recessed downward relative to the upper surface of the substrate and the convex pads are convex upward relative to the upper surface of the substrate, includes: The substrate is stamped from its two opposing upper and lower surfaces. Photolithography and etching are performed on the upper surface of the stamped substrate to expose the central pad area and the surrounding pad area. After removing the photoresist, multiple raised pads are formed in the central pad area, and multiple concave pads are formed in the surrounding pad area.

9. The chip packaging method according to claim 7, characterized in that, After packaging is complete, the following steps are also included: During cutting, the connection of the lower metal plate is kept intact or only partially cut into the lower metal plate without completely severing it; The intermediate layer and the lower metal plate are peeled off from the upper metal plate.

10. The chip packaging method according to claim 6, characterized in that, The welding temperature during the encapsulation process is 200-220℃.

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