Chip test method based on integrating sphere and optical test system

Abstract

The invention discloses an integrating sphere-based chip test method and an optical test system, and the method comprises the steps: providing an integrating sphere, a first probe and a second probe, the integrating sphere comprises an upper housing and a lower housing which are detachably connected, the upper housing is provided with a first through hole, and the lower housing is provided with a second through hole and a third through hole; the first probe and the second probe respectively extend into the lower shell through the second through hole and the third through hole; placing a to-be-tested unpackaged chip on a bearing table in the lower shell, and enabling a light-emitting surface of the chip to deviate from the bearing table; coupling a first probe to a first bonding pad of the unpackaged chip to be tested and applying a first electric signal, coupling a second probe to a second bonding pad of the unpackaged chip to be tested and applying a second electric signal, and lightening the unpackaged chip to be tested; covering the upper shell on the lower shell; and installing an optical detector in the first through hole, and testing light emitted by the to-be-tested unpackaged chip by using the optical detector. According to the method, the steps of wire bonding, desoldering and the like on the unpackaged chip are not needed, and the chip test loss rate is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a chip testing method and optical testing system based on an integrating sphere. Background Technology

[0002] Traditional integrating spheres, as core devices in the field of optical measurement used to detect key optical parameters such as luminous flux, color temperature, and color rendering index of light sources, operate on the fundamental premise of a stable connection between the light source and the power supply. From an application perspective, traditional integrating spheres were initially designed to accommodate mature light source products with standardized packaging. These light sources generally have readily available, standardized power interfaces, such as the E27 / E14 threaded connectors used in incandescent and energy-saving lamps in household lighting, the G13 lamp holder interface used in LED tubes in commercial lighting, and the DC plug interface commonly used in industrial equipment. In actual testing, operators only need to connect the light source to the matching power supply through the standard interface, place the entire light source in the designated test position inside the integrating sphere, and then start the device to complete the measurement.

[0003] As a core component of next-generation micro-display and lighting technologies, Micro-LEDs differ fundamentally from traditional standardized light sources. Unpackaged Micro-LED chips typically exist as bare dies, with dimensions mostly in the micrometer range (commonly 5μm-50μm), and lack the standardized power interface of traditional light sources. These characteristics significantly limit the use of traditional integrating spheres for measuring unpackaged Micro-LEDs, including: (1) Since unpackaged Micro-LEDs lack a standard power interface, if optical testing is to be performed on a traditional integrating sphere, extremely fine power lines (usually gold or copper wires with a diameter of 0.01-0.05 mm) must be precisely soldered to the positive and negative pins of the Micro-LED chip by manual wire bonding to establish a circuit connection between the chip and the external power supply. After the wire bonding is completed, the Micro-LED chip with the power line must be fixed on a special fixture and then placed into the test area inside the integrating sphere. On the one hand, Micro-LED chips are small and fragile, and the wire bonding operation requires high-precision equipment and experienced operators. Slight carelessness may damage the chip electrodes. On the other hand, after the wire bonding is completed, the connection point between the power line and the chip pin is extremely weak. During the process of transferring the chip to the integrating sphere, adjusting the test position, or removing it later, slight external force pulling (such as airflow disturbance or slight shaking of the fixture) may cause the power line to break or even cause the solder joint to detach.

[0004] (2) The wire bonding operation performed to achieve power connection will have an irreversible impact on the original structure and performance of the Micro-LED chip. The Micro-LED chip after wire bonding cannot be restored to its original unpackaged state. This means that after the same batch of chips has completed the luminous flux and other parameter tests of the traditional integrating sphere, it cannot be used for subsequent reliability tests (such as high and low temperature cycling, damp heat aging), electrical performance tests (such as current-voltage characteristics, reverse leakage current) or packaging process verification, which is detrimental to the continuity of experiments. Summary of the Invention

[0005] The purpose of this invention is to provide a chip testing method and optical testing system based on an integrating sphere, so as to solve the problem of chip damage caused when using a traditional integrating sphere to perform optical testing on unpackaged micro-chips (such as Micro-LED chips).

[0006] The objective of this invention is achieved through the following technical solution: This invention provides a chip testing method based on an integrating sphere, comprising: An integrating sphere, a first probe, and a second probe are provided. The integrating sphere includes a detachably connected upper shell and a lower shell, which can be fitted together to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A support platform is provided inside the lower shell. The first probe extends into the lower shell through the second through hole, and the second probe extends into the lower shell through the third through hole. The unpackaged chip under test is placed on the carrier stage, with the light-emitting surface of the unpackaged chip under test facing away from the carrier stage; wherein the light-emitting surface of the unpackaged chip under test is provided with a first pad and a second pad; The first probe is coupled to the first pad, and the second probe is coupled to the second pad; A first electrical signal is applied to the first pad through the first probe, and a second electrical signal is applied to the second pad through the second probe to illuminate the unpackaged chip under test. The upper housing is then placed over the lower housing. A photodetector is installed in the first through-hole, and the photodetector is used to test the light emitted by the unpackaged chip under test.

[0007] As a further improvement of one embodiment of the present invention, before coupling the first probe to the first pad and the second probe to the second pad, the method further includes: Provide image observation equipment; The image observation device is moved directly above the unpackaged chip under test to observe the positions of the first probe, the second probe, the first pad, and the second pad, thereby aligning the first probe with the first pad and the second probe with the second pad.

[0008] As a further improvement to one embodiment of the present invention, the step of coupling the first probe to the first pad and the second probe to the second pad specifically includes: The processor controls the first probe to move it directly above the first pad based on the image provided by the image observation device, and controls the second probe to move it directly above the second pad. The processor controls the first probe to move downwards in a vertical direction until the tip of the first probe contacts the first pad and slides a first set distance on the surface of the first pad. The processor controls the second probe to move downwards in a vertical direction until the tip of the second probe contacts the second pad and slides a second predetermined distance on the surface of the second pad.

[0009] As a further improvement to one embodiment of the present invention, the step of applying a first electrical signal to the first pad through the first probe and applying a second electrical signal to the second pad through the second probe to illuminate the unpackaged chip under test specifically includes: A power supply device is provided, and the first probe and the second probe are respectively coupled to the power supply device; The power supply device is turned on by a processor so that it outputs the first electrical signal to the first probe and the second electrical signal to the second probe.

[0010] As a further improvement of one embodiment of the present invention, before the upper housing is covered onto the lower housing, the method further includes: Move the image observation device away from the lower housing.

[0011] As a further improvement of one embodiment of the present invention, a plurality of first locking structures are uniformly arranged in the circumferential region of the outer side wall of the upper housing near the first end face, and a plurality of second locking structures are uniformly arranged in the circumferential region of the outer side wall of the lower housing near the second end face, wherein the first locking structure and the second locking structure correspond one-to-one; the step of covering the lower housing with the upper housing specifically includes: The upper housing is placed over the lower housing, such that the lower end face of the upper housing and the upper end face of the lower housing are fitted together. Multiple fasteners are provided to fix the corresponding first locking structure and second locking structure to secure the upper housing and the lower housing.

[0012] As a further improvement of one embodiment of the present invention, the upper surface of the support platform is provided with a plurality of adsorption holes, and the step of placing the unpackaged chip to be tested on the support platform further includes: A processor controls the vacuum equipment to be turned on. The vacuum equipment's vacuum pipe is connected to the adsorption hole to fix the unpackaged chip under test onto the carrier platform.

[0013] As a further improvement to one embodiment of the present invention, the testing method further includes: A processor and a display are provided, the processor and the display being coupled to each other; The processor is coupled to the photodetector, and the processor is used to acquire and process the light test data obtained by the photodetector. The processed light test data is then displayed on the display.

[0014] As a further improvement of one embodiment of the present invention, the test parameters of the unpackaged chip under test include luminous flux, operating wavelength and spectral half width at half maximum. And / or, the photodetector is a spectrometer; And / or, the photodetector has an optical interface that is connected to the first through-hole.

[0015] The present invention also provides an optical testing system based on an integrating sphere, comprising: An integrating sphere includes a detachably connected upper shell and a lower shell, which are connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A support platform is used to place an unpackaged chip under test, and the support platform is disposed inside the lower housing; wherein, the unpackaged chip under test is an unpackaged optical chip, and the unpackaged chip under test includes a first pad and a second pad; First probe and second probe; A photodetector is disposed within the first through-hole; the photodetector is used to test the light emitted by the unpackaged chip under test. When testing the unpackaged chip under test, the first probe extends through the second through-hole into the lower housing and connects to the first pad of the unpackaged chip under test, and the second probe extends through the third through-hole into the lower housing and connects to the second pad of the unpackaged chip under test; the first probe and the second probe are respectively used to apply a first electrical signal to the first pad and a second electrical signal to the second pad to light up the unpackaged chip under test.

[0016] Compared with the prior art, the beneficial effects of the present invention include at least the following: The chip testing method based on an integrating sphere provided by the present invention includes: providing an integrating sphere, a first probe, and a second probe; the integrating sphere includes a detachably connected upper shell and a lower shell, the upper shell and the lower shell being able to cooperate to form a hollow cavity; the upper shell is provided with a first through hole, the lower shell is provided with a second through hole and a third through hole, and a support stage is provided inside the lower shell; the first probe extends into the lower shell through the second through hole, and the second probe extends into the lower shell through the third through hole; the unpackaged chip to be tested is placed on the support stage, with the light-emitting surface of the unpackaged chip to be tested facing away from the support stage; wherein, the light-emitting surface of the unpackaged chip to be tested is provided with a first pad and a second pad; the first probe is coupled to the first pad, and the second probe is coupled to the second pad; a first electrical signal is applied to the first pad through the first probe, and a second electrical signal is applied to the second pad through the second probe to light up the unpackaged chip to be tested; the upper shell is closed onto the lower shell; a photodetector is installed in the first through hole, and the photodetector is used to test the light emitted by the unpackaged chip to be tested. The chip testing method provided by this invention eliminates the need for complex steps such as wire bonding and desoldering of the unpackaged chip under test. Simply place the unpackaged chip under test on the carrier platform inside the lower housing, and apply an electrical signal using the first and second probes to light up the chip. While completing the test, it protects the structural and performance integrity of the unpackaged chip to the greatest extent, without affecting subsequent tests, significantly reducing the chip test loss rate, reducing chip sample consumption, and lowering testing costs. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a chip testing method based on an integrating sphere according to one embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an optical testing system according to one embodiment of the present invention; Figure 3 This is a cross-sectional view of an upper housing according to one embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a lower shell according to one embodiment of the present invention; Figure 5This is a schematic diagram of the structure of an optical testing system according to one embodiment of the present invention (before the upper housing is closed to the lower housing, and the image observation device is shown). Figure 6 This is a schematic diagram of an automated program control according to one embodiment of the present invention; Figure 7 This is a top view of an upper housing according to one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a lower housing according to one embodiment of the present invention (showing the support platform and the second power supply device). Figure 9 This is a schematic diagram of the structure of a first power supply device / second power supply device according to one embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of an integrating sphere according to one embodiment of the present invention.

[0018] In the figure: 1. Integrating sphere; 11. Upper shell; 111. First through hole; 112. First end face; 113. First locking structure; 114. Fastener; 12. Lower shell; 121. Second through hole; 122. Third through hole; 123. Second end face; 124. Second locking structure; 2. Support platform; 21. Support part; 22. Support part; 3. First power supply device; 31. First probe holder; 32. First probe; 4. Second power supply device; 41. Second probe holder; 42. Second probe; 5. Photodetector; 61. First light shield; 62. Second light shield; 7. Image observation equipment; 8. Light blocking plate; 100. Processor; 200. Robotic arm; 300. Vacuum equipment; 400. Power supply equipment; 500. Display. Detailed Implementation

[0019] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms indicating position and direction described herein are illustrative of the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this invention.

[0020] like Figure 1 As shown, the present invention provides a chip testing method based on an integrating sphere, comprising: S1: Provides an integrating sphere, a first probe, and a second probe. The integrating sphere includes a separate upper shell and a lower shell, which can be connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A support platform is provided inside the lower shell. The first probe extends into the lower shell through the second through hole, and the second probe extends into the lower shell through the third through hole.

[0021] S2: Place the unpackaged chip under test on the carrier stage, with the light-emitting surface of the unpackaged chip under test facing away from the carrier stage; wherein the light-emitting surface of the unpackaged chip under test is provided with a first pad and a second pad.

[0022] S3: Couple the first probe to the first pad and the second probe to the second pad.

[0023] S4: Apply a first electrical signal to the first pad through the first probe, and apply a second electrical signal to the second pad through the second probe to light up the unpackaged chip under test.

[0024] S5: Cover the lower shell with the upper shell.

[0025] S6: Install the photodetector in the first through hole and use the photodetector to test the light emitted by the unpackaged chip under test.

[0026] Compared to manual wire bonding, this invention not only allows for direct testing of unpackaged chips without the need for manual wire bonding, but also simplifies the operation. Furthermore, since the unpackaged chip under test is first placed in an integrating sphere and then electrically connected using two probes (the first and second probes), adverse consequences (such as broken power cables or solder joint detachment) due to external pulling are avoided at various stages (e.g., transferring the chip to the integrating sphere, adjusting the test position, or subsequent removal). This eliminates the need for repeated wire bonding, improving testing efficiency and convenience. Moreover, because manual wire bonding and desoldering of the unpackaged chip are eliminated, there is no irreversible impact on the original structure and performance of the unpackaged chip under test, allowing for direct subsequent reliability testing and reducing chip testing loss rate.

[0027] See also Figures 2-5 The integrating sphere 1 includes a detachably connected upper shell 11 and a lower shell 12, which can be connected to form a hollow cavity. The upper shell 11 and the lower shell 12 are hemispherical shells with the same shape and size. When the upper shell 11 and the lower shell 12 are connected, the upper shell 11 is located directly above the lower shell 12, and the hollow cavity formed by the connection of the upper shell 11 and the lower shell 12 is a hollow sphere. The center of the hollow sphere is located in the plane where the connection between the upper shell 11 and the lower shell 12 is located.

[0028] The upper housing 11 is provided with a first through hole 111, and the lower housing 12 is provided with a second through hole 121 and a third through hole 122. The first through hole 111 is used to install the photodetector 5, the second through hole 121 is used to install the first power supply device 3, and the third through hole 122 is used to install the second power supply device 4.

[0029] The first power supply device 3 includes a first probe 32, which extends into the lower housing 12 through a second through hole 121. The second power supply device 4 includes a second probe 42, which extends into the lower housing 12 through a third through hole 122.

[0030] Specifically, a support platform 2 is provided inside the lower housing 12, which is used to place the unpackaged chip to be tested.

[0031] In one embodiment, step S2 specifically includes: S21: Provides unpackaged chips to be tested.

[0032] The unpackaged chip under test has a light-emitting surface and a non-light-emitting surface opposite to the light-emitting surface, and the light-emitting surface of the unpackaged chip under test is provided with a first pad and a second pad.

[0033] The unpackaged chip to be tested can be an unpackaged Micro-LED (micro light-emitting diode) chip, OLED (organic light-emitting diode) chip, or QLED (quantum dot light-emitting diode) chip.

[0034] S22: Place the unpackaged chip under test on the support surface of the support platform 2, and make the light-emitting surface of the unpackaged chip under test face away from the support surface.

[0035] The present invention does not limit the method of placing the unpackaged chip under test on the carrier platform 2. The unpackaged chip under test can be picked up by controlling a robotic arm and placed on the carrier platform 2, or it can be placed on the carrier platform 2 by manual clamping.

[0036] See Figure 6 This embodiment provides a processor 100 and a robotic arm 200, and couples the processor 100 and the robotic arm 200 together. Specifically, the processor 100 and the robotic arm 200 are signal-connected, and the processor 100 sends control signals to the robotic arm 200 to control its movement. Specifically, a program controlling the robotic arm 200 runs in the processor 100. The processor 100 controls the robotic arm 200 to automatically pick up the unpackaged chip under test and move it onto the support platform 2. By automating the picking and placing of the unpackaged chip under test using the robotic arm 200, it is ensured that the unpackaged chip under test is placed in the same position on the support platform 2 during each test. This reduces the movement range of the first probe 32 and the second probe 42 in subsequent tests, improving testing efficiency.

[0037] In this embodiment, the upper surface of the support platform 2 is provided with multiple adsorption holes, specifically, multiple adsorption holes are provided on the side of the support platform 2 facing the upper housing 11 (i.e., the support surface). See [link to documentation]. Figure 6 This embodiment provides a processor 100 and a vacuum device 300, and the processor 100 and the vacuum device 300 are coupled together. Specifically, the processor 100 is signal-connected to the vacuum device 300, and the processor 100 sends control signals to control the vacuum device 300 to start or stop. That is, after step S22, this embodiment further includes: S23: The processor 100 controls the vacuum device 300 to start. The vacuum pipe of the vacuum device 300 is connected to the adsorption hole to fix the unpackaged chip under test on the carrier stage 2.

[0038] When the unpackaged chip to be tested is placed on the carrier surface of the carrier platform 2, the unpackaged chip to be tested completely covers the multiple adsorption holes on the carrier surface (or the unpackaged chip to be tested is small and can only cover a portion of the adsorption holes; the remaining adsorption holes can be temporarily covered with tape or stickers).

[0039] After the unpackaged chip under test is placed on the support surface of the carrier stage 2, the tester can control the vacuum equipment 300 to be turned on through the processor 100 to fix the unpackaged chip under test on the support surface of the carrier stage 2, so as to prevent the unpackaged chip under test from moving when the first probe 32 is coupled to the first pad and the second probe 42 is coupled to the second pad in subsequent test steps.

[0040] In one embodiment, the method further includes the following steps before step S3: A1: Provide image observation equipment 7.

[0041] A2: Move the image observation device 7 directly above the unpackaged chip under test to observe the positions of the first probe 32, the second probe 42, the first pad, and the second pad, thereby aligning the first probe 32 with the first pad and the second probe 42 with the second pad.

[0042] See Figure 5After fixing the unpackaged chip under test onto the support platform 2, the image observation device 7 can be moved directly above the chip. Using the real-time image transmitted by the image observation device 7, the relative distance between the image observation device 7 and the unpackaged chip under test can be readjusted until the specific positions of the first and second pads, the first probe 32, and the second probe 42 of the unpackaged chip under test can be clearly observed (or by adjusting the magnification of the image observation device 7 until the specific positions of the first and second pads, the first probe 32, and the second probe 42 of the unpackaged chip under test can be clearly observed), thereby aligning the first probe 32 with the first pad and the second probe 42 with the second pad.

[0043] In this embodiment, see Figure 6 The image observation device 7 is coupled to the processor 100, specifically through a signal connection. The processor 100 can acquire the real-time image transmitted by the image observation device 7 and send control signals to the image observation device 7 to control its movement based on the acquired image. The processor 100 moves the image observation device 7 from its initial position to a preset position directly above the unpackaged chip under test based on the acquired image. The processor 100 also controls and adjusts the magnification of the image observation device 7 to a preset magnification.

[0044] Of course, in other embodiments, the position of the image observation device 7 and the magnification of the image observation device 7 can also be adjusted manually.

[0045] Specifically, the image observation device 7 is a CCD camera.

[0046] In one embodiment, step S3 specifically includes: S31: The processor 100 controls the first probe 32 to move it directly above the first pad based on the image provided by the image observation device 7, and controls the second probe 42 to move it directly above the second pad.

[0047] See Figure 6 The first probe 32 and the second probe 42 are coupled to the processor 100, specifically, the first probe 32 and the second probe 42 are signal-connected to the processor 100, and the processor 100 sends control signals to the first probe 32 and the second probe 42 to control their movement. The processor 100 can acquire the image frame transmitted by the image magnification device 72 in real time and control the movement of the first probe 32 and the second probe 42 according to the image frame.

[0048] Specifically, the processor 100 acquires the image transmitted by the image observation device 7 and identifies the positional relationship between the first pad, the second pad, the first probe 32, and the second probe 42 in the image. By identifying the positional relationship between the first probe 32 and the first pad, and the second probe 42 and the second pad, the processor 100 controls the first probe 32 to move directly above the first pad, and controls the second probe 42 to move directly above the second pad.

[0049] S32: The processor 100 controls the first probe 32 to move downward in the vertical direction until the tip of the first probe 32 contacts the first pad and slides a first set distance on the surface of the first pad.

[0050] The processor 100 controls the first probe 32 to move vertically downwards until its tip touches the surface of the first pad. At this point, the processor 100 controls the first probe 32 to continue moving. Due to the obstruction of the first pad, the first probe 32 cannot move further downwards and will slide a certain distance along the surface of the first pad. When the processor 100 detects that the first probe 32 has slid a first predetermined distance on the surface of the first pad, the processor 100 controls the first probe 32 to stop moving. At this point, stable contact between the first probe 32 and the first pad is ensured.

[0051] S33: The processor 100 controls the second probe 42 to move downward in the vertical direction until the tip of the second probe 42 contacts the second pad and slides a second set distance on the surface of the second pad.

[0052] The processor 100 controls the second probe 42 to move vertically downwards until its tip touches the surface of the second pad. At this point, the processor 100 controls the second probe 42 to continue moving. Due to the obstruction of the second pad, the second probe 42 cannot move further downwards and will slide a certain distance along the surface of the second pad. When the processor 100 detects that the second probe 42 has slid a second predetermined distance on the surface of the second pad, the processor 100 controls the second probe 42 to stop moving. At this point, stable contact between the second probe 42 and the second pad is ensured.

[0053] In this way, by using the processor 100 to control the coupling of the first probe 32 to the first pad and the coupling of the second probe 42 to the second pad, it is possible to ensure stable contact between the first probe 32 and the first pad, and between the second probe 42 and the second pad, and also to reduce the damage to the pad caused by the probe being moved by human.

[0054] The present invention does not limit the first set distance and the second set distance, which can generally be set between tens of micrometers and more than one hundred micrometers. Specifically, the setting can be adjusted according to factors such as the type of the first probe 32 and the second probe 42 used in the actual test, the pad size of the unpackaged chip under test, and the test requirements.

[0055] In one embodiment, see Figure 6 The power supply device 400 is coupled to the processor 100, specifically, the power supply device 400 is signal-connected to the processor, and the processor 100 sends control signals to the power supply device 400 to control the power supply device 400 to turn on or off. Step S4 specifically includes: S41: Provide a power supply device 400, and couple the first probe 32 and the second probe 42 to the power supply device 400 respectively.

[0056] The power supply device 400 is located outside the integrating sphere 1. The side of the first probe 32 away from the first pad is connected to the power supply device 400 for signal transmission, and the side of the second probe 42 away from the second pad is connected to the power supply device 400 for signal transmission.

[0057] Understandably, the power supply device 400 is capable of outputting signals of at least two voltages (i.e., a first electrical signal and a second electrical signal); or, the power supply device 400 includes a first power supply and a second power supply, wherein the first power supply is used to generate the first electrical signal and the second power supply is used to generate the second electrical signal.

[0058] S42: The processor 100 controls the power supply device 400 to turn on, so that the power supply device 400 outputs a first electrical signal to the first probe 32 and a second electrical signal to the second probe 42.

[0059] After the first probe 32 and the second probe 42 are coupled to the power supply device 400, the processor 100 controls the power supply device 400 to turn on and outputs a first electrical signal to the first probe 32 and a second electrical signal to the second probe 42, respectively. The first probe 32 transmits the first electrical signal to the first pad, and the second probe 42 transmits the second electrical signal to the second pad. Thus, a positive voltage signal is applied to the first pad (connected to the P-region of the PN junction inside the unpackaged chip under test) by the first probe 32, and a reference voltage signal is applied to the second pad (connected to the N-region of the PN junction inside the unpackaged chip under test) by the second probe 42. This creates a positive bias electric field between the first and second pads, driving current from the first pad through the PN junction inside the unpackaged chip under test to the second pad, forming a closed loop. Under the action of the positive current, holes in the P-region and electrons in the N-region of the PN junction migrate to the depletion region and recombine. The energy released during recombination is output in the form of photons, thereby illuminating the unpackaged chip under test.

[0060] In this embodiment, the power supply device 400 is a source meter.

[0061] In one embodiment, step S42 is followed by moving the image observation device 7 away from the lower housing 12.

[0062] Specifically, the processor 100 controls the image observation device 7 and moves the image observation device 7 to its initial position away from the lower housing 12.

[0063] In one embodiment, see Figure 3 , Figure 4 , Figures 7-8 and Figure 10 Multiple first locking structures 113 are evenly arranged in the circumferential region of the outer side wall of the upper housing 11 near the first end face 112, and multiple second locking structures 124 are evenly arranged in the circumferential region of the outer side wall of the lower housing 12 near the second end face 123. The first locking structures 113 and the second locking structures 124 correspond one-to-one. Step S5 specifically includes: S51: Cover the upper housing 11 on top of the lower housing 12, and make the lower end face of the upper housing 11 and the upper end face of the lower housing 12 fit together.

[0064] The upper housing 11 is placed on top of the lower housing 12, so that the lower end face of the upper housing 11 and the upper end face of the lower housing 12 are in close contact, and the first locking structure 113 of the upper housing 11 and the second locking structure 124 of the lower housing 12 are aligned one by one.

[0065] S52: Provide multiple fasteners 114 to fix the fasteners 114 to the corresponding first locking structure 113 and second locking structure 124 to fix the upper housing 11 and the lower housing 12.

[0066] In one embodiment, combined with Figures 2-3 and Figure 7 Step S6 specifically includes: S61: Provides a photodetector 5, which has an optical interface that can be connected to the first through hole 111.

[0067] S62: Connect the optical interface of the photodetector 5 to the first through hole 111 of the upper housing 11 so that the photodetector 5 is installed in the first through hole 111.

[0068] The unpackaged chip under test is placed on the stage 2, and the chip is lit up using the first probe 32 and the second probe 42. The light emitted by the unpackaged chip under test undergoes multiple diffuse reflections through the inner wall of the integrating sphere 1, forming a uniform light field inside the integrating sphere 1. The photodetector 5 receives the light signal in the uniform light field and measures its optical parameters (such as luminous flux, operating wavelength, and spectral half width at half maximum).

[0069] Of course, in other embodiments, the photodetector 5 can be installed in the first through hole 111 first, and then the upper housing 11 with the photodetector 5 installed can be covered on top of the lower housing 12 to assemble a complete integrating sphere 1.

[0070] In this embodiment, the photodetector 5 is a spectrometer.

[0071] In one embodiment, see Figure 6 The above testing methods also include: S71: Provides a processor 100 and a display 500, which are coupled to each other.

[0072] The processor 100 and the display 500 are connected by a signal.

[0073] S72: Couple the processor 100 to the photodetector 5; use the processor 100 to acquire and process the light test data obtained by the photodetector 5, and display the processed light test data through the display 500.

[0074] The processor 100 and the photodetector 5 are connected by a signal.

[0075] In this embodiment, the test parameters used to test the unpackaged chip under test using the above-mentioned chip testing method based on integrating sphere include luminous flux, operating wavelength, and spectral half-width.

[0076] See Figures 2-10 The present invention also provides an optical testing system based on an integrating sphere, which can be applied to the chip testing method based on an integrating sphere described in any of the above embodiments. The optical testing system includes an integrating sphere 1, a stage 2, a first probe 32, a second probe 42, and a photodetector 5.

[0077] The integrating sphere 1 includes a detachably connected upper shell 11 and a lower shell 12, which are connected to each other to form a hollow cavity. The upper shell 11 and the lower shell 12 are hemispherical shells with the same shape and size. When the upper shell 11 and the lower shell 12 are connected, the upper shell 11 is located directly above the lower shell 12, and the hollow cavity formed by the connection of the upper shell 11 and the lower shell 12 is a hollow sphere. The center of the hollow sphere is located in the plane where the connection between the upper shell 11 and the lower shell 12 is located.

[0078] Specifically, the inner diameter of the integrating sphere 1 is 8cm-12cm, meaning that the inner wall diameter of both the upper shell 11 and the lower shell 12 is 8cm-12cm. For example, the inner diameter of the integrating sphere 1 can be 8cm, 8.3cm, 8.5cm, 8.8cm, 9cm, 9.3cm, 9.5cm, 9.8cm, 10cm, 10.3cm, 10.5cm, 10.8cm, 11cm, 11.3cm, 11.5cm, 11.8cm, or 12cm.

[0079] See Figures 2-4 The upper housing 11 is provided with a first through hole 111, and the lower housing 12 is provided with a second through hole 121 and a third through hole 122. The first through hole 111 is used to install the photodetector 5, the second through hole 121 is used to install the first power supply device 3, and the third through hole 122 is used to install the second power supply device 4.

[0080] Specifically, the diameter of the first through hole 111 is larger than the diameter of the second through hole 121. The diameter of the first through hole 111 can be 1cm-3cm, for example, 1cm, 1.3cm, 1.5cm, 1.8cm, 2cm, 2.3cm, 2.5cm, 2.8cm or 3cm.

[0081] Specifically, the diameters of the second through hole 121 and the third through hole 122 are equal, and can be 0.4cm-0.6cm. For example, 0.4cm, 0.43cm, 0.45cm, 0.48cm, 0.5cm, 0.53cm, 0.55cm, 0.58cm or 0.6cm.

[0082] See Figure 3 and Figure 4 The upper housing 11 and the lower housing 12 are provided with a first end face 112 and a second end face 123 facing each other, respectively. Both the first end face 112 and the second end face 123 are designed with a wavy structure. When the upper housing 11 and the lower housing 12 are connected, the first end face 112 and the second end face 123 fit together, that is, the wavy structure of the first end face 112 and the wavy structure of the second end face 123 are complementary. Specifically, the cross-section of the first end face 112 and the second end face 123 along the vertical plane is a wavy structure. In this way, when the upper housing 11 and the lower housing 12 are assembled together, the first end face 112 and the second end face 123 can "interlock" with each other, which can further prevent the light emitted by the unpackaged chip under test from escaping from the integrating sphere 1.

[0083] For example, the first end face 112 and the second end face 123 can be configured as wavy surfaces with a "sin" shape. Here, "sin" shape refers to the shape of the sine curve corresponding to the sine function.

[0084] See Figure 5 and Figure 8The support platform 2 is used to place the unpackaged chip under test, and it is located inside the lower housing 12. The unpackaged chip under test includes a first pad and a second pad, which can be the positive and negative terminals, respectively.

[0085] The support platform 2 includes a support part 21 and a support part 22 that are fixedly connected. The support part 21 is fixedly connected to the inner side wall of the lower housing 12, and the support part 22 is located above the support part 21.

[0086] In this embodiment, the support portion 21 is a support column, which includes a lower end face fixedly connected to the inner wall of the lower housing 12 and an upper end face fixedly connected to the carrier portion 22. The carrier portion 22 is a carrier platform fixed to the upper end face of the support column, and the upper end face of the support column is located at the center of the carrier platform. The side of the carrier portion 22 facing away from the support portion 21 is a carrier surface, which is used to place the unpackaged chip under test.

[0087] Specifically, the relative distance between the side of the support platform 2 facing the upper shell 11 and the center of the bottom end of the lower shell 12 is 2cm-5cm, that is, the relative distance between the bearing surface of the support platform 2 and the center of the bottom end of the lower shell 12 is 2cm-5cm. For example, the relative distance between the side of the support platform 2 facing the upper shell 11 and the center of the bottom end of the lower shell 12 can be 2cm, 2.3cm, 2.5cm, 2.8cm, 3cm, 3.3cm, 3.5cm, 3.8cm, 4cm, 4.3cm, 4.5cm, 4.8cm or 5cm.

[0088] Combination Figure 9 The first power supply device 3 includes a first probe holder 31 and a first probe 32 connected to the first probe holder 31. The first probe holder 31 supports the first probe 32, and the first probe 32 extends through a second through-hole 121 into the lower housing 12. The second power supply device 4 includes a second probe holder 41 and a second probe 42 connected to the second probe holder 41. The second probe holder 41 supports the second probe 42, and the second probe 42 extends through a third through-hole 122 into the lower housing 12. When testing the unpackaged chip under test, the first probe 32 extends through the second through-hole 121 into the lower housing 12 and connects to the first pad of the unpackaged chip under test. The second probe 42 extends through the third through-hole 122 into the lower housing 12 and connects to the second pad of the unpackaged chip under test. The first probe 32 and the second probe 42 are respectively used to apply a first electrical signal to the first pad and a second electrical signal to the second pad to illuminate the unpackaged chip under test.

[0089] In this embodiment, the second through hole 121 and the third through hole 122 are symmetrically arranged relative to the support platform 2, and the line connecting the center of the second through hole 121 and the center of the third through hole 122 intersects the extended line of the center of the support portion 21 of the support platform 2. That is, the first power supply device 3 and the second power supply device 4 are symmetrically arranged relative to the support platform 2.

[0090] In this embodiment, the second through-hole 121 and the third through-hole 122 are higher than the support platform 2, that is, the center of the second through-hole 121 and the center of the third through-hole 122 are both higher than the support surface of the support portion 22. When the unpackaged chip under test is placed on the support surface, the initial positions of the first probe 32 and the second probe 42 are both higher than the unpackaged chip under test, which makes it easier to control and adjust the position of the first probe 32 to couple with the first pad, and to control and adjust the position of the second probe 42 to couple with the second pad.

[0091] Specifically, the relative distances between the centers of the second through hole 121 and the third through hole 122 and the center of the bottom end of the lower housing 12 are 3.5cm-4.25cm. For example, the relative distances between the centers of the second through hole 121 and the third through hole 122 and the center of the bottom end of the lower housing 12 can be 3.5cm, 3.55cm, 3.6cm, 3.65cm, 3.7cm, 3.75cm, 3.8cm, 3.85cm, 3.9cm, 3.95cm, 4cm, 4.05cm, 4.1cm, 4.15cm, 4.2cm, or 4.25cm.

[0092] For example, the inner diameter of the integrating sphere 1 is 10cm, the relative distance between the side of the support platform 2 facing the upper housing 11 and the center of the bottom end of the lower housing 12 is 3.5cm, and the relative distance between the centers of the second through hole 121 and the third through hole 122 and the center of the bottom end of the lower housing 12 is 3.75cm. The diameter of the first through hole 111 is 2cm, and the diameters of the second through hole 121 and the third through hole 122 are both 0.5cm.

[0093] Of course, the inner walls of the upper housing 11 and the lower housing 12 are both provided with a high diffuse reflection coating, such as a reflective coating made of barium sulfate, polytetrafluoroethylene, etc., so that when the unpackaged chip under test is lit up and the upper housing 11 and the lower housing 12 are connected to form an integrating sphere 1, the light emitted by the unpackaged chip under test can undergo multiple diffuse reflections on the inner wall surface of the integrating sphere 1, forming a uniform light field in the integrating sphere 1. That is, the light intensity at any position and in any direction in the integrating sphere 1 is basically the same, eliminating the problem of the initial light emission direction difference and intensity unevenness of the unpackaged chip under test.

[0094] A photodetector 5 is disposed within the first through-hole 111. The photodetector 5 receives and tests the light emitted by the unpackaged chip under test. Specifically, the photodetector 5 has an optical interface, and a threaded interface is sealed and connected to the first through-hole 111. When the unpackaged chip under test is illuminated, the photodetector 5 is installed at the first through-hole 111. The optical interface of the photodetector 5 completely seals the threaded interface at the first through-hole 111, preventing the light emitted by the illuminated unpackaged chip from escaping from the first through-hole 111. The threaded interface at the first through-hole 111 is a standard interface for a light source receiver, compatible with different types of light source receivers.

[0095] In this embodiment, the center of the first through hole 111 is located on the central axis of the upper housing 11, and the center of the support platform 2 is located on the central axis of the lower housing 12. That is, the center of the first through hole 111 is located at the top center of the upper housing 11, and the support platform 2 is located directly below the first through hole 111. In other words, in the vertical direction, the center of the projection of the first through hole 111 onto the support surface of the support platform 2 coincides with the center of the support surface. In other words, when the photodetector 5 is installed at the first through hole 111, the optical interface of the photodetector 5 is located directly above the support platform 2 (the unpackaged chip under test).

[0096] It should be noted that, see Figure 3 In this embodiment, the optical testing system also includes a light-blocking plate 8, which is spaced out directly below the first through hole 111. The light-blocking plate 8 is used to prevent the photodetector 5 from directly receiving the direct light emitted by the unpackaged chip under test, and to ensure that the photodetector 5 receives the uniform diffuse reflected light.

[0097] The present invention does not limit the fixing method of the light-blocking plate 8. It can be fixed to the inner side wall of the upper housing 11 by a fixing structure, ensuring that the light-blocking plate 8 is fixed parallel to the bottom of the first through hole 111 and has a certain distance from the first through hole 111. Of course, the present invention does not limit the shape and size of the light-blocking plate 8, as long as the surface size of the light-blocking plate 8 is larger than the radial size of the first through hole 111, and in the vertical direction, the projection of the first through hole 111 onto the surface of the light-blocking plate 8 falls completely on the surface of the light-blocking plate 8, so as to completely avoid the possibility of the photodetector 5 receiving direct light from the unpackaged chip under test.

[0098] Combination Figure 5 and Figure 8A first light-shielding plate 61 is fixedly connected to the first probe 32 near the second through-hole 121. The side of the first light-shielding plate 61 facing the second through-hole 121 is also connected to the inner wall of the lower housing 12 located around the second through-hole 121. Specifically, the curvature of the side of the first light-shielding plate 61 facing the second through-hole 121 matches the curvature of the inner wall of the lower housing 12 located around the second through-hole 121. The first light-shielding plate 61 completely blocks the gap between the second through-hole 121 and the first probe 32 on the inner wall of the lower housing 12, preventing light emitted from the unpackaged chip under test from escaping through the second through-hole 121. The second probe 42 is fixedly connected to a second light-shielding plate 62 near the third through-hole 122. The side of the second light-shielding plate 62 facing the third through-hole 122 is also connected to the inner wall of the lower housing 12 located around the third through-hole 122. Specifically, the curvature of the side of the second light-shielding plate 62 facing the third through-hole 122 matches the curvature of the inner wall of the lower housing 12 located around the third through-hole 122. The second light-shielding plate 62 completely blocks the gap between the third through-hole 122 and the second probe 42 on the inner wall of the lower housing 12, preventing light emitted from the unpackaged chip under test from escaping through the third through-hole 122.

[0099] Specifically, the first light-shielding plate 61 and the second light-shielding plate 62 are flexible light-shielding plates. Since the side of the first light-shielding plate 61 facing the second through-hole 121 is fixedly connected to the inner wall of the lower housing 12, it can be stretched and deformed during the adjustment of the position of the first probe 32. Similarly, since the side of the second light-shielding plate 62 facing the third through-hole 122 is fixedly connected to the inner wall of the lower housing 12, it can be stretched and deformed during the adjustment of the position of the second probe 42. By making the first light-shielding plate 61 and the second light-shielding plate 62 flexible light-shielding plates, they possess a certain elastic deformation capability, ensuring that the second through-hole 121 and the third through-hole 122 are completely blocked without affecting the movement of the first probe 32 and the second probe 42.

[0100] Of course, it should be noted that in this embodiment, the initial positions of the tips of the first probe 32 and the second probe 42 are close to the bearing surface of the bearing platform 2. That is, in subsequent testing, only a small degree of adjustment is needed to the positions of the first probe 32 and the second probe 42. The deformation of the first light shield 61 and the second light shield 62 during the adjustment of the first probe 32 and the second probe 42 is small.

[0101] In one embodiment, the first light-shielding plate 61 and the second light-shielding plate 62 are made of silicone.

[0102] In another embodiment, the upper housing 11 and the lower housing 12 are made of metal, such as iron or copper, and the first light-shielding plate 61 and the second light-shielding plate 62 are made of soft magnetic material. That is, the side of the first light-shielding plate 61 facing the second through hole 121 is magnetically connected to the inner wall of the lower housing 12 located around the second through hole 121, and the side of the second light-shielding plate 62 facing the third through hole 122 is magnetically connected to the inner wall of the lower housing 12 located around the third through hole 122.

[0103] Thus, by setting the first light-shielding plate 61 and the second light-shielding plate 62, light inside the integrating sphere 1 is prevented from escaping from the second through hole 121 and the third through hole 122. By setting a threaded interface at the first through hole 111, the optical interface of the photodetector 5 can be sealed and installed at the threaded interface to prevent light inside the integrating sphere 1 from escaping from the first through hole 111. Furthermore, by setting the first end face 112 and the second end face 123 as an interlocking structure with a wave-like shape, light inside the integrating sphere 1 is prevented from escaping from the junction of the first end face 112 and the second end face 123. That is, the integrating sphere 1 provided by the present invention is a sealed sphere, which can avoid the risk of light escaping from the unpackaged chip under test and improve the accuracy of optical chip testing.

[0104] Further, see Figures 3-4 , Figures 7-8 and Figure 10 The outer side wall of the upper housing 11 has a plurality of first locking structures 113 evenly arranged in the circumferential area near the first end face 112, and the outer side wall of the lower housing 12 has a plurality of second locking structures 124 evenly arranged in the circumferential area near the second end face 123. The first locking structures 113 and the second locking structures 124 correspond one-to-one. The optical testing system also includes a plurality of fasteners 114 corresponding one-to-one with the first locking structures 113. When the upper housing 11 and the lower housing 12 are connected, the fasteners 114 pass through the corresponding first locking structures 113 and second locking structures 124 to fix the relative positions of the upper housing 11 and the lower housing 12.

[0105] In this embodiment, the number of first locking structures 113 and second locking structures 124 is set to four. The four first locking structures 113 are evenly distributed on the outer side wall of the upper housing 11, that is, the angle formed by the line connecting two adjacent first locking structures 113 and the center of the integrating sphere is 90°; the four second locking structures 124 are evenly distributed on the outer side wall of the lower housing 12, that is, the angle formed by the line connecting two adjacent second locking structures 124 and the center of the integrating sphere is 90°.

[0106] In this embodiment, the number of fasteners 114 is also set to four, and the fasteners 114 can be bolts. The first locking structure 113 and the second locking structure 124 are also provided with threaded structures that cooperate with the bolts.

[0107] Of course, the present invention does not limit the number of the first locking structure 113, the second locking structure 124 and the fastener 114, or the type of the fastener 114, as long as the fastener 114 can fix the first locking structure 113 and the second locking structure 124.

[0108] Further, see Figure 6 In this embodiment, the optical testing system also includes a power supply device 400. The first probe 32 and the second probe 42 are respectively coupled to the power supply device 400. The power supply device 400 is used to transmit a first electrical signal to the first pad of the unpackaged chip under test through the first probe 32, and to transmit a second electrical signal to the second pad of the unpackaged chip under test through the second probe 42.

[0109] Specifically, understandably, the first probe 32 and the second probe 42 can also be directly electrically connected to an external power supply device. Alternatively, in combination... Figure 9 The first probe holder 31 has a first conductive structure for electrical connection with the first probe 32. The first probe holder 31 also has a first external wiring port for connecting to the first conductive structure. By connecting the first external wiring port to the power supply device 400, the power supply device 400 can transmit a first electrical signal to the first probe 32. Similarly, the second probe holder 41 has a second conductive structure for electrical connection with the second probe 42. The second probe holder 41 also has a second external wiring port for connecting to the second conductive structure. By connecting the second external wiring port to the power supply device 400, the power supply device 400 can transmit a second electrical signal to the second probe 42. Thus, when the power supply device 400 is turned on, a first electrical signal is applied to the first pad through the first probe 32, and a second electrical signal is applied to the second pad through the second probe 42, causing the optical chip under test to emit light.

[0110] In this embodiment, the power supply device 400 is a source meter. The source meter transmits a first electrical signal to the first probe 32 and a second electrical signal to the second probe 42. The first probe 32 transmits the first electrical signal to the first pad, and the second probe 42 transmits the second electrical signal to the second pad.

[0111] Further, see Figure 6 In this embodiment, the optical testing system also includes a vacuum device 300. The support platform 2 has multiple adsorption holes on one side (i.e., the support surface) facing the upper housing 11. The vacuum device 300's vacuum pipe is connected to these adsorption holes. The vacuum device 300 is used to evacuate the multiple adsorption holes through the vacuum pipe to fix the unpackaged chip under test (DUT) onto the support surface, preventing the DUT from moving when the first probe 32 is coupled to the first pad and the second probe 42 is coupled to the second pad.

[0112] Of course, in this embodiment, the optical testing system also includes an operating table, and the lower housing 12, the first power supply device 3, and the second power supply device 4 are all fixed to the operating table. Specifically, the lower housing 12 can be integrally formed with the tabletop of the operating table, or the lower housing 12 can be magnetically fixed to the operating table by an external magnetic attraction device. The first probe holder 31 of the first power supply device 3 and the second probe holder 41 of the second power supply device 4 can be provided with magnetic attraction devices inside, that is, the first probe holder 31 and the second probe holder 41 are magnetically fixed to the operating table by their internal magnetic attraction devices.

[0113] Further, see Figure 5 In this embodiment, the optical testing system also includes an image observation device 7, which is fixed on the operating table. The image observation device 7 is used to observe the position of the unpackaged chip under test, the first probe 32, and the second probe 42 before the upper housing 11 is closed to the lower housing 12.

[0114] Further, see Figure 6 In this embodiment, the optical testing system also includes a processor 100 and a display 500 coupled to each other. The processor 100 is coupled to the photodetector 5 and is used to acquire and process the optical testing data obtained by the photodetector 5. The display 500 is used to display the optical testing data processed by the processor 100.

[0115] Specifically, the vacuum device 300, power supply device 400, first probe 32, second probe 42, image observation device 7, and photodetector 5 are respectively coupled to the processor 100. The processor 100 is also used to control the vacuum device 300 and power supply device 400 to turn on or off, control the movement of the first probe 32 and the second probe 42 and their respective coupling to the first pad and the second pad, and control the movement of the image observation device 7 and acquire the real-time image transmitted by the image observation device 7.

[0116] Further, see also Figure 6 In this embodiment, the optical testing system also includes a robotic arm 200, which is coupled to a processor 100. The processor 100 is also used to control the robotic arm 200 to move and pick up the unpackaged chip under test, and to control the robotic arm 200 to move and place the unpackaged chip under test on the support surface of the support platform 2.

[0117] In summary, the chip testing method provided by this invention eliminates the need for complex steps such as wire bonding and desoldering of the unpackaged chip under test. It simply requires placing the unpackaged chip under test on a support stage within the lower housing, and applying electrical signals using the first and second probes to illuminate the chip. This maximizes the protection of the structural and performance integrity of the unpackaged chip, significantly reduces chip testing loss rates, minimizes chip sample consumption, and lowers testing costs. Furthermore, the chip testing method provided by this invention employs an automated processing procedure, improving testing efficiency and accuracy.

[0118] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the invention without departing from the principles and spirit of the invention, and all such changes should fall within the protection scope of the claims of the present invention.

Claims

1. A chip testing method based on an integrating sphere, characterized in that, include: An integrating sphere, a first probe, and a second probe are provided. The integrating sphere includes a detachably connected upper shell and a lower shell, which can be connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A support platform is provided inside the lower shell. The first probe extends into the lower shell through the second through hole, and the second probe extends into the lower shell through the third through hole. The unpackaged chip under test is placed on the carrier stage, with the light-emitting surface of the unpackaged chip under test facing away from the carrier stage; wherein the light-emitting surface of the unpackaged chip under test is provided with a first pad and a second pad; The first probe is coupled to the first pad, and the second probe is coupled to the second pad; A first electrical signal is applied to the first pad through the first probe, and a second electrical signal is applied to the second pad through the second probe to illuminate the unpackaged chip under test. The upper housing is then placed over the lower housing. A photodetector is installed in the first through-hole, and the photodetector is used to test the light emitted by the unpackaged chip under test.

2. The chip testing method based on an integrating sphere according to claim 1, characterized in that, Before coupling the first probe to the first pad and the second probe to the second pad, the method further includes: Provide image observation equipment; The image observation device is moved directly above the unpackaged chip under test to observe the positions of the first probe, the second probe, the first pad, and the second pad, thereby aligning the first probe with the first pad and the second probe with the second pad.

3. The chip testing method based on an integrating sphere according to claim 2, characterized in that, The step of coupling the first probe to the first pad and the second probe to the second pad specifically includes: The processor controls the first probe to move it directly above the first pad based on the image provided by the image observation device, and controls the second probe to move it directly above the second pad. The processor controls the first probe to move downwards in a vertical direction until the tip of the first probe contacts the first pad and slides a first set distance on the surface of the first pad. The processor controls the second probe to move downwards in a vertical direction until the tip of the second probe contacts the second pad and slides a second predetermined distance on the surface of the second pad.

4. The chip testing method based on an integrating sphere according to claim 1, characterized in that, The step of applying a first electrical signal to the first pad through the first probe and applying a second electrical signal to the second pad through the second probe to illuminate the unpackaged chip under test specifically includes: A power supply device is provided, and the first probe and the second probe are respectively coupled to the power supply device; The power supply device is turned on by a processor so that it outputs the first electrical signal to the first probe and the second electrical signal to the second probe.

5. The chip testing method based on an integrating sphere according to claim 2, characterized in that, Before the upper housing is fitted onto the lower housing, the method further includes: Move the image observation device away from the lower housing.

6. The chip testing method based on an integrating sphere according to claim 1, characterized in that, The outer side wall of the upper housing has a plurality of first locking structures evenly arranged in a circumferential region near the first end face, and the outer side wall of the lower housing has a plurality of second locking structures evenly arranged in a circumferential region near the second end face, wherein the first locking structures and the second locking structures correspond one-to-one; the step of covering the lower housing with the upper housing specifically includes: The upper housing is placed over the lower housing, such that the lower end face of the upper housing and the upper end face of the lower housing are fitted together. Multiple fasteners are provided to fix the corresponding first locking structure and second locking structure to secure the upper housing and the lower housing.

7. The chip testing method based on an integrating sphere according to claim 1, characterized in that, The upper surface of the support platform is provided with multiple adsorption holes. The step of placing the unpackaged chip to be tested on the support platform further includes: A processor controls the vacuum equipment to be turned on. The vacuum equipment's vacuum pipe is connected to the adsorption hole to fix the unpackaged chip under test onto the carrier platform.

8. The chip testing method based on an integrating sphere according to claim 1, characterized in that, The testing method also includes: A processor and a display are provided, the processor and the display being coupled to each other; The processor is coupled to the photodetector, and the processor is used to acquire and process the light test data obtained by the photodetector. The processed light test data is then displayed on the display.

9. The chip testing method based on an integrating sphere according to claim 1, characterized in that, The test parameters for the unpackaged chip under test include luminous flux, operating wavelength, and spectral half-width. And / or, the photodetector is a spectrometer; And / or, the photodetector has an optical interface that is connected to the first through-hole.

10. A light testing system based on an integrating sphere, characterized in that, include: An integrating sphere includes a detachably connected upper shell and a lower shell, which are connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A support platform is used to place an unpackaged chip under test, and the support platform is disposed inside the lower housing; wherein, the unpackaged chip under test includes a first pad and a second pad; First probe and second probe; A photodetector is disposed within the first through-hole; the photodetector is used to test the light emitted by the unpackaged chip under test. When testing the unpackaged chip under test, the first probe extends through the second through-hole into the lower housing and connects to the first pad of the unpackaged chip under test, and the second probe extends through the third through-hole into the lower housing and connects to the second pad of the unpackaged chip under test; the first probe and the second probe are respectively used to apply a first electrical signal to the first pad and a second electrical signal to the second pad to light up the unpackaged chip under test.

Images