Task processing method and computer system

Abstract

The invention provides a task processing method and a computer system, the method is applied to the computer system, a processor of the computer system is provided with a first register, and the first register is used for storing the highest priority information of an interrupted task shielded by a user mode task; the method comprises the steps that when a processor receives an interrupt task in the process of executing a user state task, the priority of the interrupt task and priority information stored in a first register are acquired; and under the condition of determining that the user state task shielding interruption is started and the priority of the interruption task is lower than the priority information stored in the first register, the processor shields the interruption task. According to the method, the occurrence frequency that the user state task is preempted by the interrupted task can be reduced, and the performance of the user state task can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a task processing method and a computer system. Background Technology

[0002] In computer systems, when a processor executes user-mode tasks, there is a problem of interrupt preemption. For example, when a user-mode task is not running on an isolated processor core, the processor may receive various interrupts, including clock interrupts, inter-core interrupts, and device interrupts. When the processor receives these interrupts, it will pause the currently executing user-mode task and execute the task corresponding to the newly received interrupt. If the preempted task is holding a mutex lock, its preemption will block the execution of other tasks that are expecting to hold the lock, thus affecting the performance of that task. Therefore, it is necessary to control and handle interrupts when the processor executes user-mode tasks to avoid affecting the performance of user-mode tasks holding mutex locks. Summary of the Invention

[0003] Based on the above-mentioned technological status, this application provides a task processing method and a computer system that can reduce the frequency of user-mode tasks being preempted by interrupted tasks, thereby improving the performance of user-mode tasks, especially the performance of user-mode tasks that are holding mutex locks.

[0004] The first aspect of this application provides a task processing method applied to a computer system, wherein the processor of the computer system is provided with a first register, the first register being used to store the highest priority information of interrupts that are masked by user-mode tasks; The method includes: When the processor receives an interrupt during the execution of a user-mode task, it obtains the priority of the interrupt and the priority information stored in the first register. If it is determined that interrupt masking is enabled for user-mode tasks, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt.

[0005] In some implementations, the processor is further provided with a second register, which is used to store enable information for user-mode task masking interrupts; When the processor receives an interrupt during the execution of a user-mode task, it also acquires the enable information stored in the second register; wherein the enable information in the second register is written by the user-mode task. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: The enable information stored in the second register indicates that interrupt masking for user-mode tasks is enabled, and the processor masks the interrupt if the priority of the interrupt is lower than the priority information stored in the first register.

[0006] In some implementations, the processor is further provided with a third register and a timer, wherein the third register is used to store the duration of user-mode task masking interrupts; The method further includes: When the processor detects that the user-mode task interrupt masking is enabled, it obtains the duration of the timer. When the timer's duration is zero, the processor starts the timer and sets the target duration of the timer to the duration stored in the third register.

[0007] In some implementations, the processor is further provided with a second register, which is used to store enable information for user-mode task masking interrupts; When the processor detects that user-mode task masking interrupts are enabled, it obtains the duration of the timer, including: When the processor detects that enable information indicating that user-mode task masking interrupts are enabled has been written into the second register, it obtains the duration of the timer. In some implementations, when it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the timer's duration has not reached the duration stored in the third register, and the interrupt's priority is lower than the priority information stored in the first register, the processor disables the interrupt.

[0008] In some implementations, after the processor starts the timer to begin timing, the method further includes: The timer is paused when the processor switches from executing the user-mode task to executing the kernel-mode task; as well as, When the processor switches from executing a kernel-mode task to continuing to execute a user-mode task, the timer is resumed and continues counting.

[0009] In some implementations, the processor is also provided with a fourth register for storing interrupt masking priority information, which indicates the lowest priority of the interrupts that the processor responds to in real time. The method further includes: When the processor selects to respond to an interrupt according to the value in the first register at its current privilege level, and when the processor detects that user-mode task masking interrupts are enabled, the processor updates the priority information stored in the first register to the fourth register. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If it is determined that interrupt masking is enabled for user-mode tasks, and the priority of the interrupt is lower than the priority information stored in the fourth register, the processor masks the interrupt.

[0010] In some implementations, the processor is also provided with a fourth register for storing interrupt masking priority information, which indicates the lowest priority of the interrupts that the processor responds to in real time. The method further includes: If the processor selects to respond to an interrupt according to the value in the first register at its current privilege level, and the processor detects that an enable message indicating that user-mode task masking interrupts are enabled has been written into the second register, the processor updates the priority information stored in the first register to the fourth register. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the timer's duration has not reached the duration stored in the third register, and the interrupt's priority is lower than the priority information stored in the fourth register, the processor masks the interrupt.

[0011] In some implementations, the method further includes: When the processor switches from executing the user-mode task to executing the kernel-mode task, the processor updates the interrupt mask priority information stored in the fourth register to the initial priority; or, When the processor switches from executing a kernel-mode task to continuing to execute a user-mode task, and the timer's duration has not reached the duration stored in the third register, the processor updates the priority information stored in the first register to the fourth register. or, When the timer reaches the duration stored in the third register, the processor updates the interrupt mask priority information stored in the fourth register to the initial priority.

[0012] In some implementations, the method further includes: When the timer reaches the duration stored in the third register, and / or the enable information stored in the second register is updated to indicate that user-mode task interrupt masking is disabled, the processor executes the task corresponding to the interrupt.

[0013] In some implementations, the method further includes: If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is not lower than the priority information stored in the first register, the processor executes the task corresponding to the interrupt.

[0014] In some implementations, the method further includes: After the processor finishes executing the task corresponding to the interrupt, it continues to execute the user-mode task. Alternatively, the processor executes the task corresponding to the interrupt through the first processor core and the user-mode task through the second processor core.

[0015] In some implementations, the processor is further provided with a fifth register; the fifth register is used to store interrupt masking priority, which represents the lowest priority of interrupts that the processor responds to in real time; If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the processor's current privilege level does not select to respond to an interrupt according to the value of the fifth register, and the user-mode task interrupt masking is enabled, then if the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt.

[0016] In some implementations, the processor is further provided with a fifth register; the fifth register is used to store interrupt masking priority, which represents the lowest priority of interrupts that the processor responds to in real time; If the timer's duration has not reached the duration stored in the third register, and the interrupt's priority is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the processor does not select to respond to the interrupt according to the value of the fifth register at its current privilege level, and the timer duration has not reached the duration stored in the third register, then the processor masks the interrupt if the priority of the interrupt is lower than the priority information stored in the first register.

[0017] In some implementations, the method further includes: If the processor selects to respond to an interrupt according to the value of the fifth register at its current privilege level, and the priority of the interrupt is not lower than the priority information stored in the fifth register, the processor executes the task corresponding to the interrupt. or, If the processor's current privilege level does not select to respond to the interrupt according to the value of the fifth register, and the timer's duration reaches the duration stored in the third register, the processor suspends the user-mode task and executes the task corresponding to the interrupt.

[0018] The second aspect of this application provides a computer system in which a first register is provided in the processor of the computer system. The first register is used to store the highest priority information of interrupts that are masked by user-mode tasks. The computer system is configured to implement the task processing method described above.

[0019] The task processing method provided in this application allows user-mode tasks to enable interrupt masking, and sets a first register in the processor to store the highest priority information of interrupt tasks masked by user-mode tasks. Based on the above settings, when the processor receives an interrupt task during the execution of a user-mode task, the processor masks the interrupt task if it confirms that interrupt masking is enabled and the priority of the interrupt task is lower than the priority information stored in the first register. It is evident that the above operation enables user-mode tasks to mask some low-priority interrupts, thereby reducing the frequency of interrupt preemption for user-mode tasks and improving their performance. For user-mode tasks currently holding a mutex lock, the above scheme can prevent the blocking of other tasks that wish to hold the same mutex lock due to preemption, thus ensuring the performance of user-mode tasks currently holding the mutex lock. Moreover, the above interrupt masking operation only masks some low-priority interrupts during the execution of user-mode tasks; high-priority interrupts can still be responded to by the processor in real time. Therefore, system malfunctions will not occur due to the processor not handling any interrupts during the execution of user-mode tasks. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating a task processing method provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the internal architecture of a processor provided in an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of another processor internal architecture provided for an embodiment of this application. Detailed Implementation

[0024] The technical solutions of this application are applicable to application scenarios where the processor switches between user mode and kernel mode. By adopting the technical solutions of this application, the processor can avoid being interrupted by unimportant interrupts when executing user mode tasks, and can respond to important interrupts in a timely manner, thereby improving the running performance of user mode tasks.

[0025] In a computer system, when the processor is running in user mode and executing user-mode tasks, there is a problem of user-mode tasks being interrupted and preempted. For example, when a user-mode task is not running on an isolated processor core, the processor may receive many types of interrupts, including clock interrupts, inter-core interrupts, and device interrupts. When the processor receives these interrupts, it will suspend the currently executing user-mode task and execute the task corresponding to the newly received interrupt. If the preempted task is holding a mutex lock, its preemption will block the execution of other tasks that expect to hold the lock, thereby affecting the performance of that task.

[0026] To address the aforementioned technical issues, some existing solutions globally disable all interrupts when the processor is executing user-mode tasks, meaning the processor does not respond to any interrupts while executing user-mode tasks to ensure their smooth operation. However, these solutions also disable real-time-related interrupts, thus impacting system real-time performance.

[0027] To address the aforementioned technical problems, embodiments of this application provide a task processing scheme for computer systems. This scheme enables the processor to reasonably and temporarily disable some low-priority interrupts when executing user-mode tasks, thereby improving the performance of user-mode tasks while avoiding user-mode task anomalies.

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] This application first provides a task processing method applied to a computer system, specifically to the processor of that computer system. The processor of the computer system includes one or more processor cores. The processor supports setting priorities for each interrupt, and an Interrupt Prioritization Mask Register (IPMR register) is provided in the processor to set the minimum priority of interrupts that the processor can respond to in real time. When the priority of an interrupt received by the processor is higher than the interrupt priority information stored in the IPMR register, the processor suspends the executed user-mode task and responds to the interrupt; when the priority of an interrupt received by the processor is not higher than the interrupt priority information stored in the IPMR register, the processor masks the interrupt and can respond to it when idle.

[0030] In addition, the processor of the computer system provided in this embodiment is also provided with a first register, wherein the first register is used to store the highest priority information of interrupts that are masked by user-mode tasks.

[0031] Specifically, the highest priority information of interrupts masked by user-mode tasks is written to the first register when the processor is in kernel mode. For example, when a user-mode application determines that it does not want to be interrupted, it can send an interrupt masking request to the kernel-mode operating system. The kernel-mode operating system, combining the system's temporarily maskable interrupt priority information and the user-mode application's real-time priority status, determines the highest priority of interrupts that can be masked by the user-mode application and writes this highest priority information to the first register. The kernel-mode operating system's write operation to the first register can be performed when the computer system starts or when a user-mode task starts running.

[0032] Based on the settings of the first register described above, the task processing method provided in this embodiment allows the user-mode task interrupt masking function to be enabled during the execution of user-mode tasks by the processor.

[0033] For example, when a user-mode task needs to disable interrupts during operation, it can send an interrupt-disable enable instruction to the processor. When the processor receives this instruction, it can determine that the interrupt-disable function of the user-mode task is enabled. When the user-mode task sends an interrupt-disable disable instruction to the processor, the processor can determine that the interrupt-disable function of the user-mode task is disabled.

[0034] Alternatively, an interrupt masking timer can be set during processing. When a user-mode task needs to enable interrupt masking, a timer start value is written to this timer. This timer start value represents the duration for which the user-mode task requests interrupt masking. The processor can determine whether this timer start value is less than a predefined maximum value. If it is less, the timer is allowed to start, indicating that the user-mode task's interrupt masking function is enabled. If it is not less, the timer is prevented from starting, indicating that the user-mode task's interrupt masking function is disabled. In other words, this limitation allows the processor to control the duration for which the user-mode task has interrupt masking enabled, preventing the user-mode task from disabling interrupts for extended periods.

[0035] In the task processing method provided in this embodiment, when the processor confirms that user-mode task interrupt masking is disabled, the processor determines whether to respond to the received interrupt according to the lowest priority information of the interrupts that the processor can respond to in real time, which is stored in the interrupt priority mask register. For example, when the processor receives an interrupt while executing the current task, it compares the priority of the interrupt with the priority information stored in the interrupt priority mask register. If the priority of the interrupt is higher than the priority information stored in the interrupt priority mask register, the processor suspends the currently executing task and responds to the interrupt; if the priority of the interrupt is not higher than the priority information stored in the interrupt priority mask register, the processor can mask the interrupt and respond to it after the current task is completed or when idle.

[0036] When the processor confirms that user-mode task-masked interrupts are enabled, it determines whether to respond to the received interrupt in real time based on the highest priority information of the interrupts masked by user-mode tasks stored in the first register. At this time, the lowest priority information of the interrupts that the processor can respond to in real time, stored in the interrupt priority mask register, is temporarily invalidated.

[0037] Specifically, in the task processing method provided in this embodiment, when the processor receives an interrupt during the execution of a user-mode task, it obtains the priority of the interrupt and the priority information stored in the first register.

[0038] If it is determined that interrupt masking is enabled for user-mode tasks, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt.

[0039] The aforementioned user-mode tasks refer to tasks executed by the processor when it is in user mode. For example, the process of the processor running a user-mode application in user mode is the process of the processor executing a user-mode task.

[0040] During the execution of this user-mode task by the processor, when the processor receives an interrupt, it first obtains the priority information of the interrupt, and at the same time, obtains the priority information stored in the first register.

[0041] As described in the above embodiments, the priority information stored in the first register is the highest priority information of the interrupt that is masked by the user-mode task.

[0042] After obtaining the interrupt priority and the priority information stored in the first register, the processor further determines whether the user-mode task interrupt masking function is enabled, and compares the interrupt priority with the priority information stored in the first register.

[0043] The processor determines whether the user-mode task interrupt masking function is enabled by verifying whether it has received an interrupt masking enable command or whether the interrupt masking timer is in a valid timing state. If the processor receives an interrupt masking enable command but does not receive an interrupt masking disable command, the user-mode task interrupt masking function is enabled; if the processor does not receive an interrupt masking enable command, the user-mode task interrupt masking function is disabled. Similarly, if the interrupt masking timer is in a valid timing state, the user-mode task interrupt masking function is enabled; if the interrupt masking timer is in an invalid state, such as not starting or paused, the user-mode task interrupt masking function is disabled.

[0044] When the processor confirms that interrupt masking is enabled for user-mode tasks, it should mask interrupts with a priority lower than the priority information stored in the first register.

[0045] In this situation, the processor compares the priority of the received interrupt with the priority information stored in the first register. If the priority of the received interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, meaning it does not respond to the interrupt and continues executing the user-mode task. The interrupt can be responded to again when the user-mode task ends or when the processor is idle.

[0046] In another embodiment, it is disclosed that if the priority of the interrupt received by the processor is not lower than the priority information stored in the first register, it indicates that the priority of the interrupt is higher, which means that the interrupt is more urgent. At this time, the processor suspends the currently executing user-mode task and begins to respond to the interrupt.

[0047] In another embodiment, it is also disclosed that if the priority of the interrupt received by the processor is not lower than the priority information stored in the first register, the processor suspends the currently executing user-mode task, begins to respond to the interrupt, and resumes the execution of the suspended user-mode task after the interrupt response is completed.

[0048] Alternatively, in another embodiment, when the processor suspends the currently executing user-mode task and begins responding to an interrupt, it can execute the user-mode task and the interrupt-corresponding task separately through different processor cores. For example, assuming the user-mode task was originally executed by the first processor core, when the processor decides to execute the task corresponding to the received interrupt, the first processor core can execute the interrupt-corresponding task, while the user-mode task is switched to another processor core, such as the second processor core, to continue executing the user-mode task.

[0049] Alternatively, in another embodiment, when the processor receives an interrupt with a priority higher than the priority information stored in the first register during the execution of a user-mode task, it is considered that the user-mode task interrupt masking is disabled. At this time, the processor responds to the interrupt and processes the user-mode task according to the processing mechanism set by the system.

[0050] As described above, the task processing method provided in this application allows user-mode tasks to enable interrupt masking, and a first register is set in the processor to store the highest priority information of interrupts masked by user-mode tasks. Based on the above settings, when the processor receives an interrupt during the execution of a user-mode task, the processor masks the interrupt if it confirms that interrupt masking is enabled and the interrupt priority is lower than the priority information stored in the first register. This operation enables user-mode tasks to mask some low-priority interrupts, thereby reducing the frequency of interrupt preemption and improving the performance of user-mode tasks. For user-mode tasks currently holding a mutex lock, the above solution avoids blocking the execution of other tasks that wish to hold the same mutex lock due to preemption, thus ensuring the performance of user-mode tasks currently holding the mutex lock. Moreover, the interrupt masking operation only masks some lower-priority interrupts during the execution of user-mode tasks; high-priority interrupts can still be responded to by the processor in real time. Therefore, system malfunctions will not occur due to the processor not handling any interrupts during the execution of user-mode tasks.

[0051] In another embodiment of the computer system processor, a second register is also provided, wherein the second register is used to store enable information for user-mode task masking interrupts.

[0052] The aforementioned second register can be written to by the user-mode task during execution. That is, during runtime, the user-mode task can enable or disable the user-mode task interrupt masking function by writing enable information to the second register. For example, when a user-mode task writes enable information indicating that the user-mode task interrupt masking is enabled to the second register, the processor can confirm that the user-mode task interrupt masking function is enabled through the value of the second register; conversely, when a user-mode task writes enable information indicating that the user-mode task interrupt masking is disabled to the second register, the processor can confirm that the user-mode task interrupt masking function is disabled through the value of the second register.

[0053] In the task processing method provided in this embodiment, when the enable information stored in the second register indicates that user-mode task interrupt masking is disabled, the processor determines whether to respond to the received interrupt in real time according to the lowest priority information of the interrupts that the processor can respond to in real time, which is stored in the interrupt priority mask register. For example, when the processor receives an interrupt during the execution of the current task, it compares the priority of the interrupt with the priority information stored in the interrupt priority mask register. If the priority of the interrupt is higher than the priority information stored in the interrupt priority mask register, the processor suspends the currently executing task and responds to the interrupt; if the priority of the interrupt is not higher than the priority information stored in the interrupt priority mask register, the processor can mask the interrupt and respond to it after the current task is completed or when idle.

[0054] When the enable information stored in the second register indicates that user-mode task interrupt masking is enabled, the processor determines whether to respond to the real-time received interrupt according to the highest priority information of the interrupts masked by user-mode tasks stored in the first register. At this time, the lowest priority information of the interrupts that the processor can respond to in real time, stored in the interrupt priority mask register mentioned above, is temporarily invalidated.

[0055] For details, see Figure 1 As shown, the task processing method provided in this embodiment includes the following processing steps: S101. When the processor receives an interrupt during the execution of a user-mode task, it obtains the priority of the interrupt, the priority information stored in the first register, and the enable information stored in the second register.

[0056] The aforementioned user-mode tasks refer to tasks executed by the processor when it is in user mode. For example, the process of the processor running a user-mode application in user mode is the process of the processor executing a user-mode task.

[0057] The enable information in the second register is written by the user-mode task. For example, when the user-mode task starts running, it can first write enable information indicating that the user-mode task's interrupt masking is enabled to the second register; or, during the operation of the user-mode task, when it is confirmed that interrupt masking is required, it can write enable information indicating that the user-mode task's interrupt masking is enabled to the second register.

[0058] Based on the above operations, when the processor receives an interrupt during the execution of the user-mode task, it first obtains the priority information of the interrupt, and at the same time, obtains the priority information stored in the first register and the enable information stored in the second register.

[0059] As described in the above embodiments, the priority information stored in the first register is the highest priority information of the interrupt that is masked by the user-mode task; the enable information stored in the second register is the enable information indicating whether the user-mode task is masking the interrupt.

[0060] After obtaining the interrupt priority, the priority information stored in the first register, and the enable information stored in the second register, the processor performs the following judgment process in step S102: S102. If the enable information stored in the second register indicates that the user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt.

[0061] Specifically, when the processor confirms that the enable information stored in the second register indicates that user-mode task interrupt masking is enabled, interrupts with a priority lower than that stored in the first register should be masked.

[0062] In this situation, the processor compares the priority of the received interrupt with the priority information stored in the first register. If the priority of the received interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, meaning it does not respond to the interrupt and continues executing the user-mode task. The interrupt can be responded to again when the user-mode task ends or when the processor is idle.

[0063] In another embodiment, it is disclosed that if the priority of the interrupt received by the processor is not lower than the priority information stored in the first register, it indicates that the priority of the interrupt is higher, which means that the interrupt is more urgent. At this time, the processor suspends the currently executing user-mode task and begins to respond to the interrupt.

[0064] In another embodiment, it is also disclosed that if the priority of the interrupt received by the processor is not lower than the priority information stored in the first register, the processor suspends the currently executing user-mode task, starts executing the interrupt, and resumes the execution of the suspended user-mode task after responding to the interrupt.

[0065] Alternatively, in another embodiment, when the processor suspends the currently executing user-mode task and begins responding to an interrupt, the user-mode task and interrupt handling can be executed separately by different processor cores. For example, assuming the user-mode task was originally executed by the first processor core, when the processor decides to handle a received interrupt, the first processor core can respond to the interrupt, while the user-mode task is switched to another processor core, such as the second processor core, to continue executing the user-mode task.

[0066] Alternatively, in another embodiment, when the processor receives an interrupt with a priority higher than the priority information stored in the first register during the execution of a user-mode task, it is considered that the user-mode task interrupt masking is disabled. At this time, the processor responds to the interrupt and processes the user-mode task according to the processing mechanism set by the system.

[0067] In another embodiment, the processor of the computer system also includes a third register and a timer.

[0068] The third register stores the duration for which user-mode tasks can mask interrupts. This duration limits how long a user-mode task can mask interrupts. If the duration is exceeded, user-mode tasks are no longer allowed to mask interrupts.

[0069] The duration for which user-mode tasks can mask interrupts is written to the aforementioned third register when the processor is in kernel mode. For example, when a user-mode application determines that it needs to mask certain low-priority interrupts, it reports the required duration to the kernel-mode operating system. The kernel-mode operating system, considering both the system's allowed temporary interrupt masking duration and the duration reported by the user-mode application, determines whether the requested duration conforms to the system settings. If it does, the kernel-mode operating system writes the requested duration to the third register; otherwise, it does not write to the third register, thus rejecting the user-mode application's interrupt masking request. The kernel-mode operating system's write operation to the third register can be performed during computer system startup or during the startup and execution of user-mode tasks.

[0070] The aforementioned timer is used to time the duration of the user-mode task masking interrupt. The timer starts counting when the user-mode task masking interrupt is enabled, and its countdown duration is the duration of the user-mode task masking interrupt. In some embodiments, the timer can use a forward counting mode, meaning it starts counting from zero and stops counting when the set target duration is reached. Alternatively, in other embodiments, the timer can use a countdown mode, meaning it starts counting down from the set target duration and stops counting when the countdown reaches zero. Regardless of the method used, as long as the timer starts counting when the user-mode task masking interrupt is enabled, the timer value can represent the duration of the user-mode task masking interrupt. At any point during the timer's counting process, the timer's countdown duration can be represented by the difference between the timer's countdown value and its initial countdown value. For example, when the timer is a positive timer, its duration can be obtained by subtracting its initial value (which is 0) from its current value. In this case, its duration is equal to its current value. When the counter is a countdown timer, its duration can be obtained by subtracting its current value from its initial value (which is the target duration).

[0071] Based on the settings of the third register and the timer described above, the processor acquires the timer's duration when it detects that a user-mode task masking interrupt is enabled, or when it detects that an enable message indicating that a user-mode task masking interrupt is enabled has been written into the second register. In other words, when the processor detects that a user-mode task masking interrupt is enabled, it acquires the timer's count value, and the duration counted by the timer can be determined based on this count value.

[0072] If the timer's duration is not zero, for example, when the timer is in positive time and its value is not zero, or when the counter is in countdown time and its value is not the initial value, it means that the user-mode task has been masking the interrupt for some time. At this time, the processor does not perform any operation to prevent malicious user-mode tasks from extending the interrupt masking duration again.

[0073] If the timer's duration is zero—for example, when the timer is a countdown timer, its value is zero (indicating it hasn't started counting), or its value is the set target duration and it has stopped counting (indicating it stopped counting after the previous countdown ended); or when the counter is a countdown timer, its value is the set target duration (indicating it hasn't started counting), or its value is zero (indicating it stopped counting after the previous countdown ended)—it means the user-mode task has not masked interrupts at the current moment. In this case, the processor starts the timer and sets its target duration to the duration stored in the third register. The timer will automatically stop counting when it reaches the duration stored in the third register. Specifically, if the timer is a countdown timer, it starts counting from zero and sets its target duration to the duration stored in the third register. When the timer reaches the duration stored in the third register, it automatically stops counting. If the timer is a countdown timer, it starts counting down from the duration stored in the third register. When it counts down to zero, it automatically stops counting.

[0074] Based on the timer settings described above, in another embodiment, if the processor receives an interrupt while executing a user-mode task and determines that the priority of the interrupt is lower than the priority information stored in the first register, the processor further verifies whether the timer duration has reached the duration stored in the third register.

[0075] If the timer's duration does not reach the duration stored in the third register (for example, the timer's value for a current timer is not the value corresponding to the duration stored in the third register, or the timer's value for a countdown timer is not zero), it indicates that the user-mode task interrupt masking is effectively enabled, and the processor will mask the interrupt.

[0076] If the timer's duration reaches the duration stored in the third register (for example, the duration of a current timer is the value corresponding to the duration stored in the third register, or the duration of a countdown timer is zero), it indicates that the user-mode task masking interrupt has timed out. Although the enable information stored in the second register indicates that the user-mode task masking interrupt is enabled, the processor considers the user-mode task masking interrupt to be invalid in this case because it has timed out. Therefore, the processor responds to the interrupt and / or processes the user-mode task according to the system settings.

[0077] In this embodiment, a timer is used to time the duration of the user-mode interrupt masking. The validity of the user-mode interrupt masking is determined by the duration of the timer. The user-mode task masking is considered valid only if the duration of the timer does not reach the target duration. In this case, the user-mode task is allowed to mask low-priority interrupts. Otherwise, the processor considers the user-mode task masking interrupt invalid and does not allow the user-mode task to mask interrupts.

[0078] The above scheme uses a timer to control the duration for which user-mode tasks mask interrupts, which can prevent user-mode tasks from masking interrupts for a long time, thereby avoiding affecting the normal operation of the system or even causing system failure.

[0079] In other embodiments, it is also disclosed that if, during the execution of a user-mode task, the processor receives an interrupt with a priority lower than the priority information stored in the first register, and the timer's duration has not reached the duration stored in the third register, the processor will mask the interrupt.

[0080] After the interrupt is masked, the processor executes the interrupt when the timer reaches the duration stored in the third register and / or the enable information stored in the second register is updated to indicate that the user-mode task has disabled interrupt masking.

[0081] If the timer's duration reaches the value stored in the third register (e.g., the countdown timer reaches the value corresponding to the duration stored in the third register, or the countdown timer reaches zero), it indicates that the user-mode task's interrupt masking has failed. In this case, the processor can execute the masked interrupt, or decide whether to execute the interrupt according to system settings. If the user-mode task has not finished running after the timer's duration reaches the duration stored in the third register, the processor can pause the user-mode task, start executing the interrupt, and resume execution of the user-mode task after the interrupt is completed.

[0082] Alternatively, after a user-mode task completes execution, or when the user-mode task does not need to mask interrupts, it writes enable information indicating that interrupt masking is disabled into a second register. When the processor detects that the enable information stored in the second register has been updated to indicate that interrupt masking is disabled, the processor can either execute the masked interrupt or decide whether to execute the interrupt according to system settings.

[0083] Through the above processing, the processor can promptly execute the masked interrupts after the user-mode task has finished masking the interrupts, thereby ensuring that the interrupts are executed in a timely manner and avoiding the impact of interrupts not being executed and affecting the normal operation of the system.

[0084] In other embodiments, when the processor detects that an enable message indicating that the user-mode task has masked interrupts has been written into the second register and starts the timer, if the processor switches from executing a user-mode task to executing a kernel-mode task, that is, the processor switches from user mode to kernel mode, the timer is paused; when the processor switches from executing a kernel-mode task back to executing a user-mode task, that is, when the processor switches back from kernel mode to user mode, the timer is resumed and continues to count.

[0085] By performing the above operations, it can be ensured that the timer only counts during the execution of user-mode tasks by the processor. This ensures accurate timing of the duration of interrupt masking for user-mode tasks and avoids the failure of interrupt masking for user-mode tasks due to inaccurate timing, which would affect the operation of user-mode tasks.

[0086] In another embodiment of this application, another implementation of the task processing method is disclosed.

[0087] See Figure 2 As shown, a first register, a second register, a third register, a fourth register, and a timer are set in the processor of a computer system.

[0088] Specifically, the first register stores the highest priority information of the interrupts masked by the user-mode task, the second register stores the enable information for the user-mode task-masked interrupts, the third register stores the duration of the user-mode task-masked interrupts, and the timer is used to time the duration of the user-mode task-masked interrupts. The specific functions, stored data contents, and working processes of the first, second, and third registers and the timer can be found in the corresponding descriptions of the above embodiments.

[0089] The fourth register mentioned above is the Interrupt Priority Mask Register (IPMR) in the processor, which is used to store interrupt mask priority information. This interrupt mask priority information is used to indicate the lowest priority of interrupts that the processor should respond to in real time. The processor determines which priority interrupts it needs to respond to in real time according to the interrupt mask priority information stored in the fourth register.

[0090] Figure 2 The EL level in the kernel is used to indicate whether the processor is currently in user mode or kernel mode. For example, EL0 indicates that the processor is in user mode, which means that the processor is executing user mode tasks; EL1 indicates that the processor is in kernel mode, which means that the processor is executing kernel mode tasks.

[0091] Based on the processor architecture described above, when the processor's current privilege level selects to respond to interrupts according to the value in the first register (e.g., the processor is currently at EL0 level) and the processor detects that user-mode task masking interrupts are enabled, or when the processor's current privilege level selects to respond to interrupts according to the value in the first register (e.g., the processor is currently at EL0 level) and the processor detects that enable information indicating that user-mode task masking interrupts are enabled has been written into the second register, the processor updates the priority information stored in the first register to the fourth register. At the same time, it obtains the timer's duration. If the timer's duration is zero, it triggers the timer to start timing and sets the timer's target duration to the duration stored in the third register.

[0092] At this time, the priority information stored in the fourth register is the highest priority information of the interrupts that are masked by user-mode tasks. The processor decides whether to respond to the interrupts received in real time according to the highest priority information of the interrupts that are masked by user-mode tasks stored in the fourth register.

[0093] Specifically, during the execution of a user-mode task by the processor, when an interrupt is received, the priority of the interrupt is determined, and the priority of the interrupt is compared with the priority information stored in the fourth register. If the priority of the interrupt is lower than the priority information stored in the fourth register, and the timer duration has not reached the duration stored in the third register, or it is determined that the user-mode task is enabled to mask interrupts, then the processor masks the interrupt.

[0094] This embodiment updates the priority information stored in the fourth register, enabling the processor to decide whether to respond to a real-time received interrupt during the execution of a user-mode task, based on the highest priority information of the interrupts masked by the user-mode task. This implementation is simple and efficient.

[0095] Another embodiment also discloses, based on Figure 2 In the processor architecture shown, if the processor switches from executing a user-mode task to executing a kernel-mode task (e.g., from EL0 to EL1), during the execution of a user-mode task, the processor updates the interrupt mask priority information stored in the fourth register to the initial priority. Simultaneously, it pauses the timer. This initial priority can be the interrupt mask priority set by the computer system; for example, it could mean not masking any interrupts or masking interrupts of certain specific priorities.

[0096] In another embodiment, it is also disclosed that when the processor switches from executing a user-mode task to executing a kernel-mode task, updates the interrupt masking priority information stored in the fourth register to the initial priority, and stops the timer, when the processor switches from executing a kernel-mode task back to continuing to execute a user-mode task (for example, switching back from EL1 level to EL0 level), the processor updates the priority information stored in the first register to the fourth register again, and resumes the timer. At this time, the processor can continue to execute the user-mode task and decide whether to respond to the received interrupt according to the highest priority of the interrupt masked by the user-mode task.

[0097] In another embodiment, it is also disclosed that when the processor's current privilege level selects to respond to interrupts according to the value in the first register (e.g., the processor is currently at EL0 level), if the processor detects that the timer's duration has reached the duration stored in the third register, the processor updates the interrupt masking priority information stored in the fourth register to the initial priority. That is, when the user-mode task masking interrupt times out, the processor resumes deciding whether to respond to the received interrupt in real time according to the initial priority.

[0098] In another embodiment of this application, another implementation of the task processing method is disclosed.

[0099] See Figure 3 As shown, the processor of a computer system includes a first register, a second register, a third register, a fifth register, a sixth register, a timer, a first selector, and a second selector.

[0100] The system comprises three registers: a first register for storing the highest priority information of interrupts masked by user-mode tasks, a second register for storing the enable information of user-mode task-masked interrupts, a third register for storing the duration of user-mode task-masked interrupts, and a timer for timing the duration of user-mode task-masked interrupts. The specific functions, stored data contents, and operating procedures of the first, second, and third registers and the timer can be found in the corresponding descriptions of the above embodiments. In this embodiment, the start and stop of the timer are controlled by the EL level. Specifically, when the EL level indicates that the processor is in user mode, the timer starts timing; when the EL level indicates that the processor is in kernel mode, the timer stops timing. According to the above control logic, when the EL level switches from user mode to kernel mode, the timer stops timing; when the EL level switches back from kernel mode to user mode, the timer resumes timing.

[0101] The fifth register mentioned above is the Interrupt Priority Mask Register (IPMR) in the processor, which is used to store interrupt mask priority information. This interrupt mask priority information is used to indicate the lowest priority of interrupts that the processor should respond to in real time. The processor determines which priority interrupts it needs to respond to in real time according to the interrupt mask priority information stored in the fifth register.

[0102] The sixth register mentioned above is used to store a specific value indicating that no interrupts are masked.

[0103] The candidate signal input terminals of the first selector are connected to the first register and the sixth register, respectively. The selection signal input terminal of the first selector is connected to the output terminal of the timer. Based on the output of the timer, the first selector selects to output the information stored in the first register or the sixth register.

[0104] The candidate signal input terminal of the second selector is connected to the fifth register and the output terminal of the first selector, respectively, and the selection signal input terminal of the second selector receives the EL level signal. Figure 3 The EL level in the selector indicates the processor's current privilege level, meaning whether the processor is currently in user mode or kernel mode. For example, EL0 indicates that the processor is in user mode, meaning it is executing user-mode tasks; EL1 indicates that the processor is in kernel mode, meaning it is executing kernel-mode tasks. The output of the second selector is used to output the final selected interrupt mask priority information.

[0105] Based on the processor architecture described above, the interrupt masking priority can be controlled and updated by controlling the first selector and the second selector.

[0106] For example, if the processor's current privilege level does not select to respond to interrupts according to the value of the fifth register (e.g., EL level is EL0), then the output of the second selector is the output signal of the first selector. The output of the first selector is controlled by a timer.

[0107] In this embodiment, when the processor's current privilege level does not select to respond to interrupts according to the value of the fifth register (e.g., EL level is EL0), when the processor detects that the user-mode task masking interrupt is enabled, or when the processor detects that enable information indicating that the user-mode task masking interrupt is enabled has been written into the second register, the processor obtains the timer's duration and determines whether the timer's duration is zero. For example, when the timer is a counting timer, its duration is zero (indicating that it has not started counting) or its duration is the set target duration and it has stopped counting (indicating that it stopped counting after the last timer ended), both of which indicate that its duration is zero. Or when the counter is a countdown timer, its duration is zero (indicating that it has not started counting) or its duration is zero (indicating that it stopped counting after the last timer ended). If the timer's duration is determined to be zero, the timer is triggered to start timing, and the target duration of the timer is set to the duration stored in the third register (that is, for a timer that is counting forward, its target duration is set to the duration stored in the third register, and timing stops when its timing value increases from zero to the value corresponding to the duration stored in the third register; for a timer that is counting down, its initial timing value is set to the value corresponding to the duration stored in the third register, and timing stops when its timing value decreases from the initial timing value to zero).

[0108] If user-mode task interrupt masking is enabled, or if the timer duration has not reached the duration stored in the third register, the first selector outputs the highest priority information of the user-mode task-masked interrupts stored in the first register. Based on the above processing, the interrupt masking priority information output by the second selector is the highest priority information of the user-mode task-masked interrupts stored in the first register. At this time, the processor decides whether to respond to interrupts received during the execution of the user-mode task in real time according to the highest priority information of the user-mode task-masked interrupts. That is, if the processor's current privilege level does not select to respond to interrupts according to the value of the fifth register (e.g., the processor's current EL level is EL0), and user-mode task interrupt masking is enabled or the timer duration has not reached the duration stored in the third register, when the processor receives an interrupt during the execution of the user-mode task, if the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt; if the priority of the interrupt is not lower than the priority information stored in the first register, the processor suspends the user-mode task and executes the task corresponding to the interrupt.

[0109] If the processor's current privilege level does not select to respond to interrupts according to the value of register 5 (e.g., EL level is EL0), when the timer's duration reaches the duration stored in register 3 or user-mode task interrupt masking is disabled, the first selector outputs the specific value stored in register 6 indicating that no interrupts are masked. Correspondingly, the interrupt masking priority information output by the second selector is specifically the specific value stored in register 6 indicating that no interrupts are masked. In this case, the processor does not mask any interrupts during the execution of the user-mode task. That is, if the processor's current privilege level does not select to respond to interrupts according to the value of register 5 (e.g., the processor's current EL level is EL0), and the timer's duration reaches the duration stored in register 3 or user-mode task interrupt masking is disabled, when the processor receives an interrupt during the execution of a user-mode task, it pauses the user-mode task and executes the task corresponding to the interrupt.

[0110] In another embodiment, if the processor's current privilege level is selected to respond to the interrupt according to the value of the fifth register, for example, if the current EL level is EL1, then the output of the second selector is the lowest priority information of the interrupt that the processor can respond to in real time, stored in the fifth register.

[0111] At this point, the processor decides whether to respond to the interrupt in real time based on the lowest priority information of the interrupts that the processor can respond to in real time, which is stored in the fifth register.

[0112] For example, when the processor's current EL level is EL1, if the processor receives an interrupt, the processor compares the priority of the interrupt with the priority information stored in the fifth register. If the priority of the interrupt is not lower than the priority information stored in the fifth register, the processor responds to the interrupt and executes the task corresponding to the interrupt; if the priority of the interrupt is lower than the priority information stored in the fifth register, the processor masks the interrupt.

[0113] Another embodiment of this application also provides a computer system in which a first register is provided during processing. The first register is used to store the highest priority information of interrupts that are masked by user-mode tasks. The computer system is configured to implement the task processing method as described in any of the above embodiments.

[0114] The specific processing steps and corresponding beneficial effects of the computer system in implementing the task processing method described in any of the above embodiments can be found in the descriptions of the corresponding embodiments above, and will not be repeated here.

[0115] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0116] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0117] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0118] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0119] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0120] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0121] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0122] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0123] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0124] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0125] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A task processing method, characterized in that, Applied to a computer system, the processor of the computer system is provided with a first register, which is used to store the highest priority information of interrupts that are masked by user-mode tasks; The method includes: When the processor receives an interrupt during the execution of a user-mode task, it obtains the priority of the interrupt and the priority information stored in the first register. If it is determined that interrupt masking is enabled for user-mode tasks, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt.

2. The method according to claim 1, characterized in that, The processor is also provided with a second register, which is used to store the enable information of user-mode task masking interrupt; When the processor receives an interrupt during the execution of a user-mode task, it also acquires the enable information stored in the second register; wherein the enable information in the second register is written by the user-mode task. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: The enable information stored in the second register indicates that interrupt masking for user-mode tasks is enabled, and the processor masks the interrupt if the priority of the interrupt is lower than the priority information stored in the first register.

3. The method according to claim 1, characterized in that, The processor is also equipped with a third register and a timer. The third register is used to store the duration of user-mode task interrupt masking. The method further includes: When the processor detects that the user-mode task interrupt masking is enabled, it obtains the duration of the timer. When the timer's duration is zero, the processor starts the timer and sets the target duration of the timer to the duration stored in the third register.

4. The method according to claim 3, characterized in that, The processor is also provided with a second register, which is used to store the enable information of user-mode task masking interrupt; When the processor detects that user-mode task masking interrupts are enabled, it obtains the duration of the timer, including: When the processor detects that an enable message indicating that a user-mode task masking interrupt is enabled has been written into the second register, it obtains the duration of the timer.

5. The method according to claim 3 or 4, characterized in that, If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the timer's duration has not reached the duration stored in the third register, and the interrupt's priority is lower than the priority information stored in the first register, the processor disables the interrupt.

6. The method according to claim 3 or 4, characterized in that, After the processor starts the timer to begin timing, the method further includes: The timer is paused when the processor switches from executing the user-mode task to executing the kernel-mode task; as well as, When the processor switches from executing a kernel-mode task to continuing to execute a user-mode task, the timer is resumed and continues counting.

7. The method according to claim 1 or 3, characterized in that, The processor also includes a fourth register for storing interrupt masking priority information, which indicates the lowest priority of interrupts that the processor can respond to in real time. The method further includes: When the processor selects to respond to an interrupt according to the value in the first register at its current privilege level, and when the processor detects that user-mode task masking interrupts are enabled, the processor updates the priority information stored in the first register to the fourth register. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If it is determined that interrupt masking is enabled for user-mode tasks, and the priority of the interrupt is lower than the priority information stored in the fourth register, the processor masks the interrupt.

8. The method according to claim 4, characterized in that, The processor also includes a fourth register for storing interrupt masking priority information, which indicates the lowest priority of interrupts that the processor can respond to in real time. The method further includes: If the processor selects to respond to an interrupt according to the value in the first register at its current privilege level, and the processor detects that an enable message indicating that user-mode task masking interrupts are enabled has been written into the second register, the processor updates the priority information stored in the first register to the fourth register. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the timer's duration has not reached the duration stored in the third register, and the interrupt's priority is lower than the priority information stored in the fourth register, the processor masks the interrupt.

9. The method according to claim 8, characterized in that, The method further includes: When the processor switches from executing the user-mode task to executing the kernel-mode task, the processor updates the interrupt mask priority information stored in the fourth register to the initial priority; or, When the processor switches from executing a kernel-mode task to continuing to execute a user-mode task, and the timer's duration has not reached the duration stored in the third register, the processor updates the priority information stored in the first register to the fourth register. or, When the timer reaches the duration stored in the third register, the processor updates the interrupt mask priority information stored in the fourth register to the initial priority.

10. The method according to claim 5, characterized in that, The method further includes: When the timer reaches the duration stored in the third register, and / or the enable information stored in the second register is updated to indicate that user-mode task interrupt masking is disabled, the processor executes the task corresponding to the interrupt.

11. The method according to claim 1, characterized in that, The method further includes: If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is not lower than the priority information stored in the first register, the processor executes the task corresponding to the interrupt.

12. The method according to claim 11, characterized in that, The method further includes: After the processor finishes executing the task corresponding to the interrupt, it continues to execute the user-mode task. Alternatively, the processor executes the task corresponding to the interrupt through the first processor core and the user-mode task through the second processor core.

13. The method according to claim 1, characterized in that, The processor also includes a fifth register; the fifth register is used to store interrupt masking priority, which represents the lowest priority of interrupts that the processor can respond to in real time. If it is determined that user-mode task interrupt masking is enabled, and the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the processor's current privilege level does not select to respond to an interrupt according to the value of the fifth register, and the user-mode task interrupt masking is enabled, then if the priority of the interrupt is lower than the priority information stored in the first register, the processor masks the interrupt.

14. The method according to claim 5, characterized in that, The processor also includes a fifth register; the fifth register is used to store interrupt masking priority, which represents the lowest priority of interrupts that the processor can respond to in real time. If the timer's duration has not reached the duration stored in the third register, and the interrupt's priority is lower than the priority information stored in the first register, the processor masks the interrupt, including: If the processor does not select to respond to the interrupt according to the value of the fifth register at its current privilege level, and the timer duration has not reached the duration stored in the third register, then the processor masks the interrupt if the priority of the interrupt is lower than the priority information stored in the first register.

15. The method according to claim 14, characterized in that, The method further includes: If the processor selects to respond to an interrupt according to the value of the fifth register at its current privilege level, and the priority of the interrupt is not lower than the priority information stored in the fifth register, the processor executes the task corresponding to the interrupt. or, If the processor's current privilege level does not select to respond to the interrupt according to the value of the fifth register, and the timer's duration reaches the duration stored in the third register, the processor suspends the user-mode task and executes the task corresponding to the interrupt.

16. A computer system, characterized in that, The processor of the computer system is provided with a first register, which is used to store the highest priority information of interrupts that are masked by user-mode tasks. The computer system is configured to implement the task processing method as described in any one of claims 1 to 15.

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