Matrix multiplication hardware acceleration method and hardware acceleration circuit
By performing parallel computation of matrices A and B in blocks and combining this with the hardware's built-in transpose function, the efficiency and energy consumption challenges of traditional hardware in large-scale matrix multiplication operations are solved, achieving efficient matrix multiplication computation.
Patent Information
- Application Number
- CN202511635460.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional general-purpose computing hardware faces challenges in terms of efficiency, energy consumption, and memory bandwidth when handling large-scale matrix multiplication operations, making it difficult to meet the computational needs of large-scale training of language models.
Matrix A and matrix B are divided into multiple smaller blocks, transposed and rearranged, and then parallel computation is performed using a matrix multiplication array and a data accumulation module. Combined with the built-in hardware transpose function, the CPU computation overhead of software transpose is reduced.
It improves the computational efficiency and parallelism of matrix multiplication, reduces the CPU computational overhead of software transposition, and greatly enhances the computational performance of matrix multiplication.
Smart Images
Figure CN121502135A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of accelerated computing and chip design technology using artificial neural networks, and particularly to a hardware acceleration method and circuit for matrix multiplication. Background Technology
[0002] In recent years, with the rapid development of artificial intelligence technology, large-scale trained language models (such as GPT and DeepSeek) have demonstrated powerful capabilities in fields such as natural language processing and computer vision. The core computation of these models relies on large-scale General Matrix Multiply (GEMM) operations, such as self-attention mechanisms and linear transformations in feed-forward networks. However, with the exponential growth of model parameter size (e.g., from hundreds of millions to trillions), traditional general-purpose computing hardware faces severe challenges in terms of efficiency, energy consumption, and memory bandwidth. Summary of the Invention
[0003] The purpose of this invention is to provide a hardware acceleration method and hardware acceleration circuit for matrix multiplication, so as to solve the problems in the background art.
[0004] To address the aforementioned technical problems, this invention provides a hardware acceleration method for matrix multiplication, comprising the following steps:
[0005] Step S1: Based on the characteristics of matrix operations, divide the data matrix A (height M × width K) and the weight matrix B (height K × width N) into multiple sub-blocks, so that each sub-block has a preset first height and first width, and the width and height of each sub-block are equal.
[0006] Step S2: Transpose the weight matrix B to obtain the transposed weight matrix B with height N × width K. T Make matrix A and matrix B T They are the same size in the width direction;
[0007] Step S3: Rearrange the data in each block, and arrange the data blocks of each row into the data buffer module in order from top to bottom and from left to right.
[0008] Step S4: Based on the number of matrix multiplication units, send the rearranged data matrix and weight matrix into the matrix multiplication array to obtain the sum of multiple parts of the result matrix;
[0009] Step S5: Accumulate the corresponding elements of the multiple parts and the matrix to obtain the matrix multiplication result.
[0010] In one embodiment, in step S1, since the scales of the input data and model parameters for matrix multiplication are large, the input data and model parameters are usually divided into multiple coarse blocks respectively, so that each coarse block of matrix A has a second length and a second width, and each block of matrix B has a third length and a third width. Then, the coarse blocks are divided into multiple fine blocks with a preset first height and first width.
[0011] In one embodiment, the second length, the second width, and the third width are respectively equal to the length, width, and length of the multiplicand matrix specified in the matrix multiplication operation, and the second width is equal to the third length.
[0012] In one embodiment, in step S3, after the hardware runs, matrix A and matrix B are read from the global memory, and the storage forms of matrix A and matrix B in the memory are both default row-major storage; matrix A is read according to the rules of local row-major and global column-major, and matrix B is read according to the rules of local row-major and global column-major, so as to manage the memory of matrix A and matrix B and ensure the consistency of the memory storage forms of matrix A and matrix B.
[0013] In one embodiment, the data buffer module is divided into two logical circular buffers, one is the matrix A data buffer and the other is the matrix B data buffer, and two read / write interfaces with a width of 1024 bits are provided to correspond to the computing requirements of the matrix computing array; the data buffer module has a circular buffer design, and the address automatically wraps around.
[0014] In one embodiment, the matrix multiplication array is composed of several matrix multiplication units, and the number of multipliers and adders in each matrix multiplication unit is c. When performing matrix operations, data of size 1×K is sent into the matrix multiplication unit for calculation. When K < c, the 1×K cube is expanded to 1×c, and the expanded part has a value of 0; when K > c, each 1×K-sized cube is divided into n 1×c-sized cubes and one 1×(K - n×c)-sized cube; where the size of n needs to satisfy the following formula: n×c < K < (n + 1)×c;
[0015] There are a total of C matrix multiplication units in the matrix multiplication array. The C matrix multiplication units independently process partial calculation tasks, and by latching the matrix B data and dynamically inputting the matrix A data, the matrix B data is reused, improving the data reuse rate.
[0016] In one implementation, the matrix multiplication array generates a large number of partial sums after computation. The data accumulation module needs to accumulate these scattered partial sums along K dimensions to obtain the complete result of one position of the final matrix. The data accumulation module uses a dual SRAM buffer design. The first SRAM is used to prefetch historical accumulated values and c new partial sums passed from the matrix multiplication array, and then sends these data into the adder array for computation. The second SRAM is used to store the final matrix result data to be sent. When the second SRAM is full, a backpressure signal is sent to the data loading module to pause the data input of the matrix multiplication array, thereby ensuring that data does not overflow when downstream is blocked and maintaining the stability of the pipeline.
[0017] The present invention also provides a matrix hardware acceleration circuit, connected to an external storage module, the external storage module being used to store multiple matrices A and B and multiple operation results; the matrix hardware acceleration circuit includes:
[0018] The data reading module reads matrices A and B required for this matrix multiplication operation from the external storage module;
[0019] A data caching module caches matrix A and B data read from the external storage module;
[0020] The data loading module reads matrix A and B data sequentially from the data cache module, performs a transpose operation on matrix B, and sends it to the matrix multiplication unit.
[0021] The matrix multiplication array receives matrix A and B data from the data loading module, performs multiplication and addition operations on them, and obtains the sum of multiple matrix parts.
[0022] The data accumulation module accumulates the partial sums of the matrix to obtain the final matrix result, and then outputs the matrix result to the external storage module.
[0023] In one implementation, the data reading module reads matrix A data sequentially from top to bottom. The number of matrix A data read each time is the same as the number of matrix multiplication units in the matrix multiplication array in the K direction. When the number of matrix A data in the K direction is less than the number of matrix multiplication units, it will be filled in the K direction with a value of 0. When the number of matrix A data in the K direction is greater than the number of matrix multiplication units, it will be read multiple times in the order from front to back.
[0024] In one implementation, the data caching module is configured into two parts according to the size of matrices A and B, which are used to store the data of matrices A and B respectively.
[0025] In one implementation, the data loading module loads an element of matrix B and a series of matrix A data that need to be multiplied with the element of matrix B in a top-to-bottom and left-to-right order according to the size of matrix A, the size of matrix B and the size of the result matrix, and sends a flag signal to indicate whether all the data for matrix multiplication between the matrix multiplication array and the current element of matrix B has been loaded.
[0026] In one embodiment, the matrix multiplication array contains multiple matrix multiplication units, each consisting of multiple multipliers and adders. Each multiplier multiplies matrix B and matrix A in a K direction, then adds the products of all multipliers to obtain a partial sum, and then calculates the matrix multiplication of the next element of matrix A and matrix B.
[0027] In one implementation, the data accumulation module is used to cache the partial sum of the same matrix B element and accumulate it with the partial sum of the next matrix B element to obtain the final matrix result.
[0028] This invention provides a hardware acceleration method and circuit for matrix multiplication. The matrix is pre-divided into multiple coarse blocks according to the size of the data cache module. The data reading module reads these coarse blocks from an external storage module in the matrix multiplication order and assigns different fine blocks of matrix A to each matrix multiplication unit in the matrix multiplication array. Simultaneously, matrix B is transposed, and one of its fine blocks is assigned to each matrix multiplication unit in the matrix multiplication array, allowing the matrix multiplication array to obtain multiple parts and data in each calculation. Each matrix multiplication unit in the matrix multiplication array obtains the part of the input matrix that should be multiplied by the assigned fine block and performs matrix multiplication on this part to complete the matrix multiplication operation between the input matrix and the model parameters of the large model. Since the matrix A blocks assigned to each matrix multiplication unit are non-overlapping, the matrix multiplication array simultaneously calculates data from multiple rows of matrix A and outputs multiple parts and data simultaneously, improving the parallelism of matrix operations and greatly increasing the computational efficiency of matrix multiplication. Furthermore, the method disclosed in this invention has a built-in hardware transpose function, reducing the CPU computational overhead of software transpose. Attached Figure Description
[0029] Figure 1 This is a flowchart illustrating a hardware acceleration method for matrix multiplication disclosed in this invention.
[0030] Figure 2 This is a schematic diagram illustrating the principle of matrix operations.
[0031] Figure 3 This diagram illustrates the memory layout format conversion of matrices A, B, and the result matrix.
[0032] Figure 4This is a schematic diagram of a matrix acceleration circuit.
[0033] Figure 5 This is a schematic diagram of the matrix multiplication unit.
[0034] Figure 6 This is a schematic diagram illustrating the loading of data for matrices A and B in a matrix multiplication array. Detailed Implementation
[0035] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the matrix multiplication hardware acceleration method and hardware acceleration circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0036] This invention proposes a hardware acceleration method for matrix multiplication, the process of which is as follows: Figure 1 As shown, it includes the following steps:
[0037] S1. Based on the characteristics of matrix operations, the data matrix A (M×K, where M is the height of matrix A and K is the width of matrix A) and the weight matrix B (K×N, where K is the height of matrix B and N is the width of matrix B) are divided into multiple smaller blocks, such that each smaller block has a preset first height and first width, and the width and height of each smaller block are equal; these divided data are read and counted by the data reading module. The hardware acceleration circuit architecture is as follows. Figure 4 As shown.
[0038] The output matrix C = A × B. The complete computation task should include matrices A and B. Assuming matrices A and B are not transposed, perform the following matrix multiplication to obtain the output matrix:
[0039]
[0040] Matrices A and B (M×K, K×N) need to be divided into multiple coarse blocks for separate calculations. Therefore, the size of a calculation block must first be determined, which is based on the size of the data caching module (used to cache matrices A and B). In the scheme of this invention, the data caching module needs to store matrices A and B of size m×k and k×n respectively. Assuming each element is of int8 precision and occupies (m×k+k×n) bytes of memory, and the storage space of memory A1 and B1 is K bytes, then the size of each block is the maximum value satisfying (m×k+k×n)≤K.
[0041] The computation tasks are sequentially transmitted to the computation core, with each computation outputting a portion of the result matrix. This embodiment is guided by a data caching module, whose capacity determines the size of each matrix block. For example, if matrix A is 8192×8192 and matrix B is 8192×8192, and assuming the data caching module can only hold two 256*256 matrices, then the blocks for matrices A and B are 256×256, and the computation task is divided into 1024 operations executed sequentially.
[0042] S2. Transpose the weight matrix B to obtain the transposed weight matrix B. T (N×K), such that matrix A and matrix B are (N×K), T They are the same size in the width direction.
[0043] After the hardware starts running, matrices A and B are read from global memory, and both matrices A and B are stored in memory in row-major order by default. To reduce software preprocessing and CPU time, matrix B does not require preprocessing after the hardware circuit begins operation. Since matrix calculation involves multiplying a row of data from matrix A by a column of data from matrix B, the data reading module in this invention includes a transpose function for matrix B. The data conversion process is as follows... Figure 3 As shown, matrix A is read according to the rule of local row priority and global column priority, and matrix B is read according to the rule of local row priority and global column priority. This facilitates the memory management of matrices A and B and ensures the consistency of the memory storage format of matrices A and B.
[0044] S3. Rearrange the data in each block, and arrange the data blocks of each row into the data buffer module in order from top to bottom and from left to right.
[0045] The S3 uses a data buffer module, a key component of the entire hardware circuit. Its primary function is to efficiently buffer and manage the data required for matrix calculations. The data buffer module is divided into two logical circular buffers: one for matrix A and one for matrix B, providing two 1024-bit wide read / write interfaces to meet the computational demands of the matrix array. The circular buffer design with automatic address wraparound avoids frequent address management, improving data throughput efficiency.
[0046] S4. Call the matrix multiplication array to perform matrix multiplication operations and obtain the sum of multiple parts of the result matrix.
[0047] S4 is used to calculate the result of a task block. In the matrix multiplication array, the number of multiplier-accumulators in each matrix multiplication unit is c. When performing matrix operations, data of size 1×K is sent into the matrix multiplication unit for calculation. When K < c, the 1×K cube is expanded to 1×c, and the expanded part has a value of 0; when K > c, each 1×K-sized cube is divided into n 1×c-sized cubes and one 1×(K - n×c)-sized cube. The size of n needs to satisfy the following formula:
[0048] n×c < K < (n + 1)×c
[0049] In the matrix multiplication array, there are C matrix multiplication units. The C matrix multiplication units independently process partial calculation tasks, and by latching the data of matrix B and dynamically inputting the data of matrix A, the data of matrix B is reused to improve the data reuse rate.
[0050] S5. Accumulate the elements at the corresponding positions of multiple partial sum matrices to obtain the result of the matrix multiplication operation.
[0051] Since a large number of partial sums are generated after the previous matrix multiplication array calculation, a data accumulation module is required to accumulate these scattered partial sums according to the K dimension to obtain the complete result of one position of the final matrix. A dual-SRAM buffer design is used in the data accumulation module. The first SRAM is used to prefetch the historical accumulated values and c new partial sums传入 from the matrix multiplication array, and send these data into the adder array for calculation; the second SRAM is used to store the data of the final matrix result to be sent. When the second SRAM is full, it sends a backpressure signal to the data loading module to pause the data input of the matrix multiplication array, so as to ensure that the data does not overflow when the downstream is blocked and maintain the stability of the pipeline.
[0052] Based on the above matrix multiplication acceleration method, the present invention also proposes a matrix multiplication hardware acceleration circuit for implementing the above matrix acceleration method, and its functional block diagram is as Figure 4 shown. Structurally, the hardware acceleration circuit includes a data reading module 42, a data caching module 43, a data loading module 44, a matrix multiplication array 45, and a data accumulation module 47. When performing matrix multiplication operations, the data reading module 42, the data caching module 43, the data loading module 44, and the matrix multiplication array 45 need to work together, and the data must flow through these four modules.
[0053] The data reading module 42 reads the feature data sequentially from top to bottom and from left to right. Each time, the number of matrix A data read in the K direction is the same as the number of matrix multiplication units 46 in the matrix multiplication array 45. When the number of matrix A data in the K direction is less than the number of matrix multiplication units 46, it will be filled in the channel direction with a value of 0. When the number of matrix A data in the K direction is greater than the number of matrix multiplication units 46, it will be read multiple times in a front-to-back order. The data reading module 42 will store these data in the data cache module 43 and inform the data loading module 44 of the amount of data to be stored.
[0054] The data caching module 43 can be configured into two parts according to the size of the feature data and weights, which are used to store matrix A and matrix B data respectively.
[0055] The data loading module 44 will load the data from matrix A and matrix B in a specific order. For example... Figure 5 As shown, when matrix B is loaded, the first cube of c columns of matrix B data is loaded sequentially. These c cubes are then loaded into c matrix multiplication units 46, and so on, until all matrix B data is loaded. Within the same matrix B data set, the loading order is k→n. During data loading, the matrix A data that is operated on with the first matrix B cube is loaded sequentially. This data is simultaneously loaded into c matrix multiplication units 46 for operation, until all data is loaded. Then, the matrix A data that is operated on with the next matrix B cube is loaded. Matrix A data is not loaded during the loading of the first matrix B cube. After the first matrix B cube is loaded, the second matrix B cube and the matrix A data that is operated on with the first matrix B cube are loaded simultaneously. After all matrix A and matrix B data are loaded, the nth matrix B cube and the feature data that is operated on with the (n-1)th matrix B cube are loaded. After loading all matrix A data corresponding to a certain matrix B cube, a flag bit is sent to update the matrix B data within the matrix multiplication unit 46.
[0056] For example, Figure 6 The diagram shows a matrix multiplication of a K×12 matrix B with an 8×K matrix A. The output size is 8*12. Each matrix B cube needs to be multiplied by a 1×K matrix. The data loading module 44 first loads B00, B01, B02, and B03, which are temporarily stored in a register. Then, it loads the matrix A data A00, A01, A02, and A03, and sends them together with the data to the matrix multiplication unit 46 for calculation.
[0057] After loading all data for matrix A and matrix B, the data loading module 44 will notify the data reading module 42 of the amount of data released so that the data for subsequent matrix multiplication operations can be stored.
[0058] The matrix multiplication array 45 consists of C matrix multiplication units 46. Each matrix multiplication unit 46 includes c multipliers. Each matrix multiplication unit 46 first loads a 1×c cube of size C weight cubes and performs an operation with a 1×c data cube of size matrix A. Each multiplier performs a 1×1 multiplication operation. Then, the results of all multipliers within a matrix multiplication unit 46 are added together to obtain a partial sum. The matrix multiplication of the next matrix A data with the element of matrix B is then calculated. During this process, the matrix multiplication array 45 continues to receive matrix B from the data loading module 44, but this matrix B data is stored in registers until a flag is received from the data loading module 44. Then, this matrix B data is loaded into the matrix multiplication unit 46 for matrix multiplication operations.
[0059] After receiving the partial sum data of the matrix multiplication array 45, the data accumulation module 47 will store these data in the FIFO in sequence. When it receives the mark that the calculation of the current matrix B data is over, it will read the partial sum in the FIFO in sequence, accumulate it with the partial sum of the next matrix B data, and then write it back to the FIFO in sequence. After the partial sum accumulation between all matrix B data is completed, the final matrix multiplication result is obtained.
[0060] In summary, compared with existing technologies, the matrix multiplication hardware acceleration method and circuit provided by this invention have the following significant advantages: Based on the size of the data cache module, matrices A and B are pre-divided into multiple coarse blocks; the data reading module reads matrix A and B data according to a preset first height and first width, and performs a transpose operation on matrix B, ensuring the consistency of the memory storage format of matrices A and B; C matrix multiplication units independently process part of the computational task, and by latching matrix B data and dynamically inputting matrix A data, matrix B data is reused, improving data reuse rate; the final part and addition calculations are completed by data accumulation modulus, maximizing the use of the hardware computing power of the matrix multiplication computation array, greatly improving the computational efficiency and parallelism of matrix multiplication, and showing significant advantages compared with traditional matrix multiplication calculation methods.
[0061] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A hardware acceleration method for matrix multiplication, characterized in that, It includes the following steps: Step S1: According to the characteristics of matrix operations, divide the data matrix A with height M×width K and the weight matrix B with height K×width N into multiple small blocks, such that each small block has a preset first height and first width, and the width and height of each small block are equal; Step S2: Transpose the weight matrix B to obtain the transposed weight matrix B with height N × width K. T Make matrix A and matrix B T They are the same size in the width direction; Step S3: Rearrange the data within each small block once. Arrange the data blocks in each row in sequence from top to bottom and from left to right into the data buffer module; Step S4: According to the number of matrix multiplication units, send the rearranged data matrix and weight matrix into the matrix multiplication array to obtain multiple partial sums of the result matrix; Step S5: Accumulate the elements at the corresponding positions of the multiple partial sum matrices to obtain the result of the matrix multiplication operation.
2. The matrix multiplication hardware acceleration method as described in claim 1, characterized in that, In step S1, since the scale of the input data and model parameters for matrix multiplication is large, usually divide the input data and model parameters into multiple large blocks respectively, such that each large block of matrix A has a second length and second width, and each block of matrix B has a third length and third width, and then divide the large blocks into multiple small blocks with a preset first height and first width.
3. The matrix multiplication hardware acceleration method as described in claim 2, characterized in that, The second length, the second width, and the third width are respectively equal to the length, width of the multiplicand matrix, and the length of the multiplier matrix specified by the matrix multiplication operation, and the second width is equal to the third length.
4. The matrix multiplication hardware acceleration method as described in claim 1, characterized in that, In step S3, after the hardware runs, read matrix A and B from the global memory, and the storage form of matrix A and B in the memory is the default row-major storage; read matrix A according to the rules of local row-major and global column-major, and read matrix B according to the rules of local row-major and global column-major, so as to manage the memory of matrix A and B and ensure the consistency of the memory storage form of matrix A and B.
5. The matrix multiplication hardware acceleration method as described in claim 1, characterized in that, The data buffer module is divided into two logical circular buffers, one is the matrix A data buffer, and the other is the matrix B data buffer, and provides two read-write interfaces with a width of 1024 bits to meet the calculation requirements of the matrix calculation array; the data buffer module has a circular buffer design, and the address automatically wraps around.
6. The matrix multiplication hardware acceleration method as described in claim 1, characterized in that, The matrix multiplication array is composed of several matrix multiplication units. The number of multipliers and adders in each matrix multiplication unit is c. When performing matrix operations, data of size 1×K is sent into the matrix multiplication unit for calculation. When K < c, the 1×K cube is expanded to 1×c, and the expanded part has a value of 0; when K > c, each 1×K-sized cube is divided into n 1×c-sized cubes and one 1×(K - n×c)-sized cube; where the size of n needs to satisfy the following formula: n×c < K < (n + 1)×c; There are a total of C matrix multiplication units in the matrix multiplication array. The C matrix multiplication units independently process partial calculation tasks, and by latching the matrix B data and dynamically inputting the matrix A data, reuse the matrix B data to improve the data reuse rate.
7. The matrix multiplication hardware acceleration method as described in claim 1, characterized in that, The matrix multiplication array generates a large number of partial sums after calculation. The data accumulation module needs to accumulate these scattered partial sums according to the K dimension to obtain the complete result of one position of the final matrix; The data accumulation module uses a dual SRAM buffer design. The first SRAM is used to prefetch historical accumulated values and c new partial sums passed from the matrix multiplication array, and then sends these data into the adder array for calculation. The second SRAM is used to store the final matrix result data to be sent. When the second SRAM is full, a backpressure signal is sent to the data loading module to pause the data input of the matrix multiplication array, thereby ensuring that data does not overflow when downstream is blocked and maintaining the stability of the pipeline.
8. A matrix hardware acceleration circuit, characterized in that, It is connected to an external storage module, which is used to store multiple matrices A and B and multiple operation results; The matrix hardware acceleration circuit includes: The data reading module reads matrices A and B required for this matrix multiplication operation from the external storage module; A data caching module caches matrix A and B data read from the external storage module; The data loading module reads matrix A and B data sequentially from the data cache module, performs a transpose operation on matrix B, and sends it to the matrix multiplication unit. The matrix multiplication array receives matrix A and B data from the data loading module, performs multiplication and addition operations on them, and obtains the sum of multiple matrix parts. The data accumulation module accumulates the partial sums of the matrix to obtain the final matrix result, and then outputs the matrix result to the external storage module.
9. The matrix hardware acceleration circuit as described in claim 7, characterized in that, The data reading module reads matrix A data sequentially from top to bottom. Each time, the number of matrix A data read in the K direction is the same as the number of matrix multiplication units in the matrix multiplication array. When the number of matrix A data in the K direction is less than the number of matrix multiplication units, it will be filled in the K direction with a value of 0. When the number of matrix A data in the K direction is greater than the number of matrix multiplication units, it will be read multiple times in a front-to-back order.
10. The matrix hardware acceleration circuit as described in claim 7, characterized in that, The data caching module is configured into two parts according to the size of matrices A and B, which are used to store the data of matrices A and B respectively.
11. The matrix hardware acceleration circuit as described in claim 7, characterized in that, The data loading module loads an element of matrix B and a series of matrix A data that need to be multiplied with the element of matrix B in a top-to-bottom and left-to-right order according to the size of matrix A, the size of matrix B and the size of the result matrix. It also sends a flag signal to indicate whether all the data for matrix multiplication between the matrix multiplication array and the current element of matrix B has been loaded.
12. The matrix hardware acceleration circuit as described in claim 7, characterized in that, The matrix multiplication array contains multiple matrix multiplication units. Each matrix multiplication unit consists of multiple multipliers and adders. Each multiplier multiplies the data of a matrix B and a matrix A in a K direction. Then, the products of all multipliers are added together to obtain a partial sum. Then, the matrix multiplication of the next element of matrix A and matrix B is calculated.
13. The matrix hardware acceleration circuit as described in claim 7, characterized in that, The data accumulation module is used to cache the partial sum of the same matrix B element and accumulate it with the partial sum of the next matrix B element to obtain the final matrix result.