Method for realizing fault diagnosis based on MaxSAT

Abstract

The invention particularly relates to a method for realizing fault diagnosis based on MaxSAT, which is characterized in that a candidate component set is reduced by iteratively applying a fault positioning model and a MaxSAT algorithm, accurate identification of fault components is realized, an enhanced model diagnosis method is provided, and fault diagnosis is realized by gradually reducing the fault positioning model by using the MaxSAT algorithm. According to the method, the maximum number of the components with output logic changes in different observation values can be identified, the fault-free components are effectively deleted from the candidate diagnosis, the method is superior to the existing advanced technology on the standard test basis, and a reliable scheme is provided for reliable diagnosis of a complex system.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a method for fault diagnosis based on MaxSAT. Background Technology

[0002] In related technologies, the continuous shrinking of standard integrated circuit cell sizes increases the challenge of fault location. To address this challenge, model-based diagnostic methods, which can identify possible causes of unexpected behavior resulting from system faults, are widely used in various fault location tasks. In the definition of model-based diagnosis, SD represents the system description, Obs represents the observed system behavior, and COMPS represents the set of components in the system. The health state of each component is represented by H(c); if H(c) is false, it indicates that the component has failed. Assuming that every component c in the system is in a healthy state, a diagnostic problem exists if the system description and observed behavior contradict each other. Given a model-based diagnostic problem, if there is no diagnostic set with a smaller cardinality, it is considered a minimum potential diagnosis; if no suitable subset satisfies the diagnostic conditions, it is called a minimum subset diagnosis. Furthermore, diagnoses directly derived from SD, COMPS, and Obs are defined as fault diagnoses, requiring no additional measurement constraints. However, existing diagnostic methods generate very large candidate diagnostic spaces, posing a significant challenge to accurate fault identification.

[0003] Model-based diagnostic methods primarily employ two approaches to address the aforementioned problems. The first type utilizes available probes for diagnosis. A representative example is the complete sequential diagnostic method proposed by Shchekotykhin KM et al., which, by leveraging efficient queries, diagnoses faults with only a few minimal conflicts within the system. The second type collects additional observations (e.g., multiple observations) to narrow down the possible interpretation set, thereby reducing the diagnostic solution space. This primarily includes SAT-based methods, O2D, D2O, DiagDO, and DPDN algorithms. In SAT coding methods, conjunctive normal form coding establishes logical equivalence between the component's unhealthy variables and its behavioral model, providing diagnosis through the SAT solver. However, both model-based diagnostic methods have certain limitations. While they can reduce diagnostic time, they often generate too many candidate diagnoses without considering whether these generated diagnoses accurately identify the defective component.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This invention provides a method for fault diagnosis based on MaxSAT, which can effectively overcome the defects existing in the prior art.

[0006] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0007] According to a first aspect of the present invention, a method for fault diagnosis based on MaxSAT is provided, the method comprising: Create a corresponding replica circuit for the original circuit to be analyzed; configure new sentinel gates for each logic gate in the original circuit and the corresponding replica gates in the replica circuit, and connect the output terminals of the logic gates and replica gates to the input terminals of the sentinel gates to build a fault location model; Hard clause encoding is performed on each logic gate in the original circuit, each copy gate and sentinel gate in the replica circuit to obtain the corresponding cell hard clause; among them, the cell hard clause is used to describe the health state constraints of the logic gate; Encode the sentry gate using soft clauses to obtain the corresponding unit soft clauses; Based on the hierarchical relationship of each sentry gate in the circuit of the fault location model, the soft clauses are weighted; and based on the number of components in the original circuit, the hard clauses are weighted. By combining soft clauses, hard clauses, and their corresponding weights, a MaxSAT problem based on a fault location model is constructed; and the MaxSAT solver is called to solve the MaxSAT problem in order to identify fault-free components in the original circuit. Based on the identification results of fault-free components, the preferred faulty components are determined in order to achieve fault location.

[0008] In some exemplary embodiments, a corresponding replica circuit is created for the original circuit to be analyzed; for each logic gate in the original circuit, a new sentinel gate is configured with the corresponding replica gate in the replica circuit, and the output terminals of the logic gates and replica gates are connected to the input terminals of the sentinel gates to construct a fault location model, including: The original circuit to be analyzed is copied to create a corresponding replica circuit, and the replica identifier is configured for each replicated component in the replica circuit with reference to the original circuit. Sentinel gates are configured for each logic gate in the original circuit, and the output terminals of each logic gate in the original circuit, the output terminals of the corresponding replica gates in the replica circuit, and the input terminals of the corresponding sentinel gates are connected to construct a fault location model. The sentinel gates are used to compare the output signals of the logic gates in the original circuit with the output signals of the corresponding replica gates in the replica circuit.

[0009] In some exemplary embodiments, the step of hard-coding each logic gate in the original circuit, each copy gate in the replica circuit, and the sentinel gate to obtain the corresponding unit hard clause includes: Hard clause encoding is performed on the inputs and outputs of each logic gate in the original circuit to obtain the unit hard clauses based on the conjunctive normal form format corresponding to each logic gate; wherein, the unit hard clauses corresponding to the logic gate are used to describe the behavior of the logic gate and realize the health status description of the logic gate behavior; Hard clause encoding is performed on the inputs and outputs of each replication gate in the replication circuit to obtain the unit hard clauses based on the conjunction normal form for each replication gate; The output of the sentinel gate is hard-coded to obtain the corresponding unit hard clause based on the conjunctive normal form. The unit hard clause of the sentinel gate is used to indicate whether the single output of the logic gate in the original circuit is consistent with the output of the corresponding copy gate in the replica circuit.

[0010] In some exemplary embodiments, the soft clauses are weighted according to the hierarchical relationship of each sentry gate in the circuit of the fault location model, including: Based on the hierarchical relationship of each sentry gate in the circuit of the fault location model, the corresponding minimum level and maximum level are configured according to the preset hierarchical weight strategy; Randomly select an integer from the minimum to the maximum level as the weight of the soft clause.

[0011] In some exemplary embodiments, the method further includes: pre-constructing a hierarchical weighting strategy, including: Obtain the relationships between components and system inputs and outputs; When a component is directly connected to a system input, the minimum level corresponding to that component is configured to be 1. When the output of a component is system output, configure the maximum level assignment and the minimum level assignment of the component to be equal; When the component is a non-system input / output component, increment the maximum value of the minimum level of each component associated with the input terminal by 1; decrement the minimum value of the minimum level of each component associated with the output terminal by 1.

[0012] In some exemplary implementations, hard clauses are weighted according to the number of components in the original circuit, including: Determine the total number of components corresponding to the components in the original circuit; Assign weights to each hard clause based on the total number of components.

[0013] In some exemplary implementations, a MaxSAT problem based on a fault location model is constructed by combining soft clauses, hard clauses, and their corresponding weights; and the MaxSAT solver is invoked to solve the MaxSAT problem to identify fault-free components in the original circuit, including: Define constraints based on soft clauses, hard clauses, and corresponding weights, construct a MaxSAT problem based on the fault location model based on the constraints, and encode the corresponding WCNF file. The MaxSAT solver is invoked and a WCNF file is input. The local search algorithm based on look-ahead sampling and Dist weighting is used to solve the problem. The set of fault-free components in the original circuit is determined based on the solution results.

[0014] In some exemplary embodiments, a preferred faulty component is determined based on the identification result of a fault-free component to achieve fault location, including: The fault location model is simplified based on the set of fault-free components, and the fault diagnosis solution is updated. The simplified fault location model is solved by iteratively calling the MaxSAT solver to obtain the set of fault-free components that satisfy all hard clauses and maximize the weight of the soft clauses. If the set of fault-free components is not empty, update the length of the fault diagnosis solution and update the fault location model; otherwise, terminate the loop.

[0015] In some exemplary implementations, the MaxSAT solver is invoked and a WCNF file is input. The solution is then performed using a local search algorithm based on a look-ahead sampling strategy and a Dist-weighted strategy, including: The initialization assignment of variables is generated using the cell propagation process, and the clause weights are initialized; wherein, the initialization assignment includes: initializing the termination time of the solver execution and the maximum number of fault-free components in the circuit; The target variable is determined based on the look-ahead sampling strategy and then flipped. After the target variable is flipped, if the current solution satisfies all hard clause constraints and the sum of the weights of the unsatisfied soft clauses is minimized, then the Dist weighting strategy is called to update the weights of the soft and hard clauses respectively.

[0016] In some exemplary embodiments, the method further includes: Randomly select at least one target component from the set of fault-free components corresponding to an iteration round, and delete the subsequent node components corresponding to the target component.

[0017] According to a second aspect of the present invention, a computer program product is provided, on which a computer program is stored, and when the computer program is executed by a processor, it implements the above-described method for fault diagnosis based on MaxSAT.

[0018] According to a third aspect of the present invention, a storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described method for fault diagnosis based on MaxSAT.

[0019] According to a fourth aspect of the present invention, an electronic device is provided, comprising: Processor; and Memory for storing the executable instructions of the processor; The processor is configured to implement the above-described method for fault diagnosis based on MaxSAT by executing the executable instructions.

[0020] The fault diagnosis method based on MaxSAT provided in this invention constructs a fault location model, encodes hard and soft clauses, and assigns weights to hard and soft clauses according to the hierarchical relationship of components in the fault location model, thereby constructing a more accurate MaxSAT problem. By iteratively applying the MaxSAT algorithm to the fault location model to reduce candidate components, the fault location model is gradually reduced, achieving fault diagnosis. This method, through the fault location model and the MaxSAT algorithm, can identify the maximum number of components with output logic changes in different observations, effectively removing fault-free components from the candidate diagnoses. It outperforms existing advanced technologies on standard test benchmarks, achieving reliable diagnosis of complex systems.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0023] Figure 1 The diagram illustrates an exemplary embodiment of the present invention of a method for fault diagnosis based on MaxSAT. Figure 2 This diagram schematically illustrates a fault location model of a combinational circuit according to an exemplary embodiment of the present invention. Figure 3 This diagram illustrates an exemplary embodiment of the present invention of a fault location model change triggered by {X2=0}. Figure 4This schematic diagram illustrates an exemplary embodiment of the present invention where a stuck-at-0 fault occurs in H1, causing H2 to output an error. Figure 5 This diagram illustrates a fault diagnosis process according to an exemplary embodiment of the present invention. Figure 6 The schematic diagram illustrates an example combinational logic circuit according to an exemplary embodiment of the present invention; Figure 7 The diagram illustrates a fault location model of an example circuit according to an exemplary embodiment of the present invention. Figure 8 This diagram illustrates a diagnostic process for an integrated circuit fault according to an exemplary embodiment of the present invention. Figure 9 The diagram illustrates the composition of an electronic device according to an exemplary embodiment of the present invention. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0026] In related technologies, in the model-based diagnostic definition, SD represents the system description, Obs represents the observed system behavior, and COMPS represents the set of components in the system. The health state of each component is represented by H(c), and if H(c) is assigned a false value (i.e., a value of 0), it indicates that the component is faulty. Assuming that every component c in the system is in a healthy state, if there is a contradiction (i.e., inconsistency) between the system description and the observed behavior, a diagnostic problem is considered to exist. Existing model diagnostic methods identify faulty components of the system through probe-based sequential diagnostic methods and SAT coding methods. Although these methods can effectively identify minimal diagnostic solutions and reduce the time required for diagnosis, they often generate a large number of redundant candidate diagnoses and do not consider whether the components in these candidate diagnoses can accurately reflect their own fault state.

[0027] To address the shortcomings and deficiencies of existing technologies, this example embodiment provides a method for fault diagnosis based on MaxSAT, which can be applied to the diagnosis and identification of faulty components in integrated circuits. (Reference) Figure 1 As shown, a method for fault diagnosis based on MaxSAT may specifically include the following steps: Step S11: Create a corresponding replica circuit for the original circuit to be analyzed; configure new sentinel gates for each logic gate in the original circuit and the corresponding replica gates in the replica circuit, and connect the output terminals of the logic gates and replica gates to the input terminals of the sentinel gates to build a fault location model. Step S12: Hard-entry encoding is performed on each logic gate in the original circuit, each copy gate in the replica circuit, and the sentinel gate to obtain the corresponding cell hard-entry; wherein, the cell hard-entry is used to describe the health state constraints of the logic gate. Step S13: Encode the sentry gate using soft clauses to obtain the corresponding unit soft clauses; Step S14: Based on the hierarchical relationship of each sentry gate in the circuit of the fault location model, the soft clauses are weighted; and based on the number of components in the original circuit, the hard clauses are weighted. Step S15: Combine soft clauses, hard clauses, and corresponding weights to construct a MaxSAT problem based on the fault location model; and call the MaxSAT solver to solve the MaxSAT problem in order to identify fault-free components in the original circuit. Step S16: Based on the identification results of the fault-free components, determine the preferred faulty components to achieve fault location.

[0028] The following will describe in more detail each step of a method for fault diagnosis based on MaxSAT in this exemplary embodiment, with reference to the accompanying drawings and embodiments.

[0029] In step S11, a corresponding replica circuit is created for the original circuit to be analyzed; for each logic gate in the original circuit, a new sentinel gate is configured with the corresponding replica gate in the replica circuit, and the output terminals of the logic gates and replica gates are connected to the input terminals of the sentinel gates to construct a fault location model.

[0030] For example, step S11 described above may include: Step S21: Copy the original circuit to be analyzed to create a corresponding copy circuit, and configure the corresponding copy identifier for each copied component in the copy circuit with reference to the original circuit. Step S22: Configure sentinel gates for each logic gate in the original circuit, and connect the output terminals of each logic gate in the original circuit, the output terminals of the corresponding replica gates in the replica circuit, and the input terminals of the corresponding sentinel gates to construct a fault location model; wherein, the sentinel gates are used to compare the output signals of the logic gates in the original circuit with the output signals of the corresponding replica gates in the replica circuit.

[0031] Specifically, the original circuit to be analyzed can be an integrated circuit in a smart terminal, vehicle terminal, or IoT terminal device. After selecting the original circuit to be analyzed, the user can create a corresponding fault diagnosis task on the smart terminal device and input the corresponding original circuit.

[0032] After determining the original circuit, a complete copy of the original circuit can be created first, resulting in a copy circuit. For each logic gate in the original circuit, the corresponding copy gate in the copy circuit is then configured with a copy identifier. For example, all copied components are marked with an ''' tag over the original component; assuming the original component is H1, its copied component is denoted as H1'.

[0033] Between the original and replica circuits, a new sentinel gate can be configured for each logic gate and its corresponding replica. Specifically, for each logic gate H and its replica H', their outputs are connected to a newly added XOR gate, also known as the sentinel gate. The sentinel gate satisfies the operational relationships of the basic logic units, describes the consistency of the outputs of the original and replica gates, and allows the fault location model of the basic logic units to be described using a standard hardware design language.

[0034] The XOR gate outputs 0 when the outputs of the logic gate and its corresponding copy gate are the same; if the two gates output different values, the XOR gate outputs 1. If the original logic gate H has a stuck-at-0 fault, its output is always 0, but the output of the normally functioning copy gate H' will change with the input. When the XOR gate outputs 1, it indicates that the original logic gate and the copy gate produce different responses to the same input. The original gate may have a stuck-at-0 (stuck-at-1) fault because its output does not change under different input values. When the XOR output is 0, it indicates that the original logic gate is not faulty, and its output is consistent with the output of a normal circuit. Based on the above principles, a fault location model for the circuit can be designed, relying on the output of the sentinel gate to detect the characteristics of a stuck-at-0 (stuck-at-1) fault, thereby achieving fault detection.

[0035] A fault location model is constructed by adding sentinel gates to both the original and replica circuits. Test vectors generated from this model can be used to compare the output of the original circuit with the output of its replica circuit, thereby identifying fault-free components.

[0036] For example, refer to Figure 2 In the fault location model shown, X1 and X2 are both sentinel gates. Their outputs can be used to determine whether H1 and H2 have a stuck-at-0 (stuck-at-1) fault. If a set of observations can be found that makes the output of X1 0, it indicates that H1 is not faulty.

[0037] In step S12, each logic gate in the original circuit, each copy gate in the replica circuit, and the sentinel gate are hard-coded to obtain the corresponding cell hard-text; wherein, the cell hard-text is used to describe the health state constraints of the logic gate.

[0038] For example, step S12 includes: Step S31: Hard clause encoding is performed on the inputs and outputs of each logic gate in the original circuit to obtain the unit hard clauses corresponding to each logic gate based on the conjunctive normal form format; wherein, the unit hard clauses corresponding to the logic gate are used to describe the behavior of the logic gate and realize the health status description of the logic gate behavior. Step S32: Hard clause encoding is performed on the inputs and outputs of each replication gate in the replication circuit to obtain the unit hard clauses based on the conjunction normal form for each replication gate. Step S33: Hard-encode the output of the sentinel gate to obtain the corresponding unit hard clause based on the conjunctive normal form; wherein, the unit hard clause of the sentinel gate is used to indicate whether the single output of the logic gate in the original circuit is consistent with the output of the corresponding copy gate in the replica circuit.

[0039] Specifically, for the original logic gates and their replicas in the fault location model, their health state constraints can be described using unit clauses. Specifically, the health state constraints of the original logic gate H1 and its replica gate H1' are encoded into hard clauses, generating two unit hard clauses, H1 and H1'. For all gates in the fault location model, their logical behavior is described using conjunctive normal form. Assuming that the inputs to the AND gate H1 (i.e., the logic gate in the original circuit) in the fault location model are A1 and B1, and the output is D1; ​​and the inputs to the replica gate H1' are A1' and B1', and the output is D1', six hard clauses are needed to describe the behavior of H1 and H1'.

[0040] Specifically, this includes: AND gate H1 based on A1 B1→D1, resulting in ¬A1 D1 ¬B1; Based on ¬A1→¬D1, we get A1 ¬D1; Based on ¬B1→¬D1, we obtain B1. Similarly, we obtain ¬D1'. D1' ¬B'、A1' ¬D1', ¬B1' → ¬D'. Similarly, encode other gates using the same method.

[0041] Additionally, the output of the sentinel gate can be encoded using unit hard clauses. The sentinel gate's function is to describe whether the outputs of the original logic gate H and the copy gate H' are consistent; if the outputs are the same, the sentinel gate outputs 0; otherwise, it outputs 1. Figure 2 For example, after encoding, you will get two unit hard clauses: O1 and O2.

[0042] Hard clause encoding uniformly adopts the conjunctive normal form, which must represent all input-output correspondences of the logic gate under all possible input combinations. The behavior of all encoded logic gates is described to achieve a health status description of the gate behavior.

[0043] In step S13, the sentry gate is encoded with soft clauses to obtain the corresponding unit soft clauses.

[0044] For example, for each sentry gate in the fault location model, all sentry gates are encoded as unit soft clauses. The soft clause encoding uses a unit clause format, with one unit soft clause corresponding to each sentry gate. For example... Figure 2 The soft clauses for the sentinel gates in the model are: ¬X1 and ¬X2. To calculate candidate diagnoses based on this fault location model, the MaxSAT solver is used to obtain the values ​​of all variables. A value of 1 for all variables representing sentinel gates in the soft clauses indicates that the corresponding component is fault-free, as these values ​​vary across different observations.

[0045] In step S14, the soft clauses are weighted according to the hierarchical relationship of each sentry gate in the circuit of the fault location model; and the hard clauses are weighted according to the number of components in the original circuit.

[0046] For example, step S14 may specifically include: Step S41: Based on the hierarchical relationship of each sentry gate in the circuit of the fault location model, configure the corresponding minimum level and maximum level according to the preset hierarchical weight strategy. Step S42: Randomly select an integer from the minimum level to the maximum level as the weight of the soft clause.

[0047] An example, a hierarchical weighting strategy includes: Step S51: Obtain the association between the component and the system inputs and outputs; Step S52: When the component is directly connected to the system input terminal, configure the minimum level corresponding to the component to be set to 1; Step S53: When the output of a component is the system output, configure the maximum level assignment and the minimum level assignment of the component to be equal; Step S54: When the component is a non-system input / output component, increment the maximum value of the minimum level of each component associated with the input terminal of the component by 1; decrement the minimum value of the minimum level of each component associated with the output terminal of the component by 1.

[0048] Specifically, the weights of the generated hard clauses and soft clauses can be calculated separately.

[0049] First, the weighting of soft clauses can be configured based on a hierarchical weighting strategy. Each component will be assigned a minimum level and a maximum level. In summary, the weighting of soft and hard clauses follows different allocation principles. The weight of soft clauses is set to a random value within a certain range using a hierarchical optimization principle, and soft clauses generated by components in different positions are assigned different weights.

[0050] Specifically: First, the newly created circuit is divided into multiple levels. The minimum level of components directly connected to the system input is assigned a value of 1. The maximum level of components directly generating system output is set to be equal to the minimum level. The minimum input level of other components is assigned the maximum value of the minimum levels of all input parts of that component plus 1, and the maximum output level is assigned the minimum value of the minimum levels of all output parts of that component minus 1. Assume component c belongs to level L. i If and only if the minimum level of the component is ≤ L i≤ The maximum level of the component. For the sentinel gate component involved in the soft unit clause obtained in step 3, obtain the minimum level and maximum level of the component, and randomly select an integer within the range of minimum level to maximum level as the weight of its corresponding soft clause.

[0051] Subsequently, the hard clauses can be weighted. Specifically, by calculating the total number of all components in the circuit, the weight of all hard clauses is assigned to the total number of components. Under this rule, the weight of each hard clause is the same. This can be achieved by assigning weights to the hard clauses based on the statistical results of the number of components in the original circuit. Alternatively, in some exemplary embodiments, the weights can also be assigned based on the statistical results of all components in the fault diagnosis model that include the sentinel gate.

[0052] By assigning a weight to each hard clause equal to the total number of all components, the weight of each hard clause remains fixed, making it easier to prioritize its satisfaction.

[0053] In step S15, a MaxSAT problem based on the fault location model is constructed by combining soft clauses, hard clauses, and corresponding weights; and the MaxSAT solver is called to solve the MaxSAT problem in order to identify fault-free components in the original circuit.

[0054] For example, step S15 described above may include: Step S61: Define constraints based on soft clauses, hard clauses, and corresponding weights, construct a MaxSAT problem based on the fault location model based on the constraints, and encode the corresponding WCNF file. Step S62: Call the MaxSAT solver and input the WCNF file. Use a local search algorithm based on look-ahead sampling strategy and Dist weighting strategy to solve the problem. Determine the set of fault-free components in the original circuit based on the solution results.

[0055] For example, step S62 above may specifically include: generating initialization assignments for variables using the cell propagation process and initializing clause weights; wherein, initialization assignments include: initializing the termination time of the solver execution and the maximum number of fault-free components in the circuit; and determining the target variable based on the look-ahead sampling strategy and flipping the target variable; after the target variable is flipped, if the current solution satisfies all hard clause constraints and the sum of the unsatisfied soft clause weights is minimized, then the Dist weighting strategy is invoked to update the weights of the soft and hard clauses respectively.

[0056] Specifically, based on the calculated weights of hard and soft clauses, the fault location model can be transformed into a MaxSAT problem. By calling the MaxSAT solver and inputting a Tseitin-encoded WCNF file, fault-free components can be identified. Subsequently, an incomplete MaxSAT algorithm—NuFPS—combining a look-ahead sampling strategy and a Dist weighting strategy is implemented. The input to this algorithm is a WCNF (Weighted Conjunctive Normal Form) file containing the weighted conjunctive normal forms obtained in the previous steps. Under the constraints of these conjunctive normal forms, the NuFPS algorithm performs a local search based on the fault location model to determine a feasible solution, which corresponds to a diagnostic solution. The look-ahead sampling strategy prevents the algorithm from getting trapped in local optima, and the Dist weighting strategy updates the distinguishing clauses through clause weights.

[0057] Specifically, the NuFPS algorithm first initializes the solver's termination time, the maximum number of fault-free components in the circuit, and the weight parameters. It then employs an incomplete algorithm combining look-ahead sampling and Dist weighting strategies to solve for fault-free components. During initialization, the cell propagation process generates variable initialization assignments and initializes clause weights. In the local search phase, a variable is flipped. The core of the two-stage look-ahead strategy is to select the best variable based on the scoring function and then find a second-best variable. The two-stage look-ahead strategy allows for the selection of a better variable for flipping at this stage. After flipping, if the current solution satisfies all hard clause constraints and the sum of unsatisfied soft clause weights is minimized (i.e., the number of fault-free components reaches its maximum), the optimal solution and the number of fault-free components are updated. After each variable flip, the Dist weighting strategy is used to update the weights of soft and hard clauses separately. By updating the hard and soft clause weights in different ways, the algorithm's performance is improved. If, after the algorithm terminates, there exists a copy of an input pair under the constraint that the output of XOR gate X1 is 1, it indicates that component H1 in the original circuit corresponding to X1 has not experienced a stuck-at-0 fault. The local search process for the fault location model must ensure that the hard clause constraints are satisfied; if the constraints are violated, the current path is immediately terminated.

[0058] In step S16, the preferred faulty component is determined based on the identification result of the fault-free component to achieve fault location.

[0059] For example, step S16 described above may specifically include: Step S71: Simplify the fault location model based on the set of fault-free components and update the fault diagnosis solution; Step S72: Iteratively call the MaxSAT solver to solve the simplified fault location model and obtain the set of fault-free components that satisfy all hard clauses and maximize the weight of the soft clauses. Step S73: If the set of fault-free components is not empty, update the length of the fault diagnosis solution and update the fault location model; otherwise, terminate the loop.

[0060] For example, the method further includes: randomly selecting at least one target component from the set of fault-free components corresponding to an iteration round, and deleting the subsequent node components corresponding to the target component.

[0061] Specifically, the method in step S15 can successfully identify fault-free components in a single round of MaxSAT calls, and continuous calls to NuFPS can effectively identify fault-free components. An EMBD (Enhanced Model-Based Diagnosis) algorithm is designed to coordinate the interaction between the algorithm and the fault location model, thereby achieving fault location.

[0062] Specifically, during the initialization phase, the maximum number of fault-free components in the circuit is set to the sum of the number of all components. The optimal solution found in step S14 is recorded, as well as the length of the fault diagnosis solution found during the diagnosis process. During the diagnosis phase, the method in step S15 is iteratively called, returning an assignment that satisfies all hard clauses and maximizes the weight of the soft clauses, along with its set of fault-free components. If the set of fault-free components is not empty, the length of the fault diagnosis solution is updated and the model is updated; otherwise, the loop terminates. By iteratively executing the above method, a closed-loop process of "identification, simplification, re-identification, ..." is achieved. Each iteration reduces the size of candidate components, converts some satisfied soft clauses into hard clauses, and reduces additional constraints.

[0063] In addition, due to fault propagation, some normal components may be incorrectly identified as faulty, such as... Figure 3 , Figure 4 As shown, it is necessary to randomly delete the subsequent nodes of the components in the diagnostic solution to avoid misjudgment.

[0064] For example, using ISCAS-85 and ITC-99 reference circuits, a random function is used to randomly insert stuck-at-0 and stuck-at-1 faults into the circuit, simulating a fault generation dataset in the system. Specifically, we obtain the system output corresponding to the system input using the SAT algorithm in the fault location model. The experimental hardware environment uses an Intel Xeon E5-1607 @ 3.00GHz processor, 16GB of memory, and Ubuntu 16.04 Linux. We use Tseitin encoding to generate WCNF files and call the MaxSAT solver to implement the EMBD method proposed in this invention.

[0065] refer to Figure 5 , Figure 7 The method shown, combined with the model-based fault diagnosis method of local search MaxSAT, includes at least the following steps: Step 1: Construct a fault location model by inserting XOR gates into the original circuit and its replica circuit; Step 2: Generate WCNF clauses using the system description, observations, and component states in the coded circuit; Step 3: Use the NuFPS algorithm to iteratively search and identify fault-free components; Step 4: Optimize the diagnostic results using the EMBD algorithm to reduce the number of candidate solutions and improve diagnostic efficiency.

[0066] Specifically, the system flowchart in this example is as follows: Figure 5 First, four stuck-at type faults are randomly injected into the circuit. The fault locations are randomly determined by an algorithm. Two sets of system inputs are generated using the MaxSAT solver to simulate the fault propagation effect and obtain the system output. Then, a model containing the original circuit and a replica circuit is constructed. The outputs of the corresponding original and replica gates are connected via XOR gates. A hierarchical weighting strategy is adopted, assigning different weights to gates at different locations. The NuFPS algorithm is then iteratively called. In each round, the MaxSAT solver is called to identify some fault-free components. Based on the results, the model is simplified by converting soft clause constraints involving fault-free gates into hard clause constraints. Redundant clauses are then eliminated through cell propagation of hard clauses, and the remaining candidate components are solved again. A dynamically adjusted search strategy is used for fault localization. For components misjudged due to fault propagation, subsequent gate nodes connected to them due to the influence of logic propagation are randomly deleted.

[0067] Simultaneously, actual faults 2, 4, 8, and 12 were injected, and the above steps were repeated. The diagnostic results were compared with traditional model diagnostic methods (HSD, CMMO, DiagDO, and DPDN). It was found that under different fault scenarios, EMBD significantly improved the fault identification rate compared to existing model diagnostic methods, achieving 100% fault coverage (the ratio of correctly identified faults to actual faults). The average diagnostic performance of EMBD reached 34.94%, 38.22%, 35.05%, and 38.79%, respectively, representing improvements of 673.6%, 254.2%, 211.5%, and 283.2% compared to traditional model diagnostic methods, and the diagnosis could be completed within approximately 300 seconds. In the best-case scenario, when the number of faults was 4, EMBD could achieve accurate fault location for c5315. In some test cases, EMBD performed poorly because the EMBD using the Downsizing Strategy might randomly remove some actual faulty components from the candidate diagnoses. Experimental results show that EMBD can significantly improve diagnostic accuracy and identify the true cause of faults, validating the effectiveness of this method.

[0068] like Figure 6 In the circuit, a stuck-at-1 fault exists. Assume that example i1...i6 = 011111, the corresponding correct system outputs O1,O2 = 01 and the faulty (actual) system outputs O1,O2 = 11. Blue and red values ​​are used to annotate the circuit; red values ​​are actual observations, whose outputs can be explicitly obtained through observation; blue values ​​are expected observations after propagating the input logic. If the blue and red values ​​of the system outputs are different, we say that at least one faulty component exists. Then, a fault localization model is constructed by replicating the circuit and inserting sentinel gates, such as... Figure 7 As shown, soft and hard clauses are generated through Tsetin encoding and solved using NuFPS. The initial diagnosis is {G1,G2,G3,G4,G5}. During the iteration process, G5 is determined to be fault-free and the relevant clauses of G5 are converted into hard clause constraints to simplify the model. In the next iteration, the fault-free components are reduced one by one. When X1 is detected to be always 1, it indicates that G1 is abnormal. The weights are dynamically adjusted, and finally the fault diagnosis {G1} is obtained.

[0069] The method provided in the embodiments of the present invention is referred to Figure 8As shown, by replicating the circuit under test and inserting an XOR gate to compare the output of the original circuit with the output of its replica, a formal fault location model is established using the weighted conjunctive paradigm. Based on look-ahead sampling strategies, a local search MaxSAT algorithm is designed to identify the number of components with the largest output logic variation across different observations, effectively removing fault-free components from candidate diagnoses. Compared with existing model diagnostic methods, this invention can accurately identify faulty components, has higher accuracy and practicality, and significantly improves existing state-of-the-art model diagnostic algorithms. It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously in multiple modules, for example.

[0070] It should be noted that although several modules or units of the device for performing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0071] Figure 9 A schematic diagram of an electronic device suitable for implementing embodiments of the present invention is shown.

[0072] It should be noted that, Figure 9 The electronic device 1000 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0073] like Figure 9 As shown, the electronic device 1000 includes a Central Processing Unit (CPU) 1001, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 1002 or programs loaded from storage section 1008 into Random Access Memory (RAM) 1003. The RAM 1003 also stores various programs and data required for system operation. The CPU 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An Input / Output (I / O) interface 1005 is also connected to the bus 1004. Furthermore, the electronic device 1000 also includes an FPGA device and a System-on-a-Chip (SoC) device.

[0074] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage section 1008 as needed.

[0075] In particular, according to embodiments of the present invention, the processes described below with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a storage medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1009, and / or installed from removable medium 1011. When the computer program is executed by central processing unit (CPU) 1001, it performs various functions defined in the system of this application.

[0076] Specifically, the aforementioned electronic devices can be airborne intelligent electronic devices, such as airborne video processing equipment.

[0077] It should be noted that the storage medium shown in the embodiments of the present invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, wherein computer-readable program code is carried. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0079] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0080] It should be noted that, as another aspect, this application also provides a storage medium, which may be included in an electronic device or may exist independently without being assembled into the electronic device. The aforementioned storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the methods described in the following embodiments. For example, the electronic device may perform... Figure 1 The steps of the method shown.

[0081] In one embodiment, this application provides a computer program product including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0082] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0083] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0084] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for fault diagnosis based on MaxSAT, characterized in that, The method includes: Create a corresponding replica circuit for the original circuit to be analyzed; configure new sentinel gates for each logic gate in the original circuit and the corresponding replica gates in the replica circuit, and connect the output terminals of the logic gates and replica gates to the input terminals of the sentinel gates to build a fault location model; Hard clause encoding is performed on each logic gate in the original circuit, each copy gate and sentinel gate in the replica circuit to obtain the corresponding cell hard clause; among them, the cell hard clause is used to describe the health state constraints of the logic gate; Encode the sentry gate using soft clauses to obtain the corresponding unit soft clauses; Based on the hierarchical relationship of each sentry gate in the circuit of the fault location model, the soft clauses are weighted; and based on the number of components in the original circuit, the hard clauses are weighted. By combining soft clauses, hard clauses, and their corresponding weights, a MaxSAT problem based on a fault location model is constructed; and the MaxSAT solver is called to solve the MaxSAT problem in order to identify fault-free components in the original circuit. Based on the identification results of fault-free components, the preferred faulty components are determined in order to achieve fault location.

2. The method according to claim 1, characterized in that, Create a corresponding replica circuit for the original circuit to be analyzed; configure new sentinel gates for each logic gate in the original circuit and its corresponding replica gate in the replica circuit, and connect the outputs of the logic gates and replica gates to the inputs of the sentinel gates to construct a fault location model, including: The original circuit to be analyzed is copied to create a corresponding replica circuit, and the replica identifier is configured for each replicated component in the replica circuit with reference to the original circuit. Sentinel gates are configured for each logic gate in the original circuit, and the output terminals of each logic gate in the original circuit, the output terminals of the corresponding replica gates in the replica circuit, and the input terminals of the corresponding sentinel gates are connected to construct a fault location model. The sentinel gates are used to compare the output signals of the logic gates in the original circuit with the output signals of the corresponding replica gates in the replica circuit.

3. The method according to claim 1, characterized in that, The step of hard-encoding each logic gate in the original circuit, each replica gate in the replica circuit, and the sentinel gate to obtain the corresponding unit hard-word includes: Hard clause encoding is performed on the inputs and outputs of each logic gate in the original circuit to obtain the unit hard clauses based on the conjunctive normal form format corresponding to each logic gate; wherein, the unit hard clauses corresponding to the logic gate are used to describe the behavior of the logic gate and realize the health status description of the logic gate behavior; Hard clause encoding is performed on the inputs and outputs of each replication gate in the replication circuit to obtain the unit hard clauses based on the conjunction normal form for each replication gate; The output of the sentinel gate is hard-coded to obtain the corresponding unit hard clause based on the conjunctive normal form. The unit hard clause of the sentinel gate is used to indicate whether the single output of the logic gate in the original circuit is consistent with the output of the corresponding copy gate in the replica circuit.

4. The method according to claim 1, characterized in that, Based on the hierarchical relationship of each sentry gate in the fault location model circuit, the soft clauses are weighted, including: Based on the hierarchical relationship of each sentry gate in the circuit of the fault location model, the corresponding minimum level and maximum level are configured according to the preset hierarchical weight strategy; Randomly select an integer from the minimum to the maximum level as the weight of the soft clause.

5. The method according to claim 4, characterized in that, The method further includes: pre-constructing a hierarchical weighting strategy, including: Obtain the relationships between components and system inputs and outputs; When a component is directly connected to a system input, the minimum level corresponding to that component is configured to be 1. When the output of a component is system output, configure the maximum level assignment and the minimum level assignment of the component to be equal; When the component is a non-system input / output component, increment the maximum value of the minimum level of each component associated with the input terminal by 1; decrement the minimum value of the minimum level of each component associated with the output terminal by 1.

6. The method according to claim 1, characterized in that, The hard clauses are weighted according to the number of components in the original circuit, including: Determine the total number of components corresponding to the components in the original circuit; Assign weights to each hard clause based on the total number of components.

7. The method according to claim 1, characterized in that, We construct a MaxSAT problem based on a fault location model by combining soft clauses, hard clauses, and their corresponding weights. The MaxSAT solver is then invoked to solve the MaxSAT problem in order to identify fault-free components in the original circuit, including: Define constraints based on soft clauses, hard clauses, and corresponding weights, construct a MaxSAT problem based on the fault location model based on the constraints, and encode the corresponding WCNF file. The MaxSAT solver is invoked and a WCNF file is input. The local search algorithm based on look-ahead sampling and Dist weighting is used to solve the problem. The set of fault-free components in the original circuit is determined based on the solution results.

8. The method according to claim 7, characterized in that, Based on the identification results of fault-free components, preferred faulty components are determined to achieve fault location, including: The fault location model is simplified based on the set of fault-free components, and the fault diagnosis solution is updated. The simplified fault location model is solved by iteratively calling the MaxSAT solver to obtain the set of fault-free components that satisfy all hard clauses and maximize the weight of the soft clauses. If the set of fault-free components is not empty, update the length of the fault diagnosis solution and update the fault location model; otherwise, terminate the loop.

9. The method according to claim 7, characterized in that, The MaxSAT solver is invoked, and a WCNF file is input. A local search algorithm based on a look-ahead sampling strategy and a Dist weighted strategy is used for solution, including: The initialization assignment of variables is generated using the cell propagation process, and the clause weights are initialized; wherein, the initialization assignment includes: initializing the termination time of the solver execution and the maximum number of fault-free components in the circuit; The target variable is determined based on the look-ahead sampling strategy and then flipped. After the target variable is flipped, if the current solution satisfies all hard clause constraints and the sum of the weights of the unsatisfied soft clauses is minimized, then the Dist weighting strategy is called to update the weights of the soft and hard clauses respectively.

10. The method according to claim 8, characterized in that, The method further includes: Randomly select at least one target component from the set of fault-free components corresponding to an iteration round, and delete the subsequent node components corresponding to the target component.

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