Method for performing logical operations based on memory, memory

Abstract

Embodiments of the present application provide a method for performing a logic operation based on a memory, and a memory; wherein the logic operation includes an AND logic operation or an OR logic operation; when performing the AND logic operation or the OR logic operation, the method comprises: step S11, pre-charging a first bit line and a second bit line to a reference voltage; step S12, causing 3m first storage units to perform charge sharing with the first bit line, and simultaneously causing 3n second storage units to perform charge sharing with the second bit line, to form a first voltage difference on the first bit line and the second bit line; wherein m+n≥2, m is a positive integer, and n is a non-negative integer; step S13, amplifying the first voltage difference on the first bit line and the second bit line by a sense amplifier, to obtain a target result of the AND logic operation or the OR logic operation on the first bit line or the second bit line.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a method for performing logic operations based on memory, and a memory. Background Technology

[0002] Logic gates based on CMOS technology are the physical foundation of digital integrated circuits. Their core principle is to use complementary pairs of NMOS and PMOS transistors to construct basic units for implementing Boolean operations. For example, AND and OR gates are usually composed of 6 transistors, while NOT gates are usually composed of 2 transistors.

[0003] However, in the traditional von Neumann architecture, the computing and storage units are separated, leading to frequent data transfer between them, which can account for more than 60% of the total power consumption. Therefore, with the rise of data-intensive applications such as AI inference and edge computing, achieving orders-of-magnitude improvements in energy efficiency and computing speed has become a key optimization direction. Summary of the Invention

[0004] This application provides a method for performing logical operations based on a memory, and a memory.

[0005] In a first aspect, embodiments of this application provide a method for performing logical operations based on a memory, wherein the memory includes a sense amplifier, a first memory array, and a second memory array; wherein the first memory array includes a first bit line and a plurality of first memory cells, the plurality of first memory cells being coupled to the sense amplifier via the first bit line; the second memory array includes a second bit line and a plurality of second memory cells, the plurality of second memory cells being coupled to the sense amplifier via the second bit line; the logical operation includes an AND logical operation and an OR logical operation, and when performing the AND logical operation or the OR logical operation, the method includes:

[0006] Step S11: Precharge the first bit line and the second bit line to the reference voltage;

[0007] Step S12: 3m first memory cells share charge with the first bit line, and simultaneously, 3n second memory cells share charge with the second bit line to form a first voltage difference on the first bit line and the second bit line; where m+n≥2, m is a positive integer and n is a non-negative integer;

[0008] Step S13: The first voltage difference between the first bit line and the second bit line is amplified by the sensing amplifier to obtain the target result of the AND logic operation or the OR logic operation on the first bit line.

[0009] In some embodiments, the data stored in the second storage unit and the corresponding data stored in the first storage unit are inverse data; before performing step S11, the method further includes:

[0010] The second storage unit stores data that is the opposite of the corresponding first storage unit; or...

[0011] The first bit line and the second bit line are precharged to the reference voltage; after the m first storage cells storing the same data in the 3m first storage cells share the charge with the first bit line, the voltage difference between the first bit line and the second bit line is amplified by the sensing amplifier to obtain the inverted data of the same data on the second bit line; the inverted data of the same data is written into the n second storage cells corresponding to the m first storage cells.

[0012] In some embodiments, m=1, n=1, one of the three first storage units is used to store fixed data, the fixed data is used to characterize the AND logic operation or the OR logic operation, and the other two of the three first storage units are used to store data to be operated;

[0013] In step S13, the target result is written into any of the first storage cells corresponding to the first bit line.

[0014] In some embodiments, m=2 and n=1, the first bit line includes a first portion and a second portion extending along a first direction, and a first connection portion electrically connecting the first portion and the second portion; the six first storage cells are arranged in a 2×3 array, and two adjacent first storage cells along the second direction are respectively coupled to the first portion and the second portion and form a pair of first storage cells storing the same data; one of the three pairs of first storage cells is used to store fixed data, the fixed data being used to characterize the AND logic operation or the OR logic operation, and the other two of the three pairs of first storage cells are used to store data to be operated;

[0015] In step S13, the target result is written into any of the first memory cell pairs corresponding to the first bit line;

[0016] The first direction and the second direction are two intersecting directions on the plane where the memory is located.

[0017] In some embodiments, m=2 and n=0, the first bit line includes a first portion and a second portion extending along a first direction, and a first connection portion electrically connecting the first portion and the second portion; the six first storage cells are arranged in a 2×3 array, and two adjacent first storage cells along the second direction are respectively coupled to the first portion and the second portion and form a pair of first storage cells storing the same data; one of the three pairs of first storage cells is used to store fixed data, the fixed data being used to characterize the AND logic operation or the OR logic operation, and the other two of the three pairs of first storage cells are used to store data to be operated;

[0018] In step S13, the target result is written into any of the first memory cell pairs corresponding to the first bit line.

[0019] In some embodiments, m=1, n=2, one of the three first storage units is used to store fixed data, the fixed data is used to characterize the AND logic operation or the OR logic operation, and the other two of the three first storage units are used to store data to be operated;

[0020] The second bit line includes a third part and a fourth part extending along the first direction, and a second connection part electrically connecting the third part and the fourth part; the six second storage cells are arranged in a 2×3 array, and two adjacent second storage cells along the second direction are respectively coupled to the third part and the fourth part, and form a pair of second storage cells storing the same data;

[0021] In step S13, the target result is written into any of the first storage cells corresponding to the first bit line.

[0022] In some embodiments, the logical operation further includes a NOT logical operation; the first memory array further includes a third bit line adjacent to the first bit line, and a third memory cell coupled to the third bit line; one of the plurality of first memory cells serves as a fourth memory cell; the lower electrode of the capacitor of the third memory cell and the corresponding fourth memory cell are coupled to the same node; when performing the NOT logical operation, the method includes:

[0023] Step S21: Precharge the first bit line and the second bit line to the reference voltage;

[0024] Step S22: The fourth memory cell shares charge with the first bit line to form a second voltage difference between the first bit line and the second bit line;

[0025] Step S23: The second voltage difference between the first bit line and the second bit line is amplified by the sensing amplifier to obtain the target result of the non-logic operation on the second bit line;

[0026] Step S24: The target result on the second bit line is transmitted to the third bit line and written to the third storage unit.

[0027] In some embodiments, the memory further includes control circuitry connected between the second bit line and the third bit line; step S24 includes:

[0028] The target result on the second bit line is transmitted to the third bit line through the control circuit and written into the third storage unit.

[0029] Secondly, embodiments of this application provide a memory, the memory including a sensing amplifier, a first memory array, and a second memory array;

[0030] The first memory array includes a first bit line and a plurality of first memory cells, the plurality of first memory cells being coupled to the sense amplifier via the first bit line;

[0031] The second memory array includes a second bit line and a plurality of second memory cells, the plurality of second memory cells being coupled to the sense amplifier via the second bit line;

[0032] The first storage array further includes a third bit line adjacent to the first bit line, and a third storage cell coupled to the third bit line; one of the plurality of first storage cells serves as a fourth storage cell; the lower electrode of the capacitor of the third storage cell and the corresponding fourth storage cell are coupled to the same node;

[0033] The memory also includes control circuitry connected between the second bit line and the third bit line.

[0034] In some embodiments, the first bit line includes a first portion and a second portion extending along a first direction, and a first connection portion electrically connecting the first portion and the second portion; two adjacent first memory cells along a second direction are respectively coupled to the first portion and the second portion and constitute a pair of first memory cells storing the same data; or,

[0035] The second bit line includes a third portion and a fourth portion extending along the first direction, and a second connection portion electrically connecting the third portion and the fourth portion; two adjacent second storage cells along the second direction are respectively coupled to the third portion and the fourth portion and form a pair of second storage cells storing the same data;

[0036] The first direction and the second direction are two intersecting directions on the plane where the memory is located.

[0037] This application provides a method for performing logical operations based on a memory, and a memory; wherein the memory includes a sensing amplifier, a first memory array, and a second memory array; wherein the first memory array includes a first bit line and a plurality of first memory cells, the plurality of first memory cells being coupled to the sensing amplifier through the first bit line; the second memory array includes a second bit line and a plurality of second memory cells, the plurality of second memory cells being coupled to the sensing amplifier through the second bit line; the logical operation includes an AND logical operation and an OR logical operation, and when performing the AND logical operation and the OR logical operation, the method includes: step S11, pre-charging the first bit line and the second bit line to a reference voltage; step S12, making 3m first memory cells share charge with the first bit line, and simultaneously making 3n second memory cells share charge with the second bit line, so as to form a first voltage difference on the first bit line and the second bit line; wherein m+n≥2, m is a positive integer, and n is a non-negative integer; step S13, amplifying the first voltage difference on the first bit line and the second bit line through the sensing amplifier, so as to obtain the target result of the AND logical operation and the OR logical operation on the first bit line.

[0038] In this application embodiment, firstly, by sharing charge between 3m first storage cells and the first bit line, and 3n second storage cells and the second bit line, the target result of the logical operation is determined by the voltage difference between the first bit line and the second bit line. This realizes the use of memory for logical operations, thereby eliminating the need for additional computing circuitry and thus eliminating the energy consumption generated by data transfer. In this way, through the "storage as computing" mode, the power consumption during operation can be reduced and the operation speed can be improved. Secondly, since m+n≥2, where m is a positive integer and n is a non-negative integer, compared with the related technology that uses 3 storage cells for logical operations, this application works collaboratively with at least 2 times (i.e., at least 6) of storage cells in each logical operation. For example, by sharing charge with 2 times the number of first storage cells, or by sharing charge with 1 times the number of first and second storage cells. This increases the voltage difference between the first bit line and the second bit line, thereby improving the signal margin of the sensing amplifier, enabling the sensing amplifier to more reliably and quickly distinguish between "0" and "1" states, greatly improving the accuracy of the calculation and the noise immunity. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of a DRAM structure provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 1 ;

[0041] Figure 3 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 2 ;

[0042] Figure 4 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 3 ;

[0043] Figure 5 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 4 ;

[0044] Figure 6 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 5 ;

[0045] Figure 7 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 6 ;

[0046] Figure 8 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 7 ;

[0047] Figure 9 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 8 ;

[0048] Figure 10 This is a schematic diagram of the connection structure between the first bit line and the second bit line provided in an embodiment of this application;

[0049] Figure 11 A flowchart illustrating a method for performing logical operations based on memory, provided in an embodiment of this application;

[0050] Figure 12 This is a flowchart illustrating another method for performing logical operations based on memory, provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant disclosure and not for limiting the disclosure. Furthermore, it should be noted that, for ease of description, only the parts related to the relevant disclosure are shown in the accompanying drawings.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0053] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0054] It should be noted that the terms "first, second, and third" used in the embodiments of this application are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0055] In related technologies, taking reading data from a memory cell (corresponding to the first memory cell in the following text) as an example, firstly, the bit line (corresponding to the first bit line in the following text) and the reference bit line (corresponding to the second bit line in the following text) are pre-charged to the reference voltage (0.5 V). blh Next, by sharing charge between the memory cell and the bit line, a voltage difference is formed between the memory cell and the reference bit line. Finally, this voltage difference is amplified by a sense amplifier to read the data stored in the memory cell. At this time, the voltage change on the bit line (i.e., the voltage difference between the bit line and the reference bit line) is as shown in Formula 1 below:

[0056] ΔV = |0.5V blh ×C S / (C BL +C S )| Formula 1;

[0057] Among them, V blh C is the power supply voltage; S C represents the capacitance value of the storage cell. BL This is the capacitance value of the parasitic capacitance on the bit line.

[0058] However, when performing AND and OR logic operations through memory, multiple memory cells and bit lines need to share charge. This reduces the voltage change on the bit lines, thus decreasing the sensing margin of the sensing amplifier. For example, when performing an AND logic operation between logic "1" and logic "0", three memory cells and bit lines need to share charge, with one memory cell storing logic "0" to represent the AND operation. In this case, the voltage change on the bit lines is as shown in Formula 2:

[0059] ΔV = |0.5Vblh ×C S / (C BL +3C S )| Formula 2.

[0060] As can be seen from the above examples, under the same parameters, due to the increase in the denominator in Formula 2, the voltage change on the bit line during logic operation is less than the voltage change on the bit line during reading. In other words, when the memory can read the data in the storage cell, it may not be able to read the data after multiple storage cells have performed charge sharing (i.e., logic operation), thus causing the memory's logic operation function to fail.

[0061] Based on this, embodiments of this application provide a method for performing logical operations based on a memory, and a memory; below, the method for performing logical operations and the memory in the embodiments of this application will be described in detail with reference to the accompanying drawings.

[0062] Before introducing the embodiments of this application, let's define three directions that may be used to describe the three-dimensional structure in the following embodiments. The three directions may include a first, a second, and a vertical direction. The vertical direction can be a direction perpendicular to the plane where the memory is located; the first and second directions are two perpendicular directions on the plane where the memory is located, wherein the first direction can be the direction in which the bit line structure extends.

[0063] First, taking memory 100 as an example of Dynamic Random Access Memory (DRAM), the overall structure of memory 100 will be introduced. (See...) Figure 1 It shows a schematic diagram of the structure of a DRAM provided in an embodiment of this application; as shown Figure 1 As shown, the DRAM includes multiple memory arrays arranged along a first direction, and a sense amplification module located between two adjacent memory arrays; wherein, the memory array is composed of a large number of memory cells (or Cells), and can perform read data, write data, or refresh data processing on selected memory cells through word lines (WL) and bit lines (BL); each sense amplification module includes multiple sense amplifiers (SA), wherein one end of the sense amplifier is connected to the bit line in the memory array above it, and the other end of the sense amplifier is connected to the bit line in the memory array below it.

[0064] Additionally, please continue to refer to Figure 1DRAM may also include row decoding and control (XDEC) circuitry, column decoding and control (YDEC) circuitry, second-level read amplifier (SSa) circuitry, and write driver circuitry. The second-level read amplifier circuitry and write driver circuitry are collectively referred to as the SSa & Write Driver circuitry. Specifically, the row decoding and control circuitry provides word line signals to enable the target word line in the memory array, and then the column decoding and control circuitry provides column selection signals to control the operation of the corresponding sense amplifiers. In turn, the sense amplifiers exchange electrical signals with the target bit lines, and finally write, read, or refresh data to the target memory cell.

[0065] It should be noted that, Figure 1 This description exemplifies the interconnections between structures within the DRAM, rather than their physical locations. For instance, the sensing amplification module and the memory array may reside on the same chip or on different chips. Furthermore, the memory 100 may also be, for example, Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), or Double Data Rate SDRAM (DDRSDRAM), etc., without specific limitations.

[0066] The structure of the memory in various embodiments of this application will be described in detail below with reference to the accompanying drawings, taking two memory arrays contained in the memory as examples.

[0067] In some embodiments, please refer to Figure 2 The memory 100 includes a sense amplifier SA, and a first memory array 110 and a second memory array 120 connected to the sense amplifier SA; wherein, the first memory array 110 includes a first bit line BL1 and a plurality of first memory cells 111, the plurality of first memory cells 111 being coupled to the sense amplifier SA through the first bit line BL1; the second memory array 120 includes a second bit line BL2 and a plurality of second memory cells 121, the plurality of second memory cells 121 being coupled to the sense amplifier SA through the second bit line BL2.

[0068] Here, the first storage array 110 is a storage array for storing data to be processed, and the second storage array 120 is another storage array connected to the sensing amplifier SA. That is, the first storage array 110 and the second storage array 120 are only used to distinguish between storing data to be processed during logical operations and the two storage arrays participating in the operation; for example, in a logical operation, such as Figure 2When a storage cell in the upper middle storage array stores data to be processed, the storage array containing that storage cell is the first storage array 110, and the storage array at the other end of the sensing amplifier SA corresponding to the first storage array 110 is the second storage array 120; for example, in the next logical operation, the data to be processed is located at Figure 2 The storage units in the lower middle section can be used as the first storage array.

[0069] Please refer to the embodiments in this application. Figure 2 Each storage array includes multiple storage cells arranged along a first direction and a second direction; the first storage cell 111 and the second storage cell 121 refer to the storage cells used to store the data to be processed and the storage cells involved in the processing, respectively, during a single operation in the first storage array 110 and the second storage array 120. For example, in a single operation, Figure 2 The gray-filled storage cells in the diagram are used for logical operations, and are thus designated as the first storage cell 111 and the second storage cell 121. The remaining diagonally filled storage cells do not participate in the operations.

[0070] Similarly, please continue to refer to Figure 2 Each memory array includes a plurality of bit lines spaced apart along a second direction; wherein odd-numbered and even-numbered bit lines are alternately coupled to sense amplifiers SA on both sides of the memory array along a first direction. The first bit line BL1 and the second bit line BL2 refer to the bit lines connected to the first memory cell 111 and the second memory cell 121, respectively.

[0071] It should be noted that, Figure 2 The image only shows, by way of example, the bit lines connected to the sense amplifier SA on both sides, without specifically showing whether it is connected to odd-numbered or even-numbered bit lines; for example, the memory cell is 6F. 2 In the first memory cell 111, the odd-numbered column bit lines along the second direction are coupled to the same sense amplifier SA along with the even-numbered column bit lines in the adjacent (as below) memory array, and the even-numbered column bit lines are coupled to the same sense amplifier SA along with the adjacent (as above) odd-numbered column bit lines. In particular, the odd-numbered and even-numbered column bit lines are only a position-based division; in fact, the odd-numbered and even-numbered column bit lines have exactly the same physical structure.

[0072] Please refer to the embodiments in this application. Figure 2Each storage cell is coupled to the intersection of a bit line and a word line. Specifically, the first storage array 110 also includes multiple first word lines WL1 (WL1_1~WL1_i), and each first storage cell 111 is located at the intersection of a bit line BL1 and a first word line WL1, and is also coupled to the first word line WL1. The second storage array 120 also includes multiple second word lines WL2 (WL2_1~WL2_j), and each second storage cell 121 is located at the intersection of a second bit line BL2 and a second word line WL2, and is also coupled to the second word line WL2. Here, i and j are set according to actual needs, and can be equal or unequal.

[0073] In some embodiments, please refer to Figure 3 This refers to the storage array at the beginning and end (Edge) positions provided in the embodiments of this application. Figure 3 The storage array shown is Figure 2 The difference in the illustrated memory arrays is that half of the bit lines in the first and last positions can be connected to the adjacent sense amplifiers, while the other half of the bit lines and their corresponding memory cells are actually unusable. For example, Figure 3 In the second memory array 120 at the beginning and end, half of the bit lines (e.g., odd-numbered columns) can be connected to adjacent sense amplifiers, while the other half (e.g., even-numbered columns) and their corresponding memory cells are actually unusable. The same applies when the first memory array 110 at the beginning and end.

[0074] Based on this, the embodiments of this application also provide another storage array with start and end positions; please refer to Figure 4 Taking the first storage array 110 at the beginning and end as an example, the first bit line BL1 includes a first part BL1a and a second part BL1b extending along a first direction, and a first connection part BL1c electrically connecting the first part BL1a and the second part BL1b; two adjacent first storage cells 111 along the second direction are coupled to the first part BL1a and the second part BL1b respectively, and form a pair of first storage cells 112 storing the same data. Here, since the two first storage cells 111 in the first storage cell pair 112 are coupled to the same first word line WL1 and the first bit line BL1, that is, the first storage cell accesses the two first storage cells 111 in 112 simultaneously, the same first storage cell stores the same data in the two first storage cells 111 in 112.

[0075] It should be noted that the structure of the remaining bit lines in the first memory array 110 can be set with reference to the first bit line BL1, and will not be described in detail here. Figure 5 The same applies to the embodiments shown.

[0076] In some embodiments, please refer to Figure 5 Taking the storage array at the beginning and end positions as the second storage array 120 as an example, the second bit line BL2 includes a third part BL2a and a fourth part BL2b extending along the first direction, and a second connection part BL2c electrically connecting the third part BL2a and the fourth part BL2b; two adjacent second storage cells 121 along the second direction are coupled to the third part BL2a and the fourth part BL2b respectively, and form a pair of second storage cells 122 storing the same data. Here, since the two second storage cells 121 in a pair of second storage cells 122 are coupled to the same second word line WL2 and second bit line BL2, that is, the two second storage cells 122 in a pair of second storage cells 122 are accessed simultaneously, the two second storage cells 121 in the same pair of second storage cells 122 store the same data.

[0077] In this embodiment, for the memory array at the beginning and end positions, since two bit lines are essentially connected to form a single bit line, the length of each bit line can be shortened by nearly half. Therefore, the memory array at the beginning and end positions not only avoids wasting memory cells, but also reduces the area of ​​the memory array at the beginning and end positions by nearly half compared to the area of ​​the memory array at the other positions, thereby increasing the integration density of the memory 100 and reducing the overall area occupied by the memory cells.

[0078] In some embodiments, please refer to Figures 6 to 9 In any one of these embodiments, the first storage array 110 further includes a third bit line BL3 adjacent to the first bit line BL1, and a third storage cell 113 coupled to the third bit line BL3; one of the plurality of first storage cells 111 serves as a fourth storage cell 114; the lower plates of the capacitors of the third storage cell 113 and the corresponding fourth storage cell 114 are coupled to the same node; the memory 100 further includes a control circuit CSL connected between the second bit line BL2 and the third bit line BL3. The control circuit CSL is used to control the interruption or conduction between the second bit line BL2 and the third bit line BL3.

[0079] For example, compared to Figure 3 The first storage array 110 shown, Figure 6 The first storage array 110 also includes a third bit line BL3 adjacent to the first bit line BL1, and a third storage cell 113 coupled to the third bit line BL3; wherein, the first two first storage cells (i.e., the fourth storage cell 114) closer to the corresponding sensing amplifier SA are coupled to the lower plate of the capacitor of the corresponding third storage cell 113 at the same node.

[0080] It should be noted that the number and position of the fourth storage cell 114 and the corresponding third storage cell 113 (i.e., the storage cell for performing NOT operations) can be set according to actual needs; for example, the lower plates of the capacitors of the three first storage cells (i.e., the fourth storage cell 114) on the side away from the corresponding sensing amplifier SA are coupled to the same node as the lower plates of the capacitors of the corresponding third storage cell 113. In addition, the structure of each bit line in the first storage array 110 can be set with reference to the first bit line BL1.

[0081] For example, compared to Figure 2 The first storage array 110 shown, Figure 7 and Figure 8 The first storage array 110 also includes a third bit line BL3 adjacent to the first bit line BL1, and a third storage cell 113 coupled to the third bit line BL3; wherein, the first two first storage cells 111 (i.e., the fourth storage cell 114) near the corresponding sensing amplifier SA are coupled to the lower plate of the capacitor of the corresponding third storage cell 113 at the same node.

[0082] here, Figure 7 and Figure 8 The difference in the first memory array 110 shown is that the structure of the column of memory cells adjacent to the third memory cell 113 (i.e., the memory cells connected to the sensing amplifier SA below it) is different; wherein, Figure 7 The column of storage cells adjacent to the third storage cell 113 is a normal storage cell, that is, it cannot be used as the first storage cell 111 when not performing operations; Figure 8 A column of storage cells adjacent to the third storage cell 113 includes the third storage cell coupled to it, and can thus serve as the first storage cell 111 during non-operational periods. Furthermore, the accompanying drawings in this embodiment do not represent actual scale dimensions and are for illustrative purposes only.

[0083] For example, compared to Figure 5 The first storage array 110 shown, Figure 9 The first storage array 110 also includes a third bit line BL3 adjacent to the first bit line BL1, and a third storage cell 113 coupled to the third bit line BL3; wherein, the first two first storage cells 111 (i.e., the fourth storage cell 114) near the corresponding sensing amplifier SA are coupled to the lower plate of the capacitor of the corresponding third storage cell 113 at the same node.

[0084] In this embodiment of the application, the lower capacitor plate of the third storage unit 113 and the corresponding fourth storage unit 114 are coupled to the same node, which means that the lower capacitor plate of the third storage unit 113 and the lower capacitor plate of the corresponding fourth storage unit 114 are electrically connected, thereby sharing charge with each other; here, the lower capacitor plate is the plate of the capacitor that is connected to the transistor.

[0085] Additionally, please refer to Figure 10 The first bit line BL1 and the second bit line BL2 are connected to the metal wiring layer M0 above them through a conductive structure, and then connected to the sense amplifier SA; while the second bit line BL2 and the third bit line BL3 are connected through a higher metal wiring layer M0U (which can be formed by self-aligned double pattern exposure SADP); here, the control circuit CSL can be set on the semiconductor substrate where the memory array is located.

[0086] In this embodiment, since a third bit line BL3 and its corresponding structure are set in the first storage array 110, NOT operations can be performed through the first storage array 110 and the second storage array 120, thereby enabling AND, OR, and NOT operations to be completed efficiently in the same memory, thus improving the operation speed.

[0087] In the embodiments of this application, such as Figure 1 The memory arrays in the DRAM (i.e., memory 100) shown can be freely combined based on the structure of the memory arrays (i.e., the first memory array and the second memory array) in the above embodiments. For example, the memory arrays not at the beginning or end can be composed of... Figure 2 , Figure 7 and Figure 8 The structure shown comprises at least one of the following, and the storage arrays at the beginning and end positions can be composed of... Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 9 It consists of one or both of the structures shown.

[0088] In addition, the memory 100 in this application embodiment is not limited to DRAM, that is, the memory 100 may include the first memory array 110, the sense amplifier SA and the second memory array 120 in the above embodiment.

[0089] In addition, this application embodiment also provides a method for performing logical operations based on the memory 100 in the above embodiments. Figure 11 A flowchart illustrating the method for performing logical operations based on memory 100 provided in this application embodiment is shown below. Figure 11 As shown, logical operations include AND and OR operations, and the method of performing logical operations includes the following steps:

[0090] Step S11: Precharge the first bit line BL1 and the second bit line BL2 to the reference voltage.

[0091] Here, the reference voltage is typically 0.5Vblh, where Vblh is the power supply voltage; step S11 ensures that the first bit line BL1 and the second bit line BL2 are in the same state at the start of the logic operation.

[0092] Step S12: 3m first storage cells 111 share charge with the first bit line BL1, and simultaneously, 3n second storage cells 121 share charge with the second bit line BL2, so as to form a first voltage difference on the first bit line BL1 and the second bit line BL2; where m+n≥2, m is a positive integer and n is a non-negative integer.

[0093] Here, the reason for having 3m first storage units 111 is that during AND and OR operations, three data are required for the operation, and each data is stored based on m first storage units 111. Among these three data, one is fixed data, and the other two are data to be operated on. The fixed data is fixed as logic "0" during AND operations and fixed as "1" during OR operations.

[0094] Furthermore, the reason for having 3n second storage units 121 is that every m first storage units 111 has n corresponding second storage units 121. For example, when there are 3 first storage units 111 and 3 second storage units 121, each second storage unit 121 and its corresponding first storage unit 111 are inverted data; or, when there are 6 first storage units 111 and 3 second storage units 121, every two second storage units 121 and their corresponding first storage units 111 are inverted data.

[0095] Step S13: The first voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain the target result of the AND or OR operation on the first bit line BL1.

[0096] In this embodiment, in the first aspect, after sharing charge between 3m first storage units 111 and the first bit line BL1, and between 3n second storage units 121 and the second bit line BL2, the target result of the logical operation is determined by the voltage difference between the first bit line BL1 and the second bit line BL2. This enables logical operations to be performed using the memory 100, thus eliminating the need for additional computing circuitry and reducing the energy consumption generated by data transfer. In this way, the power consumption during operation can be reduced and the operation speed can be increased through the "storage as computing" mode. Secondly, since m+n≥2, where m is a positive integer and n is a non-negative integer, compared to the related technologies that use 3 storage units for logical operations, this application uses at least 2 times (i.e. at least 6) storage units to work together for each logical operation. For example, charge sharing is achieved through 2 times the first storage unit 111, or charge sharing is achieved through 1 times the first storage unit 111 and the second storage unit 121. This increases the voltage difference between the first bit line BL1 and the second bit line BL2, thereby improving the signal margin of the sensing amplifier SA. This allows the sensing amplifier SA to distinguish between "0" and "1" states more reliably and quickly, greatly improving the accuracy of the calculation and its noise immunity.

[0097] Next, combined Figures 2 to 9 The methods of logical operations are described in detail.

[0098] The first type, where m=1 and n=1, is based on... Figure 2 or Figure 3 The memory 100 shown performs logical operations; the logical operations include AND logical operations and OR logical operations.

[0099] In this embodiment of the application, before executing step S11, the logical operation method further includes: storing data that is opposite to the data in the first storage unit 111 in the second storage unit 121. The data in the second storage unit 121 can be stored in the following two ways:

[0100] In the first embodiment, data opposite to that in the corresponding first storage unit 111 is pre-stored in the second storage unit 121.

[0101] For example, please refer to Figure 2 or Figure 3 When the three first storage units 111 are respectively logic "0", logic "1", and logic "0", logic "1", logic "0", and logic "1" are written to the corresponding three second storage units 121 in sequence.

[0102] The positions of the first storage unit 111 and the corresponding second storage unit 121 can be symmetrical or asymmetrical. For example, please refer to... Figure 2The three first memory cells 111 coupled to the first word lines WL1_1, WL1_2, and WL1_i correspond sequentially to the three second memory cells 121 coupled to the second word lines WL2_1, WL2_2, and WL2_j, where i and j are equal. For another example, please refer to... Figure 3 The three first storage cells 111 coupled to the first word lines WL1_1, WL1_2, and WL1_i correspond to the three second storage cells 121 coupled to the second word lines WL2_1, WL2_2, and WL2_3, respectively. The positions of the first storage cells 111 and their corresponding second storage cells 121 in subsequent embodiments can be understood with reference to this.

[0103] In the second embodiment, the first bit line BL1 and the second bit line BL2 are pre-charged to the reference voltage; after the m first storage cells 111 storing the same data in the 3m first storage cells share the charge with the first bit line BL1, the voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by a sensing amplifier to obtain the inverted data of the same data on the second bit line; the inverted data of the same data is written into the n second storage cells 121 corresponding to the m first storage cells 111.

[0104] For example, in implementation, the first bit line BL1 and the second bit line BL2 are first pre-charged to a reference voltage. Next, one of the three first memory cells 111 is made to share charge with the first bit line BL1 to create a voltage difference between the first bit line BL1 and the second bit line BL2. The voltage difference between the first bit line BL1 and the second bit line BL2 is amplified by a sensing amplifier SA to obtain inverted data of the same data on the second bit line BL2. The inverted data is then written into the corresponding second memory cell 121. This process is repeated until all second memory cells 121 are filled with the corresponding data.

[0105] In some other embodiments, the data originally stored in the second storage array 120 may not be changed. Instead, a suitable storage unit among the multiple storage units connected to the second bit line BL2 may be selected as the second storage unit based on the data type in the storage unit. For example, when the three first storage units 111 are sequentially logic "0", logic "1", and logic "0", the multiple storage units connected to the second bit line BL2 sequentially store logic "1", logic "1", logic "0", logic "0", ..., logic "1", and the storage unit corresponding to the three data points logic "1", logic "0", and logic "1" is selected as the second storage unit 121.

[0106] Step S11: Precharge the first bit line BL1 and the second bit line BL2 to the reference voltage.

[0107] In step S12, the three first storage cells 111 share charge with the first bit line BL1, and at the same time, the three second storage cells 121 share charge with the second bit line BL2, so as to form a first voltage difference on the first bit line BL1 and the second bit line BL2.

[0108] For details, please refer to Figure 2 or Figure 3 One of the three first storage units 111 is used to store fixed data, which is used to represent OR or AND logical operations; the other two of the three first storage units 111 are used to store data to be operated on. Here, the fixed data can be stored in the first storage unit 111 coupled to the first word line WL1_i, and the data to be operated on can be stored in the first storage units 111 coupled to the first word lines WL1_1 and WL1_2, respectively.

[0109] Here, the fixed data for performing AND logic operations is logic "0". The AND logic operations are explained in detail with reference to Tables 1 and 2 below. For the voltage change on the first bit line BL1, please refer to Table 1 for understanding. Each second memory cell 121 is the inverse of the corresponding first memory cell 111. For the voltage change on the second bit line BL2, please refer to Table 2 for understanding.

[0110] Table 1:

[0111]

[0112] Table 2:

[0113]

[0114] Here, as can be seen from Tables 1 and 2 above, since the data stored in the first storage unit 111 and the second storage unit 121 are inverse data, the absolute values ​​of the voltage changes of the first bit line BL1 and the second bit line BL2 are equal and opposite in sign during each AND logic operation.

[0115] In addition, the fixed data during OR logic operations is logic "1". The OR logic operations are explained in detail in conjunction with Tables 3 and 4 below. For the voltage change on the first bit line BL1, please refer to Table 3 for understanding. Each second memory cell 121 is the inverse of the corresponding first memory cell 111. For the voltage change on the second bit line BL2, please refer to Table 4 for understanding.

[0116] Table 3:

[0117]

[0118] Table 4:

[0119]

[0120] Here, as can be seen from Tables 3 and 4 above, since the data stored in the first storage unit 111 and the second storage unit 121 are inverse data, the absolute values ​​of the voltage changes of the first bit line BL1 and the second bit line BL2 are equal and opposite in sign during each OR logic operation.

[0121] Step S13: The first voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain the target result of the AND or OR operation on the first bit line BL1 or the second bit line BL2.

[0122] In this embodiment of the application, the target result is written into any first storage unit 111 corresponding to the first bit line BL1, or into any second storage unit 121 corresponding to the second bit line BL2.

[0123] Here, compared to the prior art (i.e., the change in the second bit line BL2 is 0), in this embodiment, since the absolute values ​​of the voltage changes of the first bit line BL1 and the second bit line BL2 are equal and opposite in sign, the first voltage difference on the first bit line BL1 and the second bit line BL2 is increased by 2 times, thereby improving the signal margin of the sensing amplifier, enabling the sensing amplifier to distinguish between "0" and "1" states more reliably and quickly, and greatly improving the accuracy of calculation and noise immunity.

[0124] The second type, where m=2 and n=0, is based on... Figure 4 The memory 100 shown performs logical operations; the logical operations include AND logical operations and OR logical operations.

[0125] In this embodiment of the application, before performing step S11, data opposite to that in the first storage unit 111 may not be stored in the second storage unit 121; thus, although the voltage change on the second bit line BL2 is 0, since each data to be stored is stored based on 2 storage units, the voltage change on the first bit line BL1 is increased, thereby increasing the sensing margin of the sensing amplifier SA.

[0126] Step S11: Precharge the first bit line BL1 and the second bit line BL2 to the reference voltage.

[0127] In step S12, the six first storage cells 111 share charge with the first bit line BL1, and at the same time, the zero second storage cells 121 share charge with the second bit line BL2, so as to form a first voltage difference on the first bit line BL1 and the second bit line BL2.

[0128] In the embodiments of this application, please refer to Figure 4The leftmost gray-filled storage unit has three first storage units. One of these three units is used to store fixed data, which is used to represent AND or OR logical operations. The other two units are used to store data to be processed.

[0129] Here, fixed data can be stored in the first storage unit pair 112 coupled to the first word line WL1_i, and data to be processed can be stored in the first storage unit pair 112 coupled to the first word lines WL1_1 and WL1_2 respectively.

[0130] Here, the fixed data for performing AND logic operations is logic "0". The AND logic operations are explained in detail in Table 5 below; please refer to Table 5 for understanding the voltage change on the first line BL1.

[0131] Table 5:

[0132]

[0133] In addition, the fixed data for the OR logic operation is logic "1". The following table 6 provides a detailed explanation of the AND logic operation; please refer to Table 6 for the voltage change on the first line BL1.

[0134] Table 6:

[0135]

[0136] Here, as can be seen from Tables 5 and 6 above, since each data is shared with the first bit line BL1 through two first storage cells 111, the voltage change on the first bit line BL1 is increased; in addition, the zero second storage cells 121 share charge with the second bit line BL2, so the voltage change on the second bit line BL2 is zero.

[0137] Step S13: The first voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain the target result of the AND or OR operation on the first bit line BL1.

[0138] In this embodiment of the application, the target result is written into any first storage cell pair 112 corresponding to the first bit line BL1.

[0139] Here, compared to the prior art (i.e., data is stored through a single storage unit), in this embodiment, since each piece of data is stored through two first storage units 111, the voltage change on the first bit line BL1 is higher. Therefore, the first voltage difference between the first bit line BL1 and the second bit line BL2 is increased, thereby improving the signal margin of the sensing amplifier. This allows the sensing amplifier to distinguish between "0" and "1" states more reliably and quickly, greatly improving the accuracy of calculation and noise immunity.

[0140] The third type, m=2, n=1, is based on... Figure 4 The memory 100 shown performs logical operations; the logical operations include AND logical operations and OR logical operations.

[0141] In this embodiment of the application, before performing step S11, please refer to Figure 4 The central black-filled storage cell can store data opposite to the corresponding two first storage cells 111 in one second storage cell 121. This not only ensures that each piece of data to be stored is based on two storage cells, but also makes the voltage change on the second bit line BL2 opposite to that on the first bit line BL, thereby further increasing the voltage difference between the first bit line BL1 and the second bit line BL2, thus increasing the sensing margin of the sensing amplifier SA. The data in the second storage cell 121 can be stored in the following two ways:

[0142] In the first embodiment, data opposite to that in the corresponding first storage unit 111 is pre-stored in the second storage unit 121.

[0143] In the second embodiment, the first bit line BL1 and the second bit line BL2 are pre-charged to a reference voltage; two first storage cells 111 storing the same data in the six first storage cells are charged with the first bit line BL1 to form a voltage difference between the first bit line BL1 and the second bit line BL2; the voltage difference between the first bit line BL1 and the second bit line BL2 is amplified by a sensing amplifier SA to obtain inverted data on the second bit line BL2 that is opposite to the data stored in the two first storage cells 111; the inverted data is written into the corresponding second storage cell 121. This process is repeated until all second storage cells 121 are filled with the corresponding data.

[0144] Step S11: Precharge the first bit line BL1 and the second bit line BL2 to the reference voltage.

[0145] In step S12, the six first storage cells 111 share charge with the first bit line BL1, and at the same time, the three second storage cells 121 share charge with the second bit line BL2, so as to form a first voltage difference on the first bit line BL1 and the second bit line BL2.

[0146] In the embodiments of this application, please refer to Figure 4 The black-filled storage cell in the middle has three first storage cells. One of these cells is used to store fixed data, which is used to represent OR or OR operations. The other two cells are used to store data to be processed.

[0147] Here, the logical operations are explained in detail with reference to Tables 5 and 2; the voltage change on the first bit line BL1 is explained with reference to Table 5; each second memory cell 121 and the corresponding two first memory cells 111 (first memory cell pair 112) are inverted data, and the voltage change on the second bit line BL2 is explained with reference to Table 2.

[0148] In addition, the OR logic operation is explained in detail with reference to Tables 6 and 4; the voltage change on the first bit line BL1 is explained with reference to Table 6; each second memory cell 121 and the corresponding two first memory cells 111 (first memory cell pair 112) are inverse data, and the voltage change on the second bit line BL2 is explained with reference to Table 4.

[0149] Step S13: The first voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain the target result of the AND or OR operation on the first bit line BL1.

[0150] In this embodiment of the application, the target result is written into any first storage cell pair 112 corresponding to the first bit line BL1.

[0151] In this embodiment, on the one hand, since each data is stored through two first storage units 111, the voltage change on the first bit line BL1 is relatively high; on the other hand, since the signs of the voltage changes on the first bit line BL1 and the second bit line BL2 are opposite, the first voltage difference on the first bit line BL1 and the second bit line BL2 is increased by at least 2 times, thereby improving the signal margin of the sensing amplifier, enabling the sensing amplifier to distinguish between "0" and "1" states more reliably and quickly, and greatly improving the accuracy of calculation and noise immunity.

[0152] The fourth type, m=1, n=2, is based on... Figure 5 The memory 100 shown performs logical operations; the logical operations include AND logical operations and OR logical operations.

[0153] In this embodiment of the application, before performing step S11, data opposite to that corresponding to one first storage cell 111 can be stored in two second storage cells 121 (i.e., one pair of second storage cells 122). This increases the voltage change on the second bit line BL2 and makes it opposite to that on the first bit line BL, thereby further increasing the voltage difference between the first bit line BL1 and the second bit line BL2, thereby increasing the sensing margin of the sensing amplifier SA.

[0154] Step S11: Precharge the first bit line BL1 and the second bit line BL2 to the reference voltage.

[0155] In step S12, the three first storage cells 111 share charge with the first bit line BL1, and at the same time, the six second storage cells 121 share charge with the second bit line BL2, so as to form a first voltage difference on the first bit line BL1 and the second bit line BL2.

[0156] In this embodiment of the application, one of the three first storage units 111 is used to store fixed data, which is used to represent AND-OR-OR operations, and the other two of the three first storage units 111 are used to store data to be operated.

[0157] Here, the logical operations are explained in detail with reference to Tables 1 and 7. For the voltage change on the first bit line BL1, please refer to Table 1 for understanding. The two second memory cells 121 (second memory cell pair 122) and the corresponding first memory cell 111 are inverse data of each other. For the voltage change on the second bit line BL2, please refer to Table 7 for understanding.

[0158] Table 7:

[0159]

[0160] In addition, the OR logic operation is explained in detail with reference to Tables 3 and 8; the voltage change on the first bit line BL1 is explained with reference to Table 3; the two second memory cells 121 (second memory cell pair 122) and the corresponding first memory cell 111 are inverted data, and the voltage change on the second bit line BL2 is explained with reference to Table 8.

[0161] Table 8:

[0162]

[0163] Here, as can be seen from Tables 1 and 7, as well as Tables 3 and 8 above, since the data stored in the first storage unit 111 and the second storage unit 121 are inverse data and every two second storage units 121 store the same data, therefore, during each OR logic operation, the signs of the voltage changes of the first bit line BL1 and the second bit line BL2 are opposite, and the voltage change of the second bit line BL2 is greater than that of the first bit line BL1.

[0164] Step S13: The first voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain the target result of the AND or OR operation on the first bit line BL1.

[0165] In this embodiment of the application, the target result is written into any of the first storage units 111 corresponding to the first bit line BL1.

[0166] In this embodiment, since the voltage changes of the first bit line BL1 and the second bit line BL2 have opposite signs and the voltage change of the second bit line BL2 is greater than that of the first bit line BL1, the first voltage difference between the first bit line BL1 and the second bit line BL2 is increased by at least 2 times. This can improve the signal margin of the sensing amplifier, enabling the sensing amplifier to distinguish between "0" and "1" states more reliably and quickly, and greatly improving the accuracy of calculation and noise immunity.

[0167] The fifth type, based on Figure 6 The memory 100 shown performs logical operations; logical operations also include NOT operations, please refer to [reference needed]. Figure 12 When performing non-logical operations, the method includes:

[0168] Step S21: Precharge the first bit line BL1 and the second bit line BL2 to the reference voltage.

[0169] Here, the reference voltage is typically 0.5Vblh, where Vblh is the power supply voltage; step S11 ensures that the first bit line BL1 and the second bit line BL2 are in the same state at the start of the logic operation.

[0170] Step S22, the fourth storage cell 114 (i.e. the first storage cell 111) shares charge with the first bit line BL1 to form a second voltage difference on the first bit line BL1 and the second bit line BL2.

[0171] During implementation, the first word line WL1_1 is turned on, and all the second word lines WL2 are turned off, allowing the fourth memory cell 114 (i.e., the first memory cell 111) to share charge with the first bit line BL1, thereby creating a second voltage difference on the first bit line BL1 and the second bit line BL2. Additionally, since the lower electrodes of the third memory cell 113 and the fourth memory cell 114 are connected, the third memory cell 113 also shares charge with the first bit line BL1.

[0172] Step S23: The second voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain the target result of the non-logic operation on the second bit line BL2.

[0173] In implementation, the second voltage difference on the first bit line BL1 and the second bit line BL2 is amplified by the sensing amplifier SA to obtain inverted data of the same data on the second bit line BL2, and this inverted data is used as the target result and written into any second memory cell 121 corresponding to the second bit line BL2. Figure 6 The middle part is the second memory cell 121 coupled to the second word line WL2_1.

[0174] Step S24: The target result on the second bit line BL2 is transferred to the third bit line BL3 and written to the third storage unit 113.

[0175] In this embodiment of the application, the target result on the second bit line BL2 is transmitted to the third bit line BL3 through the control circuit and written into the third storage unit 113.

[0176] During implementation, the first word line WL1_1 is turned off, and the control circuit CSL and the first word line WL1_2 are turned on. The inverted data is stored in the third storage unit 113 through the second bit line BL2 and the third bit line BL3. Since the third storage unit 113 and the fourth storage unit 114 share the lower electrode, the data is written into the fourth storage unit 114, thus realizing the non-logic operation.

[0177] It should be noted that in the examples of this application... Figures 7 to 9 Methods for performing non-logical operations and Figure 6 Similarly; in addition, Figure 9 Each target data is stored through two second storage units 121 (i.e., one second storage unit pair 122).

[0178] It should also be noted that multiple logical operations can be performed within the same memory 100, for example, in Figure 9 The structure shown allows for NOT, AND, and OR operations. The operation methods can be understood by referring to the above embodiments, and will not be repeated here.

[0179] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

[0180] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0181] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0182] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0183] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0184] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0185] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the above-described scope.

Claims

1. A method for performing logical operations based on memory, characterized in that, The memory includes a sensing amplifier, a first memory array, and a second memory array; wherein the first memory array includes a first bit line and a plurality of first memory cells, the plurality of first memory cells being coupled to the sensing amplifier via the first bit line; the second memory array includes a second bit line and a plurality of second memory cells, the plurality of second memory cells being coupled to the sensing amplifier via the second bit line; the logical operation includes an AND logical operation and an OR logical operation, and when performing the AND logical operation or the OR logical operation, the method includes: Step S11: Precharge the first bit line and the second bit line to the reference voltage; Step S12: 3m first memory cells share charge with the first bit line, and simultaneously, 3n second memory cells share charge with the second bit line to form a first voltage difference on the first bit line and the second bit line; where m+n≥2, m is a positive integer and n is a non-negative integer; Step S13: The first voltage difference between the first bit line and the second bit line is amplified by the sensing amplifier to obtain the target result of the AND logic operation or the OR logic operation on the first bit line.

2. The method according to claim 1, characterized in that, The data stored in the second storage unit and the corresponding data stored in the first storage unit are inverse data; Before performing step S11, the method further includes: The second storage unit stores data that is the opposite of the corresponding first storage unit; or... The first bit line and the second bit line are precharged to the reference voltage; after the m first storage cells storing the same data in the 3m first storage cells share the charge with the first bit line, the voltage difference between the first bit line and the second bit line is amplified by the sensing amplifier to obtain the inverted data of the same data on the second bit line; the inverted data of the same data is written into the n second storage cells corresponding to the m first storage cells.

3. The method according to claim 2, characterized in that, m=1, n=1, one of the three first storage units is used to store fixed data, the fixed data is used to characterize the AND logic operation or the OR logic operation, and the other two of the three first storage units are used to store data to be operated; In step S13, the target result is written into any of the first storage cells corresponding to the first bit line.

4. The method according to claim 2, characterized in that, m=2, n=1, the first bit line includes a first part and a second part extending along a first direction, and a first connection part electrically connecting the first part and the second part; the six first storage cells are arranged in a 2×3 array, and two adjacent first storage cells along the second direction are respectively coupled to the first part and the second part and form a pair of first storage cells storing the same data; one of the three pairs of first storage cells is used to store fixed data, the fixed data is used to characterize the AND logic operation or the OR logic operation, and the other two of the three pairs of first storage cells are used to store data to be operated; In step S13, the target result is written into any of the first memory cell pairs corresponding to the first bit line; The first direction and the second direction are two intersecting directions on the plane where the memory is located.

5. The method according to claim 1, characterized in that, m=2, n=0, the first bit line includes a first part and a second part extending along a first direction, and a first connection part electrically connecting the first part and the second part; the six first storage cells are arranged in a 2×3 array, and two adjacent first storage cells along the second direction are respectively coupled to the first part and the second part and form a pair of first storage cells storing the same data; one of the three pairs of first storage cells is used to store fixed data, the fixed data is used to characterize the AND logic operation or the OR logic operation, and the other two of the three pairs of first storage cells are used to store data to be operated; In step S13, the target result is written into any of the first memory cell pairs corresponding to the first bit line.

6. The method according to claim 4 or 5, characterized in that, The first storage array is the first and last storage arrays in a plurality of sequentially arranged storage arrays, and the second storage array is the storage array adjacent to the first storage array in the plurality of storage arrays.

7. The method according to claim 2, characterized in that, m=1, n=2, one of the three first storage units is used to store fixed data, the fixed data is used to characterize the AND logic operation or the OR logic operation, and the other two of the three first storage units are used to store data to be operated; The second bit line includes a third part and a fourth part extending along the first direction, and a second connection part electrically connecting the third part and the fourth part; the six second storage cells are arranged in a 2×3 array, and two adjacent second storage cells along the second direction are respectively coupled to the third part and the fourth part, and form a pair of second storage cells storing the same data; In step S13, the target result is written into any of the first storage cells corresponding to the first bit line.

8. The method according to claim 7, characterized in that, The second storage array is the first and last storage array in a plurality of storage arrays arranged in sequence, and the first storage array is the storage array adjacent to the second storage array in the plurality of storage arrays.

9. The method according to any one of claims 1 to 3, characterized in that, The logical operation also includes a NOT logical operation; the first storage array also includes a third bit line adjacent to the first bit line, and a third storage cell coupled to the third bit line; one of the plurality of first storage cells serves as a fourth storage cell; The lower electrode of the capacitor of the third storage unit and the corresponding fourth storage unit are coupled to the same node; When performing the non-logical operation, the method includes: Step S21: Precharge the first bit line and the second bit line to the reference voltage; Step S22: The fourth memory cell shares charge with the first bit line to form a second voltage difference between the first bit line and the second bit line; Step S23: The second voltage difference between the first bit line and the second bit line is amplified by the sensing amplifier to obtain the target result of the non-logic operation on the second bit line; Step S24: The target result on the second bit line is transmitted to the third bit line and written to the third storage unit.

10. The method according to claim 9, characterized in that, The memory further includes a control circuit connected between the second bit line and the third bit line; step S24 includes: The target result on the second bit line is transmitted to the third bit line through the control circuit and written into the third storage unit.

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