Power supply system

Abstract

The invention provides a power supply system, which can realize a detection function of power supply abnormity of a plurality of power supply devices and a safe stopping function of the power supply device with abnormity while suppressing increase of circuit scale. The power supply system includes: a plurality of power supply devices each generating an output voltage when a corresponding control signal among a plurality of control signals is in an active state; a control device that outputs a plurality of control signals to each of the plurality of power supply devices; and an abnormality transmission circuit that is provided corresponding to each of the plurality of power supply devices, includes a plurality of abnormal voltage detection circuits that detect whether or not the output voltages generated by each of the plurality of power supply devices are abnormal, and transmits a plurality of detection results of the plurality of abnormal voltage detection circuits to the control device by means of a serial signal. The control device outputs, on the basis of the plurality of detection results, a control signal of an inactive state to a power supply device for which an abnormality is detected among the plurality of power supply devices, and then outputs a control signal of an active state after stopping the operation.

Description

TECHNICAL FIELD

[0001] The present application relates to a power supply system. BACKGROUND

[0002] In a power supply device that generates a plurality of power supply voltages or a plurality of power supply devices that respectively generate a plurality of power supply voltages, a method is known in which a voltage abnormality detection circuit that detects an abnormality of a power supply voltage and a current abnormality detection circuit that detects an abnormality of a power supply current are provided for each of the plurality of power supply voltages.

[0003] For example, in a case where a control device that controls a plurality of power supply devices stops a power supply device in which an abnormality has occurred, by detecting an abnormality of a power supply voltage or a power supply current for each power supply device, the control device needs to receive a notification of an abnormality of a power supply voltage and a notification of an abnormality of a power supply current from the plurality of power supply devices. In this case, a plurality of signal lines for abnormality notification need to be wired between the plurality of power supply devices and the control device. As a result, the circuit scale of the power supply system having the plurality of power supply devices and the control device increases, and the system cost increases.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2001-312318 SUMMARY

[0005] The disclosed technology aims to achieve a power supply abnormality detection function of a plurality of power supply devices and a safe stop function of a power supply device in which an abnormality has occurred, while suppressing an increase in circuit scale.

[0006] To solve the above-described technical problem, a power supply system of one embodiment of the present application includes a plurality of power supply devices that respectively generate an output voltage when a corresponding control signal among a plurality of control signals is in an active state, a control device that outputs the plurality of control signals to the plurality of power supply devices, and an abnormality transmission circuit that is provided corresponding to the plurality of power supply devices, includes a plurality of abnormality voltage detection circuits that respectively detect whether the output voltage generated by the plurality of power supply devices is abnormal, transmits a plurality of detection results of the plurality of abnormality voltage detection circuits to the control device through a serial signal, and outputs the control signal in the active state after stopping the operation of the power supply device in which an abnormality is detected by outputting the control signal in an inactive state to the power supply device in which an abnormality is detected on the basis of the plurality of detection results.

[0007] A power supply abnormality detection function of a plurality of power supply devices and a safe stop function of a power supply device in which an abnormality has occurred can be achieved while suppressing an increase in circuit scale. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is an example of a block diagram that represents a first embodiment of the power supply system of the present application.

[0009] Figure 2 is an example of a block diagram showing an outline of the power supply device of Figure 1

[0010] Figure 3 is a circuit diagram showing a specific example of the power supply device of Figure 2

[0011] Figure 4 Figure 3

[0012] Figure 5 is a timing chart showing an example of serial data transmitted from the parallel-serial conversion circuit of Figure 1

[0013] Figure 6 is a block diagram showing an example of a circuit for detecting a voltage abnormality in another power supply system.

[0014] Figure 7 is an example of a block diagram showing a second embodiment of the power supply system of the present application. DETAILED DESCRIPTION

[0015] Hereinafter, the embodiments will be described with reference to the drawings. Hereinafter, the same symbol is sometimes used for a signal line, a signal terminal, a signal node, and a signal value through which a signal is transmitted, a voltage line, a voltage terminal, and a voltage node to which a voltage is supplied, and a signal name. In each drawing, the same symbol is attached to the same constituent part, and sometimes repeated description is omitted.

[0016] (Example of the power supply system of the first embodiment)

[0017] Figure 1 is an example of a block diagram showing a first embodiment of the power supply system of the present application. Figure 1 The power supply system SYS shown in FIG. 1 generates, for example, a power supply voltage used in a servo motor encoder, a servo amplifier, a PLC (Programmable Logic Controller), a device for data collection, and the like included in a servo system. Further, the power supply system SYS can generate a plurality of power supply voltages used in a plurality of devices included in a system other than the servo system.

[0018] Figure 1 ​​​​​The illustrated power supply system SYS has a plurality of power supply devices 100(1), 100(2), 100(3), 100(4), a power supply monitoring circuit 200, and a microcomputer 300. Hereinafter, in the case where the power supply devices 100(1) to 100(4) are not distinguished, the power supply devices 100 are also referred to. The power supply system SYS has a function of detecting abnormality such as overvoltage, low voltage, overcurrent, and the like of each power supply device 100, and safely stopping and restarting only the power supply device in which abnormality has occurred. In Figure 1 The power supply system SYS has four power supply devices 100, but the number of power supply devices 100 is not limited to four as long as it is two or more. The microcomputer 300 is an example of a control device that controls a plurality of power supply devices 100 respectively.

[0019] The power supply devices 100(1) to 100(4) operate during a period in which control signals EN1, EN2, EN3, EN4 received from the microcomputer 300 are active levels (for example, high levels), and generate output voltages VOUT1, VOUT2, VOUT3, VOUT4 using an input voltage VIN respectively. The power supply devices 100(1) to 100(4) stop operating during a period in which the control signals EN1, EN2, EN3, EN4 received from the microcomputer 300 are inactive levels (for example, low levels), and stop the generation of the output voltages VOUT1, VOUT2, VOUT3, VOUT4.

[0020] The output voltages VOUT1 to VOUT4 are supplied to the power supply monitoring circuit 200 and loads connected to the power supply devices 100(1) to 100(4) respectively. For example, the loads are servo motor encoders, servo amplifiers, PLCs, devices for data collection, and the like. In addition, the values of the output voltages VOUT1 to VOUT4 can be different from each other, can be the same as each other, or can be different from each other with the remaining being the same.

[0021] In addition, the power supply devices 100(1) to 100(4) transmit overcurrent detection signals OCFLG1, OCFLG2, OCFLG3, OCFLG4 to the microcomputer 300 respectively in the case where overcurrent of a current flowing through the input voltage line VIN in each power supply device 100 is detected (OC is Over Current). Hereinafter, in the case where the output voltages VOUT1, VOUT2, VOUT3, VOUT4 are not distinguished, the output voltages VOUT are also referred to. In the case where the control signals EN1, EN2, EN3, EN4 are not distinguished, the control signals EN are also referred to. In the case where the overcurrent detection signals OCFLG1, OCFLG2, OCFLG3, OCFLG4 are not distinguished, the overcurrent detection signals OCFLG are also referred to.

[0022] By sending an overcurrent detection signal OCFLG to the microcomputer 300 for each power supply device 100, the microcomputer 300 can use the control signal EN to stop and restart only the power supply device 100 that has experienced an overcurrent. Thus, the abnormal power supply device 100 can be restored from its abnormal state without stopping the entire power system SYS.

[0023] The power monitoring circuit 200 includes multiple abnormal voltage detection circuits 210(1), 210(2), 210(3), and 210(4) corresponding to each power supply device 100, and a parallel-to-serial conversion circuit 220. Hereinafter, without distinguishing between the abnormal voltage detection circuits 210(1), 210(2), 210(3), and 210(4), it will also be referred to as the abnormal voltage detection circuit 210. The power monitoring circuit 200 is an example of an abnormality transmission circuit that serially outputs the detection results of whether the output voltages of the multiple abnormal voltage detection circuits 210 are abnormal to the microcomputer 300.

[0024] The parallel-to-serial conversion circuit 220 includes a data latch 211 and a shift register 212, and is connected to the microcomputer 300 using an SPI (Serial Peripheral Interface) interface (I / F). Figure 1 The SPI interface shown includes a chip select signal, a clock signal CLK, and a data signal SDO, which transmit data from the parallel-to-serial conversion circuit 220 to the microcomputer 300.

[0025] The microcomputer 300 operates as the master of the SPI interface, outputting a chip select signal CS and a clock signal CLK to the parallel-to-serial converter 220. The parallel-to-serial converter 220 operates as the slave of the SPI interface, outputting a data signal SDO. Alternatively, I... 2 Other serial interfaces, such as the C (Inter-Integrated Circuit) interface, are used to transmit data from the parallel-to-serial conversion circuit 220 to the microcomputer 300.

[0026] The abnormal voltage detection circuits 210(1)-210(4) are identical except for the different values ​​of their built-in resistors. Therefore, the circuit structure and operation of the abnormal voltage detection circuit 210(1) will be explained below. In addition, when multiple abnormal voltage detection circuits 210 receive the same output voltage VOUT, the resistance values ​​of the three built-in resistors can also be the same for each resistor.

[0027] The abnormal voltage detection circuit 210(1) has resistors R11, R12, and R13 connected in series between the output voltage line VOUT1 and the ground line, and comparators CMPO and CMPU. The - and + inputs of comparator CMPO are connected to the connection nodes of resistors R11 and R12 and the reference voltage line VREF1, respectively. The + and - inputs of comparator CMPU are connected to the connection nodes of resistors R12 and R13 and the reference voltage line VREF1, respectively.

[0028] When the voltage at the connection point of resistors R11 and R12 is above the reference voltage VREF1, comparator CMPO detects that the output voltage VOUT1 is an overvoltage (first anomaly) higher than the first judgment voltage, and outputs a low-level overvoltage detection signal OV (Over Voltage) 1. When the voltage at the connection point of resistors R11 and R12 is lower than the reference voltage VREF1, comparator CMPO detects that the output voltage VOUT1 is not an overvoltage, and outputs a high-level overvoltage detection signal OV 1.

[0029] When the voltage at the connection point of resistors R12 and R13 is lower than the reference voltage VREF1, the comparator CMPU detects that the output voltage VOUT1 is a low voltage (second abnormality) lower than the second judgment voltage, and outputs a low-level low voltage detection signal UV (Under Voltage) 1. Here, the second judgment voltage is lower than the first judgment voltage. When the voltage at the connection point of resistors R12 and R13 is higher than the reference voltage VREF1, the comparator CMPU detects that the output voltage VOUT1 is not a low voltage, and outputs a high-level low voltage detection signal UV1.

[0030] Based on the above, when the output voltage VOUT1 is an overvoltage, the overvoltage detection signal OV1 and the undervoltage detection signal UV1 become low and high levels, respectively. When the output voltage VOUT1 is neither an overvoltage nor an undervoltage but within the normal range, both the overvoltage detection signal OV1 and the undervoltage detection signal UV1 become high levels. When the output voltage VOUT1 is an undervoltage, the overvoltage detection signal OV1 and the undervoltage detection signal UV1 become high and low levels, respectively.

[0031] Similar to the abnormal voltage detection circuit 210(1), the abnormal voltage detection circuit 210(2) outputs a low-level overvoltage detection signal OV2 when an overvoltage of the output voltage VOUT2 is detected, and outputs a low-level low voltage detection signal UV2 when a low voltage of the output voltage VOUT2 is detected. The abnormal voltage detection circuit 210(3) outputs a low-level overvoltage detection signal OV3 when an overvoltage of the output voltage VOUT3 is detected, and outputs a low-level low voltage detection signal UV3 when a low voltage of the output voltage VOUT3 is detected. The abnormal voltage detection circuit 210(4) outputs a low-level overvoltage detection signal OV4 when an overvoltage of the output voltage VOUT4 is detected, and outputs a low-level low voltage detection signal UV4 when a low voltage of the output voltage VOUT4 is detected.

[0032] Based on the above, each abnormal voltage detection circuit 210 can independently detect the overvoltage and undervoltage of the corresponding power supply device 100's output voltage VOUT, and can notify the microcomputer 300 of the detection results.

[0033] The data latch 211 of the parallel-to-serial conversion circuit 220 latches the logic values ​​of overvoltage detection signals OV1-OV4 and undervoltage detection signals UV1-UV4 received in parallel from multiple abnormal voltage detection circuits 210, and stores the latched logic values ​​in parallel in the shift register 212. Hereinafter, the data representing the logic values ​​of the overvoltage detection signals OV1-OV4 latched in the data latch 211 will also be referred to as data OV1 and OV4. Similarly, the data representing the logic values ​​of the undervoltage detection signals UV1-UV4 latched in the data latch 211 will also be referred to as data UV1-UV4. Data OV1-OV4 are examples of first data indicating whether there is an overvoltage, and data UV1-UV4 are examples of second data indicating whether there is an undervoltage.

[0034] During the period when the chip select signal CS is active, shift register 212 synchronously outputs the held data OV1-OV4 and UV1-UV4 sequentially to the microcomputer 300 in sync with the clock signal CLK. Thus, even when the power supply system SYS has a large number of power supply units 100, it is possible to send multiple data OV indicating whether each output voltage VOUT is overvoltage and multiple data UV indicating whether each output voltage VOUT is undervoltage to the microcomputer 300 using a minimal number of signal lines. Shift register 212 is an example of a data converter that converts the data OV1-OV4 and UV1-UV4 latched by data latch 211 into serial data.

[0035] Because the increase in the number of signal lines can be suppressed, for example, the size of the system board housing the power supply device 100, the power monitoring circuit 200, and the microcomputer 300 can be suppressed. Therefore, the increase in the circuit size of the power supply system SYS can be suppressed, and the increase in system cost can be suppressed.

[0036] The microcomputer 300 controls the operation of multiple power supply devices 100 and controls the forwarding of data OV1-OV4 and UV1-UV4 from the power monitoring circuit 200. Additionally, the microcomputer 300 receives overcurrent detection signals OCFLG from each power supply device 100. The microcomputer 300 includes an abnormal voltage discrimination circuit 310 and an overcurrent discrimination circuit 320.

[0037] The abnormal voltage detection circuit 310 determines whether the output voltages VOUT1-VOUT4 are overvoltages or undervoltages based on the logic values ​​of the data OV1-OV4 and UV1-UV4 received sequentially from the parallel-to-serial conversion circuit 220 via the data line SDO. That is, the abnormal voltage detection circuit 310 detects the occurrence of overvoltages or undervoltages for each power supply device 100.

[0038] The overcurrent discrimination circuit 320 determines whether each power supply device 100 has generated an overcurrent based on the logic values ​​of the overcurrent detection signals OCFLG1-OCFLG4 received from each power supply device 100. That is, the overcurrent discrimination circuit 320 detects the generation of overcurrent for each power supply device 100.

[0039] When the abnormal voltage discrimination circuit 310 detects an abnormal voltage (overvoltage or undervoltage), or when the overcurrent discrimination circuit 320 detects an abnormal current (overcurrent), the microcomputer 300 changes the control signal EN corresponding to the abnormal power supply device 100 to a low level, causing the operation of the abnormal power supply device 100 to stop. Afterwards, the microcomputer 300 changes the control signal EN corresponding to the abnormal power supply device 100 to a high level, causing the operation of the abnormal power supply device 100 to restart. A high level for the control signal EN is an example of an active state, and a low level for the control signal EN is an example of an inactive state.

[0040] The microcomputer 300 can restart the power supply unit 100 that malfunctioned individually after it has been stopped, thus recovering from the abnormal state by safely stopping only the malfunctioning power supply unit 100 without causing the entire power system SYS to stop. Furthermore, by providing a separate abnormal voltage detection circuit 310 corresponding to each power supply unit 100, redundancy of power supplies that cause two power supply units 100 to operate exclusively can be addressed, for example. In this case, the exclusive operation of the power supply unit 100 can be easily achieved through the control signal EN output by the microcomputer 300.

[0041] (Overview of the power supply unit)

[0042] Figure 2 It means Figure 1 An example of a block diagram of a power supply device 100. Figure 1 express Figure 1 Any one of the four power supply devices 100. For example, power supply device 100 is an LDO (Low Drop Out). Alternatively, power supply device 100 can be a DC (Direct Current) / DC converter or an AC (Alternating Current) / DC converter that converts AC voltage to DC voltage. Power supply device 100 includes a startup circuit 110, a voltage generation circuit 120, an overcurrent detection circuit 130, a latch shielding circuit 140, a latch circuit 150, a buffer BUF1, and an AND circuit.

[0043] When the control signal EN is high, the startup circuit 110 generates a reference voltage VREF and outputs it to the voltage generation circuit 120. When the control signal EN is low, the startup circuit 110 stops generating the reference voltage VREF and sets the reference voltage line VREF to, for example, 0V. The control signal EN is output to the latch circuit 150 as the control signal VRISE via the buffer BUF1.

[0044] The voltage generation circuit 120 generates the output voltage VOUT from the input voltage VIN using the reference voltage VREF during the period when it receives a positive reference voltage VREF and a low-level (active) enable signal / VEN. The voltage generation circuit 120 stops generating the output voltage VOUT during the period when it receives a 0V reference voltage VREF or a high-level (inactive) enable signal / VEN.

[0045] The overcurrent detection circuit 130 monitors the current flowing from the input voltage line VIN connected to the voltage generation circuit 120 through the external resistor RLIM to the ground line as voltage, and detects whether the current flowing from the input voltage line VIN to the output voltage line VOUT is an overcurrent.

[0046] When an overcurrent is detected, the overcurrent detection circuit 130 outputs a high-level overcurrent detection signal OC to the AND circuit, and when no overcurrent is detected, it outputs a low-level overcurrent detection signal OC to the AND circuit. Furthermore, the overcurrent detected by the overcurrent detection circuit 130 also includes the inrush current generated when the power supply device 100 starts up.

[0047] The latching shield circuit 140 outputs a low-level latching shield signal LMSK during the period when the overcurrent detection signal OC is high. The latching shield circuit 140 charges the capacitor CD by an overcurrent flowing through the input voltage line VIN, and outputs a high-level latching shield signal LMSK during the period when the voltage VCD of the capacitor CD is above a predetermined voltage.

[0048] During the period when the latch shield signal LMSK is low, the AND circuit stops outputting the high-level overcurrent detection signal OC, indicating an overcurrent, to the latch circuit 150. In this case, the AND circuit fixes the overcurrent detection signal OC1 to a low level. During the period when the latch shield signal LMSK is high, the AND circuit outputs the high-level overcurrent detection signal OC, indicating an overcurrent, as the overcurrent detection signal OC1 to the latch circuit 150. Thus, only the high-level overcurrent detection signal OC, indicating the occurrence of an overcurrent, output by the overcurrent detection circuit 130 when it detects an overcurrent or inrush current, can be output as the overcurrent detection signal OC1 to the latch circuit 150.

[0049] During the period when the control signal VRISE, which is synchronized with the control signal EN, is high, the latch circuit 150 latches the high level of the overcurrent detection signal OC1 generated due to overcurrent, and outputs a high-level enable signal / VEN and a low-level overcurrent detection signal OCFLG. Before receiving the high-level overcurrent detection signal OC1 from the AND circuit during the period when the control signal VRISE is high, the latch circuit 150 outputs a low-level enable signal / VEN and a high-level overcurrent detection signal OCFLG.

[0050] While the control signal VRISE is low, the latch circuit 150 continuously outputs a latched high-level enable signal / VEN and a low-level overcurrent detection signal OCFLG. Then, when the control signal VRISE goes high again, the latch circuit 150 releases the latch, sets the enable signal / VEN low, and sets the overcurrent detection signal OCFLG high.

[0051] Therefore, the generation of output voltage VOUT can be stopped from the time overcurrent is detected until the power supply unit 100 restarts. As a result, the generation of abnormal output voltage VOUT by voltage generation circuit 120 can be suppressed from the time overcurrent is detected until the microcomputer 300 invalidates control signal EN, and malfunctions of power supply unit 100 and power system SYS can be suppressed. In addition, the overcurrent detection signal OCFLG can also be output from the circuit that receives enable signal / VEN (not shown).

[0052] The overcurrent detection signal OCFLG is sent to Figure 1 The microcomputer 300 receives a low-level overcurrent detection signal OCFLG and detects an overcurrent in the power supply device 100, the source of the overcurrent detection signal OCFLG. Then, after setting the high-level control signal EN, which is output to the power supply device 100, the source of the overcurrent detection signal OCFLG, to a low level, the microcomputer 300 returns the control signal EN to a high level, thereby restarting the power supply device 100 that generated the overcurrent.

[0053] (Specific examples of power supply devices)

[0054] Figure 3 It means Figure 2 A circuit diagram of a specific example of a power supply device 100. In Figure 3 In the diagram, the circles marked within the rectangle representing the power supply device 100 indicate terminals. The terminal receiving the input voltage VIN is an example of the first terminal, and the terminal outputting the output voltage VOUT is an example of the second terminal. The power supply device 100, in addition to... Figure 2 In addition to the circuit shown, it also includes a buffer BUF2 and a transistor Tr4. Furthermore, a pull-up resistor RPUP is connected between the overcurrent detection signal line OCFLG of the power supply unit 100 and the power supply line VCC. The output voltage line VOUT of the power supply unit 100 has a load capacitance Cout.

[0055] The startup circuit 110 includes a bias circuit 201 and a reference voltage generation circuit 202. The bias circuit 201 is connected to the input voltage line VIN and starts the reference voltage generation circuit 202 synchronously with the rise of the control signal EN received via the buffer BUF1, causing the reference voltage generation circuit 202 to generate a reference voltage VREF. During the period when the control signal EN is low, the bias circuit 201 stops the generation of the reference voltage VREF by the reference voltage generation circuit 202, setting the reference voltage line VREF to a low level (0V or negative voltage). Additionally, during the period when the control signal EN is high, the bias circuit 201 connects the input voltage line VIN to the capacitor CD, charging the capacitor CD.

[0056] The voltage generation circuit 120 includes a comparator CMP1, a transistor Tr1, and resistors R4 and R5 connected in series. The negative input of comparator CMP1 is connected to the reference voltage line VREF, the positive input is connected to the junction of resistors R4 and R5, and the output is connected to the base of transistor Tr1. Transistor Tr1 is a PNP transistor; its emitter is connected to the input voltage line VIN, its collector is connected to the output voltage line VOUT, and its base is connected to the output of comparator CMP1. Transistor Tr1 and resistors R4 and R5 are connected in series between the input voltage line VIN and ground.

[0057] The positive input of comparator CMP1 is supplied with the voltage after the output voltage VOUT is divided by resistors R4 and R5. The reference voltage VREF supplied to the negative input of comparator CMP1 is set to the voltage represented between resistors R4 and R5 when the output voltage VOUT is the target voltage.

[0058] During the period when comparator CMP1 receives a high-level (inactive) enable signal / VEN, it outputs a high-level output voltage VOUT to the base of transistor Tr1, causing transistor Tr1 to turn off. During the period when comparator CMP1 receives a low-level (active) enable signal / VEN, it controls the base voltage of transistor Tr1 based on the difference between the output voltage VOUT and the target voltage, causing transistor Tr1 to generate the output voltage VOUT.

[0059] Furthermore, when the enable signal VEN is low, the voltage generation circuit 120 reduces the on-resistance of transistor Tr1 by lowering the base voltage of transistor Tr1 when the voltage at the connection node of resistors R4 and R5 is lower than the reference voltage VREF. That is, when the output voltage VOUT is lower than the target voltage, the voltage generation circuit 120 supplies a control voltage to the base of transistor Tr1, which reduces the on-resistance of transistor Tr1 as the output voltage VOUT decreases compared to the target voltage, thereby controlling the output voltage VOUT to approach the target voltage.

[0060] The voltage generation circuit 120 turns off transistor Tr1 by increasing its base voltage when the enable signal VEN is high or when the voltage at the connection node of resistors R4 and R5 is above the reference voltage VREF. In other words, the voltage generation circuit 120 turns off transistor Tr1 when an overcurrent causes the enable signal VEN to go high, or when the output voltage VOUT is above the target voltage.

[0061] The overcurrent detection circuit 130 includes transistor Tr2 and comparator CMP2. Transistor Tr2 is a PNP transistor, with its emitter connected to the input voltage line VIN, its collector connected to the + input of comparator CMP2 and one end of resistor RLIM, and its base connected to the output of comparator CMP1. The other end of resistor RLIM is connected to ground. Transistor Tr2, together with transistor Tr1, operates as a current mirror circuit.

[0062] The positive input of comparator CMP2 is connected to the emitter of transistor Tr2, the negative input is connected to the threshold voltage line Vth2, and the output is connected to the overcurrent detection signal line OC. When the voltage generated at one end of resistor RLIM due to the current flowing through transistor Tr2 is lower than the threshold voltage Vth2, comparator CMP2 outputs a low-level overcurrent detection signal OC indicating that no overcurrent has occurred.

[0063] When the voltage generated at one end of resistor RLIM due to the current flowing through transistor Tr2 is higher than the threshold voltage Vth2, comparator CMP2 outputs a high-level overcurrent detection signal OC indicating the occurrence of an overcurrent. For example, the threshold voltage Vth2 is set to a value slightly lower than the voltage generated at one end of resistor RLIM when overcurrent flows through transistors Tr1 and Tr2.

[0064] By using an external resistor RLIM, the current flowing through transistors Tr1 and Tr2 under overcurrent detection can be suppressed to below the rated current of transistors Tr1 and Tr2, thereby preventing damage to transistors Tr1 and Tr2.

[0065] Furthermore, when the power supply 100 starts up, an inrush current flows due to the charging of capacitor CD, and the load capacitor Cout is also charged, so the inrush current also flows through the output voltage line VOUT. Therefore, the overcurrent detection circuit 130 can detect both overcurrent and inrush current. That is, the overcurrent detection signal OC changes to a high level when an overcurrent or an inrush current is generated.

[0066] The latch shielding circuit 140 includes a transistor Tr3 and a comparator CMP3. The positive input of comparator CMP3 is connected between the bias circuit 201 and the capacitor CD, the negative input is connected to the threshold voltage line Vth1, and the output is connected to the latch shielding signal line LMSK. When the voltage VCD of capacitor CD is lower than the threshold voltage Vth1, comparator CMP3 outputs a low-level latch shielding signal LMSK. When the voltage VCD of capacitor CD is higher than the threshold voltage Vth1, comparator CMP3 outputs a high-level latch shielding signal LMSK.

[0067] Transistor Tr3 is an NPN transistor. Its collector is connected between the bias circuit 201 and the capacitor CD, its emitter is connected to ground, and its base is connected to the overcurrent detection signal line OC. Transistor Tr3 conducts when the overcurrent detection signal OC is high, connecting the junction of the bias circuit 201 and the capacitor CD to ground. Furthermore, during the conduction of transistor Tr3, the latch shield signal LMSK is set to low.

[0068] like Figure 2 As explained, the AND circuit only outputs the high-level overcurrent detection signal OC1, which corresponds to the high-level overcurrent detection signal OC indicating the generation of overcurrent, from the high-level overcurrent detection signal OC output by the overcurrent detection circuit 130 when it detects an overcurrent or inrush current, to the latch circuit 150. That is, the AND circuit suppresses the output of the high-level overcurrent detection signal OC1, which corresponds to the high-level overcurrent detection signal OC that changes to a high level due to the generation of inrush current, to the latch circuit 150.

[0069] like Figure 2 As explained, the latch circuit 150 can perform latching operation during the high level of the control signal VRISE, latching the high level of the overcurrent detection signal OC1 received when an overcurrent occurs, and outputting a high-level enable signal / VEN. Furthermore, the overcurrent detection signal OCFLG, which changes to a low level when an overcurrent occurs, is generated by the buffer BUF2 and the transistor Tr4.

[0070] The latching circuit 150 maintains the latched high level until the control signal EN (i.e., VRISE) goes high again. Thus, the enable signal / VEN can be maintained high (invalid level) until the microcomputer 300, which receives a low-level overcurrent detection signal OCFLG, restarts the power supply device 100 that generated the overcurrent, thereby stopping the voltage generation circuit 120 from generating the output voltage VOUT.

[0071] Buffer BUF2 is connected between the output of latch circuit 150 and the base of transistor Tr4, outputting a signal with the same logic value as the enable signal / VEN from latch circuit 150 to the base of transistor Tr4. Transistor Tr4 is an NPN transistor whose collector is connected to the overcurrent detection signal line OCFLG, its emitter is connected to ground, and its base is connected to the output of buffer BUF2.

[0072] Transistor Tr4 turns on when the enable signal / VEN is high due to an overcurrent (excluding inrush current), setting the overcurrent detection signal OCFLG low. Transistor Tr4 turns off when no overcurrent occurs and the enable signal / VEN is low. When transistor Tr4 is off, its collector becomes floating, and the overcurrent detection signal OCFLG is set high through the pull-up resistor RPUP.

[0073] pass Figure 3 The circuit shown allows the power supply unit 100 to stop generating the output voltage VOUT from the time an overcurrent is detected until it restarts. Furthermore, by stopping the comparator CMP1's comparison operation with a high-level enable signal / VEN, the base voltages of transistors Tr1 and Tr2 are set to high, thereby turning transistors Tr1 and Tr2 into a cutoff state.

[0074] As a result, upon detecting an overcurrent, the microcomputer 300 invalidates the control signal EN, thus suppressing the generation of an abnormal output voltage VOUT by the voltage generation circuit 120 before the control signal EN becomes high again, thereby preventing malfunctions of the power supply unit 100 and the power system SYS. Furthermore, by cutting off transistors Tr1 and Tr2 when an overcurrent occurs, the continuous flow of overcurrent through transistors Tr1 and Tr2 can be prevented, thus preventing damage to transistors Tr1 and Tr2 due to overcurrent.

[0075] (Example of power supply device operation)

[0076] Figure 4 It means Figure 3 Timing diagram of the operation of power supply device 100. Figure 4 express Figure 1 The operation of any one of the four power supply devices 100. First, in the initial state before the input voltage VIN used to operate the power supply device 100 is supplied to the power supply device 100, the control signals EN and VRISE are set to low level, the reference voltage VREF and the output voltage VOUT are set to 0V, the output current IOUT is set to 0A, the voltage VCD of the capacitor CD is set to 0V, the overcurrent detection signals OC and OC1 are set to low level, the latch shield signal LMSK is set to low level, the enable signal / VEN is set to low level, and the overcurrent detection signal OCFLG is set to high level.

[0077] After supplying input voltage VIN to power supply unit 100, microcomputer 300 starts power supply unit 100 by setting control signal EN to a high level. With control signal EN at a high level, control signal VRISE also changes to a high level. Figure 4 (a)

[0078] By controlling the high level of the signal VRISE, the startup circuit 110 generates a reference voltage VREF (not shown), thereby starting the voltage generation circuit 120 and causing the output voltage VOUT to rise to a predetermined voltage (Figure 4(b)). When the power supply 100 starts up, an inrush current flows through the capacitor CD and the load capacitance Cout, charging them. This increases the output current IOUT and raises the voltage VCD of the capacitor CD. Figure 4 (c) and (d)).

[0079] The overcurrent detection circuit 130 detects the inrush current as an overcurrent, and sets the overcurrent detection signal OC to a high level during the inrush current flow. Figure 4 (e)). The latch shielding circuit 140 maintains the latch shielding signal LMSK at a low level by using a high-level overcurrent detection signal OC. Figure 4 (f)

[0080] The AND circuit maintains a low-level overcurrent detection signal OC1 output to the latch circuit 150 via a low-level latch shield signal LMSK, thus suppressing the transmission of a high-level overcurrent detection signal OC to the latch circuit 150. Figure 4 (g) Therefore, during the period when the latch shield signal LMSK is low, regardless of the logic level of the overcurrent detection signal OC, the latch circuit 150 will maintain the enable signal / VEN at a low level. Figure 4 Since transistor Tr4 remains off, the overcurrent detection signal OCFLG is maintained at a high level indicating that no overcurrent has been detected when the inrush current occurs. Figure 4 (i)

[0081] If capacitor CD and load capacitor Cout are charged and the inrush current stops flowing, the output current IOUT decreases, and the overcurrent detection circuit 130 cannot detect the overcurrent, so the overcurrent detection signal OC changes to a low level. Figure 4 (j)). Then, the power supply device 100 reaches a stable state that generates the output voltage VOUT. In the stable state, when the overcurrent detection circuit 130 detects an overcurrent in the output current IOUT, it causes the overcurrent detection signal OC to change to a high level (j). Figure 4 (k), (l)).

[0082] During the period when the latch shielding signal LMSK is low, the high level of the AND shielding overcurrent detection signal OC is transmitted to the latching circuit 150. Figure 4 (m)). Due to overcurrent, when the voltage VCD rises and becomes above the threshold voltage Vth1, the latch shield signal LMSK changes to a high level. Figure 4(n)). The latching circuit 150 latches the high level of the overcurrent detection signal OC1 to enter the latched state, and outputs a high level enable signal / VEN. Figure 4 Therefore, the AND circuit transmits the high level of the overcurrent detection signal OC as the high level of the overcurrent detection signal OC1 to the latch circuit 150. Figure 1 (p)

[0083] With the enable signal / VEN high, the comparator CMP1 of the voltage generation circuit 120 stops comparing voltages and outputs a high level. Consequently, the voltage generation circuit 120 stops generating the output voltage VOUT, and the output voltage VOUT gradually decreases. Figure 4 (q)). Therefore, the microcomputer 300 receives from Figure 4 The power monitoring circuit 200 receives low-level data UV and can also detect the occurrence of overcurrent as a low-voltage abnormality of the output voltage VOUT.

[0084] Transistor Tr4 is turned on by receiving a high-level enable signal / VEN via buffer BUF2, setting the overcurrent detection signal OCFLG to a low level indicating the occurrence of overcurrent. Figure 4 The low level of the overcurrent detection signal OCFLG is supplied to the overcurrent discrimination circuit 320 of the microcomputer 300.

[0085] The overcurrent detection circuit 320 detects that the power supply device 100 has generated an overcurrent based on the low level of the overcurrent detection signal OCFLG. Then, the microcomputer 300 sets the control signal EN output to the power supply device 100, which is the output source of the low-level overcurrent detection signal OCFLG, to a low level, thereby stopping the operation of the power supply device 100 that generated the overcurrent. Figure 4 (s)

[0086] After a predetermined time has elapsed since the microcomputer 300 set the control signal EN to a low level, it sets the control signal EN to a high level, thereby restarting the power supply device 100 that has generated an overcurrent. Figure 4 The power supply device 100, having received a high level control signal EN, sets the control signal VRISE to a high level. Through the high level of the control signal VRISE, the latch circuit 150 is initialized, setting the enable signal / VEN to a low level. Figure 4 The transistor Tr4 responds to a high-level enable signal / VEN by setting the overcurrent detection signal OCFLG to a high level. Figure 4 (v)

[0087] The voltage generation circuit 120 begins generating the output voltage VOUT, and the output voltage VOUT rises.Figure 5 (w)). Furthermore, due to the rise in output voltage VOUT, inrush current flows, and power supply unit 100 and Figure 1 The first half of it moves in the same way.

[0088] (Timing diagram for serial data transmission)

[0089] Figure 5 It means from Figure 5 A timing diagram of an example of a parallel-to-serial conversion circuit 220 sending serial data to a microcomputer 300. Figure 5 This illustrates an example where the parallel-to-serial conversion circuit 220 transmits data synchronously with the falling edge of the chip select signal CS and the falling edge of the clock signal CLK during the active low-level chip select signal CS, and the microcomputer 300 receives data synchronously with the rising edge of the clock signal CLK.

[0090] When the microcomputer 300 sends serial data to the parallel-to-serial conversion circuit 220, it outputs the clock signal CLK to the parallel-to-serial conversion circuit 220 after changing the chip select signal CS to a low level during the low level of the clock signal CLK.

[0091] The parallel-to-serial converter 220 outputs the initial serial data to the data line SDO in sync with the falling edge of the chip select signal CS. Then, while the chip select signal CS is low, the parallel-to-serial converter 220 sequentially outputs serial data to the data line SDO in sync with the falling edge of the clock signal CLK. Figure 6 In the example shown, data OV1, UV1, OV2, UV2, OV3, UV3, OV4, and UV4 are sent to the microcomputer 300 in sequence, but the output order of the data is not limited to this. Figure 1 The example shown.

[0092] By pre-determining the transmission order of data OV1-OV4 and UV1-UV4 between the power monitoring circuit 200 and the microcomputer 300, the microcomputer 300 can identify which power supply device 100 has experienced overvoltage or undervoltage based on the received serial signals. Figure 6 In this system, the microcomputer 300 can receive 8-bit data OV1-OV4 and UV1-UV4 using three signal lines CS, CLK, and SDO. Furthermore, when the power system SYS is equipped with eight power supply units 100, it transmits 16-bit data OV1-OV8 and UV1-UV8 using the same three signal lines CS, CLK, and SDO.

[0093] (Examples of other power systems)

[0094] Figure 6This is a block diagram illustrating an example of a circuit for detecting voltage anomalies in other power supply systems. (Regarding...) Figure 7 The same elements are labeled with the same reference numerals, and detailed descriptions are omitted. For example, each power supply unit 102 is an LDO. Additionally, Figure 1 The illustrated power supply system corresponds to a comparative example of the present invention.

[0095] In the case where the abnormal voltage detection circuit 410 is composed of a single abnormal voltage detection IC 400, each power supply device 100 requires an abnormal voltage detection IC 400, increasing the number of ICs used. Furthermore, in order to output data OV and UV indicating whether the voltage is abnormal from each abnormal voltage detection IC 400, eight signal lines are required to transmit the data OV and UV to the microcomputer 300 when four power supply devices 100 are mounted. Therefore, due to the increase in the number of ICs and the increase in the number of signal lines, there is a problem of an increased size of the substrate mounted in the power supply system.

[0096] When multiple abnormal voltage detection circuits 510 are constructed using a dedicated abnormal voltage detection IC 500, each abnormal voltage detection circuit 510 needs to output data OV and UV indicating whether the voltage is abnormal. The transmission of OV and UV data requires eight signal lines. Therefore, there are problems with the increased pin count of the abnormal voltage detection IC 500 and the increased size of the substrate housing the abnormal voltage detection IC 400. Therefore, in Figure 7 The power supply system is difficult to miniaturize in both the single-IC-based and dedicated IC-based architectures shown.

[0097] For example, methods for protecting power supply devices from overcurrent include protection based on zigzag characteristics, drooping characteristics, or thermal protection circuits. In a zigzag characteristic, when an overcurrent occurs in the output current, the transistor is turned off by utilizing the characteristic of a decrease in both output voltage and output current. In a drooping characteristic, when an overcurrent occurs in the output current, the transistor is turned off by utilizing the characteristic of a decrease in output voltage while maintaining the output current. Thermal protection circuits detect the heat generated by the overcurrent and turn off the transistor.

[0098] In protection methods based on zigzag and drooping characteristics, the repeated switching of transistors based on protection function and transistors based on protection function deactivation can sometimes prevent the power supply system from shutting down properly. Furthermore, since protection methods based on zigzag and drooping characteristics are open-circuit controls, transistors may be damaged if the output current exceeds their rated current. Therefore, when using zigzag or drooping characteristics to prevent overcurrent in the protection function, a thermal protection circuit must be incorporated into the power supply unit.

[0099] In the first embodiment, even when there are a large number of power supply devices 100 mounted on the power supply system SYS, it is possible to send multiple data OV indicating whether each output voltage VOUT is overvoltage and multiple data UV indicating whether each output voltage VOUT is undervoltage to the microcomputer 300 using a minimum number of signal lines.

[0100] Because the increase in the number of signal lines can be suppressed, for example, the size of the system board housing the power supply device 100, the power monitoring circuit 200, and the microcomputer 300 can be suppressed. Therefore, the increase in the circuit size of the power supply system SYS can be suppressed, and the increase in system cost can be suppressed.

[0101] By sending an overcurrent detection signal OCFLG to the microcomputer 300 for each power supply device 100, the microcomputer 300 can use the control signal EN to individually stop only the power supply device 100 that generated the overcurrent and then restart it. Thus, the entire power system SYS can be stopped, and only the power supply device 100 that malfunctioned can be safely stopped and recovered from the abnormal state. As a result, it is possible to achieve the detection function of power supply abnormalities for multiple power supply devices 100 and the safe stopping function of the malfunctioning power supply devices 100 while suppressing the increase in circuit size.

[0102] Furthermore, by providing a separate abnormal voltage detection circuit 310 corresponding to each power supply device 100, redundancy of power supplies that cause the two power supply devices 100 to operate exclusively can be addressed, for example. In this case, the exclusive operation of the power supply device 100 can be easily achieved by the control signal EN output by the microcomputer 300.

[0103] The power supply unit 100 includes a latch circuit 150 that disables the enable signal / VEN to a high level when the microcomputer 300 activates the control signal EN to a high level. When an overcurrent is detected, the enable signal / VEN remains disabled until the control signal EN is activated again. This prevents the generation of the output voltage VOUT from the time an overcurrent is detected until the power supply unit 100 restarts. Furthermore, by controlling the comparator CMP1 with the enable signal / VEN, the base voltage of transistor Tr1 is set to a high level, thereby turning transistor Tr1 into a cutoff state.

[0104] As a result, the generation of abnormal output voltage VOUT by voltage generation circuit 120 can be suppressed from the period after overcurrent is detected until the microcomputer 300 invalidates control signal EN, and malfunctions of power supply device 100 and power system SYS can be suppressed. In addition, the continuous flow of overcurrent through transistors Tr1 and Tr2 can be suppressed, and damage to transistors Tr1 and Tr2 due to overcurrent can be suppressed.

[0105] By providing an abnormal voltage detection circuit 210 corresponding to each power supply device 100 in the power monitoring circuit 200, overvoltage and undervoltage of the output voltage VOUT of the corresponding power supply device 100 can be detected individually and notified to the microcomputer 300. Furthermore, the parallel-to-serial conversion circuit 220 can be used to send the data OV indicating whether an overvoltage abnormality has occurred in each power supply device 100 and the data UV indicating whether an undervoltage abnormality has occurred as serial data to the microcomputer 300.

[0106] (Example of a power supply system according to the second embodiment)

[0107] Figure 1 This is an example of a block diagram illustrating a second embodiment of the power supply system of the present invention. Regarding... Figure 1 The same elements are labeled with the same reference numerals, and detailed descriptions are omitted. ​ The power system SYS shown here, in addition to having a power monitoring circuit 200A to replace the power monitoring circuit 200, has the same... ​ The power supply system SYS shown has the same structure. The power monitoring circuit 200A is replaced by a parallel-to-serial conversion circuit 220A. ​ The parallel-to-serial conversion circuit 220A has a data latch 211A and a shift register 212A.

[0108] In this embodiment, the overcurrent detection signal OCFLG output from each power supply device 100 is sent as a serial signal to the microcomputer 300 via the parallel-to-serial conversion circuit 220A. Therefore, the data latch 211A, in addition to latches for data OV1-OV4 and UV1-UV4, also has latches for the logic values ​​of the overcurrent detection signals OCFLG1-OCFLG4. The shift register 212A has a register size capable of simultaneously holding the logic values ​​of data OV1-OV4 and UV1-UV4 and the logic values ​​of the overcurrent detection signals OCFLG1-4.

[0109] In the second embodiment, for example, the overcurrent detection signals OCFLG1-OCFLG4 can be transmitted to the microcomputer 300 without wiring formed on the system substrate on which the power supply device 100, the power monitoring circuit 200A, and the microcomputer 300 are mounted. Therefore, compared to the first embodiment, the increase in the size of the system substrate can be further suppressed. As a result, the increase in the circuit size of the power supply system SYS can be further suppressed, and the increase in system cost can be further suppressed.

[0110] For example, the microcomputer 300 can receive overcurrent detection signals OCFLG1-OCFLG4 via data lines SDO without using general-purpose input / output ports. Therefore, a microcomputer with fewer general-purpose input / output ports than the microcomputer 300 can be used. In this case, the increase in system cost can be further suppressed.

[0111] As described above, in the second embodiment, similarly to the first embodiment, when the number of power supply devices 100 mounted on the power supply system SYS is large, it is also possible to use a minimum number of signal lines to send multiple data OV indicating whether each output voltage VOUT is overvoltage and multiple data UV indicating whether each output voltage VOUT is undervoltage to the microcomputer 300.

[0112] Furthermore, in the second embodiment, the parallel-to-serial conversion circuit 220 can be used to transmit the logic values ​​of data OV1-OV4, UV1-UV4, and the logic values ​​of overcurrent detection signals OCFLG1-4 as serial data to the microcomputer 300. Since the overcurrent detection signals OCFLG1-OCFLG4 can be transmitted to the microcomputer 300 without wiring formed on the system substrate, the increase in the size of the system substrate can be further suppressed. Therefore, the increase in the circuit size of the power supply system SYS can be further suppressed, and the increase in system cost can be further suppressed.

[0113] The present invention has been described above based on various embodiments, but the present invention is not limited to the elements shown in the above embodiments. Changes can be made in these aspects without departing from the spirit of the invention, and can be appropriately determined according to its application.

[0114] Symbol Explanation

[0115] 100, 102 power supply units;

[0116] 110 Start-up Circuit;

[0117] 120V generation circuit;

[0118] 130 overcurrent detection circuit;

[0119] 140 latch shielding circuit;

[0120] 150 latch circuit;

[0121] 200A power supply monitoring circuit;

[0122] 201 bias circuit;

[0123] 210, 410, 510 abnormal voltage detection circuits;

[0124] 211, 211A data latches;

[0125] 212 and 212A shift registers;

[0126] 220A parallel-to-serial conversion circuit;

[0127] 300 microcomputers;

[0128] 310 Abnormal Voltage Detection Circuit;

[0129] 320 overcurrent detection circuit;

[0130] 400, 500 abnormal voltage detection IC;

[0131] AND with circuits;

[0132] BUF1 and BUF2 buffers;

[0133] CD capacitor;

[0134] CLK clock signal;

[0135] CMP1, CMP2, CMP3 comparators;

[0136] CMPO and CMPU comparators;

[0137] Cout is the load capacitor;

[0138] CS chip select signal;

[0139] EN (EN1 = EN4) control signals;

[0140] IOUT output current;

[0141] Ith1 and Ith2 threshold currents;

[0142] LMSK latches the shielded signal;

[0143] OC and OC1 overcurrent detection signals;

[0144] OCFLG (OCFLG1-OCFLG4) overcurrent detection signal; OV (OV1-OV4) overvoltage detection signal;

[0145] Resistors R4, R5, R11, R12, and R13;

[0146] RLIM resistor;

[0147] RPUP pull-up resistor;

[0148] SDO data cable;

[0149] SYS power system;

[0150] Tr1-Tr4 transistors;

[0151] UV (UV1 = UV4) low voltage detection signal;

[0152] VCC power cord;

[0153] VCD voltage;

[0154] / VEN enable signal;

[0155] VIN input voltage;

[0156] VOUT (VOUT1-VOUT4) is the output voltage.

[0157] VREF and VREF1 reference voltages;

[0158] VRISE control signal;

[0159] Vth1 and Vth2 threshold voltages.

Claims

1. A power supply system, characterized in that, have: Multiple power supply devices generate output voltages when the corresponding control signal among multiple control signals is in an active state; A control device that outputs the plurality of control signals to the plurality of power supply devices respectively; as well as An anomaly transmission circuit, corresponding to each of the plurality of power supply devices, includes multiple anomaly voltage detection circuits that detect whether the output voltage generated by the plurality of power supply devices is abnormal, and sends the multiple detection results of the multiple anomaly voltage detection circuits to the control device via a serial signal. After the control device stops the operation by outputting an invalid control signal to the power supply device among the plurality of power supply devices that was detected to be abnormal based on the plurality of detection results, it outputs an valid control signal.

2. The power supply system according to claim 1, characterized in that, The plurality of power supply devices each have: A voltage generation circuit generates the output voltage based on the input voltage received by the first terminal, and outputs the generated output voltage to the second terminal; as well as An overcurrent detection circuit detects whether the current flowing from the first terminal to the second terminal is an overcurrent and sends the detection result to the control device. After the control device stops the operation by outputting an invalid control signal to the power supply device among the plurality of power supply devices that was detected to be abnormal based on the detection result of the overcurrent detection circuit, it outputs an valid control signal.

3. The power supply system according to claim 2, characterized in that, The abnormality transmission circuit sends multiple detection results from the abnormal voltage detection circuit and the detection results from the overcurrent detection circuits of each of the multiple power supply devices to the control device via serial signals.

4. The power supply system according to claim 2, characterized in that, Each of the plurality of power supply devices has a latching circuit, which outputs an enable signal for the active state when the corresponding control signal changes to an active state. When the overcurrent detection circuit detects an overcurrent, it sets the enable signal to an inactive state until the corresponding control signal changes to an active state again. The voltage generation circuit generates the output voltage when the enable signal is active, and stops generating the output voltage when the enable signal is inactive.

5. The power supply system according to claim 4, characterized in that, The voltage generation circuit has the following features: A transistor, disposed between the first terminal and the second terminal; and A comparator that controls the base voltage of the transistor based on the difference between the input voltage and the output voltage. The comparator performs the following operations: When the enable signal is active, and the output voltage is above the target voltage, a control voltage is supplied to the base of the transistor to turn it off. When the enable signal is active, a control voltage is supplied to the base of the transistor such that the output voltage is lower than the target voltage, thereby reducing the on-resistance of the transistor; and When the enable signal is in an invalid state, a control voltage is supplied to the base of the transistor to turn the transistor off.

6. The power supply system according to any one of claims 1 to 5, characterized in that, The plurality of abnormal voltage detection circuits detect a first abnormality when the output voltage generated by the corresponding power supply device is higher than the first determination voltage, and detect a second abnormality when the output voltage generated by the corresponding power supply device is lower than the second determination voltage which is lower than the first determination voltage.

7. The power supply system according to any one of claims 1 to 5, characterized in that, The anomaly transmission circuit has a parallel-to-serial conversion circuit. The parallel-to-serial conversion circuit has the following characteristics: A data latch that latches multiple data representing the detection results in parallel; and A data converter that converts multiple data representing the detection results latched by the data latch into serial data.

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