Power management unit, power management chip and electronic equipment
By combining a multiphase parallel voltage conversion circuit and a logic control module, the problem of undershoot in the output voltage of the voltage conversion circuit under heavy load is solved, enabling stable operation under greater load and reducing ripple, while also reducing the heat generation of the power transistor.
Patent Information
- Application Number
- CN202411096926.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional voltage conversion circuits are prone to undershooting of output voltage under heavy loads, and existing optimization methods are costly, cause severe heat generation of power transistors, and are greatly affected by factors such as process corners.
A multi-phase parallel voltage conversion circuit and logic control module are adopted. By calculating the conduction time and the number of phases, the voltage conversion circuits of each phase are periodically controlled to work in turn. The conduction interval is used as the phase difference to distribute the load pressure.
Without affecting the performance of the single-phase voltage conversion circuit, it can operate under greater loads and significantly reduce output voltage ripple and power transistor heating.
Smart Images
Figure CN121508319A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power management technology, and in particular to a power management unit, a power management chip, and an electronic device. Background Technology
[0002] To adapt to various application scenarios, voltage conversion circuits need to operate under diverse load currents. Traditional voltage conversion circuits are prone to output voltage undershoot when operating under large loads, meaning they cannot properly carry the load. To address this issue, existing technologies typically use sufficiently large inductors to provide energy to the load or optimize the circuit's delay to reduce the power transistor's on-time and meet the demands of large loads. However, using large inductors is more expensive and causes significant heat generation in the power transistor; furthermore, optimizing the delay is heavily influenced by process technology and other factors, making it difficult to achieve. Summary of the Invention
[0003] To address the aforementioned problems, this application provides a power management unit, a power management chip, and an electronic device.
[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a power management unit, which includes a multi-phase parallel voltage conversion circuit and a logic control module. Each phase voltage conversion circuit is used to provide a power signal to the same load. The logic control module is connected to each phase voltage conversion circuit and is used to calculate the conduction interval based on the conduction time of a certain phase voltage conversion circuit and the number of phases of the voltage conversion circuit, and to periodically control each phase voltage conversion circuit to work in turn using the conduction interval as a phase difference.
[0005] The logic control module includes a sampling unit and a delay control unit. The sampling unit is used to collect and obtain the conduction time of a certain phase voltage conversion circuit. The delay control unit is connected to the sampling unit and each phase voltage conversion circuit. It is configured to calculate the conduction interval based on the conduction time and the number of phases of the voltage conversion circuit, and use the conduction interval as the phase difference to periodically control each phase voltage conversion circuit to work in turn.
[0006] The delay control unit includes a grouping unit and a control unit. The grouping unit is configured to divide the multi-phase parallel voltage conversion circuit into a preset number of voltage conversion circuits based on the number of phases of the voltage conversion circuit. Each voltage conversion circuit includes at least one phase voltage conversion circuit. The control unit is connected to the grouping unit and each group of voltage conversion circuits and is configured to calculate the conduction interval based on the conduction time and the preset number, and use the conduction interval as the phase difference to periodically control each phase voltage conversion circuit to work in turn.
[0007] Each phase of the voltage conversion circuit includes a drive module. The control unit is connected to the drive module of each phase voltage conversion circuit in each group of voltage conversion circuits. The control unit is configured to enable the enable signal of the upper tube of the next group of voltage conversion circuits to conduct after the conduction interval of the upper tube of the current group of voltage conversion circuits.
[0008] Each phase of the voltage conversion circuit includes a pulse width modulation signal generation module, which generates a pulse width modulation signal. The driving modules are all connected to the pulse width modulation signal generation module. Each phase driving module is used to control the power transistor in the corresponding voltage conversion circuit to turn on and off based on the pulse width modulation signal when the enable signal of the corresponding voltage conversion circuit is valid.
[0009] The control unit includes a conduction time generation circuit, which is configured to obtain the conduction interval duration based on the reference voltage corresponding to the conduction time and the number of voltage conversion circuits.
[0010] The conduction time generation circuit includes a voltage generation circuit and a time generation circuit. The voltage generation circuit is configured to perform voltage division based on the reference voltage and the number of voltage conversion circuits to obtain the reference sub-voltage corresponding to the conduction interval duration. The time generation circuit is connected to the power supply generation circuit and is used to generate the conduction interval duration based on the reference sub-voltage.
[0011] The time generation circuit includes: an operational amplifier, a first transistor, a second transistor, a third transistor, a resistor, a capacitor, a first comparator, and a second comparator. The positive input terminal of the operational amplifier receives the input voltage. The negative input terminal of the operational amplifier is connected to the second path terminal of the first transistor. The control terminal of the first transistor is connected to the output terminal of the operational amplifier. The first path terminal of the first transistor is coupled to the second path terminal of the second transistor, the control terminal of the second transistor, and the control terminal of the third transistor. The second path terminal of the first transistor is also connected to the first terminal of the resistor, and the second terminal of the resistor is grounded. The first path terminal of the second transistor is connected to the first path terminal of the third transistor, and the second path terminal of the third transistor is connected to the first terminal of the capacitor. The second terminal of the capacitor is grounded. The positive input terminals of the first and second comparators are coupled to the intermediate node connecting the second path terminal of the third transistor and the first terminal of the capacitor. The negative input terminal of the first comparator receives a reference sub-voltage to generate a corresponding conduction interval duration. The negative input terminal of the second comparator receives a reference voltage to generate a corresponding conduction time.
[0012] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a power management chip, which includes the power management unit of any one of the above-mentioned features.
[0013] To address the aforementioned technical problem, another technical solution adopted in this application is to provide an electronic device that includes the aforementioned power management chip.
[0014] Unlike existing technologies, the power management unit of this application includes a multi-phase parallel voltage conversion circuit and a logic control module. Each phase voltage conversion circuit provides a power signal to the same load. The logic control module is connected to each phase voltage conversion circuit and calculates the conduction interval based on the conduction time of a certain phase voltage conversion circuit and the number of phases of the voltage conversion circuit. It then uses the conduction interval as a phase difference to periodically control each phase voltage conversion circuit to operate in turn. Through this method, the power management unit of this application uses multi-phase parallel voltage conversion circuits to supply power to the same load. This allows the load pressure to be distributed among the multiple phase voltage conversion circuits. Furthermore, by periodically controlling each phase voltage conversion circuit to operate in turn using the conduction interval as a phase difference, the power management unit can operate under a larger load without affecting the performance of the single-phase voltage conversion circuit, and the output voltage ripple is significantly reduced. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of the power management unit of this application;
[0017] Figure 2 This is a schematic diagram of the structure of an embodiment of the logic control module of this application;
[0018] Figure 3 This is a control waveform diagram of an embodiment of the power management unit of this application;
[0019] Figure 4 This is a schematic diagram of the circuit structure of an embodiment of the conduction time generation circuit of this application;
[0020] Figure 5 This is a schematic diagram of the structure of an embodiment of the power management chip of this application;
[0021] Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation
[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0024] To adapt to various application scenarios, voltage conversion circuits need to operate under diverse load currents. Traditional voltage conversion circuits are prone to output voltage undershoot when operating under large loads, meaning they cannot properly carry the load. To address this issue, existing technologies typically use sufficiently large inductors to provide energy to the load or optimize the circuit's delay to reduce the power transistor's on-time and meet the demands of large loads. However, using large inductors is more expensive and causes significant heat generation in the power transistor; furthermore, optimizing the delay is heavily influenced by process technology and other factors, making it difficult to achieve.
[0025] To address the aforementioned problems, this application first proposes a power management unit, please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the power management unit of this application, as shown below. Figure 1 As shown, the power management unit 100 in this embodiment includes a multi-phase parallel voltage conversion circuit 10 and a logic control module 20.
[0026] like Figure 1 As shown, each phase voltage conversion circuit 10 is used to provide a power signal to the same load; the logic control module 20 is connected to each phase voltage conversion circuit 10 and is used to calculate the conduction interval duration based on the conduction time of a certain phase voltage conversion circuit 10 and the number of phases of the voltage conversion circuit 10, and to periodically control each phase voltage conversion circuit 10 to work in turn using the conduction interval duration as the phase difference.
[0027] In this embodiment, the logic control module 20 can be controlled by digital signals. By acquiring the conduction time of a certain phase voltage conversion circuit 10, and calculating the conduction interval of each phase voltage conversion circuit 10 by using the conduction time TON and the number of phases of the voltage conversion circuit 10, the module can control each phase voltage conversion circuit 10 to work in turn periodically with the conduction interval as the phase difference.
[0028] In this embodiment, the voltage conversion circuit 10 has at least two phases. Furthermore, the specific structure of the logic control module 20 is described below and will not be detailed further here.
[0029] Unlike existing technologies, the power management unit 100 of this application includes a multi-phase parallel voltage conversion circuit 10 and a logic control module 20. Each phase voltage conversion circuit 10 provides a power signal to the same load. The logic control module 20 is connected to each phase voltage conversion circuit 10 and is used to calculate the conduction interval based on the conduction time of a certain phase voltage conversion circuit 10 and the number of phases of the voltage conversion circuit 10. It then uses the conduction interval as a phase difference to periodically control each phase voltage conversion circuit 10 to work in turn. In this way, the power management unit 100 of this application uses the multi-phase parallel voltage conversion circuit 10 to supply power to the same load. The load pressure can be distributed by using the multi-phase voltage conversion circuit 10. Furthermore, by periodically controlling each phase voltage conversion circuit 10 to work in turn using the conduction interval as a phase difference, the power management unit 100 can operate under a larger load without affecting the performance of the single-phase voltage conversion circuit 10, and the output voltage ripple can be significantly reduced.
[0030] Optionally, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of an embodiment of the logic control module of this application, as shown below. Figure 2 As shown, the logic control module 20 in this embodiment includes a sampling unit 21 and a delay control unit 22.
[0031] like Figure 2 As shown, the sampling unit 21 is used to collect and obtain the conduction time of a certain phase voltage conversion circuit 10; the delay control unit 22 is connected to the sampling unit 21 and each phase voltage conversion circuit 10, and is configured to calculate the conduction interval duration based on the conduction time and the number of phases of the voltage conversion circuit 10, and use the conduction interval duration as the phase difference to periodically control each phase voltage conversion circuit 10 to work in turn.
[0032] In this embodiment, the sampling unit 21 of the logic control module 20 can be used to sample any one phase of the multiphase voltage conversion circuit 10 to obtain the conduction time of the corresponding voltage conversion circuit 10. After the sampling unit 21 obtains the conduction time, it can send the conduction time to the delay control unit 22. At this time, the delay control unit 22 can calculate the conduction interval duration based on the conduction time and the number of phases of the voltage conversion circuit 10, and use the conduction interval duration as the phase difference to periodically control each phase voltage conversion circuit 10 to work in turn.
[0033] Optionally, such as Figure 2 As shown, the delay control unit 22 in this embodiment includes a grouping unit 221 and a control unit 222. As... Figure 2As shown, the grouping unit 221 is configured to divide the multi-phase parallel voltage conversion circuit 10 into a preset number of groups of voltage conversion circuits 10 based on the number of phases of the voltage conversion circuit 10. Each group of voltage conversion circuits 10 includes at least one phase of voltage conversion circuit 10. The control unit 222 is connected to the grouping unit 221 and each group of voltage conversion circuits 10. It is configured to calculate the conduction interval duration based on the conduction time and the preset number, and use the conduction interval duration as the phase difference to periodically control each phase voltage conversion circuit 10 to work in turn.
[0034] In this embodiment, the delay control unit 22 can use the grouping unit 221 to divide the multi-phase parallel voltage conversion circuit 10 into a preset number of groups of voltage conversion circuits 10 based on the number of phases of the voltage conversion circuit 10.
[0035] In this embodiment, it is preferred to set one phase voltage conversion circuit 10 as a group of voltage conversion circuits 10. In other embodiments, it can also be set to two or more groups. That is, the number of groups of voltage conversion circuits 10 can be set according to the actual situation. After the control unit 222 divides the multi-phase parallel voltage conversion circuits 10 into a preset number of groups, it can calculate the quotient of the conduction time and the preset number to obtain the conduction interval duration. Then, it uses the conduction interval duration as the phase difference to periodically control each phase voltage conversion circuit 10 to work in turn.
[0036] Optionally, such as Figure 1 As shown, each phase voltage conversion circuit 10 includes a drive module 11. The control unit 222 is connected to the drive module 11 of each phase voltage conversion circuit 10 in each group of voltage conversion circuits 10. The control unit 222 is configured to enable the enable signal of the upper tube of the next group of voltage conversion circuits 10 to conduct after the conduction interval of the upper tube of the current group of voltage conversion circuits 10.
[0037] For example, in this embodiment, after the upper transistor of the first voltage conversion circuit 10 has been turned on for the conduction interval, the control unit 222 can then enable the enable signal of the second voltage conversion circuit 10; after the upper transistor of the second voltage conversion circuit 10 has been turned on for the conduction interval, the control unit 222 can then enable the enable signal of the third voltage conversion circuit 10, and so on, until the upper transistor of the last voltage conversion circuit 10 has been turned on for the conduction interval, at which point the control unit 222 can then enable the enable signal of the first voltage conversion circuit 10, thus forming a cycle.
[0038] Optionally, such as Figure 1As shown, each phase voltage conversion circuit 10 includes a pulse width modulation signal generation module 12. The pulse width modulation signal generation module 12 is used to generate a pulse width modulation signal. The driving modules 11 are all connected to the pulse width modulation signal generation module 12. Each phase driving module 11 is used to control the power transistor in the corresponding voltage conversion circuit 10 to turn on and off based on the pulse width modulation signal when the enable signal of the corresponding voltage conversion circuit 10 is valid.
[0039] That is, in this embodiment, if the enable signal of each phase voltage conversion circuit 10 is invalid, the phase voltage conversion circuit 10 cannot work. Only when the enable signal of the phase voltage conversion circuit 10 is valid can the phase voltage conversion circuit 10 work normally under the pulse width modulation signal. That is, when the enable signal of the phase voltage conversion circuit 10 is valid, the drive module 11 of the phase voltage conversion circuit 10 can control the conduction and cutoff of the power transistor in the corresponding voltage conversion circuit 10 based on the pulse width modulation signal.
[0040] For example, in one application scenario, with Figure 1 Taking the power management unit 100 shown as an example, Figure 1 The power management unit 100 shown includes N phase voltage conversion circuits 10 per group. In this embodiment, each group of voltage conversion circuits 10 includes only one phase voltage conversion circuit 10, that is, the power management unit 100 is divided into N groups of voltage conversion circuits 10. After obtaining the conduction time TON, the conduction interval TON / N of each group of voltage conversion circuits 10 can be calculated based on the number of groups N of voltage conversion circuits 10 and the conduction time TON. Please refer to... Figure 3 , Figure 3 This is a control waveform diagram of an embodiment of the power management unit 100 of this application. Wherein, ISUM represents the total current of the multiphase voltage conversion circuit 10, IA, IB, and IC represent the inductor current of each phase voltage conversion circuit 10; SWA represents the waveform of the switching node voltage of the first phase voltage conversion circuit 10; SWB represents the waveform of the switching node voltage of the second phase voltage conversion circuit 10; SWN represents the waveform of the switching node voltage of the Nth phase (i.e., the last phase) voltage conversion circuit 10; EN_BUCKB represents the enable signal of the second phase voltage conversion circuit 10; and EN_BUCKA represents the enable signal of the first phase voltage conversion circuit 10.
[0041] like Figure 3As shown, in this embodiment, after the upper transistor of the first phase voltage conversion circuit 10 is turned on, after a conduction interval of TON / N, the enable signal EN_BUCKB of the second phase voltage conversion circuit 10 can be enabled and flipped to a logic high level. In the second phase voltage conversion circuit 10, if the pulse width modulation signal of the second phase voltage conversion circuit 10 is at a logic high level, but the enable signal EN_BUCKB is at a logic low level, the second phase voltage conversion circuit 10 can only operate after the enable signal EN_BUCKB flips to a logic high level. After a conduction interval of TON / N for the upper transistor of the second phase voltage conversion circuit 10 is turned on, the enable signal EN_BUCKC of the third phase voltage conversion circuit 10 can be enabled, and so on, until the conduction interval of TON / N for the upper transistor of the Nth phase (i.e., the last phase) voltage conversion circuit 10 is turned on, the enable signal EN_BUCKA of the first phase voltage conversion circuit 10 can flip high, forming a cycle. Thus, with the help of loop stability, the voltage management unit can enable each phase voltage conversion circuit 10 to operate cyclically with the conduction interval TON / N as the phase difference.
[0042] Optionally, in this embodiment, the control unit 222 includes a conduction time generation circuit, which is configured to obtain the conduction interval duration TON / N based on the reference voltage corresponding to the conduction time TON and the number of groups of voltage conversion circuits 10.
[0043] Please see Figure 4 , Figure 4 This is a schematic diagram of the circuit structure of one embodiment of the conduction time generation circuit of this application. Figure 4 As shown, the conduction time generation circuit includes a voltage generation circuit 23 and a time generation circuit 24. The voltage generation circuit 23 is configured to perform voltage division based on the reference voltage and the number of groups of the voltage conversion circuit 10 to obtain the reference sub-voltage corresponding to the conduction interval duration TON / N. The time generation circuit is connected to the power generation circuit and is used to generate the conduction interval duration TON / N based on the reference sub-voltage.
[0044] Optionally, such as Figure 4As shown, the time generation circuit 24 in this embodiment includes: an operational amplifier EA, a first transistor M1, a second transistor M2, a third transistor M3, a resistor Rton, a capacitor Cton, a first comparator CMP1, and a second comparator CMP2; the positive input terminal of the operational amplifier EA receives the input voltage; the negative input terminal of the operational amplifier EA is connected to the second path terminal of the first transistor M1; the control terminal of the first transistor M1 is connected to the output terminal of the operational amplifier EA; the first path terminal of the first transistor M1 is coupled to the second path terminal of the second transistor M2, the control terminal of the second transistor M2, and the control terminal of the third transistor M3; the second path terminal of the first transistor M1 is also connected to the first terminal of the resistor Rton. The second terminal of resistor Rton is grounded. The first terminal of the second transistor M2 is connected to the first terminal of the third transistor M3. The second terminal of the third transistor M3 is connected to the first terminal of capacitor Cton. The second terminal of capacitor Cton is grounded. The positive input terminal of the first comparator CMP1 and the positive input terminal of the second comparator CMP2 are coupled at the intermediate node connecting the second terminal of the third transistor M3 and the first terminal of capacitor Cton. The negative input terminal of the first comparator CMP1 receives the reference sub-voltage VTON_ON / N to generate the corresponding conduction interval TON / N. The negative input terminal of the second comparator CMP2 receives the reference voltage VTON_ON to generate the corresponding conduction time TON.
[0045] That is, in this embodiment, when the input voltage is connected to the input terminal of the operational amplifier EA, the input voltage can charge the capacitor Cton through the operational amplifier EA, the first transistor M1, the second transistor M2 and the third transistor M3. At this time, the output feedback voltage of the intermediate node connecting the second path terminal of the third transistor M3 and the first terminal of the capacitor Cton will gradually increase. When the output feedback voltage increases to the reference voltage VTON_ON corresponding to the conduction time TON, the logic level of the output terminal of the first comparator CMP1 will turn high. The time from the input voltage being connected to the logic level of the output terminal of the first comparator CMP1 turning high is the conduction time TON. When the output feedback voltage increases to the reference sub-voltage VTON_ON / N corresponding to the conduction interval TON / N, the logic level of the output terminal of the second comparator CMP2 will turn high. The time from the input voltage being connected to the logic level of the output terminal of the second comparator CMP2 turning high is the conduction interval TON / N. In this embodiment, the reference voltage VTON_ON and the reference sub-voltage VTON_ON / N can be set based on the calculated on-time TON, the on-interval duration TON / N, and the rise rate of the capacitor Cton voltage.
[0046] Optionally, such as Figure 4As shown, the voltage generating circuit 23 in this embodiment includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a variable resistor RV, and a voltage divider resistor R.
[0047] In this configuration, the first-path terminals of the fourth transistor M4 and the fifth transistor M5 receive the power supply voltage. The control terminals of the fourth transistor M4 and the fifth transistor M5 receive the same bias voltage. The second-path terminal of the fourth transistor M4 is connected to the first-path terminal of the sixth transistor M6 and the first-path terminal of the seventh transistor M7. The control terminal of the sixth transistor M6 receives the reference voltage VTON_ON. The second-path terminal of the sixth transistor M6 is coupled to the first-path terminal of the eighth transistor M8, the control terminal of the eighth transistor M8, and the control terminal of the ninth transistor M9. The control terminal of the seventh transistor M7 also receives the reference voltage VTON_ON. The second-path terminal of the seventh transistor M7 is connected to the ninth transistor M9. The first path terminal of transistor M9 is connected, wherein the intermediate node at the connection between the second path terminal of the seventh transistor M7 and the first path terminal of the ninth transistor M9 is connected to the control terminal of the tenth transistor M10, the second path terminal of the fifth transistor M5 is connected to the first path terminal of the tenth transistor M10, the second path terminal of the tenth transistor M10 is connected to the first terminal of the variable resistor RV, the second terminal of the variable resistor RV is connected to the first terminal of the voltage divider resistor R, the second terminal of the voltage divider resistor R is connected to the second path terminal of the eighth transistor M8 and the second path terminal of the ninth transistor M9, and the second terminal of the variable resistor RV and the first terminal of the voltage divider resistor R serve as the output terminal to output the reference sub-voltage VTON_ON / N.
[0048] In this embodiment, the voltage generation circuit 23 obtains the reference sub-voltage VTON_ON / N by dividing the voltage using a voltage divider resistor R and a variable resistor RV. The calculation formula for the reference sub-voltage VTON_ON / N is as follows:
[0049]
[0050] Wherein, VTON_ON / N represents the reference sub-voltage, VTON_ON represents the reference voltage, R represents the resistance value of the voltage divider resistor, and RV represents the resistance value of the voltage divider resistor.
[0051] In this embodiment, the resistance value of the voltage divider resistor R can be set based on the number of voltage conversion circuits 10, and the specific calculation formula is as follows:
[0052] RV=(N-1)*R
[0053] Where R represents the resistance value of the voltage divider resistor, RV represents the resistance value of the voltage divider resistor, and N represents the number of groups divided by the voltage conversion circuit 10.
[0054] In other embodiments, the voltage generating circuit 23 may also be configured with other circuit structures, which are not limited here.
[0055] Optionally, this application further proposes a power management chip, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of an embodiment of the power management chip of this application. Figure 5 As shown, the power management chip 200 of this embodiment includes the power management unit 100 of any of the above embodiments.
[0056] Optionally, this application further proposes an electronic device, please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Figure 6 As shown, the electronic device 300 of this embodiment includes the power management chip 200 of the above embodiment.
[0057] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A power management unit, characterized in that, include: A multi-phase parallel voltage conversion circuit, wherein each phase of the voltage conversion circuit is used to provide a power signal to the same load; The logic control module is connected to each phase voltage conversion circuit and is used to calculate the conduction interval duration based on the conduction time of a certain phase voltage conversion circuit and the number of phases of the voltage conversion circuit, and to periodically control each phase voltage conversion circuit to work in turn using the conduction interval duration as the phase difference.
2. The power management unit according to claim 1, characterized in that, The logic control module includes: A sampling unit is used to collect and obtain the conduction time of a certain phase of the voltage conversion circuit; The delay control unit, connected to the sampling unit and the voltage conversion circuit of each phase, is configured to calculate the conduction interval duration based on the conduction time and the number of phases of the voltage conversion circuit, and to periodically control the voltage conversion circuit of each phase to work in turn using the conduction interval duration as the phase difference.
3. The power management unit according to claim 2, characterized in that, The delay control unit includes: A grouping unit is configured to divide the multi-phase parallel voltage conversion circuit into a predetermined number of groups of voltage conversion circuits based on the number of phases of the voltage conversion circuit, wherein each group of voltage conversion circuits includes at least one phase of the voltage conversion circuit. The control unit, connected to the grouping unit and each group of voltage conversion circuits, is configured to calculate the conduction interval duration based on the conduction time and the preset number, and to periodically control the voltage conversion circuits of each phase to work in turn using the conduction interval duration as the phase difference.
4. The power management unit according to claim 3, characterized in that, Each phase of the voltage conversion circuit includes a drive module. The control unit is connected to the drive module of each phase of the voltage conversion circuit in each group of voltage conversion circuits. The control unit is configured to enable the enable signal for the upper transistor of the next group of voltage conversion circuits to turn on after the conduction interval of the upper transistor of the current group of voltage conversion circuits has been turned on.
5. The power management unit according to claim 4, characterized in that, Each phase of the voltage conversion circuit includes a pulse width modulation signal generation module, which generates a pulse width modulation signal. The driving module is connected to the pulse width modulation signal generation module. Each phase driving module controls the power transistor in the corresponding voltage conversion circuit to turn on and off based on the pulse width modulation signal when the enable signal of the corresponding voltage conversion circuit is valid.
6. The power management unit according to claim 3, characterized in that, The control unit includes: A conduction time generation circuit is configured to obtain the conduction interval duration based on the reference voltage corresponding to the conduction time and the number of groups of the voltage conversion circuit.
7. The power management unit according to claim 6, characterized in that, The on-time generation circuit includes: The voltage generation circuit is configured to perform voltage division based on the reference voltage and the number of groups of the voltage conversion circuit to obtain the reference sub-voltage corresponding to the conduction interval duration; A time generation circuit, connected to the power generation circuit, is used to generate the conduction interval duration based on the reference sub-voltage.
8. The power management unit according to claim 7, characterized in that, The time generation circuit includes: an operational amplifier, a first transistor, a second transistor, a third transistor, a resistor, a capacitor, a first comparator, and a second comparator; The positive input terminal of the operational amplifier receives an input voltage; the negative input terminal of the operational amplifier is connected to the second path terminal of the first transistor; the control terminal of the first transistor is connected to the output terminal of the operational amplifier; the first path terminal of the first transistor is coupled to the second path terminal of the second transistor, the control terminal of the second transistor, and the control terminal of the third transistor; the second path terminal of the first transistor is also connected to the first end of the resistor; the second end of the resistor is grounded; the first path terminal of the second transistor is connected to the first path terminal of the third transistor; the second path terminal of the third transistor is connected to the first end of the capacitor; the second end of the capacitor is grounded; the positive input terminals of the first comparator and the second comparator are coupled to the intermediate node connecting the second path terminal of the third transistor and the first end of the capacitor; the negative input terminal of the first comparator receives the reference sub-voltage to generate the corresponding conduction interval duration; the negative input terminal of the second comparator receives the reference voltage to generate the corresponding conduction time.
9. A power management chip, characterized in that, Includes the power management unit as described in any one of claims 1-8.
10. An electronic device, characterized in that, Includes the power management chip as described in claim 9.