Broadband low-amplitude error delayer
By adding delay units to the delayer reference network and using GaAs pHEMT technology, combined with field-effect transistors and inductors/capacitors, the amplitude error problem of traditional delayers in broadband circuits is solved, achieving low error and high frequency characteristics.
Patent Information
- Application Number
- CN202511617584.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional delayers suffer from amplitude errors due to insertion loss variations with a fixed slope in broadband circuits, making them unsuitable for complex real-world environments.
A delay unit is added to the parallel resistor of the reference network. The design adopts GaAs pHEMT technology. The amplitude curve of the delay unit is fitted by the delay reference network formed by the combination of field-effect transistors and inductors and capacitors to reduce the error.
A wideband, low-amplitude delay timer was developed, featuring good frequency characteristics and area utilization efficiency, and is suitable for the 2GHz-20GHz frequency band.
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Figure CN121508489A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a broadband delay device with low amplitude error. Background Technology
[0002] Time delay units are crucial components of phased array systems. They achieve relative delays by switching between a reference state and a delay state using a single-pole double-throw switch. The core principle is to modify the group delay of the signal through a combination of passive capacitors and inductors. In the field of phased arrays, the narrowband effect and distortion of phase shifters are increasingly unable to meet the demands of increasingly complex real-world environments, making time delay units increasingly important. However, compared to phase shifters, time delay units require a larger area and face more complex simulation challenges due to microstrip line matching, thus limiting their application.
[0003] Traditional delay device structures such as Figure 1 As shown, the parallel resistor R1 of the reference network serves to reduce the amplitude error between the reference network and the delay unit. However, this method can only produce a fixed-slope insertion loss to match the insertion loss variation of the delay unit. In a broadband circuit, there are cases where the difference between the insertion loss of the reference network and the delay unit is large in some frequency bands. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention proposes a broadband delay with low amplitude error, comprising:
[0005] The system includes an input matching network, an output matching network, a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit, and a delay reference network. The input matching network is connected to one end of the first single-pole double-throw switch, and the other end of the first single-pole double-throw switch is connected to the input of the delay unit and the input of the delay reference network, respectively. One end of the second single-pole double-throw switch is connected to the output matching network, and the other end is connected to the input of the delay unit and the output of the delay reference network, respectively.
[0006] Preferably, the input matching network includes an inductor L4 and a capacitor C4 connected in series, with the series node connected to the first single-pole double-throw switch and the non-series node of capacitor C4 grounded.
[0007] Preferably, the output matching network includes an inductor L5 and a capacitor C5 connected in series, with the series node connected to the second single-pole double-throw switch and the non-series node of capacitor C5 grounded.
[0008] Preferably, the first single-pole double-throw switch includes field-effect transistors FET1 to FET4; the source of FET1 and the source of FET4 are both grounded; the gate of FET1 is connected to the gate of FET4, and the drain of FET1 is connected to the source of FET3 and the delay unit; the drain of FET2 is connected to the source of FET4 and the delay reference network, and the gate of FET2 is connected to the gate of FET3; the drain of FET3 and the drain of FET4 are both connected to the input matching network.
[0009] Preferably, the second single-pole double-throw switch includes field-effect transistors FET5 to FET8; the source of FET5 and the source of FET6 are both grounded; the gate of FET5 is connected to the gate of FET8, and the drain of FET5 is connected to the source of FET7 and the delay reference network; the drain of FET6 is connected to the source of FET8 and the delay unit, and the gate of FET6 is connected to the gate of FET7; the drain of FET7 and the drain of FET8 are both connected to the output matching network.
[0010] Preferably, the delay unit includes inductor L1, inductor L2 and capacitor C1; one end of capacitor C1 is connected to one end of inductor L1 and one end of inductor L2, and the other end of capacitor C1 is grounded; the other end of inductor L1 is connected to a first single-pole double-throw switch, and the other end of inductor L2 is connected to a second single-pole double-throw switch.
[0011] Preferably, the delay reference network includes a resistor R1, a capacitor C2, a capacitor C3, and an inductor L3; one end of the inductor L3 is connected to one end of the resistor R1, one end of the capacitor C2, and a first single-pole double-throw switch, and the other end of the inductor L3 is connected to one end of the capacitor C3 and a second single-pole double-throw switch; the other ends of the resistor R1, the capacitor C2, and the capacitor C3 are all grounded.
[0012] The beneficial effects of this invention are as follows: This invention adds a set of delay units to the parallel resistors of the reference network to obtain a delay reference network; this allows the amplitude curve of the delay units to be fitted into the amplitude curve of the network itself, reducing the amplitude error between the delay units and the reference network. The delay device designed in this invention has a wide bandwidth and large delay function, and has good application prospects. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of a traditional delay device structure in this invention;
[0014] Figure 2 This is an overall block diagram of the broadband low-amplitude error delay device structure in this invention;
[0015] Figure 3 This is a schematic diagram of the broadband low-amplitude error delay device structure in this invention. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] This invention proposes a broadband delay with low amplitude error, such as... Figure 2 As shown, the delay unit includes: an input matching network, an output matching network, a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit, and a delay reference network; the input matching network is connected to one end of the first single-pole double-throw switch, and the other end of the first single-pole double-throw switch is connected to the input end of the delay unit and the input end of the delay reference network, respectively; one end of the second single-pole double-throw switch is connected to the output matching network, and the other end is connected to the input end of the delay unit and the output end of the delay reference network, respectively.
[0018] like Figure 3 As shown, in some preferred embodiments of the present invention, the input matching network includes an inductor L4 and a capacitor C4 connected in series, with the series node connected to a first single-pole double-throw switch, and the non-series node of capacitor C4 grounded; the non-series node of inductor L4 serves as the input terminal of a delay unit. Adjusting the values of inductor L4 and capacitor C4 can change the input and output standing waves.
[0019] The output matching network consists of an inductor L5 and a capacitor C5 connected in series. The series node is connected to the second single-pole double-throw switch, the non-series node of capacitor C5 is grounded, and the non-series node of inductor L5 serves as the output terminal of the delay circuit. Adjusting the values of inductor L5 and capacitor C5 can change the input and output standing waves.
[0020] In some preferred embodiments of the present invention, the first single-pole double-throw switch includes field-effect transistors FET1 to FET4; the source of FET1 and the source of FET4 are both grounded; the gate of FET1 is connected to the gate of FET4, and the drain of FET1 is connected to the source of FET3 and the delay unit; the drain of FET2 is connected to the source of FET4 and the delay reference network, and the gate of FET2 is connected to the gate of FET3; the drains of FET3 and FET4 are both connected to the input matching network. The second single-pole double-throw switch includes field-effect transistors FET5 to FET8; the source of FET5 and the source of FET6 are both grounded; the gate of FET5 is connected to the gate of FET8, and the drain of FET5 is connected to the source of FET7 and the delay reference network; the drain of FET6 is connected to the source of FET8 and the delay unit, and the gate of FET6 is connected to the gate of FET7; the drains of FET7 and FET8 are both connected to the output matching network.
[0021] FET3, FET4, FET7, and FET8 are larger-sized switching transistors used to control the on / off state of the signal. The remaining switching transistors are smaller-sized transistors connected in parallel to ground, which prevents the signal from conducting into the input path when it is off, thus improving signal isolation.
[0022] In some preferred embodiments of the present invention, the delay unit includes inductor L1, inductor L2, and capacitor C1; one end of capacitor C1 is connected to one end of inductor L1 and one end of inductor L2, and the other end of capacitor C1 is grounded; the other end of inductor L1 is connected to a first single-pole double-throw switch, and the other end of inductor L2 is connected to a second single-pole double-throw switch. The delay unit with this structure can better control the area and has the effect of large delay capacity of a single unit that can be cascaded.
[0023] In some preferred embodiments of the present invention, the present invention is designed using a depletion-mode GaAs pHEMT process with a gate length of 0.5 μm. Compared to a reference network using resistors connected in parallel to ground, the delay reference network can fit the amplitude variation of the delay unit, thereby reducing the amplitude difference between the delay unit and the reference network. Therefore, the delay reference network of the present invention, as a reference delay branch for the delay unit, has the function of broadband high-slope attenuation to match the delay unit. The delay reference network includes a resistor R1, a capacitor C2, a capacitor C3, and an inductor L3; one end of the inductor L3 is connected to one end of the resistor R1, one end of the capacitor C2, and a first single-pole double-throw switch, and the other end of the inductor L3 is connected to one end of the capacitor C3 and a second single-pole double-throw switch; the other ends of the resistor R1, the capacitor C2, and the capacitor C3 are all grounded. Adjusting the value of R1 can adjust the amplitude curve. Adjusting the values of C2, C3, and L3 can change the slope of the amplitude curve at different positions.
[0024] Compared to traditional delayers, this invention adds a set of delay units to the parallel resistors of the reference network. This allows the amplitude curve of the delay units to be fitted into the amplitude curve of the network itself, reducing amplitude errors. Furthermore, because the reference network uses small delay units, which have characteristics such as small delay, large insertion loss, small area, and good stability, more redundant delay space and area are available when designing the delay units. In some preferred embodiments, based on GaAs technology, the circuit structure of this invention can realize a delayer operating in the 2GHz-20GHz range.
[0025] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A broadband, low-amplitude error delay timer, characterized in that, include: Input matching network, output matching network, first single-pole double-throw switch, second single-pole double-throw switch, delay unit and delay reference network; The input matching network is connected to one end of the first single-pole double-throw switch, and the other end of the first single-pole double-throw switch is connected to the input of the delay unit and the input of the delay reference network, respectively; one end of the second single-pole double-throw switch is connected to the output matching network, and the other end is connected to the input of the delay unit and the output of the delay reference network, respectively.
2. The broadband low-amplitude error delay device according to claim 1, characterized in that, The input matching network includes an inductor L4 and a capacitor C4 connected in series, with the series node connected to the first single-pole double-throw switch and the non-series node of capacitor C4 grounded.
3. The broadband low-amplitude error delay device according to claim 1, characterized in that, The output matching network includes an inductor L5 and a capacitor C5 connected in series, with the series node connected to the second single-pole double-throw switch and the non-series node of capacitor C5 grounded.
4. A broadband low-amplitude error delay device according to claim 1, characterized in that, The first single-pole double-throw switch includes field-effect transistors FET1 to FET4; the source of FET1 and the source of FET4 are both grounded; the gate of FET1 is connected to the gate of FET4, and the drain of FET1 is connected to the source of FET3 and the delay unit; the drain of FET2 is connected to the source of FET4 and the delay reference network, and the gate of FET2 is connected to the gate of FET3; the drain of FET3 and the drain of FET4 are both connected to the input matching network.
5. A broadband low-amplitude error delay device according to claim 1, characterized in that, The second single-pole double-throw switch includes field-effect transistors FET5 to FET8; the source of FET5 and the source of FET6 are both grounded; the gate of FET5 is connected to the gate of FET8, and the drain of FET5 is connected to the source of FET7 and the delay reference network; the drain of FET6 is connected to the source of FET8 and the delay unit, and the gate of FET6 is connected to the gate of FET7; the drain of FET7 and the drain of FET8 are both connected to the output matching network.
6. A broadband, low-amplitude error delay device according to claim 1, characterized in that, The delay unit includes inductor L1, inductor L2 and capacitor C1; one end of capacitor C1 is connected to one end of inductor L1 and one end of inductor L2, and the other end of capacitor C1 is grounded; the other end of inductor L1 is connected to a first single-pole double-throw switch, and the other end of inductor L2 is connected to a second single-pole double-throw switch.
7. A broadband, low-amplitude error delay device according to claim 1, characterized in that, The delay reference network includes a resistor R1, a capacitor C2, a capacitor C3, and an inductor L3; one end of the inductor L3 is connected to one end of the resistor R1, one end of the capacitor C2, and a first single-pole double-throw switch, and the other end of the inductor L3 is connected to one end of the capacitor C3 and a second single-pole double-throw switch; the other ends of the resistor R1, the capacitor C2, and the capacitor C3 are all grounded.