Network-on-chip full error type fault-tolerant optimization system and method based on redundant transmission

Abstract

The invention discloses a network-on-chip full error type fault-tolerant optimization system and method based on redundant transmission, belongs to the technical field of computer network communication, and aims to solve the technical problem of how to realize effective detection and response of network-on-chip soft and hard errors. Comprising a hard error detection module, a soft error detection module and a data packet synchronization module, and the soft error detection module completes SEU / MBU detection, error correction and retransmission; the hard error detection module monitors states of a link and a router in real time, outputs error identification and position information and dynamically adjusts a routing algorithm based on an error state; the data packet synchronization module solves the problem of disorder in redundant transmission and guarantees data integrity, the three modules are matched to cover full error types, an integrated system of accurate fault tolerance and data synchronization is supported, and high-reliability design is provided for manufacturing of a high-precision network-on-chip.

Description

Technical Field

[0001] This invention relates to the field of computer network communication technology, specifically to an on-chip network full error type fault-tolerant optimization system and method based on redundant transmission. Background Technology

[0002] As semiconductor process feature sizes continue to shrink (entering the deep submicron level), chip integration has increased significantly. Dozens or even hundreds of processor cores can be integrated on a single chip. On-chip networks, with their advantages of high scalability, high bandwidth, and low latency, have become the mainstream interconnect architecture for multi-core processors, gradually replacing traditional bus structures.

[0003] However, while deep submicron technology is driving the development of NoC (No-Chip), it also brings serious error challenges: On the one hand, the chip's sensitivity to external interference such as alpha particle bombardment, signal crosstalk, and electromagnetic interference is significantly increased, leading to frequent soft errors such as single event flip (SEU) and multiple bit flip (MBU). Among these, errors in the control fields of the head and tail dies can cause network deadlock and virtual channel resource leakage, seriously affecting communication reliability. On the other hand, manufacturing defects, circuit aging, and other factors lead to an increase in the incidence of hard errors such as link breakage and router core component failure. Traditional fault-tolerant solutions mostly focus on single errors and lack an effective detection and response mechanism for both soft and hard errors.

[0004] Furthermore, NoC design requires a strict balance between fault tolerance, transmission latency, and hardware resource overhead. Traditional solutions may lead to resource waste due to excessive redundancy or insufficient reliability due to imperfect detection logic, failing to meet the core requirements of "high reliability, low latency, and low overhead" in deep submicron processes.

[0005] How to effectively detect and respond to hardware and software errors in on-chip networks is a technical problem that needs to be solved. Summary of the Invention

[0006] The technical objective of this invention is to address the above-mentioned shortcomings by providing a fault-tolerant optimization system and method for on-chip networks based on redundant transmission, thereby solving the technical problem of how to effectively detect and respond to software and hardware errors in on-chip networks.

[0007] In a first aspect, the present invention provides an on-chip network full error type fault-tolerant optimization system based on redundant transmission, including a hard error detection module, a soft error detection module, and a data packet synchronization module;

[0008] The hard error detection module is used to perform real-time detection of on-chip network links, obtain the misalignment type and location of the links and routers, and store the misalignment identifier and error location through the error status register;

[0009] The soft error detection module is used to perform the following:

[0010] For a data packet to be sent that includes multiple micro-pieces in the source node, based on the three-modulus redundancy voting mechanism, three copies of the control fields in the head micro-piece and the tail micro-piece are generated. The micro-pieces and copies are duplicated, and CRC check bits and Hamming code bits are added to the micro-pieces and copies. The data packets are copied to obtain double redundant data packets. The data packet synchronization module adds the same timestamp and different redundancy identifiers to the double redundant data packets, and sends the double redundant data packets to the on-chip network link in a heterogeneous routing manner.

[0011] For the dual redundant data packets received by the target node, error detection is performed based on Hamming code and CRC check code. The risk of Hamming code misjudgment is avoided by using a three-to-two selection logic based on three copies. Timeout detection is performed based on timestamp and through the data packet synchronization module. The existence of error fragments is determined based on the error detection results and timeout detection results. A retransmission trigger signal is generated for the error fragments. An error request bit and an error fragment sequence number are appended to the tail fragment of the data packet, and the error fragment sequence number is returned to the source node.

[0012] For the source node, the error micro-segment sequence number is stored in the retransmission queue, the corresponding micro-segment is extracted from the local machine and encoded to obtain a retransmission micro-segment with CRC check code bits, Hamming code bits and retransmission flag, and the retransmission micro-segment is sent to the target node through the original channel.

[0013] For the target node, after verifying the retransmission micro-chip based on CRC encoding and Hamming code encoding, the original erroneous micro-chip is replaced by the retransmission micro-chip that passes the verification.

[0014] Preferably, the hard error detection module includes an error status register, a link hard error detection module, a router error detection module, and a route switching module;

[0015] The error status register stores the storage link error flag, cross switch error flag, virtual channel unit error flag, and route calculation unit error flag, which are then called by the route switching module.

[0016] The link hard error detection module is used to realize the link transmitter and receiver through the generation and comparison of test micro-chips, and to identify link error based on the link hard error detection results;

[0017] The router hard error detection module is used to detect errors in the router's cross switch, virtual channel allocation unit, and routing calculation unit, and to mark the cross switch error flag, virtual channel unit error flag, and routing calculation unit error flag according to the detection results;

[0018] The routing switching module is used to dynamically adjust the transmission scheme and routing algorithm for redundant transmission based on the value of the error status register.

[0019] As a preferred embodiment, the link hard error detection module's detection logic is divided into two parts: In terms of test micro-piece generation, the sending end generates a test micro-piece at a predetermined period, with the format being a fixed prefix + test code used to distinguish ordinary service micro-pieces; In terms of receiving end comparison, the test code is extracted and compared with the locally stored test code. If there is a mismatch after a predetermined number of consecutive times, a link hard error flag is triggered, and the link error flag is set to 1. The transmission priority of the test micro-piece is lower than that of ordinary micro-pieces, and it is only sent when the link is idle to avoid affecting normal communication.

[0020] The router error detection module is used to perform the following:

[0021] Cross switch detection: The status register records the result of each channel switching. When a predetermined number of consecutive switching failures occur, a hard error flag for the cross switch is triggered, and the cross switch error flag in the error status register is set to 1.

[0022] Virtual channel allocation detection counts the number of timeouts for virtual channel requests. If a predetermined number of timeouts occur consecutively, a virtual channel hard error flag is triggered, and the virtual channel allocation error flag in the error status register is set to 1.

[0023] The route calculation detection checks the validity of the input and output coordinates of the route calculation. If illegal route results are output multiple times in a row, a hard error flag for the route calculation is triggered, and the route calculation error flag in the error status register is set to 1.

[0024] The routing switching module supports three working modes: normal mode, link fault-tolerant mode, and router fault-tolerant mode. The normal mode is triggered when the flag bit of the error status register is 1, and the routing algorithm follows the original scheme without any additional adjustments. The link fault-tolerant mode is triggered when there is only a hard link error, and the routing algorithm is adjusted to bypass the faulty link by calculating the shortest path to avoid the faulty link, thus ensuring data transmission efficiency.

[0025] The fault-tolerant mode of a router is triggered by a hard error in the router. The routing algorithm is adjusted to bypass the faulty router across the entire network, marking it as unavailable. All transmission paths avoid this router to prevent the fault from spreading.

[0026] As a preferred embodiment, the soft error detection module includes a soft error encoding and sending module, a soft error judgment module, a retransmission request generation module, and a retransmission chip processing module.

[0027] The soft error coding sending module performs the following: At the source node, based on the three-modulus redundancy voting mechanism, three copies of the control fields in the header and tail micro-pieces are generated. Each micro-piece and each copy are CRC-encoded and Hamming-encoded respectively. Both the micro-pieces and copies are appended with CRC check bits and Hamming bits. The data packets are copied to obtain double redundant data packets. The data packet synchronization module is called to add a unified identifier to the double redundant data packets. The heterogeneous routing algorithm is assigned to the double redundant data packets. The double redundant data packets with the added unified identifier are injected in parallel into the on-chip network link.

[0028] The soft error detection module is used to perform the following: at the target node, it performs soft error trigger detection on the double redundant data packets based on Hamming code, CRC check code and timestamp, and avoids the risk of Hamming code misjudgment based on three copies and through three-to-two logic, generates a retransmission trigger signal based on the judgment result, and sends the retransmission trigger signal to the retransmission request generation module.

[0029] After receiving the retransmission trigger signal, the retransmission request generation module sets the error request bit NACK and the error fragment number in the tail fragment of the current data packet, and sends the data packet with the NACK bit and the error fragment number set to the source node through the on-chip network link. After receiving the data packet, the source node stores the error fragment number in the retransmission queue. The NACK bit indicates a request for retransmission, and the number of bits in the error fragment number is determined according to the number of error fragments and is used to identify the position of the error fragment in the data packet.

[0030] The retransmission fragment processing module performs the following: It retrieves the erroneous fragment sequence number from the retransmission queue of the source node, extracts the corresponding fragment from the local cache, performs CRC encoding and Hamming code encoding on the extracted fragment to obtain the retransmission fragment, attaches a retransmission flag R_FLAG to the retransmission fragment, sets R_FLAG = 1, and sends it to the target node through the original data channel with a higher priority than ordinary fragments; the target node detects R_FLAG = 1, prioritizes the retransmission fragment, replaces the original erroneous fragment, updates the data packet after CRC verification, and calculates the retransmission count for each retransmission fragment. If the retransmission count reaches a predetermined value and verification still fails, it triggers upper-layer protocol processing.

[0031] Preferably, the data packet synchronization module includes a synchronization identifier generation module, a matching logic module, and a synchronization cache module;

[0032] The synchronization identifier generation module provides a basis for matching dual redundant data packets by assigning a unified identifier. The identifier field format includes an 8-bit timestamp TS and a 2-bit redundancy identifier RID. Dual redundant packets from the same data source share the same timestamp TS. The timestamp TS increments by 1 for each set of redundant packets sent, with an initial value of 0. The redundancy identifier RID is used to distinguish the type of redundant packets: 00 = XY routing packet, 01 = YX routing packet, and 10 = retransmission packet. The generation logic is as follows: before sending data packets, the source node NA assigns the same timestamp TS to the dual redundant packets and automatically sets the redundancy identifier RID according to the routing algorithm. The timestamp counter is cleared when the system is reset and automatically increments by 1 for each set of redundant packets sent. It is reused cyclically after overflow.

[0033] The synchronization cache module is used to temporarily store redundant data packets to be matched. It supports comparison of two redundant data packets. The cache structure stores only two redundant data packets. Each cache entry contains an 8-bit timestamp TS, a 2-bit redundancy identifier RID, a data packet pointer, and a 1-bit valid bit. The data packet pointer points to the data packet storage address of the original NA receiver. The valid bit marks whether the cache entry is valid. The writing logic is as follows: After the source node receives the header micro-piece, it extracts the timestamp TS and the redundancy identifier RID. If there is no valid entry with the same timestamp TS in the cache, it writes the timestamp TS, redundancy identifier RID, and data packet pointer of the current packet into an empty cache entry and sets the valid bit to 1. If the cache is full, it replaces the earliest written entry first to ensure efficient use of cache resources.

[0034] The matching logic module is used to correctly filter and output redundant packets through identifier matching and timeout handling. The matching process is as follows: after a new data packet is written to the buffer, the buffer entries are traversed to find two data packets with different timestamps (TS) and redundancy identifiers (RID); after a matching pair is found, the original CRC check logic is called for comparison, and the data packet with the correct CRC is selected and output to the IP core. If both data packets are correct, the data packet that arrives first is selected; after output, the corresponding two entries in the buffer are cleared. In terms of timeout handling, a timeout counter is set for each buffer entry. The initial value is the dynamic timeout time. The counter is decremented by 1 every cycle. If no matching packet is found when the timeout reaches 0, a lightweight retransmission is triggered, and the buffer entry is cleared.

[0035] Secondly, the present invention provides an on-chip network full error type fault tolerance optimization method based on redundant transmission, including hard error detection, soft error detection, and data synchronization;

[0036] During hard error detection, the on-chip network links are detected in real time to obtain the misalignment type and location of the links and routers, and the misalignment identifier and error location are stored in the error status register.

[0037] Soft error detection includes the following operations:

[0038] For a data packet to be sent that includes multiple micro-pieces in the source node, based on the three-mode redundancy voting mechanism, three copies of the control fields in the head micro-piece and the tail micro-piece are generated. The micro-pieces and copies are replicated, and CRC check bits and Hamming code bits are added to the micro-pieces and copies. The data packets are copied to obtain double redundant data packets. The double redundant data packets are added with the same timestamp and different redundancy identifiers through data packet synchronization. The double redundant data packets are sent to the on-chip network link in a heterogeneous routing manner.

[0039] For the dual redundant data packets received by the target node, error detection is performed based on Hamming code and CRC check code. The risk of Hamming code misjudgment is avoided by using a three-to-two selection logic based on three copies. Timeout detection is performed based on timestamp and data packet synchronization. The existence of error fragments is determined based on the error detection results and timeout detection results. A retransmission trigger signal is generated for the error fragments. An error request bit and an error fragment sequence number are appended to the tail fragment of the data packet, and the error fragment sequence number is returned to the source node.

[0040] For the source node, the error micro-segment sequence number is stored in the retransmission queue, the corresponding micro-segment is extracted from the local machine and encoded to obtain a retransmission micro-segment with CRC check code bits, Hamming code bits and retransmission flag, and the retransmission micro-segment is sent to the target node through the original channel.

[0041] For the target node, after verifying the retransmission micro-chip based on CRC encoding and Hamming code encoding, the original erroneous micro-chip is replaced by the retransmission micro-chip that passes the verification.

[0042] Preferably, hard error detection includes link hard error detection, router error detection, and route switching;

[0043] The error status register stores the storage link error flag, cross switch error flag, virtual channel unit error flag, and route calculation unit error flag, which are then called by the route switching module.

[0044] During link hard error detection, the link transmitter and receiver are identified by generating and comparing test chips, and the link error is identified based on the link hard error detection results.

[0045] During router hard error detection, errors are detected in the router's cross switch, virtual channel allocation unit, and routing calculation unit. Based on the detection results, error flags are marked for the cross switch, virtual channel unit, and routing calculation unit.

[0046] During routing switching, the transmission scheme and routing algorithm for redundant transmission are dynamically adjusted based on the value of the error status register.

[0047] As a preferred option, the detection logic for link hard error detection is divided into two parts: In terms of test micro-chip generation, the sending end generates a test micro-chip at a predetermined period, with the format being a fixed prefix + test code used to distinguish ordinary service micro-chips; In terms of receiver comparison, the test code is extracted and compared with the test code stored locally. If there is a mismatch after a predetermined number of consecutive times, the link hard error flag is triggered and the link error flag is set to 1. The transmission priority of the test micro-chip is lower than that of ordinary micro-chips, and it is only sent when the link is idle to avoid affecting normal communication.

[0048] Router error detection includes the following operations:

[0049] Cross switch detection: The status register records the result of each channel switching. When a predetermined number of consecutive switching failures occur, a hard error flag for the cross switch is triggered, and the cross switch error flag in the error status register is set to 1.

[0050] Virtual channel allocation detection counts the number of timeouts for virtual channel requests. If a predetermined number of timeouts occur consecutively, a virtual channel hard error flag is triggered, and the virtual channel allocation error flag in the error status register is set to 1.

[0051] The route calculation detection checks the validity of the input and output coordinates of the route calculation. If illegal route results are output multiple times in a row, a hard error flag for the route calculation is triggered, and the route calculation error flag in the error status register is set to 1.

[0052] The routing switching module supports three working modes: normal mode, link fault-tolerant mode, and router fault-tolerant mode. The normal mode is triggered when the flag bit of the error status register is 1, and the routing algorithm follows the original scheme without any additional adjustments. The link fault-tolerant mode is triggered when there is only a hard link error, and the routing algorithm is adjusted to bypass the faulty link by calculating the shortest path to avoid the faulty link, thus ensuring data transmission efficiency.

[0053] The fault-tolerant mode of a router is triggered by a hard error in the router. The routing algorithm is adjusted to bypass the faulty router across the entire network, marking it as unavailable. All transmission paths avoid this router to prevent the fault from spreading.

[0054] As a preferred embodiment, soft error detection includes soft error encoding and transmission, soft error judgment, retransmission request generation, and retransmission chip processing.

[0055] When sending soft error coding, the following steps are performed: At the source node, based on the three-modulus redundancy voting mechanism, three copies of the control fields in the header and tail micro-pieces are generated. Each micro-piece and each copy are CRC-encoded and Hamming-encoded respectively. Both the micro-pieces and the copies are appended with CRC check bits and Hamming bits. The data packets are copied to obtain double redundant data packets. A unified identifier is added to the double redundant data packets through data packet synchronization. A heterogeneous routing algorithm is assigned to the double redundant data packets. The double redundant data packets with the added unified identifier are injected in parallel into the on-chip network link.

[0056] The soft error detection process is as follows: At the target node, soft error trigger detection is performed on the double redundant data packets based on Hamming code, CRC check code and timestamp. Based on three copies, the risk of Hamming code misjudgment is avoided by using a three-to-two selection logic. A retransmission trigger signal is generated based on the detection result and sent to the retransmission request generation module.

[0057] The retransmission request generation process performs the following operations: After receiving the retransmission trigger signal, the error request bit NACK and the error fragment number are set in the tail fragment of the current data packet, and the data packet with the NACK bit and the error fragment number is sent to the source node through the on-chip network link. After receiving the data packet, the source node stores the error fragment number in the retransmission queue. The NACK bit indicates a retransmission request, and the number of bits in the error fragment number is determined according to the number of error fragments and is used to identify the position of the error fragment in the data packet.

[0058] The retransmission fragment processing is performed as follows: The erroneous fragment sequence number is retrieved from the retransmission queue of the source node, and the corresponding fragment is extracted from the local cache. The extracted fragment is then CRC-encoded and Hamming-encoded to obtain the retransmission fragment. A retransmission flag R_FLAG is appended to the retransmission fragment, and R_FLAG is set to 1. The fragment is then sent to the target node via the original data channel with a higher priority than ordinary fragments. When the target node detects R_FLAG = 1, it prioritizes the retransmission fragment, replaces the original erroneous fragment, updates the data packet after CRC verification, and calculates the retransmission count for each retransmission fragment. If the retransmission count reaches a predetermined value and verification still fails, upper-layer protocol processing is triggered.

[0059] Preferably, data packet synchronization includes synchronization identifier generation, matching logic, and synchronization caching;

[0060] During synchronization identifier generation, a unified identifier is assigned to provide a basis for matching the two redundant data packets. The identifier field format includes an 8-bit timestamp TS and a 2-bit redundancy identifier RID. Two redundant packets from the same data source share the same timestamp TS. The timestamp TS is incremented by 1 for each set of redundant packets sent, and the initial value of the timestamp TS is 0. The redundancy identifier RID is used to distinguish the type of redundant packets: 00 = XY routing packet, 01 = YX routing packet, and 10 = retransmission packet. The generation logic is as follows: before sending data packets, the source node NA assigns the same timestamp TS to the two redundant packets and automatically sets the redundancy identifier RID according to the routing algorithm. The timestamp counter is cleared when the system is reset, and is automatically incremented by 1 for each set of redundant packets sent. After overflowing, it is reused cyclically.

[0061] The synchronization cache performs the following operations: It temporarily stores redundant data packets to be matched, supports comparison of two redundant data packets, and the cache structure stores only two redundant data packets. Each cache entry contains an 8-bit timestamp TS, a 2-bit redundancy identifier RID, a data packet pointer, and a 1-bit valid bit. The data packet pointer points to the data packet storage address of the original NA receiver, and the valid bit marks whether the cache entry is valid. The writing logic is as follows: After the source node receives the header micro-piece, it extracts the timestamp TS and the redundancy identifier RID. If there is no valid entry with the same timestamp TS in the cache, it writes the timestamp TS, redundancy identifier RID, and data packet pointer of the current packet into an empty cache entry and sets the valid bit to 1. If the cache is full, it replaces the earliest written entry first to ensure efficient use of cache resources.

[0062] The matching logic performs the following operations: Through identifier matching and timeout handling, redundant packets are correctly filtered and output. The matching process is as follows: After a new data packet is written to the buffer, the buffer entries are traversed to find two data packets with different timestamps (TS) and redundancy identifiers (RID); after a matching pair is found, the original CRC check logic is called for comparison, and the data packet with the correct CRC is selected and output to the IP core. If both data packets are correct, the data packet that arrives first is selected; after output, the corresponding two entries in the buffer are cleared. In terms of timeout handling, a timeout counter is set for each buffer entry. The initial value is the dynamic timeout time. The counter is decremented by 1 every cycle. If no matching packet is found when the timeout reaches 0, a lightweight retransmission is triggered, and the buffer entry is cleared.

[0063] The on-chip network full error type fault tolerance optimization method and system based on redundant transmission of the present invention has the following advantages: the soft error detection module completes the detection, error correction and retransmission of SEU / MBU; the hard error detection module monitors the link and router status in real time, outputs error identifiers and location information and dynamically adjusts the routing algorithm based on the error status; the data packet synchronization module solves the out-of-order problem in redundant transmission and ensures data integrity. The three modules cover all error types and support a precise fault tolerance and data synchronization integrated system, which provides a high-reliability design for the manufacturing of high-precision on-chip networks. Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0065] The invention will be further described below with reference to the accompanying drawings.

[0066] Figure 1 This is a block diagram of an on-chip network full error type fault-tolerant optimization system based on redundant transmission, as described in Example 1.

[0067] Figure 2 This is a flowchart illustrating the workflow of an on-chip network full error type fault tolerance optimization method based on redundant transmission, as described in Example 2. Detailed Implementation

[0068] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0069] This invention provides an on-chip network full error type fault-tolerant optimization system based on redundant transmission, which is used to solve the technical problem of how to effectively detect and deal with software and hardware errors in on-chip networks.

[0070] Example 1:

[0071] This invention discloses an on-chip network full error type fault-tolerant optimization system based on redundant transmission, including a hard error detection module, a soft error detection module, and a data packet synchronization module.

[0072] The hard error detection module is used to perform real-time detection of on-chip network links, obtain the misalignment type and location of the links and routers, and store the misalignment identifier and error location through the error status register.

[0073] In this embodiment, the hard error detection module includes an error status register, a link hard error detection module, a router error detection module, and a route switching module.

[0074] The error status register stores link error flags, crossbar switch error flags, virtual channel unit error flags, and route calculation unit error flags for use by the routing switching module. This register uses 4-bit flags: bit 0 for link error flags, bit 1 for crossbar switch error flags, bit 2 for virtual channel allocation unit error flags, and bit 3 for route calculation unit error flags. The transmission scheme is dynamically adjusted based on the different error flag bits.

[0075] The link hard error detection module is used to detect link errors at both the sending and receiving ends by generating and comparing test chips, and to identify link errors based on the hard error detection results. The detection logic of the link hard error detection module is divided into two parts: For test chip generation, the sending end generates a test chip at a predetermined period (100 clock cycles), with a format of a fixed prefix + test code used to distinguish it from ordinary service chips; For receiver comparison, the test code is extracted and compared with locally stored test codes. If there is a mismatch after a predetermined number of times (3 times), a link hard error is triggered, and the link error flag is set to 1. Test chips have lower transmission priority than ordinary chips and are only sent when the link is idle to avoid affecting normal communication.

[0076] The router hard error detection module designs differentiated detection logic for the router's core components to ensure coverage of critical fault points. The cross switch detection records the result of each channel switch (success = 1, failure = 0) through a status register. Five consecutive failures trigger a hard error flag on the cross switch, setting bit 1 of the error status register to 1. The virtual channel allocation unit detects and counts the "timeout count" of virtual channel requests (failure to allocate within 10 clock cycles after the request). Three consecutive timeouts trigger a hard error flag on the virtual channel, setting bit 2 of the error status register to 1. The route calculation unit checks the validity of input and output coordinates (e.g., whether they exceed the coordinate range). Five consecutive outputs of invalid routing results trigger a hard error flag on the route calculation, setting bit 3 of the error status register to 1. Specifically, the router error detection module performs the following:

[0077] (1) Cross switch detection: The result of each channel switching is recorded by the status register. When a predetermined number of consecutive switching failures occur, the hard error flag of the cross switch is triggered, and the cross switch error flag in the error status register is set to 1.

[0078] (2) Virtual channel allocation detection: count the number of timeouts for virtual channel requests. If a predetermined number of timeouts occur consecutively, a virtual channel hard error flag is triggered, and the virtual channel allocation error flag in the error status register is set to 1.

[0079] (3) Route calculation detection: The legality of the input and output coordinates of the route calculation is verified. If illegal route results are output multiple times in a row, the route calculation hard error flag is triggered and the route calculation error flag in the error status register is set to 1.

[0080] The routing switching module dynamically adjusts the transmission scheme and redundant transmission routing algorithm based on the value of the error status register. The module supports three operating modes: normal mode, link fault-tolerant mode, and router fault-tolerant mode. Normal mode is triggered when the flag bit in the error status register is 1; the routing algorithm uses the original scheme without additional adjustment. Link fault-tolerant mode is triggered when only a link experiences a hard fault; the routing algorithm is adjusted to use multiple paths to bypass the faulty link, calculating the shortest path to avoid the faulty link and ensuring data transmission efficiency. Router fault-tolerant mode is triggered when a router experiences a hard fault; the routing algorithm is adjusted to bypass the entire network, marking the faulty router as unavailable, and all transmission paths avoid this router to prevent the fault from spreading.

[0081] The soft error detection module is used to perform the following:

[0082] (1) For a data packet to be sent that includes multiple micro-pieces in the source node, based on the three-mode redundancy voting mechanism, three copies of the control fields in the head micro-piece and the tail micro-piece are generated. The micro-piece and the copy are copied, and CRC check bits and Hamming code bits are added to the micro-piece and the copy. The data packet is copied to obtain a double redundant data packet. The data packet synchronization module adds the same timestamp and different redundancy identifiers to the double redundant data packets, and sends the double redundant data packets to the on-chip network link in a heterogeneous routing manner.

[0083] (2) For the double redundant data packets received by the target node, error detection is performed based on Hamming code and CRC check code. Based on three copies, the risk of Hamming code misjudgment is avoided by using a three-to-two logic. Based on the timestamp, timeout detection is performed by the data packet synchronization module. Based on the error detection result and the timeout detection result, it is determined whether there is an error micro-piece. A retransmission trigger signal is generated for the error micro-piece. An error request bit and an error micro-piece sequence number are appended to the micro-piece at the end of the data packet. The error micro-piece sequence number is returned to the source node.

[0084] (3) For the source node, the error micro-segment number is stored in the retransmission queue, the corresponding micro-segment is extracted from the local machine and encoded to obtain a retransmission micro-segment with CRC check code bit, Hamming code bit and retransmission mark, and the retransmission micro-segment is sent to the target node through the original channel.

[0085] (4) For the target node, after verifying the retransmission micro-slice based on CRC encoding and Hamming code encoding, the retransmission micro-slice that passes the verification replaces the original erroneous micro-slice.

[0086] In this embodiment, the soft error detection module includes a soft error encoding and sending module, a soft error judgment module, a retransmission request generation module, and a retransmission chip processing module.

[0087] The soft error coding transmission module implements real-time error correction for the SEU using Hamming code encoding, covering 1-bit flip protection for data and control fields, and providing efficient verification support for data comparison at the receiving end through CRC encoding, thereby improving detection accuracy. It also designs dual redundancy for the control fields of the header and tail micro-pieces, using Triple Modular Redundancy (TMR) to avoid the risk of Hamming code misjudgment. Through parallel transmission of dual data and heterogeneous routing allocation, it provides a redundancy basis for MBU detection, reducing the probability of simultaneous errors in both sets of data. Specifically, this module performs the following: At the source node, based on the TMR voting mechanism, it generates three copies of the control fields in the header and tail micro-pieces. Each micro-piece and each copy is then CRC-encoded and Hamming-encoded, with CRC check bits and Hamming bits appended to both the micro-piece and the copy. The data packets are then copied to obtain dual redundant data packets. The data packet synchronization module is then called to add a unified identifier to the dual redundant data packets. A heterogeneous routing algorithm is then allocated to the dual redundant data packets, and the dual redundant data packets with the added unified identifier are injected in parallel into the on-chip network link.

[0088] The core function of the soft error detection module is to output a retransmission trigger signal based on signals generated from single-bit and multi-bit errors. The error signals involved include CRC_ERR, MBU_DET, and TIMEOUT: CRC_ERR is the error detection signal output by the CRC module, set to 1 when both copies of redundant data are incorrect; MBU_DET is a multi-bit flip detection signal added by the Hamming code decoding module, set to 1 when 2 or more bits of error are detected; TIMEOUT is the timeout signal output by the data packet synchronization module, set to 1 when no copies of the packet are received. When any one of the following conditions is met—CRC_ERR = 1, MBU_DET = 1, or TIMEOUT = 1—the retransmission trigger signal RETRY_TRIG = 1 is output. Specifically, this module performs the following: at the target node, it performs soft error trigger detection on the dual redundant data packets based on Hamming codes, CRC checksums, and timestamps. It also avoids the risk of Hamming code misjudgment by using a 3-to-2 selection logic based on three copies, generates a retransmission trigger signal based on the detection result, and sends the retransmission trigger signal to the retransmission request generation module.

[0089] The core of the retransmission request generation module is defining the NACK micro-fragment format and sending logic to ensure accurate delivery of retransmission requests. The NACK micro-fragment retains necessary control information and adds retransmission-related information, including a 1-bit NACK bit (1 indicates a retransmission request) and an error micro-fragment sequence number (the number of bits is determined by the number of error micro-fragments and is used to identify the position of the error micro-fragment within the data packet). The sending logic is as follows: After the receiving end detects RETRY_TRIG = 1, it sets the NACK bit and error sequence number in the tail micro-fragment of the current data packet and sends it to the source node via NoC to avoid consuming data bandwidth; after receiving the NACK, the source node stores the error sequence number in the retransmission queue, supporting multi-packet retransmission queuing. In a specific implementation, after receiving the retransmission trigger signal, the module performs the following: sets the error request bit NACK and the error fragment number in the tail fragment of the current data packet, and sends the data packet with the NACK bit and the error fragment number set to the source node through the on-chip network link. After receiving the data packet, the source node stores the error fragment number in the retransmission queue. The NACK bit indicates a request for retransmission, and the number of bits in the error fragment number is determined according to the number of error fragments and is used to identify the position of the error fragment in the data packet.

[0090] The retransmission chip processing module achieves efficient retransmission and replacement of erroneous chips by defining retransmission flags, procedures, and retransmission count control. The retransmission flag is designed by adding a 1-bit retransmission flag (R_FLAG) to the "type" field of the chip. When R_FLAG = 1, it indicates that the chip is to be retransmitted. The retransmission process consists of four steps: the source node reads the erroneous chip sequence number from the "retransmission queue" and retrieves the corresponding chip from its local cache; the original encoding process is performed on the retransmitted chip, i.e., Hamming code encoding is performed before entering the router cache, and CRC encoding is performed when leaving the NA; a retransmission flag (R_FLAG = 1) is added to the retransmitted chip, and it is transmitted through the original data channel with higher priority than ordinary chips; when the receiving end detects R_FLAG = 1, it prioritizes processing the chip, replaces the original erroneous chip, and updates the data packet after CRC verification. The retransmission count is controlled so that each erroneous chip can be retransmitted a maximum of 2 times. If the error persists, upper-layer protocol processing (such as interrupt notification) is triggered. In a specific implementation, this module performs the following: It retrieves the erroneous micro-fragment sequence number from the retransmission queue of the source node, extracts the corresponding micro-fragment from the local cache, performs CRC encoding and Hamming code encoding on the extracted micro-fragment to obtain the retransmission micro-fragment, attaches a retransmission flag R_FLAG to the retransmission micro-fragment, sets R_FLAG=1, and sends it to the target node through the original data channel with a higher priority than ordinary micro-fragments; the target node detects R_FLAG=1, prioritizes the retransmission micro-fragment, replaces the original erroneous micro-fragment, updates the data packet after CRC verification, and calculates the retransmission count for each retransmission micro-fragment. If the retransmission count reaches a predetermined value and verification still fails, it triggers upper-layer protocol processing.

[0091] In this embodiment, the data packet synchronization module includes a synchronization identifier generation module, a matching logic module, and a synchronization cache module.

[0092] The synchronization identifier generation module provides a basis for matching dual redundant data packets by assigning a unified identifier. The identifier field format includes an 8-bit timestamp TS and a 2-bit redundancy identifier RID. Dual redundant packets from the same data source share the same timestamp TS. The timestamp TS increments by 1 for each set of redundant packets sent, with an initial value of 0. The redundancy identifier RID is used to distinguish the type of redundant packets: 00 = XY routing packet, 01 = YX routing packet, and 10 = retransmission packet. The generation logic is as follows: before sending data packets, the source node NA assigns the same timestamp TS to the dual redundant packets and automatically sets the redundancy identifier RID according to the routing algorithm. The timestamp counter is cleared when the system is reset and automatically increments by 1 for each set of redundant packets sent. After overflowing, it is used cyclically.

[0093] The synchronization cache module is used to temporarily store redundant data packets to be matched. It supports comparison of two redundant data packets. The cache structure stores only two redundant data packets. Each cache entry contains an 8-bit timestamp TS, a 2-bit redundancy identifier RID, a data packet pointer, and a 1-bit valid bit. The data packet pointer points to the data packet storage address of the original NA receiver. The valid bit marks whether the cache entry is valid. The writing logic is as follows: After the source node receives the header micro-piece, it extracts the timestamp TS and the redundancy identifier RID. If there is no valid entry with the same timestamp TS in the cache, it writes the timestamp TS, redundancy identifier RID, and data packet pointer of the current packet into an empty cache entry and sets the valid bit to 1. If the cache is full, it replaces the earliest written entry first to ensure efficient use of cache resources.

[0094] The matching logic module is used to correctly filter and output redundant packets through identifier matching and timeout handling. The matching process is as follows: after a new data packet is written to the buffer, the buffer entries are traversed to find two data packets with different timestamps (TS) and redundancy identifiers (RID); after a matching pair is found, the original CRC check logic is called for comparison, and the data packet with the correct CRC is selected and output to the IP core. If both data packets are correct, the data packet that arrives first is selected. After output, the corresponding two entries in the buffer are cleared. In terms of timeout handling, a timeout counter is set for each buffer entry. The initial value is the dynamic timeout time. The counter is decremented by 1 every cycle. If no matching packet is found when the timeout reaches 0, a lightweight retransmission is triggered (TIMEOUT=1 is output to the retransmission request generation unit), and the buffer entry is cleared.

[0095] In this embodiment, the various modules of the system interact with each other through error status registers and control signals: the soft error detection module completes the detection, error correction and retransmission of SEU / MBU; the hard error detection module monitors the link and router status in real time, outputs error identifiers and location information and dynamically adjusts the routing algorithm based on the error status; the data packet synchronization module solves the out-of-order problem in redundant transmission and ensures data integrity.

[0096] To address single-bit errors (SEU), a dual redundancy strategy of "CRC code + Hamming code error correction + partial retransmission" is employed. Hamming codes are used for error detection and correction, and CRC is used to determine the correctness of the received chip. The sender generates a CRC checksum based on the transmitted information, and the Hamming code encodes the chip and its associated CRC checksum, protecting both the information bits and the check bits. Furthermore, Hamming codes possess real-time forward error correction capabilities; after decoding, errors can be located and automatically corrected without the need for buffers or redundant components, effectively saving area and cost. When the Hamming code module detects a 1-bit flip, it directly completes error correction through check bit calculation. The receiver generates a checksum using the same method based on the received information codeword and compares it with the received checksum to determine whether the received information is correct. Considering the different impacts of different chip types on network performance, errors in the head chip or tail chip can lead to network deadlock or virtual channel occupancy. Therefore, a triple modular redundancy (TMR) voting mechanism is added to these chips. Based on three copies of the control field, the correct value is confirmed through a "two out of three" logic to avoid the risk of misjudgment that may exist in Hamming code error correction.

[0097] For Multi-Bit Flip (MBU), since Hamming codes cannot correct it, a "double data redundancy + lightweight retransmission" mechanism is adopted. The sending end uses a parallel micro-slice transmission mode for the data field, simultaneously sending two identical micro-slices using different routing modes such as XY and YX to avoid data congestion. The receiving end compares the two data copies using CRC checksums, prioritizing the copy with correct checksum. If both copies are incorrect (MBU_DET=1), the retransmission request generation unit sends a NACK (NACK=1) signal to the source node, triggering a second transmission of the erroneous micro-slice. To reduce retransmission overhead, the retransmission micro-slice only contains the erroneous field and reuses the original virtual channel buffer resources.

[0098] Example 2:

[0099] This invention provides an on-chip network full error type fault tolerance optimization method based on redundant transmission, including hard error detection, soft error detection, and data synchronization.

[0100] During hard error detection, the on-chip network links are detected in real time to obtain the misalignment type and location of the links and routers, and the misalignment identifier and error location are stored in the error status register.

[0101] In this embodiment, hard error detection includes link hard error detection, router error detection, and route switching.

[0102] The error status register stores link error flags, crossbar switch error flags, virtual channel unit error flags, and route calculation unit error flags for use by the routing switching module. This register uses 4-bit flags: bit 0 for link error flags, bit 1 for crossbar switch error flags, bit 2 for virtual channel allocation unit error flags, and bit 3 for route calculation unit error flags. The transmission scheme is dynamically adjusted based on the different error flag bits.

[0103] Link hard error detection is achieved at both the sending and receiving ends by generating and comparing test chips, and a link error identifier is displayed based on the link hard error detection result. The link hard error detection module's detection logic is divided into two parts: In terms of test chip generation, the sending end generates a test chip at a predetermined period (100 clock cycles), with a format of a fixed prefix + test code used to distinguish it from ordinary service chips; In terms of receiver comparison, the test code is extracted and compared with the locally stored test code. If there is a mismatch after a predetermined number of times (3 times), the link hard error identifier is triggered and set to 1. The transmission priority of the test chip is lower than that of ordinary chips, and it is only sent when the link is idle to avoid affecting normal communication.

[0104] During router hard error detection, differentiated detection logic is designed for core router components to ensure coverage of critical fault points. Cross-switch detection records the result of each channel switch (success = 1, failure = 0) via a status register. Five consecutive failures trigger a hard error flag on the cross-switch, setting bit 1 of the error status register to 1. The virtual channel allocation unit counts the number of timeouts for virtual channel requests (failure to allocate within 10 clock cycles after the request). Three consecutive timeouts trigger a hard error flag on the virtual channel, setting bit 2 of the error status register to 1. The routing calculation unit performs validity checks on input and output coordinates (e.g., whether they exceed the coordinate range). Five consecutive outputs of invalid routing results trigger a hard error flag on the routing calculation, setting bit 3 of the error status register to 1. Specifically, router error detection is performed as follows:

[0105] (1) Cross switch detection: The result of each channel switching is recorded by the status register. When a predetermined number of consecutive switching failures occur, the hard error flag of the cross switch is triggered, and the cross switch error flag in the error status register is set to 1.

[0106] (2) Virtual channel allocation detection: count the number of timeouts for virtual channel requests. If a predetermined number of timeouts occur consecutively, a virtual channel hard error flag is triggered, and the virtual channel allocation error flag in the error status register is set to 1.

[0107] (3) Route calculation detection: The legality of the input and output coordinates of the route calculation is verified. If illegal route results are output multiple times in a row, the route calculation hard error flag is triggered and the route calculation error flag in the error status register is set to 1.

[0108] During route switching, the transmission scheme and redundant transmission routing algorithm are dynamically adjusted based on the value of the error status register. The route switching module supports three working modes: normal mode, link fault-tolerant mode, and router fault-tolerant mode. The normal mode is triggered when the flag bit of the error status register is 1, and the routing algorithm uses the original scheme without additional adjustment. The link fault-tolerant mode is triggered when there is only a hard link error, and the routing algorithm is adjusted to multi-path bypass, calculating the shortest path to avoid the faulty link to ensure data transmission efficiency. The router fault-tolerant mode is triggered when there is a hard router error, and the routing algorithm is adjusted to bypass the entire network, marking the faulty router as unavailable, and all transmission paths avoid this router to prevent the fault from spreading.

[0109] Soft error detection includes the following operations:

[0110] (1) For a data packet to be sent that includes multiple micro-pieces in the source node, based on the three-mode redundancy voting mechanism, three copies of the control fields in the head micro-piece and the tail micro-piece are generated. The micro-pieces and copies are copied, and CRC check bits and Hamming code bits are added to the micro-pieces and copies. The data packets are copied to obtain double redundant data packets. The double redundant data packets are added with the same timestamp and different redundancy identifiers through data packet synchronization. The double redundant data packets are sent to the on-chip network link in a heterogeneous routing manner.

[0111] (2) For the double redundant data packets received by the target node, error detection is performed based on Hamming code and CRC check code. Based on three copies, the risk of Hamming code misjudgment is avoided by using the three-to-two logic. Based on the timestamp, timeout detection is performed by data packet synchronization. Based on the error detection result and the timeout detection result, it is determined whether there is an error micro-piece. A retransmission trigger signal is generated for the error micro-piece. An error request bit and an error micro-piece sequence number are appended to the micro-piece at the end of the data packet. The error micro-piece sequence number is returned to the source node.

[0112] (3) For the source node, the error micro-segment number is stored in the retransmission queue, the corresponding micro-segment is extracted from the local machine and encoded to obtain a retransmission micro-segment with CRC check code bit, Hamming code bit and retransmission mark, and the retransmission micro-segment is sent to the target node through the original channel.

[0113] (4) For the target node, after verifying the retransmission micro-slice based on CRC encoding and Hamming code encoding, the retransmission micro-slice that passes the verification replaces the original erroneous micro-slice.

[0114] In this embodiment, soft error detection includes soft error encoding and transmission, soft error judgment, retransmission request generation, and retransmission chip processing.

[0115] Soft error coding transmission achieves real-time error correction for the SEU through Hamming code encoding, covering 1-bit flip protection for data and control fields, and providing efficient verification support for data comparison at the receiving end through CRC encoding, thus improving detection accuracy. Dual redundancy is designed for the control fields of the header / tail micro-chips, and triple modular redundancy (TMR) is used to avoid the risk of Hamming code misjudgment. Parallel transmission of dual data and heterogeneous routing allocation provide a redundancy basis for MBU detection, reducing the probability of simultaneous errors in both sets of data. Specifically, this step is executed as follows: At the source node, based on the TMR voting mechanism, three copies of the control fields in the header and tail micro-chips are generated. Each micro-chip and each copy are CRC-encoded and Hamming-encoded respectively. Both the micro-chip and the copy are appended with CRC check bits and Hamming bits. The data packets are then copied to obtain dual redundant data packets. The data packet synchronization module is called to add a unified identifier to the dual redundant data packets. A heterogeneous routing algorithm is assigned to the dual redundant data packets, and the dual redundant data packets with the added unified identifier are injected in parallel into the on-chip network link.

[0116] The core function of soft error detection is to output a retransmission trigger signal based on signals generated from single-bit and multi-bit errors. The error signals involved include CRC_ERR, MBU_DET, and TIMEOUT: CRC_ERR is the error detection signal output by the CRC module, set to 1 when both copies of redundant data are incorrect; MBU_DET is a multi-bit flip detection signal added by the Hamming code decoding module, set to 1 when 2 or more bits of error are detected; TIMEOUT is the timeout signal output by the data packet synchronization module, set to 1 when no copies of the packet are received. When any one of the following conditions is met—CRC_ERR = 1, MBU_DET = 1, or TIMEOUT = 1—the retransmission trigger signal RETRY_TRIG = 1 is output. Specifically, this step is executed as follows: At the target node, soft error trigger detection is performed on the dual redundant data packets based on Hamming code, CRC checksum, and timestamp. Using three copies and a 3-to-2 selection logic to avoid the risk of Hamming code misjudgment, a retransmission trigger signal is generated based on the detection result and sent to the retransmission request generation module.

[0117] The core of retransmission request generation is defining the NACK chip format and sending logic to ensure accurate delivery of retransmission requests. The NACK chip, while retaining necessary control information, adds retransmission-related information, including a 1-bit NACK bit (1 indicates a retransmission request) and an error chip sequence number (the number of bits is determined by the number of error chips and used to identify the position of the error chip within the data packet). The sending logic is as follows: After the receiving end detects RETRY_TRIG = 1, it sets the NACK bit and error sequence number in the tail chip of the current data packet and sends it to the source node via NoC to avoid consuming data bandwidth; after receiving the NACK, the source node stores the error sequence number in the retransmission queue, supporting multi-packet retransmission queuing. In a specific implementation, after receiving the retransmission trigger signal, the following steps are performed: an error request bit NACK and an error fragment number are set in the tail fragment of the current data packet, and the data packet with the NACK bit and the error fragment number is sent to the source node through the on-chip network link. After receiving the data packet, the source node stores the error fragment number in the retransmission queue. The NACK bit indicates a request for retransmission, and the number of bits in the error fragment number is determined according to the number of error fragments and is used to identify the position of the error fragment in the data packet.

[0118] Retransmission fragment processing achieves efficient retransmission and replacement of erroneous fragments by defining retransmission flags, procedures, and retransmission count control. The retransmission flag is designed by adding a 1-bit retransmission flag (R_FLAG) to the "type" field of the fragment. When R_FLAG = 1, it indicates that the fragment is to be retransmitted. The retransmission process consists of four steps: the source node reads the erroneous fragment sequence number from the "retransmission queue" and retrieves the corresponding fragment from its local cache; the original encoding process is performed on the retransmitted fragment, i.e., Hamming code encoding is performed before entering the router cache, and CRC encoding is performed when leaving the NA; a retransmission flag (R_FLAG = 1) is added to the retransmitted fragment, and it is transmitted through the original data channel with higher priority than ordinary fragments; when the receiving end detects R_FLAG = 1, it prioritizes processing this fragment, replaces the original erroneous fragment, and updates the data packet after CRC verification. The retransmission count is controlled so that each erroneous fragment can be retransmitted a maximum of 2 times. If the error persists, upper-layer protocol processing (such as interrupt notification) is triggered. In specific implementation, this step is performed as follows: The erroneous micro-fragment sequence number is obtained from the retransmission queue of the source node, and the corresponding micro-fragment is extracted from the local cache. The extracted micro-fragment is CRC-encoded and Hamming-encoded to obtain the retransmission micro-fragment. A retransmission flag R_FLAG is attached to the retransmission micro-fragment, and R_FLAG = 1 is set. The micro-fragment is then sent to the target node through the original data channel with a higher priority than ordinary micro-fragments. When the target node detects R_FLAG = 1, it prioritizes the retransmission micro-fragment and replaces the original erroneous micro-fragment. After CRC verification, the data packet is updated, and the retransmission count is calculated for each retransmission micro-fragment. If the retransmission count reaches a predetermined value and verification still fails, the upper-layer protocol processing is triggered.

[0119] In this embodiment, data packet synchronization includes synchronization identifier generation, matching logic, and synchronization caching.

[0120] Synchronization identifier generation provides a basis for matching dual redundant data packets by allocating a unified identifier. The identifier field format includes an 8-bit timestamp TS and a 2-bit redundancy identifier RID. Dual redundant packets from the same data source share the same timestamp TS. The timestamp TS increments by 1 for each set of redundant packets sent, with an initial value of 0. The redundancy identifier RID is used to distinguish the type of redundant packets: 00 = XY routing packet, 01 = YX routing packet, and 10 = retransmission packet. The generation logic is as follows: Before sending data packets, the source node NA allocates the same timestamp TS to the dual redundant packets and automatically sets the redundancy identifier RID according to the routing algorithm. The timestamp counter is cleared when the system is reset and automatically increments by 1 for each set of redundant packets sent. After overflowing, it is reused cyclically.

[0121] During synchronization caching, redundant data packets to be matched are temporarily stored, supporting comparison of two redundant data packets. The cache structure stores only two redundant data packets. Each cache entry contains an 8-bit timestamp TS, a 2-bit redundancy identifier RID, a data packet pointer, and a 1-bit valid bit. The data packet pointer points to the data packet storage address of the original NA receiver, and the valid bit marks whether the cache entry is valid. The writing logic is as follows: after the source node receives the header micro-piece, it extracts the timestamp TS and the redundancy identifier RID. If there is no valid entry with the same timestamp TS in the cache, the timestamp TS, redundancy identifier RID, and data packet pointer of the current packet are written to an empty cache entry and the valid bit is set to 1. If the cache is full, the earliest written entry is replaced first to ensure efficient use of cache resources.

[0122] During the matching logic, redundant packets are correctly filtered and output through identifier matching and timeout handling. The matching process is as follows: after a new data packet is written to the buffer, the buffer entries are traversed to find two data packets with different timestamps (TS) and redundancy identifiers (RID); after a matching pair is found, the original CRC check logic is called for comparison, and the data packet with the correct CRC is selected and output to the IP core. If both data packets are correct, the data packet that arrives first is selected; after output, the corresponding two entries in the buffer are cleared. In terms of timeout handling, a timeout counter is set for each buffer entry. The initial value is the dynamic timeout time. The counter is decremented by 1 every cycle. If no matching packet is found when the timeout reaches 0, a lightweight retransmission is triggered (TIMEOUT=1 is output to the retransmission request generation unit), and the buffer entry is cleared.

[0123] The method in this embodiment can be implemented based on the system disclosed in Embodiment 1.

[0124] The above provides a detailed description of the on-chip network full error type fault-tolerant optimization system method based on redundant transmission provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A fault-tolerant optimization system for on-chip networks based on redundant transmission, characterized in that, It includes a hard error detection module, a soft error detection module, and a data packet synchronization module; The hard error detection module is used to perform real-time detection of on-chip network links, obtain the misalignment type and location of the links and routers, and store the misalignment identifier and error location through the error status register; The soft error detection module is used to perform the following: For a data packet to be sent that includes multiple micro-pieces in the source node, based on the three-modulus redundancy voting mechanism, three copies of the control fields in the head micro-piece and the tail micro-piece are generated. The micro-pieces and copies are duplicated, and CRC check bits and Hamming code bits are added to the micro-pieces and copies. The data packets are copied to obtain double redundant data packets. The data packet synchronization module adds the same timestamp and different redundancy identifiers to the double redundant data packets, and sends the double redundant data packets to the on-chip network link in a heterogeneous routing manner. For the dual redundant data packets received by the target node, error detection is performed based on Hamming code and CRC check code. The risk of Hamming code misjudgment is avoided by using a three-to-two selection logic based on three copies. Timeout detection is performed based on timestamp and through the data packet synchronization module. The existence of error fragments is determined based on the error detection results and timeout detection results. A retransmission trigger signal is generated for the error fragments. An error request bit and an error fragment sequence number are appended to the tail fragment of the data packet, and the error fragment sequence number is returned to the source node. For the source node, the error micro-segment sequence number is stored in the retransmission queue, the corresponding micro-segment is extracted from the local machine and encoded to obtain a retransmission micro-segment with CRC check code bits, Hamming code bits and retransmission flag, and the retransmission micro-segment is sent to the target node through the original channel. For the target node, after verifying the retransmission micro-chip based on CRC encoding and Hamming code encoding, the original erroneous micro-chip is replaced by the retransmission micro-chip that passes the verification.

2. The on-chip network full error type fault-tolerant optimization system based on redundant transmission according to claim 1, characterized in that, The hard error detection module includes an error status register, a link hard error detection module, a router error detection module, and a route switching module; The error status register stores the storage link error flag, cross switch error flag, virtual channel unit error flag, and route calculation unit error flag, which are then called by the route switching module. The link hard error detection module is used to realize the link transmitter and receiver through the generation and comparison of test micro-chips, and to identify link error based on the link hard error detection results; The router hard error detection module is used to detect errors in the router's cross switch, virtual channel allocation unit, and routing calculation unit, and to mark the cross switch error flag, virtual channel unit error flag, and routing calculation unit error flag according to the detection results; The routing switching module is used to dynamically adjust the transmission scheme and routing algorithm for redundant transmission based on the value of the error status register.

3. The on-chip network full-fault type fault-tolerant optimization system based on redundant transmission according to claim 2, characterized in that, The link hard error detection module's detection logic is divided into two parts: In terms of test micro-chip generation, the sending end generates a test micro-chip at a predetermined period, with the format being a fixed prefix + test code used to distinguish ordinary service micro-chips; In terms of receiving end comparison, the test code is extracted and compared with the locally stored test code. If there is a mismatch after a predetermined number of consecutive times, the link hard error flag is triggered, and the link error flag is set to 1. The transmission priority of the test micro-chip is lower than that of ordinary micro-chips, and it is only sent when the link is idle to avoid affecting normal communication. The router error detection module is used to perform the following: Cross switch detection: The status register records the result of each channel switching. When a predetermined number of consecutive switching failures occur, a hard error flag for the cross switch is triggered, and the cross switch error flag in the error status register is set to 1. Virtual channel allocation detection counts the number of timeouts for virtual channel requests. If a predetermined number of timeouts occur consecutively, a virtual channel hard error flag is triggered, and the virtual channel allocation error flag in the error status register is set to 1. The route calculation detection checks the validity of the input and output coordinates of the route calculation. If illegal route results are output multiple times in a row, a hard error flag for the route calculation is triggered, and the route calculation error flag in the error status register is set to 1. The routing switching module supports three working modes: normal mode, link fault-tolerant mode, and router fault-tolerant mode. The normal mode is triggered when the flag bit of the error status register is 1, and the routing algorithm uses the original scheme without any additional adjustments. The link fault-tolerant mode is triggered when there is only a hard link error, and the routing algorithm is adjusted to multi-path bypass, calculating the shortest path to avoid the faulty link to ensure data transmission efficiency. The router fault-tolerant mode is triggered when there is a hard router error, and the routing algorithm is adjusted to bypass the entire network, marking the faulty router as unavailable, and all transmission paths avoid the router to prevent the fault from spreading.

4. The on-chip network full error type fault-tolerant optimization system based on redundant transmission according to claim 1, characterized in that, The soft error detection module includes a soft error encoding and sending module, a soft error judgment module, a retransmission request generation module, and a retransmission chip processing module; The soft error coding sending module performs the following: At the source node, based on the three-modulus redundancy voting mechanism, three copies of the control fields in the header and tail micro-pieces are generated. Each micro-piece and each copy are CRC-encoded and Hamming-encoded respectively. Both the micro-pieces and copies are appended with CRC check bits and Hamming bits. The data packets are copied to obtain double redundant data packets. The data packet synchronization module is called to add a unified identifier to the double redundant data packets. The heterogeneous routing algorithm is assigned to the double redundant data packets. The double redundant data packets with the added unified identifier are injected in parallel into the on-chip network link. The soft error detection module is used to perform the following: at the target node, it performs soft error trigger detection on the double redundant data packets based on Hamming code, CRC check code and timestamp, and avoids the risk of Hamming code misjudgment based on three copies and through three-to-two logic, generates a retransmission trigger signal based on the judgment result, and sends the retransmission trigger signal to the retransmission request generation module. After receiving the retransmission trigger signal, the retransmission request generation module sets the error request bit NACK and the error fragment number in the tail fragment of the current data packet, and sends the data packet with the NACK bit and the error fragment number set to the source node through the on-chip network link. After receiving the data packet, the source node stores the error fragment number in the retransmission queue. The NACK bit indicates a request for retransmission, and the number of bits in the error fragment number is determined according to the number of error fragments and is used to identify the position of the error fragment in the data packet. The retransmission fragment processing module performs the following: It retrieves the erroneous fragment sequence number from the retransmission queue of the source node, extracts the corresponding fragment from the local cache, performs CRC encoding and Hamming code encoding on the extracted fragment to obtain the retransmission fragment, attaches a retransmission flag R_FLAG to the retransmission fragment, sets R_FLAG = 1, and sends it to the target node through the original data channel with a higher priority than ordinary fragments; the target node detects R_FLAG = 1, prioritizes the retransmission fragment, replaces the original erroneous fragment, updates the data packet after CRC verification, and calculates the retransmission count for each retransmission fragment. If the retransmission count reaches a predetermined value and verification still fails, it triggers upper-layer protocol processing.

5. The on-chip network full error type fault-tolerant optimization system based on redundant transmission according to claim 1, characterized in that, The data packet synchronization module includes a synchronization identifier generation module, a matching logic module, and a synchronization cache module; The synchronization identifier generation module provides a basis for matching dual redundant data packets by assigning a unified identifier. The identifier field format includes an 8-bit timestamp TS and a 2-bit redundancy identifier RID. Dual redundant packets from the same data source share the same timestamp TS. The timestamp TS increments by 1 for each set of redundant packets sent, with an initial value of 0. The redundancy identifier RID is used to distinguish the type of redundant packets: 00 = XY routing packet, 01 = YX routing packet, and 10 = retransmission packet. The generation logic is as follows: before sending data packets, the source node NA assigns the same timestamp TS to the dual redundant packets and automatically sets the redundancy identifier RID according to the routing algorithm. The timestamp counter is cleared when the system is reset and automatically increments by 1 for each set of redundant packets sent. It is reused cyclically after overflow. The synchronization cache module is used to temporarily store redundant data packets to be matched. It supports comparison of two redundant data packets. The cache structure stores only two redundant data packets. Each cache entry contains an 8-bit timestamp TS, a 2-bit redundancy identifier RID, a data packet pointer, and a 1-bit valid bit. The data packet pointer points to the data packet storage address of the original NA receiver. The valid bit marks whether the cache entry is valid. The writing logic is as follows: After the source node receives the header micro-piece, it extracts the timestamp TS and the redundancy identifier RID. If there is no valid entry with the same timestamp TS in the cache, it writes the timestamp TS, the redundancy identifier RID, and the data packet pointer of the current packet into an empty cache entry and sets the valid bit to 1. If the cache is full, the earliest written item will be replaced first to ensure efficient use of cache resources; The matching logic module is used to correctly filter and output redundant packets through identifier matching and timeout handling. The matching process is as follows: after a new data packet is written to the buffer, the buffer entries are traversed to find two data packets with different timestamps (TS) and redundancy identifiers (RID); after a matching pair is found, the original CRC check logic is called for comparison, and the data packet with the correct CRC is selected and output to the IP core. If both data packets are correct, the data packet that arrives first is selected; after output, the corresponding two entries in the buffer are cleared. In terms of timeout handling, a timeout counter is set for each buffer entry. The initial value is the dynamic timeout time. The counter is decremented by 1 every cycle. If no matching packet is found when the timeout reaches 0, a lightweight retransmission is triggered, and the buffer entry is cleared.

6. A fault-tolerant optimization method for on-chip networks based on redundant transmission, characterized in that, This includes hard error detection, soft error detection, and data synchronization; During hard error detection, the on-chip network links are detected in real time to obtain the misalignment type and location of the links and routers, and the misalignment identifier and error location are stored in the error status register. Soft error detection includes the following operations: For a data packet to be sent that includes multiple micro-pieces in the source node, based on the three-mode redundancy voting mechanism, three copies of the control fields in the head micro-piece and the tail micro-piece are generated. The micro-pieces and copies are replicated, and CRC check bits and Hamming code bits are added to the micro-pieces and copies. The data packets are copied to obtain double redundant data packets. The double redundant data packets are added with the same timestamp and different redundancy identifiers through data packet synchronization. The double redundant data packets are sent to the on-chip network link in a heterogeneous routing manner. For the dual redundant data packets received by the target node, error detection is performed based on Hamming code and CRC check code. The risk of Hamming code misjudgment is avoided by using a three-to-two selection logic based on three copies. Timeout detection is performed based on timestamp and data packet synchronization. The existence of error fragments is determined based on the error detection results and timeout detection results. A retransmission trigger signal is generated for the error fragments. An error request bit and an error fragment sequence number are appended to the tail fragment of the data packet, and the error fragment sequence number is returned to the source node. For the source node, the error micro-segment sequence number is stored in the retransmission queue, the corresponding micro-segment is extracted from the local machine and encoded to obtain a retransmission micro-segment with CRC check code bits, Hamming code bits and retransmission flag, and the retransmission micro-segment is sent to the target node through the original channel. For the target node, after verifying the retransmission micro-chip based on CRC encoding and Hamming code encoding, the original erroneous micro-chip is replaced by the retransmission micro-chip that passes the verification.

7. The on-chip network full error type fault tolerance optimization method based on redundant transmission according to claim 6, characterized in that, Hard error detection includes link hard error detection, router error detection, and route switching; The error status register stores the storage link error flag, cross switch error flag, virtual channel unit error flag, and route calculation unit error flag, which are then called by the route switching module. During link hard error detection, the link transmitter and receiver are identified by generating and comparing test chips, and the link error is identified based on the link hard error detection results. During router hard error detection, errors are detected in the router's cross switch, virtual channel allocation unit, and routing calculation unit. Based on the detection results, error flags are marked for the cross switch, virtual channel unit, and routing calculation unit. During routing switching, the transmission scheme and routing algorithm for redundant transmission are dynamically adjusted based on the value of the error status register.

8. The on-chip network full error type fault tolerance optimization method based on redundant transmission according to claim 7, characterized in that, The detection logic for link hard error detection is divided into two parts: In terms of test chip generation, the sending end generates a test chip at a predetermined period, with the format being a fixed prefix + test code used to distinguish ordinary service chips; In terms of receiver comparison, the test code is extracted and compared with the locally stored test code. If there is a mismatch after a predetermined number of consecutive times, the link hard error flag is triggered and the link error flag is set to 1. The transmission priority of the test chip is lower than that of the ordinary chip, and it is only sent when the link is idle to avoid affecting normal communication. Router error detection includes the following operations: Cross switch detection: The status register records the result of each channel switching. When a predetermined number of consecutive switching failures occur, a hard error flag for the cross switch is triggered, and the cross switch error flag in the error status register is set to 1. Virtual channel allocation detection counts the number of timeouts for virtual channel requests. If a predetermined number of timeouts occur consecutively, a virtual channel hard error flag is triggered, and the virtual channel allocation error flag in the error status register is set to 1. The route calculation detection checks the validity of the input and output coordinates of the route calculation. If illegal route results are output multiple times in a row, a hard error flag for the route calculation is triggered, and the route calculation error flag in the error status register is set to 1. The routing switching module supports three working modes: normal mode, link fault-tolerant mode, and router fault-tolerant mode. The normal mode is triggered when the flag bit of the error status register is 1, and the routing algorithm follows the original scheme without any additional adjustments. The link fault-tolerant mode is triggered when there is only a hard link error, and the routing algorithm is adjusted to bypass the faulty link by calculating the shortest path to avoid the faulty link, thus ensuring data transmission efficiency. The fault-tolerant mode of a router is triggered by a hard error in the router. The routing algorithm is adjusted to bypass the faulty router across the entire network, marking it as unavailable. All transmission paths avoid this router to prevent the fault from spreading.

9. The on-chip network full error type fault tolerance optimization method based on redundant transmission according to claim 6, characterized in that, Soft error detection includes soft error encoding and transmission, soft error judgment, retransmission request generation, and retransmission chip processing; When sending soft error coding, the following steps are performed: At the source node, based on the three-modulus redundancy voting mechanism, three copies of the control fields in the header and tail micro-pieces are generated. Each micro-piece and each copy are CRC-encoded and Hamming-encoded respectively. Both the micro-pieces and the copies are appended with CRC check bits and Hamming bits. The data packets are copied to obtain double redundant data packets. A unified identifier is added to the double redundant data packets through data packet synchronization. A heterogeneous routing algorithm is assigned to the double redundant data packets. The double redundant data packets with the added unified identifier are injected in parallel into the on-chip network link. The soft error detection process is as follows: At the target node, soft error trigger detection is performed on the double redundant data packets based on Hamming code, CRC check code and timestamp. Based on three copies, the risk of Hamming code misjudgment is avoided by using a three-to-two selection logic. A retransmission trigger signal is generated based on the detection result and sent to the retransmission request generation module. The retransmission request generation process performs the following operations: After receiving the retransmission trigger signal, the error request bit NACK and the error fragment number are set in the tail fragment of the current data packet, and the data packet with the NACK bit and the error fragment number is sent to the source node through the on-chip network link. After receiving the data packet, the source node stores the error fragment number in the retransmission queue. The NACK bit indicates a retransmission request, and the number of bits in the error fragment number is determined according to the number of error fragments and is used to identify the position of the error fragment in the data packet. The retransmission fragment processing is performed as follows: The erroneous fragment sequence number is retrieved from the retransmission queue of the source node, and the corresponding fragment is extracted from the local cache. The extracted fragment is then CRC-encoded and Hamming-encoded to obtain the retransmission fragment. A retransmission flag R_FLAG is appended to the retransmission fragment, and R_FLAG is set to 1. The fragment is then sent to the target node via the original data channel with a higher priority than ordinary fragments. When the target node detects R_FLAG = 1, it prioritizes the retransmission fragment, replaces the original erroneous fragment, updates the data packet after CRC verification, and calculates the retransmission count for each retransmission fragment. If the retransmission count reaches a predetermined value and verification still fails, upper-layer protocol processing is triggered.

10. The on-chip network full error type fault tolerance optimization method based on redundant transmission according to claim 6, characterized in that, Data packet synchronization includes synchronization identifier generation, matching logic, and synchronization caching; During synchronization identifier generation, a unified identifier is assigned to provide a basis for matching the two redundant data packets. The identifier field format includes an 8-bit timestamp TS and a 2-bit redundancy identifier RID. Two redundant packets from the same data source share the same timestamp TS. The timestamp TS is incremented by 1 for each set of redundant packets sent, and the initial value of the timestamp TS is 0. The redundancy identifier RID is used to distinguish the type of redundant packets: 00 = XY routing packet, 01 = YX routing packet, and 10 = retransmission packet. The generation logic is as follows: before sending data packets, the source node NA assigns the same timestamp TS to the two redundant packets and automatically sets the redundancy identifier RID according to the routing algorithm. The timestamp counter is cleared when the system is reset, and is automatically incremented by 1 for each set of redundant packets sent. After overflowing, it is reused cyclically. The synchronization cache performs the following operations: It temporarily stores redundant data packets to be matched, supports comparison of two redundant data packets, and the cache structure stores only two redundant data packets. Each cache entry contains an 8-bit timestamp TS, a 2-bit redundancy identifier RID, a data packet pointer, and a 1-bit valid bit. The data packet pointer points to the data packet storage address of the original NA receiver, and the valid bit marks whether the cache entry is valid. The writing logic is as follows: After the source node receives the header micro-piece, it extracts the timestamp TS and the redundancy identifier RID. If there is no valid entry with the same timestamp TS in the cache, it writes the timestamp TS, the redundancy identifier RID, and the data packet pointer of the current packet into an empty cache entry and sets the valid bit to 1. If the cache is full, the earliest written item will be replaced first to ensure efficient use of cache resources; The matching logic performs the following operations: Through identifier matching and timeout handling, redundant packets are correctly filtered and output. The matching process is as follows: After a new data packet is written to the buffer, the buffer entries are traversed to find two data packets with different timestamps (TS) and redundancy identifiers (RID); after a matching pair is found, the original CRC check logic is called for comparison, and the data packet with the correct CRC is selected and output to the IP core. If both data packets are correct, the data packet that arrives first is selected; after output, the corresponding two entries in the buffer are cleared. In terms of timeout handling, a timeout counter is set for each buffer entry. The initial value is the dynamic timeout time. The counter is decremented by 1 every cycle. If no matching packet is found when the timeout reaches 0, a lightweight retransmission is triggered, and the buffer entry is cleared.

Images