Distributed TSN traffic scheduling and hardware acceleration method

Abstract

The invention relates to a distributed TSN traffic scheduling and hardware acceleration method. The method comprises the steps that each TSN node comprises a PS module constructed based on an ARM and a PL module constructed based on an FPGA; the PS module operates an IEEE 802.1 AS protocol according to the synchronization frames sent by the other TSN nodes to perform local clock synchronization; the configuration frame is sent to a neighbor TSN node through an LLDP protocol in the PL module, and a local information resource library is constructed in the PS module according to the configuration frame sent by the neighbor TSN node; each TSN node performs state feature extraction on the processing condition of the queue to be processed, and performs performance analysis on the extracted state features through a PS module; a GCL gating list is generated in a reinforcement learning mode according to the local information resource library and the performance analysis result, and data in the queue to be processed are processed according to the GCL gating list in a PL module of the TSN node. According to the invention, the reliability, the dynamic adaptability and the expansibility of the TSN network can be greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of industrial communication network technology, specifically relating to a distributed TSN traffic scheduling and hardware acceleration method. Background Technology

[0002] With the rapid development of industrial automation, vehicle networks, and other fields, the underlying communication networks need to meet stringent requirements for deterministic latency, high reliability, and dynamic adaptability. Time-Sensitive Networking (TSN), as an Ethernet real-time communication standard developed by the IEEE 802.1 TSN working group, provides crucial support for real-time communication through time synchronization, traffic shaping, and scheduling mechanisms. Among them, the time-aware shaper defined in the IEEE 802.1 Qbv protocol, which uses a periodic gating configuration list (GCL) to control the opening and closing of the switch's egress queue, allocates dedicated transmission time slots for time-triggered (TT) traffic and is the core technology for achieving conflict-free transmission of TT traffic.

[0003] Most current mainstream TSN scheduling schemes based on IEEE 802.1Qbv adopt a centralized architecture, relying on a central controller to collect network topology, traffic information and timing constraints, generate a globally conflict-free GCL by solving complex combinatorial optimization problems, and then distribute it to each switch node. Each node only executes the static scheduling policy.

[0004] However, centralized solutions have significant drawbacks in practical applications: First, they have a high risk of single-point failures; a failure of the central controller or a link interruption can paralyze the entire network scheduling, failing to meet the high reliability requirements of industrial and vehicle scenarios. Second, static configuration lacks flexibility; once the GCL is generated, it is executed in a fixed manner. When the network topology changes or traffic fluctuates, information needs to be collected again and optimization problems solved, resulting in delayed scheduling updates. Third, they lack dynamic adaptability; in dynamic scenarios such as the start-up and shutdown of industrial equipment and changes in vehicle road conditions, centralized recalculation is costly and time-consuming, making it difficult to respond quickly. Fourth, they have poor scalability on a large scale; the growth in the number of nodes and traffic will exponentially increase the information processing and computing pressure on the central controller, reducing scheduling efficiency and accuracy. Summary of the Invention

[0005] To address the above problems, this invention provides a distributed TSN traffic scheduling and hardware acceleration method, comprising:

[0006] S1: Construct a distributed scheduling system based on an ARM+FPGA heterogeneous computing platform. The distributed scheduling system includes: multiple TSN nodes, each TSN node including a PS module built on ARM and a PL module built on FPGA, and the PS module and PL module communicate with each other; each TSN node interacts with other TSN nodes and external devices through the PL module.

[0007] S2: Each TSN node generates a synchronization frame through the PS module, forwards it to the other TSN nodes through the PL module, and performs local clock synchronization by running the IEEE 802.1AS protocol in the PS module based on the synchronization frames sent by the other TSN nodes.

[0008] S3: Each TSN node generates a configuration frame in the PS module based on local information resources, and sends it to its neighboring TSN nodes in the PL module via the LLDP protocol. It also builds a local information resource library in the PS module based on the configuration frames sent by its neighboring TSN nodes.

[0009] S4: Each TSN node receives data frames sent by other TSN nodes and external devices through the PL module and puts them into the processing queue. It also extracts the status features of the processing queue and performs performance analysis on the extracted status features through the PS module to obtain the performance analysis results.

[0010] S5: The PS module in the TSN node generates a GCL gating list using reinforcement learning based on the local information resource library and performance analysis results. The PL module in the TSN node processes the data in the queue to be processed based on the GCL gating list.

[0011] Another aspect of the present invention provides a distributed TSN traffic scheduling and hardware acceleration system, the system including a memory and a processor; the memory is used to store an application program; the processor is used to run the application program and execute the distributed TSN traffic scheduling and hardware acceleration method.

[0012] Another aspect of the present invention provides a computer storage medium storing a remote monitoring program, which, when executed by a processor, implements the aforementioned distributed TSN traffic scheduling and hardware acceleration method.

[0013] The present invention has at least the following beneficial effects:

[0014] This invention constructs a distributed scheduling system based on an ARM+FPGA heterogeneous computing platform. Each TSN node uses the PS module to achieve local clock synchronization (running the IEEE 802.1AS protocol), build a local information resource library (interacting with neighboring nodes to configure frames based on the LLDP protocol), and dynamically generate the GCL gating list using reinforcement learning. Simultaneously, the PL module accelerates state feature extraction, data frame processing, and gating execution, enabling each TSN node to have autonomous decision-making and neighborhood coordination capabilities. This avoids the single point of failure risks of centralized architectures and allows for real-time adaptation to network topology changes and traffic load fluctuations through reinforcement learning, rapidly updating the GCL gating list. Furthermore, the ARM+FPGA hardware-software co-design significantly accelerates the convergence speed of distributed algorithms and improves scheduling real-time performance while effectively reducing hardware resource consumption. This provides high-precision deterministic latency guarantees for complex scenarios such as industrial automation and automotive networks, greatly improving the reliability, dynamic adaptability, and scalability of TSN networks. Attached Figure Description

[0015] Figure 1 Overall structural diagram of the TSN switch designed for this invention;

[0016] Figure 2 This is a flowchart of the distributed scheduling scheme of the present invention. Detailed Implementation

[0017] The embodiments of the present invention will be illustrated below through specific examples, providing a clear and complete description of the technical solution. The present invention can also be implemented and applied through different specific embodiments, and various details can be based on different viewpoints and applications. All other embodiments obtained based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0018] Please see Figure 1 and Figure 2 One aspect of the present invention provides a distributed TSN traffic scheduling and hardware acceleration method, comprising:

[0019] S1: Construct a distributed scheduling system based on an ARM+FPGA heterogeneous computing platform. The distributed scheduling system includes: multiple TSN nodes, each TSN node including a PS module built on ARM and a PL module built on FPGA, and the PS module and PL module communicate with each other; each TSN node interacts with other TSN nodes and external devices through the PL module.

[0020] S2: Each TSN node generates a synchronization frame through the PS module, forwards it to the other TSN nodes through the PL module, and performs local clock synchronization by running the IEEE 802.1AS protocol in the PS module based on the synchronization frames sent by the other TSN nodes.

[0021] S3: Each TSN node generates a configuration frame in the PS module based on local information resources, and sends it to its neighboring TSN nodes in the PL module via the LLDP protocol. It also builds a local information resource library in the PS module based on the configuration frames sent by its neighboring TSN nodes.

[0022] S4: Each TSN node receives data frames sent by other TSN nodes and external devices through the PL module and puts them into the processing queue. It also extracts the status features of the processing queue and performs performance analysis on the extracted status features through the PS module to obtain the performance analysis results.

[0023] S5: The PS module in the TSN node generates a GCL gating list using reinforcement learning based on the local information resource library and performance analysis results. The PL module in the TSN node processes the data in the queue to be processed based on the GCL gating list.

[0024] In this embodiment, the PS module of the TSN node is equipped with a distributed decision service module, a local information resource library, a performance monitoring and analysis module, and a time state synchronization machine; the PL module of the TSN node is equipped with an exchange matrix, a queue & gating, a state feature extraction module, a timestamp, a MAC parsing module, a local clock, and a device interface.

[0025] In this embodiment, each TSN node adopts an ARM+FPGA heterogeneous architecture, including: a PS module (e.g., based on ARM Cortex-A53), responsible for running an embedded Linux operating system, deploying functions such as a distributed decision service module, a local information resource library, a performance monitoring and analysis module, and a time state synchronization machine, interacting with the PL module through an AXI series bus interface; and a PL module (e.g., FPGA programmable logic, implementing high-speed parallel processing), deploying functions such as a switching matrix (supporting multi-path concurrent data forwarding), queues & gating (setting multiple priority queues corresponding to different priorities of industrial traffic, with synchronization frames and configuration frames having the highest priority), a state feature extraction module (obtaining relevant state feature information from queues & gating and timestamps), a timestamp (recording the transmission and reception times of time frames, configuration frames, and data frames), a MAC parsing module (parsing Ethernet frame header information), and a local clock (used as a clock reference for the entire TSN node). The system includes a device interface (supporting connection to external devices / other TSN nodes); the distributed scheduling system contains multiple TSN nodes, each covering multiple external devices (e.g., temperature sensors, motor controllers, robotic arm actuators, etc.). Each TSN node connects to the other TSN nodes and external devices through the device interface of the PL module; after the external device (e.g., temperature sensor) collects data, it sends data frames via Ethernet, which are then transmitted to the MAC parsing module of the PL module through the device interface of the TSN node (e.g., RJ45 interface), parsing out the device identifier, priority, and other information in the frame header; the switching matrix of the PL module forwards the data frame to the corresponding priority queue according to the MAC parsing result, and at the same time, the timestamper adds a receiving timestamp to the data frame; the PL module uploads the status information of the data frame (queue number, receiving timestamp, frame length, etc.) to the PS module through the AXI series bus interface and the status feature extraction module for use by the subsequent performance monitoring and analysis module.

[0026] Preferably, the local clock synchronization using the IEEE 802.1AS protocol includes: synchronization frame transmission and synchronization frame reception; synchronization frame transmission includes: the time state synchronizer generating a synchronization frame, and the synchronization frame being transmitted to the remaining TSN nodes sequentially through the switching matrix, queue & gating, timestamp, TX interface of the MAC parsing module and device interface.

[0027] Synchronization frame reception includes: synchronization frames sent by other devices are sequentially sent to the time status synchronizer via the device interface, the RX interface of the MAC parsing module, and the timestampr. The time status synchronizer runs the IEEE 802.1AS protocol to generate clock update information based on the synchronization frames sent by the other TSN nodes and sends it to the local clock. The local clock updates its clock based on the clock update information to complete local clock synchronization.

[0028] In this embodiment, the core of step S2 is that each TSN node generates a synchronization frame through the PS module, forwards it through the PL module, and then runs the IEEE 802.1AS protocol through the PS module to achieve local clock synchronization, ultimately enabling all nodes in the network to establish a unified time base. During this process, the PS module of each TSN node generates a synchronization frame and dynamically elects a master clock by comparing the clock precision and priority of each TSN node. Taking three TSN nodes A, B, and C as an example: Assume that node A is elected as the "best master clock"; in the PS module of node A, the time state synchronizer generates a synchronization frame. The frame structure includes: master clock identifier (node ​​A device ID: TSN-A-001), master clock current timestamp (e.g., T1=1000000000ns, i.e., 1 second, generated by the local clock of the PS module); synchronization frame sequence number (Seq-001, used for deduplication at the receiving end); after the synchronization frame is generated, the PS module transmits the data through the AXI series bus interface. The synchronization frame is sent to the PL module. After receiving the synchronization frame, the PL module at node A transmits it sequentially through the switching matrix, queue & gating (the synchronization frame is placed in the highest priority queue), timestamp (to add a "send timestamp" (T2=1000000002ns) to the synchronization frame, recording the precise time the synchronization frame leaves the PL module), MAC parsing module (to add an Ethernet frame header, with the destination MAC address being the MAC address of nodes B and C) TX interface and device interface to the other TSN nodes (nodes B and C). Taking node B receiving the synchronization frame from node A as an example, node B then transmits it through the device interface, the RX interface of the MAC parsing module (to confirm the master clock identifier and sequence number are correct), and the timestamp (to add a "receive timestamp" (T3=1000000504ns) to the time status synchronizer. After receiving the data uploaded by the PL, the time status synchronizer of node B's PS module runs IEEE 802.The core algorithm of the 1AS protocol: Extracting key timestamps: A node's master clock transmission time T1 (1000000000ns), A node's PL transmission time T2 (1000000002ns), B node's PL reception time T3 (1000000504ns); Calculating the one-way delay of the link: Delay = [(T3-T2) - (B node's local clock current time - T1)] / 2 = -10ns (the negative deviation originates from the node clock error, and the absolute value of 10ns is taken as the actual one-way delay); Calculating the clock deviation between B node and the master clock (A): Offset = T1 + Delay - the corresponding time of B node's local clock at time T3 = 20ns. The result shows that B node's local clock is 20ns faster than A node's, and needs to be slowed down by 20ns; B node's PS module generates... A "clock calibration command" (content: slow down the local clock of the PL module by 20ns) is generated and sent to the PL module via the AXI series bus interface. Upon receiving the command, the PL module adjusts its local clock from "1000000522ns" to "1000000502ns," reducing the clock deviation from node A to a preset error range, such as within 2ns, typically ≤10ns. Node A continuously generates synchronization frames at 10ms intervals, and nodes B and C repeat the "receive-calculate-calibrate" process. After multiple iterations, the local clock deviations of the three TSN nodes A, B, and C are all less than the set error, achieving full network clock synchronization. Through the above example, those skilled in the art should understand the entire clock synchronization process of this application and be able to perform practical operations based on the above description.

[0029] Preferably, the construction of the local information resource database includes: sending configuration frames and receiving configuration frames;

[0030] Configuration frame transmission: The TSN node generates a configuration frame containing its own information in the distributed decision service module, and transmits it to the neighboring TSN node periodically through the exchange matrix, queue & gating, timestamp, MAC parsing module's TX interface and device interface based on the LLDP protocol.

[0031] Configuration frame reception: The TSN node receives the configuration frame sent by the neighboring TSN node and transmits it to the local information resource database in sequence through the device interface, the RX interface of the MAC resolution module, the timestampr, and the distributed decision service module; wherein, the configuration frame includes: the device identifier of the TSN node, the MAC address forwarding table, the physical link bandwidth, and the flow object information.

[0032] In this embodiment, each TSN node generates a configuration frame containing local information through the PS module. The PL module sends the configuration frame to neighboring nodes based on the LLDP protocol. Then, based on the configuration frames fed back by the neighbors, the PS module builds / updates the local information resource library. The following description uses the three TSN nodes A, B, and C as an example to illustrate the construction of the local information resource library: Taking node A as an example, the PS module generates a "configuration frame" that conforms to the LLDP protocol format based on its own hardware configuration and the traffic parameters of the access device. The core content of the configuration frame is shown in Table 1 below:

[0033] Table 1 Configuration Frame

[0034]

[0035] The flow object information in Table 1 can be represented as shown in Table 2:

[0036] Table 2 Stream Object Information

[0037]

[0038] After the PS module of node A generates a configuration frame, it sends it to the PL module of node A via the AXI series bus interface. Upon receiving the configuration frame, the PL module of node A sequentially transmits it to the neighboring TSN nodes (B and C) through the following methods: a switching matrix (routing the configuration frame to "port 1 connecting node B" and "port 2 connecting node C"), queue & gating (the configuration frame is assigned to a high-priority queue), a timestamp (adding a "timestamp of node A's PL sending" to the configuration frame (e.g., T_send=1000000005ns, recording the precise time the configuration frame leaves the PL module of node A), the TX interface of the MAC parsing module (adding two headers to the configuration frame: an LLDP protocol header and an Ethernet frame header), and the device interface (sending the encapsulated LLDP configuration frame to neighboring nodes, with a transmission period following the LLDP protocol's standard value (30 seconds / time, ensuring real-time information updates)). Taking node B receiving the configuration frame from node A as an example, it sequentially transmits it through the device interface (receiving the configuration frame from node A). The configuration frame is generated by the RX interface of the MAC parsing module (extracting core information from the configuration frame, such as device identifier, MAC forwarding table, and flow object information), the timestamp (adding a "PL reception timestamp" to the configuration frame), and the distributed decision service module, and transmitted to the local information resource library. Similarly, after receiving the configuration frame from node A, node C executes the same process. At the same time, nodes B and C also generate their own LLDP configuration frames and send them to node A and each other through the PL module, forming a two-way information exchange. After receiving the neighbor's configuration frame, each node's PS module builds a local resource library. If a new node connects to node A, node D will automatically send an LLDP configuration frame. After the PS module of node A detects the new neighbor, it immediately adds the information of node D to the local resource library without manual configuration. The PS module checks the timestamp of the neighbor's configuration frame every 30 seconds. If it does not receive a new configuration frame from a neighbor (such as node B) for more than 60 seconds, it marks the neighbor's link as "suspected failure" and makes a note in the resource library.

[0039] Preferably, the generation of the gating list includes: data frames sent by external devices and / or other TSN nodes are transmitted sequentially through the device interface, the RX interface of the MAC parsing module, the timestamp, and the switching matrix to the queue and gating queue to be processed; the state feature extraction module monitors the state feature information of the queue and gating and the timestamp on the processing status of data frames in the queue to be processed; the performance monitoring and analysis module performs performance analysis on the state feature information monitored by the state feature extraction module and transmits the performance analysis results to the distributed decision service module; the distributed decision service module generates the GCL gating list using reinforcement learning based on the local information resource library and the performance analysis results of the performance monitoring and analysis module; the queue and gating release the data frames in the queue to be processed according to the GCL gating list and transmit them sequentially through the timestamp, the TX interface of the MAC parsing module, and the device interface to the external devices and / or other TSN nodes.

[0040] Preferably, the step of generating the GCL gating list using reinforcement learning based on the local information resource database and the performance analysis results from the performance monitoring and analysis module includes:

[0041] Define the state space S:

[0042]

[0043] in, , Indicates priority as The bandwidth utilization rate of the pending queue within the most recent preset time period; Indicates priority as The instantaneous depth of the queue to be processed; Indicates the number of priority queues; This indicates the remaining time until the next GCL entry switch; This represents the physical link bandwidth of the TSN node; , Indicates the first The processing latency of each data stream; Indicates the number of data streams;

[0044] Define action space A:

[0045]

[0046]

[0047] in, Indicates the first Action information for each data stream; Indicates the first The phase offset of the start time of the time-triggered flow window for each data stream; Indicates the first The amount of time-triggered flow window duration adjustment for each data stream;

[0048] Define the reward function R:

[0049]

[0050]

[0051]

[0052] in, These are the weighting coefficients; Indicates variance; Indicates the first The end-to-end latency of a data stream over the most recent N periods; This indicates a jitter penalty item; This indicates the set constraint / penalty item; Indicates bandwidth utilization; Indicates priority as The weight parameters of the queue to be processed; This indicates the set basic reward;

[0053] S51: In each gating update cycle, construct the target network and the value network based on the Dueling architecture; input the observed environmental state into the value network to calculate the value of each action combination in the action space, and calculate whether the conflict-free constraint and the delay constraint are satisfied after each data stream executes the corresponding action in the action combination. If both are satisfied, use the action combination with the highest value as the final execution action to construct the GCL gating list.

[0054] S53: Calculate the reward function based on the final execution action selected for each data stream, and update the parameters of the value network using the classic temporal difference loss function of DQN according to the reward function; update the parameters of the target network using the parameters of the value network at each preset number of iterations.

[0055] Preferably, the loss function is expressed as follows:

[0056]

[0057] Where L represents the loss function, This indicates that the final action to be performed is selected under the current environment state S. The reward function, Indicates the discount factor; These represent the parameters of the target network. Indicates the execution of an action The next environmental state; Indicates any action; Indicates taking The maximum value; Parameters representing the value network;

[0058] In this embodiment, steps S4 and S5 will still be described in detail using the three TSN nodes A, B and C mentioned above. The core of step S4 is that each TSN node enqueues the data frames received by the PL module, extracts state features, and performs performance analysis by the PS module. The core of step S5 is that the PS module generates a GCL gating list based on reinforcement learning, and the PL module processes the queue data to be processed according to the GCL. Together, they realize distributed TSN traffic management of "state awareness-dynamic scheduling".

[0059] Taking node A as an example again, steps S4 and S5 of this application will be further explained. First, a local information resource database is constructed through step S3, which stores the link bandwidth and flow object information of itself and nodes B / C. The temperature sensor sends data frames at a period of 10ms. The data frames pass through the device interface (receiving data frames), the timestampr (adding a "receive timestamp" to the data frame, such as T_rx=1000010000ns), the RX interface of the MAC parsing module (verifying the "flow identifier" and "priority" of the data frame), and the exchange matrix (based on "priority"). The data frame is routed to the corresponding priority queue and transmitted to the queue and gating queue (at which point there are already 2 frames of data to be processed in the queue). The PL module's status feature extraction module monitors the "priority queue" and link status in real time and extracts the timestamp information of the data frame (mainly including: the percentage of data transmitted in the priority queue within a 100μs window, real-time counting by the queue and gating module, and timestamps based on the PL module, etc.). The performance analysis module generates performance analysis results based on the extracted features, mainly including: the bandwidth utilization rate of priority p within the preset time window; the priority is... The instantaneous depth of the queue to be processed; the remaining time until the next GCL entry switch; the... Data stream processing latency ; Indicates the timestamp of its record The sending time of each data stream; The record is the first The data stream reception time; in the distributed decision service module, according to the defined state space S, a "state feature vector" is generated, and the reinforcement learning logic is executed. First, the action space is defined. Deep reinforcement learning models employ a dueling architecture to construct the target network and the value network. The dueling architecture primarily includes: shared parameters. Feature extraction branch, and model parameters are The value function branches and model parameters are The dominant function branch; where shared parameters The feature extraction branch generates shared features based on the state space parameters S. The value function and advantage function generate corresponding value values ​​and advantage values ​​based on the shared features, respectively, and finally obtain the final value of selecting each action under environment S. The formula is expressed as follows:

[0060]

[0061] in, This represents the final value of choosing action a in state s; Represents the value function; Represents the dominance function; Represents an action index, referring to any action in the action space; This represents the total number of actions in the action space. Since the minimum time slot of an FPGA has units, the actions in the action space are discrete and have a finite number.

[0062] The value function can be used to calculate the value of each action combination in the current environment; conflict detection is performed on each action combination (i.e., whether each data stream satisfies the no-conflict constraint and the time delay constraint after executing the corresponding action; if there is no conflict, the action combination with the highest value is used as the final action to construct the GCL gating list); after execution, the reward value is calculated according to the defined reward function, and the parameters of the value network are updated according to the classic time difference loss function of DQN; at each preset number of iterations, the parameters of the target network are updated using the parameters of the value network.

[0063] In this embodiment, conflict detection mainly includes conflict constraint and delay constraint detection, based on two data streams. and For example, data stream After adjustment ; ; ; in, and The first data stream One transmission cycle; Represents data stream The transmission interval; Represents data stream The transmission interval; Represents the empty set; Represents data stream Adjusted start time; Represents data stream Adjusted duration; Represents data stream Adjusted start time; Represents data stream Adjusted duration; delay constraint detection, in data stream For example, data stream Processing latency ; ; Represents data stream Queuing delay; Represents data stream Fixed processing delay;

[0064] The delay constraints include the following:

[0065]

[0066] in, Represents data stream Processing delay at switch s; Represents data stream In the link Transmission delay; Represents data stream The maximum end-to-end delay threshold;

[0067]

[0068] in, Represents data stream Processing latency of the already passed TSN switch nodes; Represents data stream Minimum processing latency at untouched TSN switch nodes; Represents data stream In the link The minimum link transmission delay;

[0069]

[0070] in, Represents data stream At the last switch Latest transmission offset; Represents data stream Maximum frame length; Indicates port bandwidth; Represents data stream End-point link transmission delay;

[0071]

[0072] in, Represents data stream The average end-to-end delay over the most recent N periods; Represents data stream The variance of end-to-end delay over the most recent N cycles.

[0073] Another aspect of the present invention provides a distributed TSN traffic scheduling and hardware acceleration system, the system including a memory and a processor; the memory is used to store an application program; the processor is used to run the application program and execute the distributed TSN traffic scheduling and hardware acceleration method.

[0074] Another aspect of the present invention provides a computer storage medium storing a remote monitoring program, which, when executed by a processor, implements the aforementioned distributed TSN traffic scheduling and hardware acceleration method.

[0075] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0076] This invention constructs a distributed scheduling system based on an ARM+FPGA heterogeneous computing platform. Each TSN node uses the PS module to achieve local clock synchronization (running the IEEE 802.1AS protocol), build a local information resource library (interacting with neighboring nodes to configure frames based on the LLDP protocol), and dynamically generate the GCL gating list using reinforcement learning. Simultaneously, the PL module accelerates state feature extraction, data frame processing, and gating execution, enabling each TSN node to have autonomous decision-making and neighborhood coordination capabilities. This avoids the single point of failure risks of centralized architectures and allows for real-time adaptation to network topology changes and traffic load fluctuations through reinforcement learning, rapidly updating the GCL gating list. Furthermore, the ARM+FPGA hardware-software co-design significantly accelerates the convergence speed of distributed algorithms and improves scheduling real-time performance while effectively reducing hardware resource consumption. This provides high-precision deterministic latency guarantees for complex scenarios such as industrial automation and automotive networks, greatly improving the reliability, dynamic adaptability, and scalability of TSN networks.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention. Based on the detailed description given, those skilled in the art should understand that various modifications or equivalent substitutions can be made on the basis of the technical solutions of the present invention. As long as they do not depart from the spirit and scope of the solution, they should all be covered within the scope of the claims of the present invention.

Claims

1. A distributed TSN traffic scheduling and hardware acceleration method, characterized in that, Including the following steps: S1: Construct a distributed scheduling system based on an ARM+FPGA heterogeneous computing platform. The distributed scheduling system includes: multiple TSN nodes, each TSN node including a PS module built on ARM and a PL module built on FPGA, and the PS module and PL module communicate with each other; each TSN node interacts with other TSN nodes and external devices through the PL module. S2: Each TSN node generates a synchronization frame through the PS module, forwards it to the other TSN nodes through the PL module, and performs local clock synchronization by running the IEEE 802.1AS protocol in the PS module based on the synchronization frames sent by the other TSN nodes. S3: Each TSN node generates a configuration frame in the PS module based on local information resources, and sends it to its neighboring TSN nodes in the PL module via the LLDP protocol. It also builds a local information resource library in the PS module based on the configuration frames sent by its neighboring TSN nodes. S4: Each TSN node receives data frames sent by other TSN nodes and external devices through the PL module and puts them into the processing queue. It also extracts the status features of the processing queue and performs performance analysis on the extracted status features through the PS module to obtain the performance analysis results. S5: The PS module in the TSN node generates a GCL gating list using reinforcement learning based on the local information resource library and performance analysis results. The PL module in the TSN node processes the data in the queue to be processed based on the GCL gating list.

2. The distributed TSN traffic scheduling and hardware acceleration method according to claim 1, characterized in that, The PS module of the TSN node is equipped with a distributed decision service module, a local information resource database, a performance monitoring and analysis module, and a time state synchronization machine; the PL module of the TSN node is equipped with an exchange matrix, queue & gating, state feature extraction module, timestamp, MAC parsing module, local clock, and device interface.

3. The distributed TSN traffic scheduling and hardware acceleration method according to claim 2, characterized in that, The local clock synchronization using the IEEE 802.1AS protocol includes: synchronization frame transmission and synchronization frame reception; synchronization frame transmission includes: the time state synchronizer generating a synchronization frame, and the synchronization frame being transmitted to the remaining TSN nodes sequentially through the switching matrix, queue & gating, timestamp, TX interface of the MAC parsing module and device interface. Synchronization frame reception includes: synchronization frames sent by other devices are sequentially sent to the time status synchronizer via the device interface, the RX interface of the MAC parsing module, and the timestampr. The time status synchronizer runs the IEEE 802.1AS protocol to generate clock update information based on the synchronization frames sent by the other TSN nodes and sends it to the local clock. The local clock updates its clock based on the clock update information to complete local clock synchronization.

4. The distributed TSN traffic scheduling and hardware acceleration method according to claim 2, characterized in that, The construction of the local information resource library includes: sending configuration frames and receiving configuration frames; Configuration frame transmission: The TSN node generates a configuration frame containing its own information in the distributed decision service module, and transmits it to the neighboring TSN node periodically through the exchange matrix, queue & gating, timestamp, MAC parsing module's TX interface and device interface based on the LLDP protocol. Configuration frame reception: The TSN node receives the configuration frame sent by the neighboring TSN node and transmits it to the local information resource database in sequence through the device interface, the RX interface of the MAC parsing module, the timestampr, and the distributed decision service module.

5. A distributed TSN traffic scheduling and hardware acceleration method according to claim 2, characterized in that, The configuration frame includes: the device identifier of the TSN node, the MAC address forwarding table, the physical link bandwidth, and the flow object information.

6. The distributed TSN traffic scheduling and hardware acceleration method according to claim 2, characterized in that, The generation of the gating list includes: data frames sent by external devices and / or other TSN nodes are transmitted sequentially through the device interface, the RX interface of the MAC parsing module, the timestamp, and the switching matrix to the queue and gating queue to be processed; the state feature extraction module monitors the state feature information of the queue and gating and the timestamp on the processing status of data frames in the queue to be processed; the performance monitoring and analysis module performs performance analysis on the state feature information monitored by the state feature extraction module and transmits the performance analysis results to the distributed decision service module; the distributed decision service module generates the GCL gating list using reinforcement learning based on the local information resource library and the performance analysis results of the performance monitoring and analysis module; the queue and gating release the data frames in the queue to be processed according to the GCL gating list and transmit them sequentially through the timestamp, the TX interface of the MAC parsing module, and the device interface to the external devices and / or other TSN nodes.

7. A distributed TSN traffic scheduling and hardware acceleration method according to claim 6, characterized in that, The step of generating the GCL gating list using reinforcement learning based on the local information resource database and the performance analysis results from the performance monitoring and analysis module includes: Define the state space S: in, , Indicates priority as The bandwidth utilization rate of the pending queue within the most recent preset time period; Indicates priority as The instantaneous depth of the queue to be processed; Indicates the number of priority queues; This indicates the remaining time until the next GCL entry switch; This represents the physical link bandwidth of the TSN node; , Indicates the first The processing latency of each data stream; Indicates the number of data streams; Define action space A: in, Indicates the first Action information for each data stream; Indicates the first The phase offset of the start time of the time-triggered flow window for each data stream; Indicates the first The amount of time-triggered flow window duration adjustment for each data stream; Define the reward function R: in, These are the weighting coefficients; Indicates variance; Indicates the first The end-to-end latency of a data stream over the most recent N periods; This indicates a jitter penalty item; This indicates the set constraint / penalty item; Indicates bandwidth utilization; Indicates priority as The weight parameters of the queue to be processed; This indicates the set basic reward; S51: In each gating update cycle, construct the target network and the value network based on the Dueling architecture; input the observed environmental state into the value network to calculate the value of each action combination in the action space, and calculate whether the conflict-free constraint and the delay constraint are satisfied after each data stream executes the corresponding action in the action combination. If both are satisfied, use the action combination with the highest value as the final execution action to construct the GCL gating list. S53: Calculate the reward function based on the final execution action selected for each data stream, and update the parameters of the value network using the classic temporal difference loss function of DQN according to the reward function; update the parameters of the target network using the parameters of the value network at each preset number of iterations.

8. A distributed TSN traffic scheduling and hardware acceleration system, characterized in that, The system includes a memory and a processor; the memory is used to store an application program; the processor is used to run the application program and execute a distributed TSN traffic scheduling and hardware acceleration method as described in any one of claims 1 to 7.

9. A computer storage medium, characterized in that, The computer storage medium stores a remote monitoring program, which, when executed by the processor, implements a distributed TSN traffic scheduling and hardware acceleration method as described in any one of claims 1 to 7.

Images