Analog video signal encryption and decryption system

Abstract

The invention relates to the technical field of signal transmission, in particular to an analog video signal encryption and decryption system, which comprises an encryption key generation module used for generating a unique sub-key; the encryption recombination output module is used for executing image signal encryption operation, recombining the signals and converting and outputting the signals; the decrypted signal receiving and separating module is used for receiving the encrypted signal and separating the synchronous signal from the encrypted image signal; the decryption block matching module is used for completing block matching according to an encryption end rule; the decryption key synchronization module is used for generating a synchronization sub-key according to the analyzed number; and the decryption recombination output module is used for executing reverse decryption operation, recombining the signal, converting the signal into a standard video and outputting the standard video. According to the method, breakthrough is realized in the aspects of real-time performance, computing power adaptation, encryption strength and compatibility.

Description

Technical Field

[0001] This invention relates to the field of signal transmission technology, and more specifically to an analog video signal encryption and decryption system. Background Technology

[0002] Analog video requires "intra-frame real-time encryption." The processing time for a single frame in PAL is ≤40ms. The encryption granularity (line encryption / pixel block encryption / full-frame encryption) needs to be adapted to real-time requirements: ① If "pixel block encryption" is used, such as 8×8 pixel blocks, the sampled streaming data needs to be grouped first. The grouping process increases processing latency, and the group boundaries are easy to become weak points for cracking; ② If "line encryption" is used, the encryption strength is insufficient, and single-line data is easy to be cracked by brute force; ③ If "full-frame encryption" is used, the amount of data per frame is too large. Embedded terminals, such as analog cameras, have an MCU main frequency ≤1GHz, which is insufficient for computing power, resulting in frame loss.

[0003] Therefore, if the "streaming characteristics" of analog video are incompatible with the "block processing characteristics" of encryption algorithms, data processing requires additional time costs for "blocking / deblocking". Summary of the Invention

[0004] The purpose of this invention is to provide an analog video signal encryption and decryption system to solve the problems mentioned in the background art.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] An analog video signal encryption and decryption system, including:

[0007] The encrypted signal acquisition and separation module is used to acquire analog video signals and separate synchronization signals from valid image signals;

[0008] The encrypted streaming block module is used to perform unbuffered parallel blocking of valid image signals;

[0009] The encryption key generation module is used to generate unique subkeys;

[0010] The encrypted reconstruction output module is used to perform image signal encryption operations, reconstruct the signal, and convert the output.

[0011] The decryption signal receiving and separating module is used to receive encrypted signals and separate synchronization signals from encrypted image signals;

[0012] The decryption block matching module is used to complete block matching according to the encryption end rules;

[0013] The decryption key synchronization module is used to generate a synchronization subkey based on the parsed number;

[0014] The decryption and reconstruction output module is used to perform reverse decryption operations, reconstruct the signal, and convert it into standard video output.

[0015] Furthermore, the analog video signal is acquired, and the synchronization signal and the effective image signal are separated. Specifically, the acquisition chip is activated to acquire the analog video signal and output discrete digital signals. Based on the timing parameters of the video standard, the horizontal and vertical synchronization signals are extracted by the hardware timing discrimination circuit and separated into a synchronization signal group and an effective image digital signal. The synchronization signal group maintains its original physical characteristics and timing standard and does not participate in the encryption operation. The effective image digital signal directly enters the next level of processing.

[0016] Furthermore, the effective image signal is subjected to unbuffered parallel block segmentation. Specifically, the sampling and block segmentation are performed in parallel mode. The effective image digital signal flows into the block segmentation logic in real time with the sampling, without buffering the entire line or frame of data. The block segmentation window advances along the line direction as new pixels are acquired. There are overlapping areas between adjacent encrypted blocks and no fixed group boundaries. The block segmentation operation is completed synchronously with the sampling.

[0017] Furthermore, the encryption key generation module generates a unique subkey. Specifically, the encryption end pre-stores a fixed root key and generates a dynamic subkey based on the current frame number, line number, and block sequence number using a simplified hash function. Each encryption block corresponds to a unique subkey, and the subkey generation and block division operations are processed in parallel.

[0018] Furthermore, the image signal encryption operation is performed, the signal is recombined and converted for output. Specifically, a key stream matching the encryption block is generated using a dynamic subkey, and pixel-by-pixel XOR encryption is performed, proceeding block by block according to the block completion order. After encryption, the encrypted image signal and synchronization signal are recombined according to the original video format timing, and the recombined digital signal is converted into an analog video signal, which is transmitted through a conventional channel. The signal conforms to traditional specifications and does not require modification of hardware parameters.

[0019] Furthermore, the encrypted signal is received, and the synchronization signal and encrypted image signal are separated. Specifically, the decryption end activates the acquisition chip with the same parameters as the encryption end, receives the transmitted encrypted analog video signal and converts it into a discrete digital signal. Using the same hardware timing discrimination circuit as the encryption end, the horizontal and vertical synchronization signals are extracted according to the video standard timing parameters, and the synchronization signal group used for timing calibration and the encrypted valid image digital signal that enters the subsequent decryption are separated.

[0020] Furthermore, block matching is completed according to the encryption end rules. Specifically, a parallel mode of signal reception and block matching is adopted. The encrypted valid image digital signal flows into the block logic in real time as it is acquired by the decryption end. The block parameters, order and number are completely consistent with those of the encryption end. The block window advances as new pixels are received. Adjacent blocks have overlapping areas and no fixed boundaries. The block operation is completed synchronously with signal reception.

[0021] Furthermore, a synchronization subkey is generated based on the parsed number. Specifically, the decryption end pre-stores the same fixed root key as the encryption end, obtains the frame number, line number, and block sequence number of the received signal through the parsing of the synchronization signal group, and generates a unique dynamic subkey corresponding to the encryption end based on these numbers through a simplified hash function. The subkey generation logic and operation process are completely matched with the encryption end, and the generation operation and block matching are processed in parallel.

[0022] Furthermore, a reverse decryption operation is performed to reconstruct the signal and convert it into a standard video output. Specifically, a corresponding key stream is generated using a synchronous dynamic subkey, and the original valid image digital signal is decrypted pixel by pixel using XOR. The decrypted image signal and the synchronization signal are then reconstructed according to the original video format timing. The reconstructed digital signal is converted into an analog video signal and output to the display device, maintaining the original image characteristics without any abnormalities.

[0023] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the functions of the analog video signal encryption and decryption system described above.

[0024] Compared with existing technologies, this invention has the following advantages: It achieves breakthroughs in real-time performance, computing power adaptability, encryption strength, and compatibility. In terms of real-time performance, the "sampling and block parallel" mode and bufferless streaming processing reduce processing latency caused by data grouping. Based on lightweight algorithms and parallel processing, the PAL single-frame processing time is optimized to meet intra-frame real-time encryption requirements. Regarding computing power adaptability, a simplified version of SM3 hashing and an improved RC4 algorithm are used, reducing the amount of computation per frame and solving the frame loss problem caused by insufficient computing power in embedded terminals. Encryption strength is significantly improved. Dynamic subkeys are generated based on frame number, line number, and block sequence number. Overlapping block processing eliminates weak points at fixed boundaries, increasing the difficulty of cracking compared to line encryption and resisting brute-force and statistical analysis attacks. In terms of compatibility, it adheres to PAL timing and signal characteristics throughout the process. Synchronization signals maintain their original parameters, and recombined signals conform to traditional transmission standards. No modification to existing hardware such as coaxial cables and analog cameras is required, resulting in strong adaptability. Attached Figure Description

[0025] Figure 1 This is a block diagram of the analog video signal encryption and decryption system of the present invention. Detailed Implementation

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] This application discloses an analog video signal encryption and decryption system, such as Figure 1 As shown, it includes:

[0028] The encrypted signal acquisition and separation module is used to acquire analog video signals and separate synchronization signals from valid image signals; the encrypted streaming block module is used to perform unbuffered parallel block segmentation on valid image signals.

[0029] The encryption key generation module is used to generate unique subkeys;

[0030] The encrypted reconstruction output module is used to perform image signal encryption operations, reconstruct the signal, and convert the output.

[0031] The decryption signal receiving and separating module is used to receive encrypted signals and separate synchronization signals from encrypted image signals;

[0032] The decryption block matching module is used to complete block matching according to the encryption end rules;

[0033] The decryption key synchronization module is used to generate a synchronization subkey based on the parsed number;

[0034] The decryption and reconstruction output module is used to perform reverse decryption operations, reconstruct the signal, and convert it into standard video output.

[0035] The process involves acquiring analog video signals and separating the synchronization signal from the valid image signal. Specifically, the ADC chip is activated to perform real-time acquisition of the input PAL analog video signal. The sampling rate is set to 13.5MHz, the quantization bit is 10 bits, and the sampling time per pixel is fixed at 0.074μs. Discrete digital signals are continuously output. Based on the PAL standard timing parameters, each line has a total duration of 64μs, including 12μs of line synchronization pulse and 52μs of valid image signal. Each frame has 2 fields, each field has 287.5 lines, each frame has 575 valid image lines, and each line has 720 valid pixels. The line synchronization signal and field synchronization signal are extracted by the hardware timing discrimination circuit and separated into a synchronization signal group and a valid image digital signal. The synchronization signal group retains its original physical characteristics, with the line synchronization pulse amplitude at -0.3V and the field synchronization pulse amplitude at -0.3V. The timing interval strictly follows the PAL standard and does not participate in encryption calculations. The valid image digital signal directly enters the next level of processing. The entire line separation time is ≤0.8μs.

[0036] Unbuffered parallel block segmentation is performed on the valid image signal. Specifically, sampling and block segmentation are performed in parallel. The valid image digital signal flows into the block segmentation logic in real time along with the ADC sampling. The entire row or frame of data is not buffered, which reduces the processing delay caused by data grouping. The block segmentation parameters are set. The size of the encrypted block is 5×5 pixels. 25 pixels constitute the smallest encrypted unit. The sliding step is 3 pixels. That is, every time 3 new pixels are collected, the block window advances 3 pixels along the row direction. There is a 2×5 pixel overlap area between adjacent encrypted blocks. There is no fixed grouping boundary. The number of blocks for a single row of 720 pixels of image signal is (720-5)÷3+1=239 blocks. The block segmentation operation is completed synchronously with sampling, without additional time consumption.

[0037] The encryption key generation module generates a unique subkey. In practice, the encryption end pre-stores a 128-bit fixed root key. Based on the current frame number, it uses a cyclic count (0-65535), a row number (1-575), a sequential count (1-239), and a row-by-row count. Using a simplified version of the SM3 hash function, the computation time is ≤70 clock cycles to generate a 128-bit dynamic subkey. Each 5×5 encryption block corresponds to a unique subkey. Subkey generation and block division are processed in parallel. The subkey generation time for a single block is ≤0.03μs, without occupying additional processing time.

[0038] The image signal encryption operation is performed, the signal is reconstructed and converted for output. Specifically, in implementation, a keystream generator is initialized using a dynamic subkey as a seed, generating a 25-byte keystream that perfectly matches the 5×5 pixel data volume. Pixel-by-pixel XOR encryption is performed, XORing the 5×5 pixel digital signal with the corresponding keystream byte-by-byte. The time for a single XOR operation is ≤0.01μs / byte, and the total time for a single block encryption is ≤0.3μs. The encryption process proceeds in real-time, block by block, in the order of "block completion → key generation → encryption execution." The time for encrypting a single image signal is ≤239 blocks × 0.3μs / block = 71.7μs. After encryption, the encrypted valid image digital signal is output according to the original PAL timing. The image signal is precisely reassembled from the separated synchronization signal group. The horizontal synchronization pulse is 12μs, followed by a 52μs encrypted effective image signal. The vertical synchronization signal is then inserted at intervals of every 287.5 lines. The reassembly timing error is ≤±0.1μs. The reassembled digital signal is input to the DAC chip with parameters consistent with the ADC, 10-bit quantization, and a 13.5MHz conversion rate. It is converted into a standard analog video signal with an amplitude range of 0-1V and a DAC conversion delay of ≤1.5μs. Finally, the reassembled and converted encrypted analog video signal is transmitted in real time through a coaxial cable or analog wireless channel. The signal physical characteristics conform to the traditional analog video transmission specifications, and there is no need to modify the link impedance or transmission frequency hardware parameters.

[0039] The process involves receiving encrypted signals and separating synchronization signals from encrypted image signals. Specifically, the decryption end activates an ADC chip with parameters identical to those of the encryption end: a 13.5MHz sampling rate and 10-bit quantization. It receives encrypted analog video signals transmitted via coaxial cable or analog wireless channel and converts them into discrete digital signals. Subsequently, using the same hardware timing discrimination circuit as the encryption end, based on PAL standard timing parameters, each line has a total duration of 64μs, including 12μs of line synchronization pulses and 52μs of effective image signals. Each frame has 2 fields, each field has 287.5 lines, each frame has 575 effective image lines, and each line has 720 effective pixels. The line synchronization signal and field synchronization signal are extracted, and the synchronization signal group and the encrypted effective image digital signal are separated. The synchronization signal group is used for timing calibration, while the encrypted effective image digital signal directly enters the subsequent decryption process. The entire line separation process takes ≤0.8μs.

[0040] The block matching is performed according to the encryption end's rules. In practice, a parallel mode of signal reception and block matching is adopted, so that the separated encrypted valid image digital signal flows into the block matching logic in real time along with the signal reception process of the decryption end's ADC chip. The entire line or frame of data is not buffered to eliminate waiting delay. The block matching is strictly followed according to the block matching rules preset by the encryption end. The block matching parameters are set to be completely consistent with those of the encryption end. The size of the encrypted block is 5×5 pixels, and 25 pixels constitute the smallest encryption unit. The sliding step size is 3 pixels, that is, every time 3 new pixels are received, the block window advances 3 pixels along the line direction. There is a 2×5 pixel overlap area between adjacent blocks and no fixed boundary. The block matching operation is performed on the encrypted valid image digital signal. The block matching order and the number of blocks of 720 pixels of image signal per line (239 blocks) are consistent with those of the encryption end. The block matching operation is completed synchronously with the signal reception without additional delay. The time for block matching of image signal per line is ≤71.7μs.

[0041] A synchronization subkey is generated based on the parsed number. Specifically, in implementation, the decryption end pre-stores a 128-bit fixed root key identical to that of the encryption end. The frame number of the currently received signal is obtained through parsing the synchronization signal group. The sequence numbers are: 0-65535 (cyclic count, line number), 1-575 (sequential count, block number), and 1-239 (line count). Based on these numbers, a simplified SM3 hash function is used, with a computation time ≤70 clock cycles, to generate a 128-bit dynamic subkey that is completely identical to the corresponding encryption block on the encryption end. Each 5×5 encryption block corresponds to a unique synchronization subkey. The subkey generation logic and computation process are completely matched with the encryption end. The subkey generation time for a single block is ≤0.03μs, and it is processed in parallel with the block matching operation, without consuming additional processing time.

[0042] The reverse decryption operation is performed, the signal is reconstructed, and converted into standard video output. Specifically, the keystream generator is initialized using a synchronously generated 128-bit dynamic subkey as a seed, restoring a 25-byte keystream that perfectly corresponds to the encryption end. This keystream perfectly matches the data volume of a 5×5 pixel block. A pixel-by-pixel XOR decryption operation is performed, XORing the encrypted valid image digital signal with the corresponding keystream byte by byte, thus recovering the original valid image digital signal. The decryption time per block is ≤0.3μs, and the decryption time for a single row of image signals is ≤239 blocks × 0.3μs / block = 71.7μs. After decryption, the decrypted original valid image digital signal is reconstructed and converted to standard video output according to the original PAL timing. The output synchronization signal group is accurately reassembled, with a horizontal synchronization pulse of 12μs, followed by a 52μs original effective image signal, and then the vertical synchronization signal is inserted at intervals of every 287.5 lines. The reassembly timing error is ≤±0.1μs. The reassembled digital signal is input to the DAC chip, with parameters completely consistent with the ADC at the encryption end. It is 10-bit quantized and has a conversion rate of 13.5MHz, converting it into a standard PAL analog video signal with an amplitude range of 0-1V and a DAC conversion delay of ≤1.5μs. Finally, the converted standard analog video signal is output to the display device. The output signal maintains the brightness level and color reproduction of the original picture, with a distortion of ≤0.8% and no screen tearing, scrolling, or synchronization abnormalities.

[0043] Pixel-by-pixel XOR decryption technology is a basic symmetric encryption method with limited resistance to cracking. Therefore, this application further proposes to use a synchronously generated 128-bit dynamic subkey as dual input, and to restore the encrypted signal through an "improved Logistic chaotic sequence generation module" and an "improved Feistel network decryption module", ultimately achieving signal reconstruction and output. The specific process is as follows:

[0044] The encrypted valid image digital signal (denoted as C) of 5×5 pixels is split into 32-bit data blocks in row-major order, resulting in a total of 4 32-bit data blocks (C1, C2, C3, C4, C5, C6, C7, C8, C9, C90 ... The binary concatenation result of the pixel values ​​corresponding to each data block, with values ​​ranging from [0, 2]. 32 -1]; at the same time, the 128-bit dynamic subkey (K) is split into four 32-bit round keys. These are used as the initial parameters of the chaotic sequence and the round key of the Feistel network, respectively. The splitting rule is to divide them equally by bytes: bits 1-32 of K are K1, bits 33-64 are K2, bits 65-96 are K3, and bits 9-128 are... .

[0045] Using the round key K1 as the initial value, a 32-bit pseudo-random sequence is generated through an improved Logistic chaotic mapping, which serves as the input to the round function of the Feistel network. The formula for the Logistic mapping is:

[0046] ;

[0047] The parameters are as follows: μ is a control parameter with a value of 3.999 (to ensure that the mapping is in a completely chaotic state); Let be the chaotic value in the nth iteration, and be the initial value. Depend on The conversion method is as follows: (Normalize the 32-bit integer key to the (0,1) range); The value of chaos in the (n+1)th iteration.

[0048] Iterative process: for Perform 30 iterations (discarding the results of the first 30 iterations to eliminate transient effects), and starting from the 31st iteration, take the results of 8 consecutive iterations. to ), each Multiply After rounding, we get eight 8-bit integers, which are then concatenated into a 32-bit pseudo-random sequence S. (By bitwise OR concatenation), the range of values ​​for S is... .

[0049] A 4-round Feistel network structure is adopted, with C1-C4 as inputs, K2-K4 as round keys, and S as auxiliary parameters of the round function. Each round iteration includes three steps: "block partitioning - round function transformation - swapping".

[0050] The round function F is used to perform a scrambling transformation on the input 32-bit data block:

[0051] ;

[0052] The parameters are as follows: R is the right half of the Feistel network data block (32 bits); K is the round key of the i-th round (32 bits, i=1,2,3,4); S is the pseudo-random sequence generated by the chaotic sequence (32 bits); ⊕ is the bitwise XOR operation; · is the unsigned 32-bit multiplication operation; ROT(a,8) means circularly shifting the 32-bit integer a to the left by 8 bits; the output is the 32-bit obfuscated data.

[0053] Let the input of the i-th round be (L i R i The output is (L) i+1 R i+1 The iterative formula is:

[0054] ;

[0055] ;

[0056] For example, the specific iterative steps are as follows:

[0057] Round 1 input (L1=C1, R1=C2), round key K2, calculate F(R1, K2, S), output (L2=R1, R2=L1⊕F(R1, K2, S)).

[0058] In the second round, input (L2, R2), round key K3, calculate F(R2, K3, S), and output (L3=R2, R3=L2⊕F(R2, K3, S)).

[0059] Round 3: Input (L3, R3), round key K4, calculate F(R3, K4, S), output (L4=R3, R4=L3⊕F(R3, K4, S)).

[0060] Round 4 (Final Round): Input (L4, R4), round key K1 (reuse the initial round key), calculate F(R4, K1, S), do not perform swap operation, output (P1=R4⊕F(L4, K1, S), P2=L4).

[0061] The output (P1, P2) from the fourth round is combined with the remaining data blocks C3 and C4 according to the rule "P1, P2, C3⊕S, C4⊕K1" to obtain four 32-bit original data blocks (P1, P2, P3, P4), where P3=C3⊕S and P4=C4⊕K1. Then, the four data blocks are reversed according to the original splitting order to restore the original 5×5 pixel digital image signal P.

[0062] After decryption, the original valid digital image signal P is precisely reassembled with the separated synchronization signal group according to the original PAL timing sequence. The horizontal synchronization pulse is pre-positioned at 12μs, followed by the original valid image signal at 52μs. The vertical synchronization signal is inserted at intervals of 287.5μs, with a reassembly timing error ≤ ±0.1μs. The reassembled digital signal is input to a DAC chip and converted into a standard PAL analog video signal (amplitude range 0-1V, DAC conversion delay ≤ 1.5μs), and finally output to the display device. The output signal has a brightness level deviation ≤ 5%, color reproduction ≥ 95%, distortion ≤ 0.5%, and no screen tearing, scrolling, or synchronization abnormalities.

[0063] This application also protects an electronic device that is deployed using the aforementioned analog video signal encryption / decryption system.

[0064] This application also protects a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, performs the functions of the analog video signal encryption / decryption system provided in the embodiments of the present invention.

[0065] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device.

[0066] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, system, or device.

[0067] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, or any suitable combination thereof.

[0068] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An analog video signal encryption and decryption system, characterized in that, include: The encrypted signal acquisition and separation module is used to acquire analog video signals and separate synchronization signals from valid image signals; The encrypted streaming block module is used to perform unbuffered parallel blocking of valid image signals; The encryption key generation module is used to generate unique subkeys; The encrypted reconstruction output module is used to perform image signal encryption operations, reconstruct the signal, and convert the output. The decryption signal receiving and separating module is used to receive encrypted signals and separate synchronization signals from encrypted image signals; The decryption block matching module is used to complete block matching according to the encryption end rules; The decryption key synchronization module is used to generate a synchronization subkey based on the parsed number; The decryption and reconstruction output module is used to perform reverse decryption operations, reconstruct the signal, and convert it into standard video output.

2. The analog video signal encryption and decryption system according to claim 1, characterized in that, The process involves acquiring analog video signals and separating synchronization signals from valid image signals. Specifically, the acquisition chip is activated to acquire analog video signals and output discrete digital signals. Based on the timing parameters of the video standard, the horizontal and vertical synchronization signals are extracted through a hardware timing discrimination circuit and separated into a synchronization signal group and a valid image digital signal. The synchronization signal group maintains its original physical characteristics and timing standards and does not participate in encryption operations. The valid image digital signal directly enters the next stage of processing.

3. The analog video signal encryption and decryption system according to claim 1, characterized in that, The effective image signal is subjected to unbuffered parallel block segmentation. Specifically, the sampling and block segmentation are performed in parallel mode. The effective image digital signal flows into the block segmentation logic in real time with the sampling. The entire row or frame of data is not buffered. The block segmentation window advances along the row direction as new pixels are acquired. There are overlapping areas between adjacent encrypted blocks and no fixed group boundaries. The block segmentation operation is completed synchronously with the sampling.

4. The analog video signal encryption and decryption system according to claim 1, characterized in that, The encryption key generation module generates a unique subkey. Specifically, the encryption end pre-stores a fixed root key and generates a dynamic subkey based on the current frame number, line number, and block sequence number using a simplified hash function. Each encryption block corresponds to a unique subkey, and the subkey generation and block division operations are processed in parallel.

5. The analog video signal encryption and decryption system according to claim 1, characterized in that, The process involves performing image signal encryption operations, reconstructing the signal, and converting the output. Specifically, a key stream matching the encryption block is generated using a dynamic subkey, and pixel-by-pixel XOR encryption is performed, proceeding block by block in the order of completion. After encryption, the encrypted image signal and synchronization signal are reconstructed according to the original video format timing. The reconstructed digital signal is then converted into an analog video signal and transmitted through a conventional channel. The signal conforms to traditional specifications and requires no modification to hardware parameters.

6. The analog video signal encryption and decryption system according to claim 1, characterized in that, The process involves receiving encrypted signals and separating synchronization signals from encrypted image signals. Specifically, the decryption end activates a data acquisition chip with parameters identical to those of the encryption end, receives the transmitted encrypted analog video signal, converts it into a discrete digital signal, and uses the same hardware timing discrimination circuit as the encryption end to extract line and field synchronization signals based on the video format timing parameters. This process separates the synchronization signal group used for timing calibration from the encrypted valid image digital signal that will be used for subsequent decryption.

7. The analog video signal encryption and decryption system according to claim 1, characterized in that, Block matching is completed according to the encryption end rules. Specifically, a parallel mode of signal reception and block matching is adopted. The encrypted valid image digital signal flows into the block logic in real time as the decryption end acquires it. The block parameters, order and number are completely consistent with the encryption end. The block window advances as new pixels are received. Adjacent blocks have overlapping areas and no fixed boundaries. The block operation is completed synchronously with signal reception.

8. The analog video signal encryption and decryption system according to claim 1, characterized in that, A synchronization subkey is generated based on the parsed number. Specifically, the decryption end pre-stores the same fixed root key as the encryption end. The frame number, line number, and block sequence number of the received signal are obtained by parsing the synchronization signal group. Based on these numbers, a unique dynamic subkey corresponding to the encryption end is generated using a simplified hash function. The subkey generation logic and operation process are completely matched with the encryption end. The generation operation and block matching are processed in parallel.

9. The analog video signal encryption and decryption system according to claim 1, characterized in that, Perform reverse decryption operation, reconstruct the signal and convert it into standard video output. Specifically, generate a corresponding key stream with a synchronous dynamic subkey, XOR decrypt it pixel by pixel to restore the original valid image digital signal, reconstruct the decrypted image signal and synchronization signal according to the original video format timing, and convert the reconstructed digital signal into an analog video signal for output to the display device, maintaining the original image characteristics without any abnormalities.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, performs the function of the analog video signal encryption and decryption system as described in any one of claims 1-9.

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