Static random access memory unit and memory

Abstract

The invention discloses a static random access memory unit and a memory. The unit comprises a fin extending along a first direction, and the fin is provided with an active region and a gate structure; the first interconnection metal structure is arranged on the first side of the fin and is electrically connected with the active region and the gate structure so as to form a first transmission transistor, a second transmission transistor, a first read-write transistor and a second read-write transistor which are arranged in rows and columns and correspond to the channel region in the same column along the second direction; the second interconnection metal structure is arranged on the second side of the fin and is electrically connected with the active region and the gate structure to form a first pull-up transistor and a second pull-up transistor, and the second interconnection metal structure is interconnected with the first interconnection metal structure through a via hole. The static random access memory unit and the memory have the effects of compact layout, interconnection simplification, read-write stability improvement, process tolerance improvement and the like.

Description

Technical Field

[0001] This specification relates to the field of semiconductor integrated circuit technology, and in particular to a static random access memory cell and memory. Background Technology

[0002] Static Random Access Memory (SRAM) is a widely used semiconductor memory with advantages such as high access speed and low power consumption. It is commonly used in cache, register files, and on-chip high-speed storage. Some SRAM cells employ a six-transistor (6T) structure, consisting of two cross-coupled inverters and two access transistors.

[0003] In related technologies, to achieve symmetrical driving of inverters and effective control of read / write transistors, N-type transistors (NMOS) and P-type transistors (PMOS) need to be arranged simultaneously in the semiconductor structure. One implementation is to concentrate N-type transistors on one side of the semiconductor structure and P-type transistors on the other side. Although this layout can form a complementary structure, it still has the following specific problems in the design of static random access memory (SRAM) cells: First, the N-type and P-type transistors are located on opposite sides of the semiconductor structure, and the channel regions of the two types of transistors are geometrically separated, resulting in insufficient symmetry in the overall layout of the SRAM cell and limiting area reduction. Second, SRAM cells are arrayed, and in an arrayed setup, the transistor arrangements between different cells are not completely consistent, the interconnection methods differ, the overall regularity of the array is restricted, and the processing difficulty increases. Third, the large differences in the positional distribution of different transistors can easily lead to characteristic deviations during manufacturing, thus adversely affecting the performance and stability of the SRAM cell.

[0004] Therefore, it is urgent to make relevant improvements to the structure and layout of static random access memory cells. Summary of the Invention

[0005] To further reduce the area of ​​static random access memory (SRAM) cells, lower the fabrication difficulty of SRAM cells, and improve the stability of SRAM cells, this application provides a static random access memory cell and a memory.

[0006] According to a first aspect of this application, a static random access memory (SRAM) cell is provided, the SRAM cell comprising: A semiconductor structure including at least one fin extending along a first direction, the fin having an active region and a gate structure; A first interconnect metal structure is disposed on a first side of the semiconductor structure and electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first transmission transistor, a second transmission transistor, a first read / write transistor, and a second read / write transistor; wherein the channel regions of the first transmission transistor and the first read / write transistor are in the same row along a second direction; the channel regions of the second transmission transistor and the second read / write transistor are in the same row along the second direction; the second direction is perpendicular to the first direction; A second interconnect metal structure is disposed on the second side of the semiconductor structure. The second interconnect metal structure is electrically connected to the active region and the gate structure to form a first pull-up transistor and a second pull-up transistor. Wherein, the second side is the opposite side of the first side, the transistor formed by the first interconnect metal structure and the transistor formed by the second interconnect metal structure share a fin as a channel carrier; the second interconnect metal structure is interconnected with the first interconnect metal structure through a via.

[0007] In some embodiments of this disclosure, the first pull-up transistor and the second pull-up transistor are P-type transistors; The first transmission transistor, the second transmission transistor, the first read / write transistor, and the second read / write transistor are N-type transistors; or, The first pull-up transistor and the second pull-up transistor are N-type transistors; The first transmission transistor, the second transmission transistor, the first read / write transistor, and the second read / write transistor are P-type transistors.

[0008] In some embodiments of this disclosure, adjacent static random access memory cells are mirrored along the first direction.

[0009] In some embodiments of this disclosure, the channel regions of the first transmission transistor and the second transmission transistor are arranged in the same row along the first direction; The channel regions of the first read / write transistor and the second read / write transistor are arranged in the same row along the first direction.

[0010] In some embodiments of this disclosure, the static random access memory cell further includes a shared bit line and a complementary bit line extending along the first direction; The first interconnect metal structure includes a first conductive substructure and a second conductive substructure extending along the second direction; The first conductive substructure is electrically connected to the active region of the first transmission transistor, and the shared bit line is electrically connected to the first conductive substructure through a via. The second conductive substructure is electrically connected to the active region of the first read / write transistor, and the complementary bit line is electrically connected to the second conductive substructure through a via; Along the second direction, the first conductive substructure and the second conductive substructure are arranged in the same row.

[0011] In some embodiments of this disclosure, the first conductive substructure and the second conductive substructure are disposed between adjacent static random access memory cells; The first conductive substructure is used to simultaneously send the first transmission transistor loading signal to the adjacent static random access memory cell. The second conductive substructure is used to simultaneously apply signals to the second read / write transistors in adjacent static random access memory cells.

[0012] In some embodiments of this disclosure, the first conductive substructure and the second conductive substructure are symmetrically arranged about the second direction.

[0013] In some embodiments of this disclosure, the static random access memory cell further includes a reference voltage line extending along the first direction and a third conductive electronic structure extending along the second direction. The third conductive substructure is electrically connected to the active region of the second transmission transistor and the active region of the second read / write transistor, respectively. The reference voltage line is electrically connected to the third conductive electronic structure through a via.

[0014] In some embodiments of this disclosure, the second transmission transistor includes a first fin extending along a first direction; The second read / write transistor includes a second fin extending along a first direction; Wherein, the orthographic projection of one end of the third conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the first fin onto the semiconductor structure; the orthographic projection of the other end of the third conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the second fin onto the semiconductor structure.

[0015] In some embodiments of this disclosure, the first conductive substructure, the second conductive substructure, and the third conductive substructure are disposed in the same layer.

[0016] In some embodiments of this disclosure, the channel regions of the first pull-up transistor and the second pull-up transistor are arranged in the same column along the second direction.

[0017] In some embodiments of this disclosure, the second interconnect metal structure includes a fourth conductive substructure and a fifth conductive substructure extending along the second direction; There is a gap between adjacent static random access memory cells, and the fourth conductive substructure and the fifth conductive substructure are disposed within the gap; Wherein, the orthogonal projection of the fourth conductive electronic structure onto the semiconductor structure overlaps with the orthogonal projection of the first conductive electronic structure onto the semiconductor structure; The orthogonal projection of the fifth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthogonal projection of the second conductive electronic structure onto the semiconductor structure.

[0018] In some embodiments of this disclosure, the static random access memory cell further includes a power supply voltage line extending along a first direction; The second interconnect metal structure further includes a sixth conductive electronic structure extending along the second direction; The sixth conductive electronic structure is electrically connected to the active regions of the first pull-up transistor and the second pull-up transistor, respectively. The power supply voltage line is electrically connected to the sixth conductive electronic structure through a via.

[0019] In some embodiments of this disclosure, the first pull-up transistor and the second transmission transistor share the first fin extending along the first direction; The second pull-up transistor and the second read / write transistor share the second fin extending along the first direction; Wherein, the orthographic projection of one end of the sixth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the first fin onto the semiconductor structure; the orthographic projection of the other end of the sixth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the second fin onto the semiconductor structure.

[0020] In some embodiments of this disclosure, the first interconnect metal structure further includes a first local interconnect substructure extending along the first direction; the second interconnect metal structure further includes a second local interconnect substructure extending along the first direction. One end of the first local interconnect substructure is electrically connected to the active region of the first transmission transistor, and the other end is electrically connected to the gate structure of the second read / write transistor through a via. One end of the second local interconnect substructure is electrically connected to the active region of the second pull-up transistor, and the other end is electrically connected to the gate structure of the first pull-up transistor through a via; wherein, the orthographic projection of the first local interconnect substructure on the semiconductor structure partially overlaps with the orthographic projection of the second local interconnect substructure on the semiconductor structure.

[0021] In some embodiments of this disclosure, the static random access memory unit further includes: A first power supply structure located on the side of the first interconnect metal structure away from the semiconductor structure; a second power supply structure located on the side of the second interconnect metal structure away from the semiconductor structure; a power supply voltage line and a reference voltage line extending along the first direction; The reference voltage line is located on the second power supply structure; The power supply voltage line is located on the first power supply structure.

[0022] In some embodiments of this disclosure, the gate structure of the second pull-up transistor is electrically connected to the gate structure of the second read / write transistor via a via. Wherein, the first pull-up transistor and the second transmission transistor share a first fin extending along the first direction; The second pull-up transistor and the second read / write transistor share a second fin extending along the first direction; The region where the gate structure of the first pull-up transistor is electrically connected to the gate structure of the second transfer transistor is located in the orthographic projection of the semiconductor structure between the first fin and the second fin in the orthographic projection of the semiconductor structure. According to a second aspect of this application, a memory is provided, the memory comprising a plurality of row-column distributed static random access memory cells.

[0023] Beneficial effects: By sharing fins extending along the first direction as channel carriers for transistors on both sides of the semiconductor structure, the number of fins can be reduced to further reduce the area of ​​the static random access memory (SRAM) cell and improve cell integration. By aligning the channel regions of the first transmission transistor and the first read / write transistor along the second direction, and aligning the second transmission transistor and the second read / write transistor along the second direction, the regularity of the SRAM cell's row and column arrangement is achieved, reducing fabrication difficulty. By setting the first interconnect metal structure and the second interconnect metal structure on opposite sides of the fins, different types of transistors are arranged separately, resulting in a compact SRAM cell structure. Furthermore, by using vias to achieve electrical connection between the first interconnect metal structure and the second interconnect metal structure on both sides, the reliability of signal transmission in the SRAM cell is ensured.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0026] Figure 1This is a schematic diagram of the film structure of a static random access memory cell.

[0027] Figure 2 This is a schematic diagram of the stacking of fins and a first interconnect metal structure in one embodiment of a plurality of static random access memory cells.

[0028] Figure 3 This is a schematic diagram of the stacking of fins and a second interconnect metal structure in one embodiment of a plurality of static random access memory cells.

[0029] Figure 4 It is the equivalent circuit diagram of a static random access memory cell.

[0030] Figure 5 This is a schematic diagram of the stacking between a fin and a first interconnect metal structure in one embodiment of a static random access memory cell.

[0031] Figure 6 This is a schematic diagram of the stacking between fins and a second interconnect metal structure in one embodiment of a static random access memory cell.

[0032] Figure 7 This is a schematic diagram of the stacking between the fin and the first interconnect metal structure in a static random access memory cell.

[0033] Figure 8 This is a schematic diagram of the arrangement of the metal fins near the first interconnect structure in a static random access memory cell.

[0034] Figure 9 This is a schematic diagram of the structure of the first metal layer in the first interconnect metal structure of a static random access memory cell.

[0035] Figure 10 This is a schematic diagram of the structure of the second metal layer in the first interconnect metal structure of a static random access memory cell.

[0036] Figure 11 This is a schematic diagram of the third metal layer in the first interconnect metal structure of a static random access memory cell.

[0037] Figure 12 This is a schematic diagram of the stacking between the fin and the second interconnect metal structure in a static random access memory cell.

[0038] Figure 13 This is a schematic diagram of the arrangement of the metal fins near the second interconnect structure in a static random access memory cell.

[0039] Figure 14This is a schematic diagram of the fourth metal layer in the second interconnect metal structure of a static random access memory cell.

[0040] Figure 15 This is a schematic diagram of the fifth metal layer in the second interconnect metal structure of a static random access memory cell.

[0041] Figure 16 This is a schematic diagram of the sixth metal layer in the second interconnect metal structure of a static random access memory cell.

[0042] Figure 17 This application is a schematic diagram of the stacking between the fin and the first interconnect metal structure in another embodiment.

[0043] Figure 18 This application is a schematic diagram of the stacking between the fin and the second interconnect metal structure in another embodiment.

[0044] Explanation of reference numerals in the attached figures: FEOL, Semiconductor structure; BEOL1, First interconnect metal structure; M1, First metal layer; M2, Second metal layer; M3, Third metal layer; BEOL2, Second interconnect metal structure; M4, Fourth metal layer; M5, Fifth metal layer; M6, Sixth metal layer; PSS1, First power supply structure; PSS2, Second power supply structure; WL, Word line; BL, Shared bit line; BLB, Complementary bit line; VDD, Power supply voltage; VSS, Reference voltage; VDL, Power supply voltage line; VSL, Reference voltage line; PG0, First transfer transistor; PD0, Second transfer transistor Transistors; PU0, First Pull-Up Transistor; PU1, Second Pull-Up Transistor; PG1, First Read / Write Transistor; PD1, Second Read / Write Transistor; Q1, First Memory Node; Q2, Second Memory Node; FIN, Fin; FIN1, First Fin; FIN2, Second Fin; MA1, First Conductor Substructure; MA2, Second Conductor Substructure; MA3, Third Conductor Substructure; MA4, Fourth Conductor Substructure; MA5, Fifth Conductor Substructure; MA6, Sixth Conductor Substructure; MS1, First Metal Structure; MS2, Second Metal Structure; MS3, Third Metal Structure; MS4 HA1, 4th metal structure; MS5, 5th metal structure; MS6, 6th metal structure; MS7, 7th metal structure; MS8, 8th metal structure; MS9, 9th metal structure; MS10, 10th metal structure; HA1, 1st lower via area; HA2, 2nd lower via area; HA3, 3rd lower via area; HA4, 4th lower via area; HA5, 5th lower via area; HA6, 6th lower via area; HA7, 7th lower via area; HA8, 8th lower via area; HA9, 9th lower via area; HA10, 10th lower via area; HA11, 11th lower via area; HA1 2. Twelfth lower via area; HA13. Thirteenth lower via area; HB1. First upper via area; HB2. Second upper via area; HB3. Third upper via area; HB4. Fourth upper via area; HB5. Fifth upper via area; HB6. Sixth upper via area; HB7. Seventh upper via area; HB8. Eighth upper via area; HB9. Ninth upper via area; HB10. Tenth upper via area; HB11. Eleventh upper via area; HB12. Twelfth upper via area; HB13. Thirteenth upper via area; DH. First direction; DV. Second direction; A1. First side; A2. Second side. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0046] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0047] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0048] In related technologies, static random access memory (SRAM) is a commonly used semiconductor memory. Due to its fast access speed and low power consumption, it is widely used in processor caches, register files, and on-chip high-speed storage. Some SRAM cells typically employ a six-transistor structure, consisting of two pairs of cross-coupled inverters and two read / write transistors.

[0049] As integrated circuit technology continues to shrink, the cell area of ​​static random access memory (SRAM) is gradually decreasing, and the device channel length is shortening, presenting new challenges for layout design. For example, limited transistor and interconnect placement makes it difficult to further reduce cell area; increased cross-layer interconnects and vias lead to increased parasitic capacitance and signal delay; the lack of shared conductor structures between adjacent cells results in wiring redundancy, affecting layout utilization; layout asymmetry causes poor device matching, affecting read / write stability; unreasonable power supply and reference voltage network design can easily introduce noise and power supply voltage drop, affecting reliability; and insufficient process tolerance affects manufacturing yield. These factors limit the development of static random access memory.

[0050] Based on this, this application provides a static random access memory (SRAM) cell and a memory, which can reduce the area of ​​the SRAM cell and improve the stability of use.

[0051] The following is a detailed introduction to this static random access memory unit.

[0052] Figure 1 A schematic diagram of the film structure of the static random access memory cell is shown in this embodiment. Figure 2 This example illustrates a schematic diagram of the stacking of fins and a first interconnect metal structure among multiple static random access memory cells in this embodiment. Figure 3 This embodiment illustrates a schematic diagram of the stacking between fins and the second interconnect metal structure in multiple static random access memory cells. See also... Figure 1 , Figure 2 and Figure 3 The static random access memory cell of this application includes a semiconductor structure FEOL, including at least one fin extending along a first direction DH, the fin having a source region and a gate structure; a first interconnect metal structure BEOL1 is disposed on a first side A1 of the semiconductor structure FEOL, and electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first transmission transistor PG0, a second transmission transistor PD0, a first read / write transistor PG1, and a second read / write transistor PD1; wherein the channel regions of the first transmission transistor PG0 and the first read / write transistor PG1 are in the same column along a second direction DV, and the channel regions of the second transmission transistor PD0 and the second read / write transistor PG1 are in the same column along a second direction DV. The channel region of read / write transistor PD1 is aligned with the second direction DV, which is perpendicular to the first direction DH. The second interconnect metal structure BEOL2 is disposed on the second side A2 of the semiconductor structure FEOL and is electrically connected to the active region and the gate structure to form the first pull-up transistor PU0 and the second pull-up transistor PU1. The second side A2 is opposite to the first side A1. The transistors formed by the first interconnect metal structure BEOL1 and the transistors formed by the second interconnect metal structure BEOL2 share the fin FIN as the channel carrier. The second interconnect metal structure BEOL2 is interconnected with the first interconnect metal structure BEOL1 through vias.

[0053] It should be noted that in this application, "row" refers to the direction extending along the first direction DH, and "column" refers to the second direction DV perpendicular to it. Further, the gate structure refers to the control electrode portion formed above the fin channel, which includes a gate dielectric layer and a gate electrode, used to regulate the on or off state of the fin channel by an applied voltage, thereby achieving precise control of the transistor current. The active region refers to the region in the fin that participates in conduction, including the channel region, source region, and drain region, and is the main region for current carrying and signal transmission in the transistor. The gate structure and the active region work together to enable the transistor to perform the basic functions of logic switching and memory cells in a row and column arrangement.

[0054] In this embodiment of the invention, a first interconnect metal structure BEOL1 is provided on the first side A1 of the semiconductor structure FEOL. The first interconnect metal structure BEOL1 forms a first transmission transistor PG0, a second transmission transistor PD0, a first read / write transistor PG1, and a second read / write transistor PD1 on the first side A1 of the semiconductor structure FEOL. The channel regions of the first transmission transistor PG0 and the first read / write transistor PG1 are arranged in the same column along the second direction DV. The channel regions of the second transmission transistor PD0 and the second read / write transistor PD1 are also arranged in the same column along the second direction DV. This allows for a further reduction in the area of ​​the static random access memory (SRAM) cell. At the same time, the above-mentioned regular design can reduce the characteristic deviations of the SRAM cell during the manufacturing process and improve the stability of the SRAM cell.

[0055] It is understood that in this application, the channel regions of the first transmission transistor PG0 and the first read / write transistor PG1 are aligned along the second direction DV; the channel regions of the second transmission transistor PD0 and the second read / write transistor PD1 are also aligned along the second direction DV. This allows for a regular arrangement of transistors of the same polarity along the second direction DV, thereby simplifying layout design and intermediate interconnect layer routing, reducing cross-column traces and via density, reducing wiring congestion, and further compressing static random access memory cells. Furthermore, the regularized array layout also improves manufacturing process consistency and scalability, and reduces fabrication difficulty.

[0056] A second interconnect metal structure BEOL2 is provided on the second side A2 of the semiconductor structure FEOL. The second interconnect metal structure BEOL2 forms a first pull-up transistor PU0 and a second pull-up transistor PU1 on the second side A2 of the semiconductor structure FEOL. The second interconnect metal structure BEOL2 is electrically connected to the first interconnect metal structure BEOL1 on the first side A1 through a via to form a stable inverter pair, which improves the data retention capability of the static random access memory cell.

[0057] Furthermore, by sharing a fin as a channel carrier between the transistors formed by the first interconnect metal structure BEOL1 and the transistors formed by the second interconnect metal structure BEOL2, the number of fins and the cell area can be reduced, improving the consistency of transistors on both sides of the semiconductor structure FEOL and the process yield. The transistors formed by the first interconnect metal structure BEOL1 and the multilayer metal layers in the second interconnect metal structure BEOL2 are directly interconnected through vias, which shortens the signal path, reduces interconnect resistance and capacitance, further improving access speed and reducing power consumption.

[0058] In some embodiments of this disclosure, adjacent static random access memory (SRAM) cells are mirrored along the first direction DH. In this embodiment, by mirroring adjacent SRAM cells along the first direction DH, an array-level symmetrical layout can be achieved, which can reduce the fabrication difficulty of SRAM cells to a certain extent; at the same time, it can balance the resistance and capacitance of bit lines (shared bit lines BL, complementary bit lines BLB), word lines WL, and local interconnects, thereby improving the stability of SRAM cells in use.

[0059] The basic principle of a static random access memory (SRAM) cell is explained below, using the equivalent circuit diagram of the SRAM cell: Figure 4 An equivalent circuit diagram of a static random access memory cell in an embodiment of this disclosure is illustrated. See also Figure 4 In this circuit diagram, the source of the first pull-up transistor PU0 is electrically connected to the power supply voltage trace VDL (used to load the power supply voltage VDD), and the drain of the first pull-up transistor PU0 is electrically connected to the first storage node Q1.

[0060] The source of the first transmission transistor PG0 is electrically connected to the shared bit line BL; the gate of the first transmission transistor PG0 is electrically connected to the word line WL; the drain of the first transmission transistor PG0 is electrically connected to the drain of the first pull-up transistor PU0 and the first memory node Q1.

[0061] The source of the first read / write transistor PG1 is electrically connected to the complementary bit line BLB; the gate of the first read / write transistor PG1 is electrically connected to the word line WL; the drain of the first read / write transistor PG1 is electrically connected to the drain of the second pull-up transistor PU1 and the second memory node Q2.

[0062] The source of the first pull-up transistor PU0 is electrically connected to the power supply voltage line VDL; the drain of the first pull-up transistor PU0 is electrically connected to the first memory node Q1; and the gate of the first pull-up transistor PU0 is electrically connected to the second memory node Q2.

[0063] The source of the second pull-up transistor PU1 is electrically connected to the power supply voltage line VDL; the drain of the second pull-up transistor PU1 is electrically connected to the second memory node Q2; and the gate of the second pull-up transistor PU1 is electrically connected to the first memory node Q1.

[0064] The source of the second transfer transistor PD0 is electrically connected to the reference voltage line VSL (used to apply the reference voltage VSS); the drain of the second transfer transistor PD0 is electrically connected to the first memory node Q1; and the gate of the second transfer transistor PD0 is electrically connected to the first memory node Q1.

[0065] The source of the second read / write transistor PD1 is electrically connected to the reference voltage line VSL; the drain of the second read / write transistor PD1 is electrically connected to the second memory node Q2; and the gate of the second read / write transistor PD1 is electrically connected to the first memory node Q1.

[0066] In this circuit, the first pull-up transistor PU0 and the second transfer transistor PD0 together form the first inverter, with the second storage node Q2 as the input and the first storage node Q1 as the output. Similarly, the second pull-up transistor PU1 and the second read / write transistor PD1 together form the second inverter, with the first storage node Q1 as the input and the second storage node Q2 as the output. The first and second inverters are cross-coupled to form a bistable latch circuit, used to store the logic state of the memory cell.

[0067] In some embodiments of this disclosure, the first pull-up transistor PU0 and the second pull-up transistor PU1 can be P-type transistors; the first transmission transistor PG0, the second transmission transistor PD0, the first read / write transistor PG1, and the second read / write transistor PD1 can be N-type transistors. Of course, the first pull-up transistor PU0 and the second pull-up transistor PU1 can also be N-type transistors; the first transmission transistor PG0 and the second transmission transistor PD0, the first read / write transistor PG1, and the second read / write transistor PD1 can also be P-type transistors. This application does not specifically limit these aspects.

[0068] Furthermore, the working principle of the static random access memory (SRAM) unit circuit is explained in detail.

[0069] The circuit works as follows: it has a data holding phase, a write operation phase, and a read operation phase.

[0070] During the data holding phase, the word line WL remains low, and both the first transfer transistor PG0 and the first read / write transistor PG1 are off. The first memory node Q1 is disconnected from the shared bit line BL, and the second memory node Q2 is disconnected from the complementary bit line BLB, completely isolating the cell from external bit lines. At this time, the first inverter (composed of the first pull-up transistor PU0 and the second transfer transistor PD0) and the second inverter (composed of the second pull-up transistor PU1 and the second read / write transistor PD1) are in a cross-coupled state: if the first memory node Q1 is high, the second memory node Q2 is low. At this time, the first pull-up transistor PU0 is turned on, and the power supply voltage VDD provides current to the first memory node Q1 through the source of the first pull-up transistor PU0 to maintain a high level; the second transfer transistor PD0 is turned off to prevent the node from being pulled low. Simultaneously, the second read / write transistor PD1 is turned on, connecting the second memory node Q2 to the reference voltage line VSL through the source of the second read / write transistor PD1, thus maintaining a low level; the second pull-up transistor PU1 is turned off to prevent the node from being incorrectly pulled high.

[0071] If the first storage node Q1 is low, then the second storage node Q2 is high. At this time, the second transmission transistor PD0 is turned on, connecting the first storage node Q1 to the reference voltage line VSL to maintain a low level; the first pull-up transistor PU0 is turned off. Simultaneously, the second pull-up transistor PU1 is turned on, connecting the second storage node Q2 to the power supply voltage line VDL to maintain a high level; the second read / write transistor PD1 is turned off to prevent the second storage node Q2 from being pulled low.

[0072] Through the aforementioned complementary on and off states, the two storage nodes (the first storage node Q1 and the second storage node Q2) always maintain complementary levels, so that the entire storage cell is in a stable bistable latching state, enabling data to be retained for a long time without refreshing.

[0073] During the write operation phase, the external control circuit first drives the shared bit line BL and the complementary bit line BLB to complementary levels. For example, when writing a logic "1", the shared bit line BL is driven high and the complementary bit line BLB is driven low. Subsequently, the word line WL is pulled high, turning on the first transmission transistor PG0 and the first read / write transistor PG1, thereby connecting the first storage node Q1 to the shared bit line BL and the second storage node Q2 to the complementary bit line BLB.

[0074] When the first storage node Q1 is initially at a low level, current flows into the first storage node Q1 through the first transfer transistor PG0 due to the shared bit line BL being driven to a high level, causing its level to rise. As the first storage node Q1 gradually rises, the second transfer transistor PD0 gradually turns off, cutting off the pull-down channel to the reference voltage line VSL. At the same time, the second storage node Q2 is forcibly pulled low by the complementary bit line BLB, and is turned on through the second read / write transistor PD1 to discharge to the reference voltage line VSL, causing the second pull-up transistor PU1 to turn off. Finally, the two nodes stabilize in a state where the first storage node Q1 is at a high level and the second storage node Q2 is at a low level.

[0075] If logic "0" needs to be written, the shared bit line BL will be driven low and the complementary bit line BLB will be driven high. The process is exactly the opposite: after the first transmission transistor PG0 is turned on, the first storage node Q1 is forced low, and the second transmission transistor PD0 is turned on to form a stable pull-down path. At the same time, the low level of the first storage node Q1 turns on the second pull-up transistor PU1, which pulls the second storage node Q2 high, thus completing the data flip.

[0076] During the write phase, the cross-coupled inverter is in a dynamically toggling state, and the external bit line provides strong driving capability, ensuring that even if the cell was originally in the opposite state, the target data can still be forcibly written. After the write is completed, the word line WL returns to a low level, the first transfer transistor PG0 and the first read / write transistor PG1 are turned off, and the cell re-enters the data holding phase. The newly written data is maintained by the first inverter (first pull-up transistor PU0 + second transfer transistor PD0) and the second inverter (second pull-up transistor PU1 + second read / write transistor PD1).

[0077] During the read operation phase, the shared bit line BL and the complementary bit line BLB are first precharged to a high level. Subsequently, the word line WL is pulled high, turning on the first transfer transistor PG0 and the first read / write transistor PG1, thereby electrically connecting the first memory node Q1 to the shared bit line BL and the second memory node Q2 to the complementary bit line BLB.

[0078] If the first storage node Q1 is low, the second transfer transistor PD0 is turned on. The source of the second transfer transistor PD0 is electrically connected to the reference voltage line VSL. The conduction of the second transfer transistor PD0 pulls the first storage node Q1 and the shared bit line BL low. At the same time, the second storage node Q2 is high, the second read / write transistor PD1 is off, and the complementary bit line BLB remains high. After detecting the voltage difference between the shared bit line BL and the complementary bit line BLB, the differential amplifier outputs the corresponding logic value, thereby completing the data reading.

[0079] If the first storage node Q1 is at a high level, the second transmission transistor PD0 is turned off, and the first storage node Q1 and the shared bit line BL remain at a high level; if the second storage node Q2 is at a low level, the second read / write transistor PD1 is turned on, causing the complementary bit line BLB to be pulled low through the second read / write transistor PD1, forming a level difference with the shared bit line BL and being recognized by the differential amplifier.

[0080] After the word line WL returns to a low level, the first transmission transistor PG0 and the first read / write transistor PG1 are turned off, and the cell re-enters the static storage state maintained by the cross-coupled first inverter (first pull-up transistor PU0 + second transmission transistor PD0) and second inverter (second pull-up transistor PU1 + second read / write transistor PD1).

[0081] Figure 5 This example illustrates a schematic diagram of the stacking between fins and the first interconnect metal structure in adjacent static random access memory cells in this embodiment. Figure 6 This example illustrates the stacking of fins and the second interconnect metal structure in adjacent static random access memory cells according to this embodiment. It should be noted that... Figure 5 and Figure 6 In the middle, the larger dashed box on the outside selects the region of a static random access memory cell; the smaller dashed box within the larger dashed box selects the region of the fin FIN channel.

[0082] In some embodiments of this disclosure, see Figure 5 and Figure 6 Along the first direction DH, adjacent static random access memory (SRAM) cells are mirrored. In this embodiment, by arranging adjacent SRAM cells mirrored along the first direction DH, two adjacent SRAM cells can share some fins, gates, and interconnect layouts, reducing redundant space occupation and achieving a more compact cell arrangement. Simultaneously, this arrangement can also reduce the overall area of ​​the SRAM cells, increase the integration density of the memory array, reduce wiring length, and improve the row and column utilization of the array.

[0083] Figure 7 This example illustrates the stacking of fins and a first interconnect metal structure within a static random access memory cell in this embodiment. It should be noted that... Figure 7 In the middle, the larger dashed box on the outside selects the region of a static random access memory cell; the smaller dashed box within the larger dashed box selects the region of the fin FIN channel.

[0084] In some embodiments of this disclosure, see Figure 7The channel regions of the first transmission transistor PG0 and the second transmission transistor PD0 are arranged in the same row along the first direction DH; the channel regions of the first read / write transistor PG1 and the second read / write transistor PD1 are also arranged in the same row along the first direction DH. By arranging the channel regions of the first transmission transistor PG0 and the second transmission transistor PD0 in the same row along the first direction DH, and arranging the channel regions of the first read / write transistor PG1 and the second read / write transistor PD1 in another row along the first direction DH, this arrangement can further regularize and compact the transistor layout, while also reducing the interconnect length and crossover between transistors, thereby improving layout utilization and integration density.

[0085] In some embodiments of this disclosure, see Figure 7 The static random access memory cell further includes a shared bit line BL and a complementary bit line BLB extending along the first direction DH; the first interconnect metal structure BEOL1 includes a first conductive substructure MA1 and a second conductive substructure MA2 extending along the second direction DV; the first conductive substructure MA1 is electrically connected to the active region of the first transmission transistor PG0, and the shared bit line BL is electrically connected to the first conductive substructure MA1 through a via; the second conductive substructure MA2 is electrically connected to the active region of the first read / write transistor PG1, and the complementary bit line BLB is electrically connected to the second conductive substructure MA2 through a via; wherein, along the second direction DV, the first conductive substructure MA1 and the second conductive substructure MA2 are arranged in the same column. In this application, by arranging the first conductive electronic structure MA1 and the second conductive electronic structure MA2 in a straight line along the second direction DV, firstly, the alignment of the contact points of the bit lines (shared bit line BL and complementary bit line BLB) can be achieved, simplifying the wiring and via layout; secondly, the regularity of the layout can be improved, reducing the process deviation caused by uneven via density; and thirdly, the intersection of bit lines and local interconnects can be reduced, improving signal consistency and array yield.

[0086] Figure 7This example illustrates a stacked schematic of the first interconnect metal structure BEOL1 and the fins (FINs) on the semiconductor structure FEOL in a static random access memory (SRAM) cell. It can be seen that the channel regions of the first transfer transistor PG0 and the first read / write transistor PG1 are aligned along the second direction DV; the channel regions of the second transfer transistor PD0 and the second read / write transistor PD1 are also aligned along the second direction DV. The channel regions of the first transfer transistor PG0 and the second read / write transistor PD1 are arranged in the same row along the first direction DH; the channel regions of the first read / write transistor PG1 and the second transfer transistor PD0 are also arranged in the same row along the first direction DH. This scheme, by aligning the first transfer transistor PG0 and the first read / write transistor PG1 along the second direction DV, and the second transfer transistor PD0 and the second read / write transistor PD1 along the second direction DV, and using a cross-alignment in the first direction DH, gives the overall structure a regular and symmetrical characteristic. This arrangement not only simplifies the interconnection between bit lines (shared bit line BL and complementary bit line BLB) and word lines WL, improving the symmetry and matching of the circuit, but also reduces the ineffective area between static random access memory cells, thereby achieving higher integration.

[0087] Figure 8 This example illustrates the arrangement of the FIN fins on the side closest to the first interconnect metal structure BEOL1 in a static random access memory cell within this embodiment. See [link to example]. Figure 7 , Figure 8 The fin has a source region and a gate structure. The first interconnect metal structure BEOL1 is electrically connected to the active region and the gate structure to form a row-and-column arrangement of the first transmission transistor PG0, the second transmission transistor PD0, the first read / write transistor PG1, and the second read / write transistor PD1.

[0088] In some implementations, the fins are preferably made of semiconductor materials, such as single-crystal silicon, and can be formed by etching a silicon substrate. To improve device performance, the fins can also be made of strained semiconductors or high-mobility materials, such as silicon-germanium, germanium, or group III-V compound semiconductors, to improve the carrier mobility of the channel. Depending on the process requirements, the fins can have different doped regions, where the active region is generally heavily doped through ion implantation or epitaxial growth, while the channel region remains lightly doped or intrinsic to ensure effective control of the channel conduction by the gate. The gate structure spans the channel region of the fin and typically includes a high-dielectric-constant gate dielectric layer and a metal gate material, which is isolated from the channel region of the fin to achieve modulation of the channel conductivity state.

[0089] Furthermore, to ensure the electrical characteristics of the static random access memory (SRAM) cells, the fins can have design parameters such as fin width and fin height, thereby achieving precise control over the channel length and channel area to meet the performance requirements of SRAM cells in high-density integration. This application will not elaborate on this further.

[0090] Figure 9 This example illustrates a schematic diagram of the first metal layer M1 in the first interconnect metal structure BEOL1 within a static random access memory cell in this embodiment.

[0091] The first metal layer M1 includes metal structures arranged sequentially along a first direction DH; the metal structures include a first metal structure MS1, a second metal structure MS2, and a third metal structure MS3. The first metal structure MS1 extends along a second direction DV; a first lower via region HA1 is provided on the first metal structure MS1, which is used to electrically connect with the conductive substructures in the other film layers (electrically connected to the word line WL in this application) to achieve the purpose of loading signals onto the first metal structure MS1.

[0092] The second metal structure MS2 extends along the second direction DV, and the second metal structure MS2 has a twelfth upper via region HB12.

[0093] The third metal structure MS3 extends along the second direction DV, and has an eighth lower via region HA8 and a thirteenth upper via region HB13. The eighth lower via region HA8 and the thirteenth upper via region HB13 are used for electrical connection with the conductive electronic structures in the remaining film layers.

[0094] The static random access memory (SRAM) cell includes a word line WL laid out along the second direction DV. The word line WL is electrically connected to the first metal structure MS1 through a first lower via region HA1, thereby loading the control signal of the word line WL onto the first metal structure MS1 to drive and control the gates of the first transmission transistor PG0 and the first read / write transistor PG1. This design results in a simple interconnect path between the word line WL and the first metal layer M1, with low parasitic resistance and capacitance, which is beneficial for improving read / write speed and reducing power consumption. Simultaneously, it reserves independent via regions for the second metal structure MS2 and the third metal structure MS3, facilitating independent routing of differential signals, bit lines, and memory nodes, reducing interconnect coupling interference, and improving the signal integrity and stability of the memory cell array.

[0095] In some embodiments, the second metal structure MS2 and the third metal structure MS3 are arranged in the same column along the second direction DV.

[0096] Figure 10This embodiment illustrates a schematic diagram of the second metal layer M2 in a first interconnect metal structure BEOL1 within a static random access memory cell. The second metal layer M2 includes a first conductive substructure MA1, a second conductive substructure MA2, a third conductive substructure MA3, a fourth metal structure MS4, and a fifth metal structure MS5. Specifically, the first conductive substructure MA1 and the second conductive substructure MA2 are located on the same straight line along the second direction DV; the fourth metal structure MS4 and the fifth metal structure MS5 are located on the same straight line along the second direction DV; and the third conductive structure MA3 extends along the second direction DV to form a reference voltage VSS channel.

[0097] In this embodiment, a fourth lower via region HA4 is provided on the first conductive electronic structure MA1; a fifth lower via region HA5 is provided on the second conductive electronic structure MA2; a sixth upper via region HB6 and a seventh lower via region HA7 are provided on the fourth metal structure MS4; a ninth upper via region HB9 is provided on the fifth metal structure MS5; and a third lower via region HA3 is provided on the third conductive electronic structure MA3.

[0098] The static random access memory (SRAM) cell includes a reference voltage line VSL laid out along the second direction DV. The reference voltage line VSL is electrically connected to the third conductive substructure MA3 through the third lower via region HA3, thereby loading the reference voltage VSS onto the third conductive substructure MA3. The reference voltage VSS is electrically connected to the active regions of the second transmission transistor PD0 and the second read / write transistor PD1 through the third conductive substructure MA3, realizing the distribution and stable control of the reference voltage VSS. Furthermore, by setting the first conductive substructure MA1 and the second conductive substructure MA2 extending along the second direction DV in the second metal layer M2, and arranging the first conductive substructure MA1 and the second conductive substructure MA2 in a straight line along the second direction DV, it can be ensured that the corresponding transistor contact points of the first conductive substructure MA1 and the second conductive substructure MA2 are regularly aligned, simplifying local interconnections. The third conductive substructure MA3 is set as a dedicated reference voltage VSS channel, electrically connected to the reference voltage line VSL through the third lower via region HA3, directly loading the reference voltage VSS onto the second transmission transistor PD0 and the second read / write transistor PD1, ensuring a stable and consistent reference level. The above structural design not only makes the metal layer layout of the static random access memory cell symmetrical and regular, but also reduces the coupling interference of bit lines (shared bit line BL and complementary bit line BLB) and word lines WL, which helps to improve the speed, power efficiency and yield of the static random access memory cell array.

[0099] In some implementations, see Figure 6A first conductive substructure MA1 and a second conductive substructure MA2 are disposed between adjacent static random access memory (SRAM) cells. The first conductive substructure MA1 is used to simultaneously load a signal onto the first transmission transistor PG0 in the adjacent SRAM cell; the second conductive substructure MA2 is used to simultaneously load a signal onto the second read / write transistor PD1 in the adjacent SRAM cell. In this embodiment, by distributing the first conductive substructure MA1 and the second conductive substructure MA2 between adjacent SRAM cells and using them to simultaneously load signals onto the first transmission transistor PG0 and the second read / write transistor PD1 in the adjacent cells, parallel driving of multiple SRAM cells by the same signal is achieved, simplifying the interconnect wiring structure and reducing the wiring area. Furthermore, it ensures the consistency of signal allocation, improves the synchronization and stability of signal transmission, and thus helps to improve the integration and operating efficiency of the memory array.

[0100] Further, see Figure 7 In some embodiments, the first conductive electronic structure MA1 and the second conductive electronic structure MA2 are symmetrically arranged about the second direction DV. By symmetrically arranging the first conductive electronic structure MA1 and the second conductive electronic structure MA2 about the second direction DV, the circuit layout structure can exhibit regular symmetry, which not only helps to reduce wiring deviations but also ensures the geometric balance of signal paths, thereby reducing coupling interference and delay differences caused by interconnect asymmetry. Through this symmetrical design, the electrical consistency and stability of the static random access memory cell array can be effectively improved, thereby enhancing the overall integration and reliability of the memory.

[0101] In some embodiments, the static random access memory (SRAM) cell further includes a reference voltage line VSL extending along a first direction DH and a third conductive substructure MA3 extending along a second direction DV. The third conductive substructure MA3 is electrically connected to the active regions of the second transfer transistor PD0 and the second read / write transistor PD1, respectively. The reference voltage line VSL is electrically connected to the third conductive substructure MA3 through vias. In this embodiment, the SRAM cell has a reference voltage line VSL extending along the first direction DH and is electrically connected to the third conductive substructure MA3 extending along the second direction DV through vias. The third conductive substructure MA3 is electrically connected to the active regions of the second transfer transistor PD0 and the second read / write transistor PD1, respectively. This design enables the reference voltage VSS to be directly and stably distributed within the cell, reducing redundant wiring paths and lowering parasitic resistance and capacitance. Simultaneously, it ensures the level consistency and reliability of the second transfer transistor PD0 and the second read / write transistor PD1 during operation, thereby improving the read / write speed and anti-interference capability of the memory cell, which is beneficial to the stability and yield of large-scale memory arrays.

[0102] Furthermore, the second transmission transistor PD0 includes a first fin FIN1 extending along the first direction DH; the second read / write transistor PD1 includes a second fin FIN2 extending along the first direction DH; wherein, the orthographic projection of one end of the third conductive electronic structure MA3 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the first fin FIN1 onto the semiconductor structure FEOL; the orthographic projection of the other end of the third conductive electronic structure MA3 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second fin FIN2 onto the semiconductor structure FEOL. Through this design, the third conductive electronic structure MA3 can achieve direct interconnection of the active regions of the second read / write transistor PD1 and the second transmission transistor PD0 on the layout, reducing the occupation of additional wiring layers, shortening the interconnection path, and reducing parasitic resistance and capacitance; simultaneously, this interconnection relationship is geometrically regular and compact, which is beneficial for process alignment and photolithography consistency, thereby improving the integration density of the memory cell and the stability of signal transmission.

[0103] In some implementations, the first conductive substructure MA1, the second conductive substructure MA2, and the third conductive substructure MA3 are arranged on the same layer. This co-layer arrangement allows for the distribution and interconnection of related signals within the same metal layer, reducing the number of vias required for cross-layer interconnects, lowering parasitic resistance and capacitance, thereby shortening signal transmission paths and increasing signal transmission speed. Simultaneously, this co-layer arrangement simplifies the layout structure, improves wiring regularity and process implementation consistency, and helps enhance the stability and overall integration of the static random access memory cell array. Figure 11 This illustration shows a schematic diagram of the third metal layer M3 of a first interconnect metal structure BEOL1 in a static random access memory cell, according to an embodiment of the present disclosure. The third metal layer M3 includes a first local interconnect substructure IS1 extending along a first direction DH.

[0104] The first local interconnect substructure IS1 has a seventh upper via region HB7 and an eighth upper via region HB8. The seventh upper via region HB7 and the seventh lower via region HA7 overlap and are connected by vias; the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected by vias.

[0105] Figure 12This illustration demonstrates a stacked schematic of the second interconnect metal structure BEOL2 and the fin FIN in a static random access memory cell, according to an embodiment of this disclosure. It can be seen that the channel regions of the first pull-up transistor PU0 and the second pull-up transistor PU1 are arranged in the same column along the second direction DV. By arranging the channel regions of the first pull-up transistor PU0 and the second pull-up transistor PU1 in the same column along the second direction DV, the first pull-up transistor PU0 and the second pull-up transistor PU1 are kept vertically aligned in the layout, simplifying the wiring connection of the power supply voltage line VDL, reducing trace crossings, and improving the symmetry of the circuit structure and device matching. At the same time, this arrangement has strong regularity, facilitating the repeated expansion of cells in the memory array, thereby achieving higher integration and better overall performance.

[0106] Figure 13 This illustration shows a schematic diagram of a fin arrangement on the side near the second interconnect metal structure BEOL2 in a static random access memory cell, according to an embodiment of the present disclosure. The fin has a source region and a gate structure, and the second interconnect metal structure BEOL2 is electrically connected to the source region and the gate structure to form a row-column arrangement of a first pull-up transistor PU0 and a second pull-up transistor PU1.

[0107] In some implementations, the fins are preferably made of semiconductor materials, such as single-crystal silicon, and can be formed by etching a silicon substrate. To improve device performance, the fins can also be made of strained semiconductors or high-mobility materials, such as silicon-germanium, germanium, or group III-V compound semiconductors, to improve the carrier mobility of the channel. Depending on the process requirements, the fins can have different doped regions, where the active region is generally heavily doped through ion implantation or epitaxial growth, while the channel region remains lightly doped or intrinsic to ensure effective control of the channel conduction by the gate. The gate structure spans the channel region of the fin and typically includes a high-dielectric-constant gate dielectric layer and a metal gate material, which is isolated from the channel region of the fin to achieve modulation of the channel conductivity state.

[0108] Furthermore, to ensure the electrical characteristics of the static random access memory (SRAM) cells, the fins can have design parameters such as fin width and fin height, thereby achieving precise control over the channel length and channel area to meet the performance requirements of SRAM cells in high-density integration. This application will not elaborate on this further.

[0109] Figure 14 A schematic diagram of the fourth metal layer M4 in the second interconnect metal structure BEOL2 in a static random access memory cell is illustrated in an embodiment of this disclosure.

[0110] The fourth metal layer M4 includes metal structures arranged sequentially along the first direction DH; the metal structures include a sixth metal structure MS6, a seventh metal structure MS7, and an eighth metal structure MS8. The sixth metal structure MS6 extends along the second direction DV, wherein the orthographic projection of the sixth metal structure MS6 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the first metal structure MS1 onto the semiconductor structure FEOL. The seventh metal structure MS7 extends along the second direction DV and has a twelfth lower via region HA12 and an eleventh lower via region HA11; wherein the twelfth lower via region HA12 overlaps with the twelfth upper via region HB12 and is connected through a via. The eighth metal structure MS8 extends along the second direction DV and has a thirteenth lower via region HA13; wherein the thirteenth lower via region HA13 overlaps with the thirteenth upper via region HB13 and is connected through a via.

[0111] In some embodiments, the seventh metal structure MS7 and the eighth metal structure MS8 are arranged in the same column along the second direction DV.

[0112] This scheme, by sequentially arranging a sixth metal structure MS6, a seventh metal structure MS7, and an eighth metal structure MS8 along the first direction DH in the fourth metal layer M4, and setting the sixth metal structure MS6 to at least partially overlap with the first metal structure MS1 in the orthogonal projection of the semiconductor structure FEOL, not only ensures reliable interconnection between multiple metal layers but also optimizes electrical continuity and signal integrity. Simultaneously, the seventh metal structure MS7 and the eighth metal structure MS8 can be arranged co-linearly in the second direction DV, making the overall structure more regular, simplifying wiring and process implementation, improving layout symmetry and integration, and making it suitable for interconnection optimization of large-scale integrated circuits.

[0113] Figure 15 An example of an embodiment of the present disclosure is shown, illustrating a schematic diagram of the fifth metal layer M5 of the second interconnect metal structure BEOL2 in a static random access memory cell.

[0114] The fifth metal layer M5 includes a fourth conductive electronic structure MA4, a fifth conductive electronic structure MA5, a sixth conductive electronic structure MA6, a ninth metal structure MS9, and a tenth metal structure MS10. Specifically, the fourth conductive electronic structure MA4 and the fifth conductive electronic structure MA5 are located on the same straight line along the second direction DV, the ninth metal structure MS9 and the tenth metal structure MS10 are located on the same straight line along the second direction DV, and the sixth conductive electronic structure MA6 extends along the second direction DV to form a power supply voltage VDD channel.

[0115] In this embodiment, the orthographic projection of the fourth conductive electronic structure MA4 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the first conductive electronic structure MA1 onto the semiconductor structure FEOL. The orthographic projection of the fifth conductive electronic structure MA5 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second conductive electronic structure MA2 onto the semiconductor structure FEOL. The sixth conductive electronic structure MA6 has a second lower via region HA2. The static random access memory cell includes a power supply voltage line VDL (for loading a power supply voltage VDD) extending along a first direction DH. The power supply voltage line VDL is electrically connected to the sixth conductive electronic structure MA6 through the second lower via region HA2 to achieve the purpose of loading the power supply voltage VDD loaded on the power supply voltage line VDL onto the sixth conductive electronic structure MA6. The ninth metal structure MS9 has a sixth lower via region HA6, which overlaps with the sixth upper via region HB6 and is connected through a via. The tenth metal structure MS10 is provided with a tenth lower via region HA10 and a ninth lower via region HA9; wherein, the ninth lower via region HA9 overlaps with the ninth upper via region HB9 and is connected by vias.

[0116] By incorporating the fourth conductive substructure MA4, fifth conductive substructure MA5, sixth conductive substructure MA6, ninth metal structure MS9, and tenth metal structure MS10 within the fifth metal layer M5, and utilizing projection overlap with the underlying conductive substructures and multi-point via connections, reliable cross-layer interconnection is achieved, while ensuring electrical path continuity and signal integrity. Specifically, the projection overlap of the fourth and fifth conductive substructures MA4 and MA5 improves inter-layer coupling matching; the sixth conductive substructure MA6, serving as a power supply voltage VDD channel, can directly apply voltage through the power supply voltage line VDL, thereby stabilizing the operation of static random access memory (SRAM) cells; and the multiple via regions on the ninth and tenth metal structures MS9 and MS10 enhance interconnect redundancy and reliability. The overall scheme features a well-organized layout and good electrical symmetry, which is beneficial for interconnection optimization and power distribution in large-scale integrated circuits (especially memory arrays).

[0117] In some implementations, see Figure 6The second interconnect metal structure BEOL2 includes a fourth conductive substructure MA4 and a fifth conductive substructure MA5 extending along the second direction DV. A gap exists between adjacent static random access memory (SRAM) cells, and the fourth conductive substructure MA4 and the fifth conductive substructure MA5 are disposed within the gap. The orthographic projection of the fourth conductive substructure MA4 onto the semiconductor structure FEOL partially overlaps with the orthographic projection of the first conductive substructure MA1 onto the semiconductor structure FEOL. The orthographic projection of the fifth conductive substructure MA5 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second conductive substructure MA2 onto the semiconductor structure FEOL. By arranging the fourth conductive substructure MA4 and the fifth conductive substructure MA5 within the gap between adjacent SRAM cells, not only is the gap area between cells fully utilized, improving layout utilization, but the overall cell area is also effectively reduced, which is beneficial for improving the integration density of the memory array. Furthermore, the orthographic projections of the fourth conductive electronic structure MA4 and the first conductive electronic structure MA1, and the fifth conductive electronic structure MA5 and the second conductive electronic structure MA2 onto the FEOL semiconductor structure, partially overlap, ensuring the directness and stability of cross-layer interconnects, shortening the signal transmission path, and reducing parasitic resistance and capacitance, thereby improving signal transmission speed and reliability. This design also makes the interconnection relationship more geometrically regular and allows for a larger process alignment margin, which is beneficial for improving lithographic consistency and circuit manufacturing yield.

[0118] In some embodiments, the static random access memory (SRAM) cell further includes a power supply voltage line VDL extending along a first direction DH; the second interconnect metal structure BEOL2 further includes a sixth conductive electronic structure MA6 extending along a second direction DV; the sixth conductive electronic structure MA6 is electrically connected to the active regions of the first pull-up transistor PU0 and the second pull-up transistor PU1; the power supply voltage line VDL is electrically connected to the sixth conductive electronic structure MA6 through a via. By providing a power supply voltage line VDL extending along the first direction DH in the SRAM cell, and combining it with the sixth conductive electronic structure MA6 extending along the second direction DV in the second interconnect metal structure BEOL2, flexible allocation of the power supply voltage VDD can be achieved in a two-dimensional direction. The power supply voltage line VDL is electrically connected to the sixth conductive electronic structure MA6 through a via, and the sixth conductive electronic structure MA6 is then directly connected to the active regions of the first pull-up transistor PU0 and the second pull-up transistor PU1, thereby ensuring that the power supply voltage VDD can be stably loaded onto the pull-up transistors. This design not only shortens the power supply voltage VDD transmission path and reduces parasitic resistance and capacitance, but also improves the uniformity and reliability of power supply, ensuring that storage nodes can maintain a high level for a long time in the logic "1" state, thus enhancing the stability and anti-interference capability of the storage cells. At the same time, this power distribution structure has a regular layout, which is beneficial to the consistency and manufacturing yield of large-scale storage arrays.

[0119] Furthermore, the second pull-up transistor PU1 and the second read / write transistor PD1 share a second fin FIN2 extending along the first direction DH; the first pull-up transistor PU0 and the second transmission transistor PD0 share a first fin FIN1 extending along the first direction DH; wherein, the orthographic projection of one end of the sixth conductive electronic structure MA6 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the first fin FIN1 onto the semiconductor structure FEOL, and the orthographic projection of the other end of the sixth conductive electronic structure MA6 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second fin FIN2 onto the semiconductor structure FEOL.

[0120] By having the second pull-up transistor PU1 and the second read / write transistor PD1 share the second fin FIN2, and the first pull-up transistor PU0 and the second transmit transistor PD0 share the first fin FIN1, not only is the utilization rate of the fin FIN area improved and the number of fin FINs required for the cell reduced, thereby reducing the cell area, but the compactness and symmetry of the circuit layout are also maintained.

[0121] Furthermore, the orthogonal projection of the sixth conductive electronic structure MA6 onto the semiconductor structure FEOL simultaneously overlaps with the regions of the first fin FIN1 and the second fin FIN2, enabling direct interconnection of related transistors on the layout. This shortens the signal transmission path, reduces parasitic resistance and capacitance, and improves the stability and consistency of signal loading. This design optimizes space utilization, improves electrical performance and manufacturability, and is beneficial for the integration and yield improvement of large-scale memory arrays.

[0122] Figure 16 An example of an embodiment of the present disclosure is shown, illustrating a schematic diagram of the sixth metal layer M6 of the second interconnect metal structure BEOL2 in a static random access memory cell.

[0123] The schematic diagram of the sixth metal layer M6 includes a second local interconnect substructure IS2 extending along the first direction DH. The second local interconnect substructure IS2 has a tenth upper via region HB10 and an eleventh upper via region HB10. The tenth upper via region HB10 and the tenth lower via region HA10 overlap and are connected by vias; the eleventh lower via region HA11 overlaps with the eleventh upper via region HB11 and is connected by vias.

[0124] In some embodiments of this disclosure, the first interconnect metal structure BEOL1 includes a first partial interconnect substructure IS1 extending along the first direction DH; the second interconnect metal structure BEOL2 includes a second partial interconnect substructure IS2 extending along the first direction DH; one end of the first partial interconnect substructure IS1 is electrically connected to the active region of the first transmission transistor PU1, and the other end of the first partial interconnect substructure IS1 is electrically connected to the gate structure of the second read / write transistor PD1 through a via; one end of the second partial interconnect substructure IS2 is electrically connected to the active region of the second pull-up transistor PU1, and the other end of the second partial interconnect substructure IS2 is electrically connected to the gate structure of the first pull-up transistor PU0 through a via; wherein, the orthographic projection of the first partial interconnect substructure IS1 on the semiconductor structure FEOL partially overlaps with the orthographic projection of the second partial interconnect substructure IS2 on the semiconductor structure FEOL.

[0125] By setting a first local interconnect substructure IS1 and a second local interconnect substructure IS2 in the first interconnect metal structure BEOL1 and the second interconnect metal structure BEOL2 respectively, and arranging them in a partially overlapping manner in the orthographic projection of the semiconductor structure FEOL, efficient interconnection between the gate and the active region can be achieved. At the same time, this design can effectively reduce the number of contact points and simplify wiring complexity.

[0126] Furthermore, the design of the first local interconnect substructure IS1 and the second local interconnect substructure IS2 avoids physical crossovers while ensuring electrical interconnection at shared contact points, thereby improving layout regularity and symmetry, and expanding process alignment margins. Thus, the overall design not only saves wiring resources and reduces parasitic resistance and capacitance, but also improves electrical consistency and manufacturability, thereby increasing the integration density and yield of the memory array. In some embodiments of this disclosure, the static random access memory cell further includes a first power supply structure PSS1 located on the side of the first interconnect metal structure BEOL1 away from the semiconductor structure FEOL; a second power supply structure PSS2 located on the side of the second interconnect metal structure BEOL2 away from the semiconductor structure FEOL; a power supply voltage line VDL and a reference voltage line VSL extending along a first direction DH; wherein the reference voltage line VSL is disposed on the second power supply structure PSS2; and the power supply voltage line VDL is disposed on the first power supply structure PSS1.

[0127] By setting up a first power supply structure PSS1 and a second power supply structure PSS2 on the side of the first interconnect metal structure BEOL1 and the second interconnect metal structure BEOL2 away from the semiconductor structure FEOL, and routing the reference voltage line VSL on the second power supply structure PSS2 and the power supply voltage line VDL on the first power supply structure PSS1, the power supply voltage VDD and the reference voltage VSS are separated and powered on different interconnect structure layers. This layout not only effectively alleviates the congestion of wiring on the same layer and improves wiring regularity and electrical isolation, but also allows for flexible adjustment based on the wiring resources on different surfaces, optimizing the overall routing strategy and saving wiring space. Furthermore, the distribution of the reference voltage VSS and the power supply voltage VDD on different metal structure layers can reduce coupling interference between power lines, improve the stability and consistency of power supply, thereby improving the performance and manufacturing yield of the memory cell array. At the same time, arranging the reference voltage line VSL on the second power supply structure PSS2 can save the winding resources of the first interconnect metal structure BEOL1.

[0128] In this disclosure, see Figure 17 and Figure 18 and Figure 7 and Figure 17 The difference lies in the following: the gate structure of the second pull-up transistor PU1 is electrically connected to the gate structure of the second read / write transistor PD1 through vias (the twelfth upper via region HB12 and the twelfth lower via region HA12); the second pull-up transistor PU1 and the second read / write transistor PD1 share the second fin FIN2 extending along the first direction DH; the first pull-up transistor PU0 and the second transmission transistor PD0 share the first fin FIN1 extending along the first direction DH; the region where the gate structure of the second pull-up transistor PU1 is electrically connected to the gate structure of the second read / write transistor PD1 (the region where the twelfth upper via region HB12 and the twelfth lower via region HA12 are electrically connected) is located between the first fin FIN1 and the second fin FIN2 in the orthogonal projection of the semiconductor structure FEOL.

[0129] The beneficial effects of this embodiment are as follows: by electrically connecting the gate structure of the second pull-up transistor PU1 and the gate structure of the second read / write transistor PD1 through the twelfth upper via region HB12 and the twelfth lower via region HA12, not only can reliable transmission of gate signals be achieved, reducing metal interconnect paths, reducing interconnect resistance and parasitic capacitance, but it is also beneficial to improve the switching speed and signal integrity of the device.

[0130] Furthermore, the second pull-up transistor PU1 and the second read / write transistor PD1 share the second fin FIN2 extending along the first direction DH, and the first pull-up transistor PU0 and the second transmission transistor PD0 share the first fin FIN1 extending along the first direction DH. The shared design of the fin FIN area effectively improves the utilization rate of the fin FIN area, reduces the cell area occupied, and thus improves the integration density of the static random access memory cell.

[0131] Furthermore, by placing the area where the gate structure of the second pull-up transistor PU1 is electrically connected to the second read / write transistor PD1 between the first fin FIN1 and the second fin FIN2 in the orthogonal projection of the semiconductor structure FEOL, the device spacing limitation can be reduced in the layout and process implementation, the photolithography process window can be expanded, the pattern transfer consistency and manufacturing yield can be improved, thereby enhancing the stability and manufacturability of the memory circuit.

[0132] Finally, the signal loading flow of the static random access memory cell provided in this embodiment is described in detail, taking into account the traces (word line WL, shared bit line BL, and complementary bit line BLB), via regions (first upper via region HB1 to thirteenth upper via region HB13; first lower via region HA1 to thirteenth lower via region HA13), conductive substructures (first conductive structure MA1 to sixth conductive structure MA6), metal structures (first metal structure MS1 to tenth metal structure MS10), first local interconnect substructure IS1, and second local interconnect substructure IS2. The word line WL is configured to extend along the second direction DV and is electrically connected to the first metal structure MS1 via the first lower via region HA1 located in the first metal layer M1, thereby loading a signal onto the first metal structure MS1. This drives the gates of the first transmission transistor PG0 and the first read / write transistor PG1 to turn on or off. Specifically, when the word line WL is loaded with a high level, the first transmission transistor PG0 and the first read / write transistor PG1 are turned on, causing the first memory node Q1 and the second memory node Q2 to connect to the shared bit line BL and the complementary bit line BLB, enabling data writing or reading.

[0133] Power supply voltage VDD loading path: The power supply voltage line VDL extends along the first direction DH. The power supply voltage line VDL is electrically connected to the sixth conductive electronic structure MA6 through the second lower via region HA2, thereby loading the power supply voltage VDD onto the sixth conductive electronic structure MA6. Subsequently, the sixth conductive electronic structure MA6 is electrically connected to the source of the first pull-up transistor PU0 and the second pull-up transistor PU1. This ensures that when the first memory node Q1 and the second memory node Q2 are in the logic "1" state, the first pull-up transistor PU0 or the second pull-up transistor PU1 is turned on, providing a continuous power supply voltage VDD. This ensures that the high level of the memory node is not easily lost and is stably maintained.

[0134] Reference voltage VSS loading path: The reference voltage line VSL is laid along the second direction DV, electrically connected to the third conductive electronic structure MA3 through the third lower via region HA3 of the second metal layer M2, and then loaded to the source of the second transmission transistor PD0 and the second read / write transistor PD1. When the first memory node Q1 or the second memory node Q2 is in the logic "0" state: the second transmission transistor PD0 or the second read / write transistor PD1 is turned on accordingly, which can reliably pull the node voltage down to the reference voltage VSS; this ensures the stability of the low-level state and avoids interference causing switching.

[0135] Loading paths for shared bit line BL and complementary bit line BLB: Shared bit line BL is electrically connected to the first conductive substructure MA1 via the fourth lower via region HA4, and the first conductive substructure MA1 is electrically connected to the source of the first transmission transistor PG0. Complementary bit line BLB is electrically connected to the second conductive substructure MA2 via the fifth lower via region HA5, and the second conductive substructure MA2 is electrically connected to the source of the first read / write transistor PG1.

[0136] During a write operation, the external drive circuit loads data onto the shared bit line BL or the complementary bit line BLB, and transmits the data signal to the first storage node Q1 and the second storage node Q2 through the first transfer transistor PG0 and the first read / write transistor PG1. If a high level is applied to the shared bit line BL and a low level is applied to the complementary bit line BLB, then the first storage node Q1 is written as "1" and the second storage node Q2 is written as "0".

[0137] During a read operation, the word line WL is loaded with a high level. At this time, the first transmission transistor PG0 and the first read / write transistor PG1 are turned on. The levels of the first storage node Q1 and the second storage node Q2 are output through the shared bit line BL and the complementary bit line BLB. The external circuit determines the stored data content by comparing the voltage difference between the shared bit line BL and the complementary bit line BLB.

[0138] Storage nodes (first storage node Q1 and second storage node Q2) are maintained and toggled: First storage node Q1 is connected by a first pull-up transistor PU0, a second transfer transistor PD0, and a first transfer transistor PG0; second storage node Q2 is connected by a second pull-up transistor PU1, a first read / write transistor PG1, and a second read / write transistor PD1; first storage node Q1 and second storage node Q2 are cross-connected to form a bistable latch. At any time: if first storage node Q1=1, the first pull-up transistor PU0 provides the power supply voltage VDD to maintain a high level, while the second read / write transistor PD1 is turned on to pull second storage node Q2 to the reference voltage VSS; if first storage node Q1=0, the second transfer transistor PD0 pulls it down to the reference voltage VSS, while the second pull-up transistor PU1 provides the power supply voltage VDD to maintain second storage node Q2=1.

[0139] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A static random access memory (SRAM) cell, characterized in that, The static random access memory unit includes: A semiconductor structure including at least one fin extending along a first direction, the fin having an active region and a gate structure; A first interconnect metal structure is disposed on a first side of the semiconductor structure and electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first transmission transistor, a second transmission transistor, a first read / write transistor, and a second read / write transistor; wherein the channel regions of the first transmission transistor and the first read / write transistor are in the same row along a second direction; the channel regions of the second transmission transistor and the second read / write transistor are in the same row along the second direction; the second direction is perpendicular to the first direction; A second interconnect metal structure is disposed on the second side of the semiconductor structure. The second interconnect metal structure is electrically connected to the active region and the gate structure to form a first pull-up transistor and a second pull-up transistor. Wherein, the second side is the opposite side of the first side, the transistor formed by the first interconnect metal structure and the transistor formed by the second interconnect metal structure share a fin as a channel carrier; the second interconnect metal structure is interconnected with the first interconnect metal structure through a via.

2. The static random access memory unit according to claim 1, characterized in that, The first pull-up transistor and the second pull-up transistor are P-type transistors; The first transmission transistor, the second transmission transistor, the first read / write transistor, and the second read / write transistor are N-type transistors; or, The first pull-up transistor and the second pull-up transistor are N-type transistors; The first transmission transistor, the second transmission transistor, the first read / write transistor, and the second read / write transistor are P-type transistors.

3. The static random access memory unit according to claim 1, characterized in that, Along the first direction, adjacent static random access memory cells are mirrored.

4. The static random access memory unit according to claim 1, characterized in that, The channel regions of the first transmission transistor and the second transmission transistor are arranged in the same row along the first direction; The channel regions of the first read / write transistor and the second read / write transistor are arranged in the same row along the first direction.

5. The static random access memory unit according to claim 1, characterized in that, The static random access memory cell further includes a shared bit line and a complementary bit line extending along the first direction; The first interconnect metal structure includes a first conductive substructure and a second conductive substructure extending along the second direction; The first conductive substructure is electrically connected to the active region of the first transmission transistor, and the shared bit line is electrically connected to the first conductive substructure through a via. The second conductive substructure is electrically connected to the active region of the first read / write transistor, and the complementary bit line is electrically connected to the second conductive substructure through a via; Along the second direction, the first conductive substructure and the second conductive substructure are arranged in the same row.

6. The static random access memory unit according to claim 5, characterized in that, The first conductive substructure and the second conductive substructure are disposed between adjacent static random access memory cells; The first conductive substructure is used to simultaneously send the first transmission transistor loading signal to the adjacent static random access memory cell. The second conductive substructure is used to simultaneously apply signals to the second read / write transistors in adjacent static random access memory cells.

7. The static random access memory unit according to claim 5, characterized in that, The first conductive substructure and the second conductive substructure are symmetrically arranged about the second direction.

8. The static random access memory unit according to claim 4, characterized in that, The static random access memory cell further includes a reference voltage line extending along the first direction and a third conductive electronic structure extending along the second direction. The third conductive substructure is electrically connected to the active region of the second transmission transistor and the active region of the second read / write transistor, respectively. The reference voltage line is electrically connected to the third conductive electronic structure through a via.

9. The static random access memory unit according to claim 8, characterized in that, The second transmission transistor includes a first fin extending along a first direction; The second read / write transistor includes a second fin extending along a first direction; Wherein, the orthographic projection of one end of the third conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the first fin onto the semiconductor structure; the orthographic projection of the other end of the third conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the second fin onto the semiconductor structure.

10. The static random access memory unit according to claim 8, characterized in that, The first conductive substructure, the second conductive substructure, and the third conductive substructure are arranged in the same layer.

11. The static random access memory unit according to claim 1, characterized in that, The channel regions of the first pull-up transistor and the second pull-up transistor are arranged in the same column along the second direction.

12. The static random access memory unit according to claim 5, characterized in that, The second interconnect metal structure includes a fourth conductive substructure and a fifth conductive substructure extending along the second direction; There is a gap between adjacent static random access memory cells, and the fourth conductive substructure and the fifth conductive substructure are disposed within the gap; Wherein, the orthogonal projection of the fourth conductive electronic structure onto the semiconductor structure overlaps with the orthogonal projection of the first conductive electronic structure onto the semiconductor structure; The orthogonal projection of the fifth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthogonal projection of the second conductive electronic structure onto the semiconductor structure.

13. The static random access memory unit according to claim 1, characterized in that, The static random access memory unit further includes a power supply voltage line extending along the first direction; The second interconnect metal structure further includes a sixth conductive electronic structure extending along the second direction; The sixth conductive electronic structure is electrically connected to the active regions of the first pull-up transistor and the second pull-up transistor, respectively. The power supply voltage line is electrically connected to the sixth conductive electronic structure through a via.

14. The static random access memory unit according to claim 13, characterized in that, The first pull-up transistor and the second transmission transistor share the first fin extending along the first direction; The second pull-up transistor and the second read / write transistor share the second fin extending along the first direction; Wherein, the orthographic projection of one end of the sixth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the first fin onto the semiconductor structure; the orthographic projection of the other end of the sixth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the second fin onto the semiconductor structure.

15. The static random access memory unit according to claim 1, characterized in that, The first interconnect metal structure further includes a first local interconnect substructure extending along the first direction; the second interconnect metal structure further includes a second local interconnect substructure extending along the first direction; One end of the first local interconnect substructure is electrically connected to the active region of the first transmission transistor, and the other end is electrically connected to the gate structure of the second read / write transistor through a via. One end of the second local interconnect substructure is electrically connected to the active region of the second pull-up transistor, and the other end is electrically connected to the gate structure of the first pull-up transistor through a via; wherein, the orthographic projection of the first local interconnect substructure on the semiconductor structure partially overlaps with the orthographic projection of the second local interconnect substructure on the semiconductor structure.

16. The static random access memory unit according to claim 1, characterized in that, The static random access memory unit further includes: A first power supply structure located on the side of the first interconnect metal structure away from the semiconductor structure; a second power supply structure located on the side of the second interconnect metal structure away from the semiconductor structure; a power supply voltage line and a reference voltage line extending along the first direction; The reference voltage line is located on the second power supply structure; The power supply voltage line is located on the first power supply structure.

17. The static random access memory unit according to claim 1, characterized in that, The gate structure of the second pull-up transistor is electrically connected to the gate structure of the second read / write transistor through a via. Wherein, the first pull-up transistor and the second transmission transistor share a first fin extending along the first direction; The second pull-up transistor and the second read / write transistor share a second fin extending along the first direction; The region where the gate structure of the first pull-up transistor is electrically connected to the gate structure of the second transmission transistor is located in the orthographic projection of the semiconductor structure between the first fin and the second fin in the orthographic projection of the semiconductor structure.

18. A memory, characterized in that, The static random access memory cell includes multiple rows and columns distributed as described in any one of claims 1 to 17.

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