Apparatus for adjusting a retention voltage of a static random access memory and method thereof

Abstract

Embodiments of the present disclosure relate to circuitry for regulating a hold voltage of a static random access memory. A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between a first voltage and a second voltage. A reference voltage generator generates a reference voltage proportional to absolute temperature, an amplitude curve of the reference voltage is based on a control word. A low dropout amplifier sets and maintains the second voltage equal to the reference voltage. A control circuitry generates the control word based on process variation information about the SRAM device. In one example, the control circuitry monitors an alarm bit cell and increments the control word, thereby increasing the amplitude curve of the reference voltage, until the alarm bit cell fails. In another example, the control circuitry measures an oscillation frequency of a ring oscillator, and selects the control word based on the measured oscillation frequency.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 104,222, filed October 22, 2020, the contents of which are incorporated by reference in their entirety as if fully set forth below to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present disclosure relates to the field of static random access memory (SRAM) devices, and in particular to a circuit for setting a hold mode voltage of an SRAM to track temperature and process to reduce power consumption. BACKGROUND

[0004] A conventional SRAM cell 1 is shown in Figure 1 The SRAM cell 1 is formed from cross-coupled inverters 2 and 3. The inverter 2 includes a p-channel transistor MP1 having a source coupled to a SRAM supply voltage VDDX received from a SRAM supply voltage generator 4 that generates the SRAM supply voltage VDDX from a supply voltage VCC, a drain coupled to a drain of an n-channel transistor MN1, and a gate coupled to a gate of the n-channel transistor MN1. The source of the n-channel transistor MN1 is coupled to a SRAM ground voltage GNDX received from a SRAM ground voltage generator 5 that generates the SRAM ground voltage GNDX. The inverter 3 includes a p-channel transistor MP2 having a source coupled to the SRAM supply voltage VDDX, a drain coupled to a drain of an n-channel transistor MN2, and a gate coupled to a gate of the n-channel transistor MN2. The source of the n-channel transistor MN2 is coupled to the SRAM ground voltage GNDX.

[0005] N-channel pass-gate transistors PG1 and PG2 selectively connect the outputs of the cross-coupled inverters 2 and 3 to a bit line BL and a complementary bit line BLB, respectively. The pass-gate transistors PG1 and PG2 are selectively enabled by a word line signal on a word line WL.

[0006] The disclosure herein focuses on the time when the SRAM cell 1 is in a hold mode, i.e., no read or write operation is performed, and instead the SRAM 1 only operates to hold the current state of its inverters 2 and 3. Therefore, for brevity, the circuitry for performing reads and writes is not shown.

[0007] When the SRAM cell 1 is to perform a read or write, the VDDX generator 4 and the GNDX generator 5 set VDDX and GNDX such that the voltage therebetween (VDDX - GNDX) is sufficient to allow the read or write to be performed.

[0008] However, in the hold mode, the voltage (i.e., VDDX-GNDX) between which inverters 2 and 3 are powered can be less than the case when a write operation or a read operation is performed. Thus, VDDX generator 4 and GNDX generator 5 set VDDX and GNDX such that the difference (VDDX-GNDX) therebetween is lower than during the read / write mode. However, if this hold voltage is too low, then the state of inverters 2 and 3 can change and the data stored in the SRAM cell 1 will be lost.

[0009] Conventionally, the SRAM supply voltage generator 4 and the SRAM ground voltage generator 5 are designed such that the hold voltage will be sufficient even for the worst process corner of the slowest batch of SRAM dies expected to be generated. However, while this does result in SRAM cells that effectively hold their state in the hold mode, this design is inefficient because better performing batches of SRAM dies are able to operate with a lower hold voltage than the worse performing batches. Thus, many of the dies generated operate with a higher hold voltage than is necessary to hold the data in the hold mode, resulting in increased leakage current and thus additional power consumption. Since many of the devices into which SRAM is now put are battery operated (e.g., cell phones), this additional power consumption is unnecessary. This additional power consumption problem is perhaps even worse than it sounds because SRAM cells spend a large portion of their operating time in the hold mode.

[0010] Accordingly, further development of the design of SRAM cells is commercially desirable in order to produce SRAM cells that hold the voltage no greater than is necessary to hold their data content during the hold mode. SUMMARY

[0011] In an embodiment, a static random access memory (SRAM) device includes an array of SRAM cells powered between a first voltage and a second voltage in a hold mode; a reference voltage generator configured to generate a reference voltage proportional to absolute temperature, wherein a magnitude curve of the reference voltage as a function of temperature change is based on a control word; a circuit configured to set and maintain the second voltage equal to the reference voltage; and control circuitry configured to generate the control word based on information about the SRAM device.

[0012] The second voltage can be a virtual ground, and the first voltage can be a supply voltage.

[0013] The second voltage can be a virtual supply voltage, and the first voltage can be a ground.

[0014] The control circuitry can include: at least one canary cell configured to fail in a retention mode at a higher than a retention voltage of the array of SRAM cells, wherein the failure in the retention mode includes an undesired change in a state of retention data, and wherein the retention voltage is a difference between a first voltage and a second voltage; a failure detector configured to detect the undesired change in the state of the retention data in the at least one canary cell and generate an output of the failure detector based on the undesired change; and a controller configured to generate a control word based on the output of the failure detector.

[0015] The controller of the control circuitry can be configured to perform the following steps: a) set the control word to a default control word, wherein the reference voltage generator is configured to generate a reference voltage having a magnitude profile that the SRAM device is not expected to fail in a retention mode in response to the default control word; b) increment the control word to a next control word, wherein the reference voltage generator is configured to generate a reference voltage having a magnitude profile that the SRAM device can fail in the retention mode in response to the next control word; c) if the output of the failure detector indicates a failure, then maintain the control word sent to the reference voltage generator at the control word of step b); and d) if the output of the failure detector does not indicate a failure of the canary cell, then return to step b).

[0016] The controller can be configured to perform step a) at each start-up of the SRAM device.

[0017] The at least one canary cell can include a plurality of canary cells, each configured to fail in the retention mode at a higher than the retention voltage of the array of SRAM cells; wherein the failure detector is configured to detect the undesired change in the state of the retention data in the plurality of canary cells and generate its output based on the undesired change.

[0018] The control circuitry can include: a SRAM process monitoring circuit configured to operate in a manner that tracks the array of SRAM cells across process variations; and a process information decoder configured to generate the control word based on the operation of the SRAM process monitoring circuit.

[0019] The reference voltage can track temperature to ensure data within the array of SRAM cells and reduce leakage current within the array of SRAM cells during the retention mode.

[0020] The reference voltage generator can include: a current generator configured to generate a current proportional to absolute temperature having a magnitude profile based on the control word; and a resistor coupled between the current generator and ground, wherein the reference voltage is developed across the resistor.

[0021] The reference voltage generator can comprise: a plurality of reference voltage generators each configured to generate a reference voltage proportional to absolute temperature, wherein the reference voltage generated by each of the plurality of reference voltage generators has an amplitude curve different from one another; and a multiplexer configured to pass the reference voltage generated by one of the plurality of reference voltage generators to the circuit configured to set and maintain the second voltage equal to the reference voltage, wherein the control word defines which of the plurality of reference voltage generators will have its reference voltage passed by the multiplexer.

[0022] The circuit configured to set and maintain the second voltage equal to the reference voltage can be a low-dropout amplifier.

[0023] A method of operating a static random access memory (SRAM) device in a retention mode can comprise: powering an array of SRAM cells powered between a first voltage and a second voltage in the retention mode; detecting process variation information about the array of SRAM cells and generating a control word based on the process variation information; generating a reference voltage proportional to absolute temperature and having an amplitude curve set by the control word; and maintaining the second voltage equal to the reference voltage.

[0024] Generating the control word can comprise the steps of: a) setting the control word to a default control word, wherein the reference voltage is generated in response to the default control word to have an amplitude curve for which the array of SRAM cells is not expected to fail in the retention mode; b) incrementing the control word to a next control word, wherein the reference voltage is generated in response to the next control word to have an amplitude curve for which the array of SRAM cells can fail in the retention mode; c) maintaining the control word of step b) if a failure of the alarm bit cell occurs; and d) returning to step b) if a failure of the alarm bit cell occurs.

[0025] The method can further comprise performing step a) at each start-up of the SRAM device.

[0026] Detecting the process variation information can comprise: operating a ring oscillator formed on a same die as the array of SRAM cells; detecting an oscillation frequency of the ring oscillator; and determining the process variation information based on the oscillation frequency of the ring oscillator.

[0027] Generating the reference voltage can comprise: generating a current proportional to absolute temperature having an amplitude curve set by the control word; and providing the current proportional to absolute temperature to a resistor such that the reference voltage will be formed across the resistor.

[0028] Generating the reference voltage can include selecting one of a plurality of reference voltages based on the control word, each reference voltage being proportional to absolute temperature and having an amplitude curve different from one another, and delivering the selected reference voltage as the reference voltage.

[0029] In an embodiment, an apparatus includes an array of memory cells powered between a first voltage and a second voltage, a reference voltage generator configured to generate a reference voltage proportional to absolute temperature in response to a control word, a circuit configured to set and maintain the second voltage equal to the reference voltage, and a control circuitry configured to generate the control word. The control circuitry includes at least one sentinel bit cell configured to fail at a voltage higher than the array of SRAM cells, wherein failing includes an undesirably altered state of holding data, a failure detector configured to detect an undesirably altered state of holding data in the at least one sentinel bit cell and generate its output based on the undesirably altered state, and a controller configured to generate the control word based on the output of the failure detector.

[0030] The at least one sentinel bit cell can include a plurality of sentinel bit cells, each sentinel bit cell configured to fail at a holding voltage higher than the array of SRAM cells, and the failure detector can be configured to detect an undesirably altered state of holding data in the plurality of sentinel bit cells and generate its output based on the undesirably altered state.

[0031] The controller of the control circuitry can be configured to perform the following steps: a) set the control word to a default control word, b) increment the control word to a next control word, c) if the output of the failure detector indicates a failure, then maintain the control word sent to the reference voltage generator at the control word of step b), and d) if the output of the failure detector does not indicate a failure of the sentinel bit cell, then return to step b).

[0032] In one example, the second voltage can be a virtual ground and the first voltage can be a power supply voltage.

[0033] In another example, the second voltage can be a virtual power supply voltage and the first voltage can be a ground.

[0034] The circuit configured to set and maintain the second voltage equal to the reference voltage can be a low-dropout amplifier.

[0035] The reference voltage generator can include a current generator configured to generate a current proportional to absolute temperature having an amplitude curve based on the control word, and a resistor coupled between the current generator and a ground, wherein the reference voltage is formed across the resistor.

[0036] The reference voltage generator can comprise: a plurality of reference voltage generators, each reference voltage generator configured to generate a reference voltage proportional to an absolute temperature, wherein the reference voltage generated by each of the plurality of reference voltage generators has a different amplitude curve from one another; and a multiplexer configured to pass the reference voltage generated by one of the plurality of reference voltage generators to a circuit configured to set and maintain a second voltage equal to the reference voltage, wherein the control word defines which of the plurality of reference voltage generators is to have its reference voltage passed by the multiplexer. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a schematic block diagram of a prior art SRAM cell.

[0038] Figure 2A is a schematic block diagram of an SRAM array disclosed herein including circuitry for adjusting the hold voltage to reduce power consumption by adjusting the SRAM ground voltage.

[0039] Figure 2B is a schematic block diagram of an SRAM array disclosed herein including circuitry for adjusting the hold voltage to reduce power consumption by adjusting the SRAM supply voltage.

[0040] Figure 3 is a graph showing the SRAM ground voltage generated and used by Figure 2A 's SRAM array as a function of temperature and at different settings.

[0041] Figure 4A is a schematic block diagram of an SRAM array disclosed herein including circuitry for adjusting the hold voltage to reduce power consumption by using an alert bit cell to determine the appropriate SRAM ground voltage based on process.

[0042] Figure 4B is a schematic block diagram of an SRAM array disclosed herein including circuitry for adjusting the hold voltage to reduce power consumption by using an alert bit cell to determine the appropriate SRAM supply voltage based on process.

[0043] Figure 5 is a flowchart illustrating the operation of Figures 4A-4B 's digital controller.

[0044] Figure 6 is a timing diagram showing the operation of Figure 4A 's SRAM array.

[0045] Figure 7AThis is a schematic block diagram of the SRAM array disclosed herein, which includes circuitry for regulating the holding voltage to reduce power consumption by using multiple different alarm bit cells to more accurately determine the appropriate SRAM ground voltage based on the process.

[0046] Figure 7B This is a schematic block diagram of the SRAM array disclosed herein, which includes circuitry for regulating the holding voltage to reduce power consumption (by using multiple different alarm bit cells to more accurately determine the appropriate SRAM power supply voltage based on the process).

[0047] Figure 8A This is a schematic block diagram of an SRAM array disclosed herein, which includes circuitry for regulating the holding voltage to reduce power consumption by using the SRAM process monitoring array to determine the appropriate SRAM ground voltage based on the process.

[0048] Figure 8B This is a schematic block diagram of an SRAM array disclosed herein, which includes circuitry for regulating and holding voltages to reduce power consumption by using an SRAM process monitoring array to determine an appropriate SRAM power supply voltage based on the process.

[0049] Figure 9A This is a schematic block diagram of the SRAM array disclosed herein, in which a multiplexer passes a reference voltage, used as the SRAM ground voltage, from one of a plurality of different reference voltage generators.

[0050] Figure 9B This is a schematic block diagram of the SRAM array disclosed herein, in which a multiplexer passes a reference voltage, used as the SRAM power supply voltage, from one of a plurality of different reference voltage generators. Detailed Implementation

[0051] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the broadest scope consistent with the principles and features disclosed or suggested herein.

[0052] Initial Reference Figure 2A SRAM array 10 is described, which includes a memory array 11 powered between a power supply voltage VDD and a settable SRAM ground voltage GNDX. Since the SRAM ground voltage GNDX is settable, it can be considered as a “virtual” or “floating” ground voltage, and can also be referred to as the SRAM source voltage.

[0053] The memory array 11 is an array of SRAM cells, for example a standard 6-transistor layout with a pair of cross-coupled CMOS inverters, where respective pairs selectively connect the outputs of the cross-coupled inverters to a bit line and a complementary bit line through a gate transistor. However, it should be noted that the SRAM cells of the memory array 11 can have any suitable SRAM structure and are not limited to a 6-transistor design.

[0054] The SRAM ground voltage GNDX can be set by a low-dropout amplifier (LDO) arrangement that maintains the SRAM ground voltage GNDX equal to a set reference voltage VREF_low; this LDO arrangement is formed by an amplifier 12, for example an operational amplifier, whose non-inverting terminal is coupled to a virtual ground node Nvgnd of the memory array 11, whose inverting terminal is coupled to the set reference voltage VREF_low, and whose output is coupled to the gate of an n-channel transistor MN, whose drain is coupled to the virtual ground node Nvgnd of the memory array 11 and whose source is coupled to ground. By “virtual ground node” it is meant a node connected to the source of the n-channel transistor of an SRAM cell within the memory array 11, as will be appreciated by the skilled person.

[0055] The reference voltage VREF_low is set by a programmable current generator 13 that generates a current Iptat proportional to absolute temperature, with a slope proportional to absolute temperature, and the amplitude of the current vs temperature curve of Iptat, which can be referred to as the amplitude curve of Iptat, can be set by a minimum retention voltage control bit RMin received from a controller 14. In particular, by setting the amplitude curve of Iptat, it is meant that the whole curve is shifted up or down, while the slope can or can not remain the same. This Iptat current flowing through a resistor R generates the reference voltage VREF_low at the inverting terminal of the amplifier 12, and as explained, the amplifier 12 maintains GNDX at its output equal to VREF_low. Therefore, the control bit RMin can be seen as setting the amplitude of the voltage vs temperature curve of GNDX, which can be referred to as the amplitude curve of GNDX. By setting the amplitude curve of GNDX, it is meant that the whole curve is shifted up or down, while the slope can or can not remain the same.

[0056] The controller 14 generates the control bit RMin based on known conditions of the SRAM array 10, determination of which will be described below, so that VREF_low produces a maximum value of GNDX at which the retention voltage (VDD - GNDX, for current operating temperature) across the memory array 11 is sufficient to maintain the data stored by it. The effect of varying the control bit RMin on the amplitude curve of GNDX can be seen inFigure 3 The control bit RMin can be changed, for example, to change GNDX from following the P2 amplitude curve to alternatively following the PI amplitude curve. The reason these curves are set to be proportional to absolute temperature is that it has been found that the minimum retention voltage (VDD-GNDX) at which data is properly held by the memory array 11 decreases as operating temperature increases. Thus, by increasing GNDX with temperature, the minimum necessary retention voltage for current operating temperatures is obtained and maintained. As an example, for a certain test memory type, it has been found that the minimum retention voltage is 0.77V at -40°C, 0.74V at 25°C, and 0.71V at 125°C.

[0057] As noted above, the programmable current generator 13 is capable of generating Iptat with a plurality of different amplitude curves, and which of these amplitude curves Iptat has depends on the last received control bit RMin. In some instances, the number of selectable amplitude curves for Iptat can equal the number of states that can be represented by the control bit RMin. For example, if there is one control bit RMin, then there can be two Iptat amplitude curves to choose from, resulting in ultimately two curves PI and P2 for GNDX, as shown in FIG. 3B, for example. In other instances, the number of selectable amplitude curves for Iptat can be less than the number of states that can be represented by the control bit RMin— for example, RMin can be two bits, but there can be three selectable amplitude curves for Iptat, despite the fact that two bits can represent four numbers (binary 00, 01, 10, and 11). Figure 3

[0058] Instead of the SRAM array 10 being powered between the supply voltage VDD and the SRAM ground voltage GNDX, the SRAM array 10 can instead be powered between a SRAM supply voltage VDDX (e.g., a virtual supply voltage) and ground. This arrangement is shown in FIG. 3C, where the illustrated SRAM array 10' is powered between a SRAM supply voltage VDDX and ground. The SRAM supply voltage VDDX is set by an LDO arrangement formed by an amplifier 12 (e.g., an operational amplifier) whose non-inverting terminal is coupled to a virtual supply node Nvdd of the memory array 11, whose inverting terminal is coupled to a settable reference voltage VREF_high, and whose output is coupled to the gate of a p-channel transistor MP. The source of the p-channel transistor MP is coupled to VDD, its drain is coupled to the virtual supply node Nvdd of the memory array 11, and its gate is coupled to the output of the amplifier 12. By "virtual supply node" is meant a node that connects the sources of the p-channel transistors of the SRAM cells within the memory array 11, as will be appreciated by those skilled in the art. Figure 2B ​​

[0059] The reference voltage VREF_high of the SRAM array 10' and thus the SRAM supply voltage VDDX is set by the Ictat current generated by the programmable current generator 13' and flowing through the resistor R, and the amplitude profile of the Ictat current is set by the control bits RMin received from the controller 14, as explained above with reference to Figure 2A Although not shown, the potential amplitude profile of VDDX behaves as the inverse of the profile of GNDX as shown in Figure 3 and thus decreases linearly over the temperature range, since as described, the minimum holding voltage (here VDDX-GND) that is properly held by the memory array 11 decreases as the operating temperature increases.

[0060] An embodiment in which the controller 14 is described will now be described. Reference is made to Figure 4A the SRAM array 20, where it can be seen that the difference compared to Figure 2A is that the controller 24 is shown in detail. Here, the controller 24 comprises an alarm bit cell 25 connected between VDD and GNDX that provides an output to a fault detector 26. The alarm bit cell 25 is a dummy SRAM cell that is intentionally designed to be unbalanced so that its minimum holding voltage (VDD-GNDX) will be slightly higher than the minimum holding voltage of the SRAM cells of the memory array 11. It is noted that the alarm bit cell 25 is formed on the same die (e.g. chip) as the memory array 11 and can be physically positioned in close proximity to the memory 11 on the die and thus tracks the memory array 11 across process variations. The fault detector 26 detects when the state of the alarm bit cell 25 has changed, which indicates that the data contained thereby has been lost, and generates a fault output signal Fout to be received by a digital controller 27 in response thereto.

[0061] Reference is now additionally made to Figures 5-6 describes the operation of the controller 24 for performing a configuration at electronic wafer sort (EWS) using an alarm bit cell and associated circuitry. This is performed for each die to decide on the appropriate RMin value for that lot. In this way, the worst case design approach of setting the virtual ground GNDX or virtual supply voltage VDDS for the worst case is avoided, since each lot is tuned for process while maintaining suitable margins to accommodate statistical variations on each particular die. It is noted that in some instances, this configuration can also be performed periodically, such as at each power on, to track age related drifts.

[0062] Reference is made to Figure 5 the flowchart 100, the controller 24 operates in a calibration phase that starts (see block 101, start) for example at power on. At power on (block 102, power on), the alarm bit cell 25 is programmed to a known state (block 103, program alarm bit cell 25 to known state) and the fault detector 26 is reset (block 104, reset fault detector 26). The alarm bit cell 25 is then read (block 105, read alarm bit cell 25) and the result is compared to the known state (block 106, compare alarm bit cell 25 to known state). If the result is not the known state (block 107, alarm bit cell 25 not equal to known state), then the fault detector 26 is set (block 108, set fault detector 26) and the alarm bit cell 25 is reprogrammed to the known state (block 109, reprogram alarm bit cell 25 to known state). If the result is the known state (block 107, alarm bit cell 25 equal to known state), then the fault detector 26 is reset (block 110, reset fault detector 26) and the alarm bit cell 25 is read again (block 111, read alarm bit cell 25). The result is compared to the known state (block 112, compare alarm bit cell 25 to known state). If the result is not the known state (block 113, alarm bit cell 25 not equal to known state), then the fault detector 26 is set (block 114, set fault detector 26) and the alarm bit cell 25 is reprogrammed to the known state (block 115, reprogram alarm bit cell 25 to known state). If the result is the known state (block 113, alarm bit cell 25 equal to known state), then the calibration phase is complete (block 116, calibration complete) and the controller 24 is ready to operate in the normal phase (block 117, normal phase). Figure 5at time Tl in FIG. 1, the control bit RMin is set by the digital controller 27 to the default value stored in the lookup table. The default value of RMin is such that the amplitude curve of the current Iptat output by the programmable current generator 13 results in a GNDX having an amplitude curve of the voltage across temperature that is sufficiently low to cause the hold voltage (VDD-GNDX) to be sufficient for proper operation, even at the worst corner of a bad performing lot of SRAM dies, regardless of operating temperature.

[0063] Next, at time T2, the control bit RMin is incremented by the digital controller 27 to the next value stored in the lookup table (block 102). For example, the default RMin control bit can be binary 00, and the first increment at block 102 results in the RMin control bit being incremented to binary 01. The programmable current generator 13 responds to the incremented RMin control bit by incrementing the amplitude curve of Iptat from the default value, resulting in the amplitude curve of the generated GNDX being shifted upward compared to the default (meaning that for a given temperature, the GNDX resulting from the incremented RMin control bit is greater than the GNDX resulting from the default RMin control bit). As can be seen between times T2 and T3 in FIG. 1, the value of GNDX is thus greater than the value between times Tl and T2, meaning that the hold voltage (VDD-GNDX) has been reduced. Figure 6

[0064] If the status of the alarm bit cell has not changed, the fault detector 26 de-asserts the fault output signal Fout (block 103). As can be seen in the example of FIG. 1, the fault output signal Fout remains at a logical low between times T2 and T3. It can thus be assumed that the memory array 11 can be operating correctly with the current amplitude curve of GNDX, and that the current hold voltage (VDD-GNDX) is sufficient. Figure 6

[0065] The digital controller 27 then again increments the control bit RMin (block 104) to the next value stored in the lookup table. As explained, this results in the programmable current generator 13 incrementing the amplitude curve of Iptat from the previous value, resulting in the amplitude curve of the generated GNDX being shifted upward compared to its previous setting. As can be seen after time T3, the value of GNDX is greater than the value between times T2 and T3. If the status of the alarm bit cell has changed, the fault detector 26 asserts the fault output signal Fout. As can be seen in the example of FIG. 1, the fault output signal Fout is asserted at time T3. Figure 6 ​​As can be seen, after time T3, the assertion fault output signal Fout indicates that the state of the alarm bit cell has changed. Therefore, the alarm bit cell has failed (block 105), and the digital controller 27 has reached the final setting of the control bit RMin (block 106) – note that the alarm bit cell is specifically designed to be unbalanced so that it fails before the worst SRAM cell in the memory array 11 fails, and the selectable amplitude curve of Iptat is set such that at the first amplitude curve of Iptat when the alarm bit cell 25 fails (when passing through the curve increment), the holding voltage (VDD-GNDX) will be sufficient to allow the memory array 11 to retain data without loss.

[0066] As an alternative to supplying the SRAM array 20 between the power supply voltage VDD and the SRAM ground voltage GNDX, it can alternatively be supplied between the SRAM power supply voltage VDDX (e.g., a dummy power supply voltage) and ground. This arrangement is in Figure 4B As shown, the SRAM array 20' illustrated is powered between the SRAM power supply voltage VDDX and ground. The SRAM power supply voltage VDDX is set by an LDO arrangement that maintains VDDX equal to VREF_high. This LDO arrangement is formed by an amplifier 12 (e.g., an operational amplifier). The non-inverting terminal of the amplifier 12 is coupled to a virtual power supply node Nvdd of the memory array 11, its inverting terminal is coupled to a settable reference voltage VREF_high, and its output is coupled to the gate of a p-channel transistor MP. The source of the p-channel transistor MP is coupled to VDD, its drain is coupled to the virtual power supply node Nvdd of the memory array 11, and its gate is coupled to the output of the amplifier 12. By "virtual power supply node," we mean the node connecting the source of the p-channel transistor of the SRAM cell within the memory array 11, as those skilled in the art will understand.

[0067] The reference voltage VREF_high of the SRAM array 20' and therefore the SRAM power supply voltage VDDX are set by the Ictat current generated by the programmable current generator 13' and flowing through the resistor R. The amplitude curve of the Ictat current is set by the control bit RMin received from the controller 24. As explained in detail above, in addition to the downward shift of the VDDX amplitude curve, each increment of RMin is alternatively shifted upward. It should be noted that here, the alarm bit unit 25' is powered between VDDX and ground.

[0068] It should be understood that multiple alarm bit units can exist alternatively to replace one alarm bit unit 25. Figure 7A This embodiment is shown in the figure, in which the comparison is visible. Figure 4AThe difference is that the controller 24 includes multiple alarm bit cells 35a-35c. Each of the alarm bit cells 35a-35c is intentionally designed to be unbalanced such that its minimum retention voltage (VDD-GNDX) will be higher than that of the SRAM cells of the memory array 11.

[0069] In some examples, each of the alarm bit cells 35a-35c is intentionally designed such that its unbalance is different from the other alarm bit cells 35a-35c. For example, alarm bit cell 35a can be designed such that its minimum retention voltage (VDD-GNDX) will be a first amount higher than that of the SRAM cells of the memory array 11, alarm bit cell 35b is designed such that its minimum retention voltage (VDD-GNDX) will be a second amount higher than that of the SRAM cells of the memory array 11, and alarm bit cell 35c is designed such that its minimum retention voltage (VDD-GNDX) will be a third amount higher than that of the SRAM cells of the memory array 11, where the third amount is less than the second amount, and the second amount is less than the first amount.

[0070] In other examples, each of the alarm bit cells 35a-35c can have the same unbalance as each other.

[0071] The fault detector 36 monitors the state of each of the alarm bit cells 35a-35c and generates a fault output signal Fout having a number of bits capable of representing the number of alarm bit cells that are present (since any number of alarm bit cells can be present). Here, since there are three alarm bit cells 35a-35c, the fault output signal Fout is a two-bit signal.

[0072] The digital controller 37 can operate like the digital controller 27 described above by setting the control bit RMin to a default value at startup and then incrementing the control bit RMin while monitoring the fault output signal Fout. The digital controller 37 may, for example, increment the control bit RMin until two of the three alarm bit cells 35a-35c have failed, or until one of the three alarm bit cells 35a-35c has failed.

[0073] Instead of the SRAM array 30 being powered between the supply voltage VDD and the SRAM ground voltage GNDX, it can instead be powered between a SRAM supply voltage VDDX (e.g., a virtual supply voltage) and ground. This arrangement is in Figure 7BThe SRAM array 30' is powered between SRAM supply voltage VDDX and ground, as shown in the middle, where the illustrated SRAM array 30' is powered between SRAM supply voltage VDDX and ground. The SRAM supply voltage VDDX is set by an LDO arrangement that maintains VDDX equal to VREF_high, formed by an amplifier 12, e.g., an operational amplifier, whose non-inverting terminal is coupled to a virtual supply node Nvdd of the memory array 11, whose inverting terminal is coupled to a settable reference voltage VREF_high, and whose output is coupled to the gate of a p-channel transistor MP. The source of the p-channel transistor MP is coupled to VDD, its drain is coupled to the virtual supply node Nvdd of the memory array 11, and its gate is coupled to the output of the amplifier 12. By "virtual supply node" is meant a node that connects the sources of the p-channel transistors of the SRAM cells within the memory array 11, as will be appreciated by those skilled in the art.

[0074] The reference voltage VREF_high and thus the SRAM supply voltage VDDX of the SRAM array 30' is set by the Ictat current generated by the programmable current generator 13' and flowing through the resistor R, and the amplitude curve of the Ictat current is set by the control bits RMin received from the controller 34', as explained in detail above. It is noted that here the alarm bit unit 35' is powered between VDDX and ground.

[0075] Reference is now made to Figure 8A Another alternative configuration of the controller 14 without an alarm bit unit is described. In this example of the SRAM memory 40, the controller 44 includes an SRAM process monitoring circuit 45 powered between the supply voltage VDD and the SRAM ground voltage GNDX, and a process information decoder 47 that receives an output from the SRAM process monitoring circuit 45.

[0076] The SRAM process monitoring circuit 45 is a circuit that tracks the performance of the memory array 11 for process variations. Thus, the SRAM process monitoring circuit 45 is on the same die as the memory array 11, and can be located immediately adjacent to that die. The process information decoder 47 detects the performance of the SRAM process monitoring circuit 45, and generates the RMin bits based on that performance. The process information decoder 47 can be located on the same die as the SRAM process monitoring circuit 45 and the memory array 11, but is alternatively located in a test fixture used at manufacturing time in some examples.

[0077] As an example, the SRAM process monitoring circuit 45 can be a ring oscillator, whose specific frequency indicates the condition of the die (e.g., low performing means a higher retention voltage is needed compared to average or high performing dies to prevent data loss in retention mode, average performing means a higher retention voltage is needed compared to high performing dies but lower than low performing dies, or high performing means a lower retention voltage is needed compared to low performing and average performing dies); the lower the frequency, the lower the performance of the die. Thus, in the case where the SRAM process monitoring circuit 45 is a ring oscillator, the process information decoder 47 can be a counter that detects the frequency of the ring oscillator SRAM process monitoring circuit 45 and selects the appropriate RMin bit from a lookup table based on the detected frequency (which maintains the minimum retention voltage without data failure in retention mode).

[0078] As an alternative to the SRAM array 40 being powered between the supply voltage VDD and the SRAM ground voltage GNDX, it can alternatively be powered between a SRAM supply voltage VDDX (e.g., a virtual supply voltage) and ground. This arrangement is shown in Figure 8B where the illustrated SRAM array 40’ is powered between a SRAM supply voltage VDDX and ground. The SRAM supply voltage VDDX is set by an LDO arrangement that maintains VDDX equal to VREF_high, which LDO arrangement is formed by an amplifier 12 (e.g., an operational amplifier) whose non-inverting terminal is coupled to a virtual supply node Nvdd of the memory array 11, whose inverting terminal is coupled to a settable reference voltage VREF_high, and whose output is coupled to the gate of a p-channel transistor MP. The source of the p-channel transistor MP is coupled to VDD, its drain is coupled to the virtual supply node Nvdd of the memory array 11, and its gate is coupled to the output of the amplifier 12. By “virtual supply node” is meant a node that connects the sources of the p-channel transistors of the SRAM cells within the memory array 11, as will be appreciated by those skilled in the art.

[0079] The reference voltage VREF_high, and thus the SRAM supply voltage VDDX, of the SRAM array 40’ is set by a programmable current generator 13’ that generates a current complementary to an absolute temperature Ictat current that flows through a resistor R, and the amplitude curve of the Ictat current is set by control bits RMin received from a controller 44’, as explained in detail above. Note that here, the SRAM processing circuit 45 is powered between VDDX and ground.

[0080] Figure 9AAn example is shown in SRAM array 10” where controller 44 is not shown (and can take any form disclosed herein) and where instead of a programmable current generator, there is a programmable voltage generator 13” that generates VREF_low proportional to absolute temperature. Programmable current generator 13” includes n number of reference voltage generators 13a-13n that generate different reference voltages proportional to absolute temperature, respectively. Each reference voltage generated thus has the same (or similar but not identical) voltage versus temperature slope, but has a different amplitude curve from one another. Thus, for example, the voltage versus temperature curve generated by reference voltage generator 13a can be generally the same as the voltage versus temperature curve generated by reference voltage generator 13b, but shifted up, and the voltage versus temperature curve generated by reference voltage generator 13n can be generally the same as the voltage versus temperature curve generated by reference voltage generator 13b, but shifted up.

[0081] In operation, multiplexer 13z receives RMin bits as input and passes a voltage from one of reference voltage generators 13a-13n as reference voltage VREF_low fed to the inverting input of amplifier 12.

[0082] As an alternative to SRAM array 10” being powered between supply voltage VDD and SRAM ground voltage GNDX, it can alternatively be powered between SRAM supply voltage VDDX (e.g. virtual supply voltage) and ground. This arrangement is shown in Figure 9B SRAM supply voltage VDDX is set by an LDO arrangement that maintains VDDX equal to VREF_high, formed by amplifier 12 (e.g. operational amplifier) whose non-inverting terminal is coupled to virtual supply node Nvdd of memory array 11, whose inverting terminal is coupled to settable reference voltage VREF_high, and whose output is coupled to the gate of p-channel transistor MP. The source of p-channel transistor MP is coupled to VDD, its drain is coupled to virtual supply node Nvdd of memory array 11, and its gate is coupled to the output of amplifier 12. By “virtual supply node” is meant a node that connects the sources of p-channel transistors of SRAM cells within memory array 11, as will be appreciated by those skilled in the art.

[0083] Reference voltage VREF_high, and thus SRAM supply voltage VDDX, of SRAM array 10”’ is set by multiplexer 13z that selects output to pass from one of reference voltage generators 13a-13n based on RMin bits.

[0084] In the above example, calibration (where RMin is determined and GNDX or VDDX is set) is performed each time the device is powered up (or at electronic wafer sort, EWS). This thus facilitates adjustment of the hold voltage (VDD - GNDX or VDDX - GND) over time, which can be useful because the performance of SRAM cells can change with aging and because the voltage actually generated by the LDO in response to different RMin bits can change with aging.

[0085] However, it should be understood that calibration can be performed only once during the manufacturing step, where the RMin bits remain unchanged during subsequent power - ups of the device. It should also be understood that calibration can alternatively be performed periodically during operation of the device, or can alternatively be performed at every given number of power - ups of the device (e.g., once every 10 power - ups).

[0086] In the above examples ( Figure 2A 、 2B ; 4A, 4B; 7A, 7B; 8A; 8B; and 9A, 9B), embodiments are shown in which GNDX or VDDX is generated and regulated (A and B versions for each example, respectively). However, for each example, the two illustrated embodiments can be combined, where the memory array is powered between VDDX and GNDX, and the techniques and hardware described for each embodiment are used to regulate both VDDX and GNDX.

[0087] Although the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art to which the present disclosure pertains will appreciate that other embodiments can be designed without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A static random access memory (SRAM) device, comprising: An array of SRAM cells is powered between a first voltage and a second voltage in hold mode; A reference voltage generator is configured to generate a reference voltage proportional to absolute temperature, wherein the amplitude curve of the reference voltage according to temperature changes is based on a control word; The circuit is configured to set and maintain the second voltage equal to the reference voltage; as well as A control circuit is configured to generate the control word based on information about the SRAM device.

2. The SRAM device of claim 1, wherein the second voltage is a virtual ground and the first voltage is a power supply voltage.

3. The SRAM device of claim 1, wherein the second voltage is a virtual power supply voltage and the first voltage is ground.

4. The SRAM device of claim 1, wherein the control circuitry comprises: At least one alarm bit cell is configured to fail in hold mode at a hold voltage higher than that of the array of SRAM cells, wherein the failure in hold mode includes an undesirable change in the state of the hold data, and wherein the hold voltage is the difference between the first voltage and the second voltage; A fault detector is configured to detect an undesirable change in the state of the held data in the at least one alarm bit unit, and to generate the output of the fault detector based on the undesirable change. as well as The controller is configured to generate the control word based on the output of the fault detector.

5. The SRAM device of claim 4, wherein the controller of the control circuitry is configured to perform the following steps: a) Set the control word as the default control word, wherein the reference voltage generator is configured to generate the reference voltage having an amplitude curve in which the SRAM device is not expected to fail in hold mode in response to the default control word; b) Increment the control word to a next control word, wherein the reference voltage generator is configured to generate the reference voltage having an amplitude curve in which the SRAM device would fail in hold mode in response to the next control word; c) If the output of the fault detector indicates a fault, the control word sent to the reference voltage generator is maintained at the control word in step b); as well as d) If the output of the fault detector does not indicate a fault in the alarm bit unit, then return to step b).

6. The SRAM device of claim 5, wherein the controller is configured to perform step a) at each startup of the SRAM device.

7. The SRAM device of claim 4, wherein the at least one alarm bit unit comprises a plurality of alarm bit units, each alarm bit unit being configured to fail in a hold mode at a hold voltage above the hold voltage of the array of SRAM units; and wherein the fault detector is configured to detect an undesired change in the state of the hold data in the plurality of alarm bit units, and to generate an output of the fault detector based on the undesired change.

8. The SRAM device of claim 1, wherein the control circuitry comprises: The SRAM process monitoring circuit is configured to operate in a manner that tracks the array of SRAM cells across process variations; as well as The process information decoder is configured to generate the control word based on the operation of the SRAM process monitoring circuit.

9. The SRAM device of claim 1, wherein the reference voltage tracks temperature to protect data within the array of SRAM cells during hold mode and reduce leakage current within the array of SRAM cells.

10. The SRAM device of claim 1, wherein the reference voltage generator comprises: A current generator is configured to generate a current with an amplitude curve proportional to absolute temperature based on the control word. as well as A resistor is coupled between the current generator and ground, wherein the reference voltage is formed across the resistor.

11. The SRAM device of claim 1, wherein the reference voltage generator comprises: Multiple reference voltage generators, each configured to generate a reference voltage proportional to absolute temperature, wherein the reference voltage generated by each of the multiple reference voltage generators has a different amplitude profile from each other; as well as A multiplexer is configured to pass a reference voltage generated by one of the plurality of reference voltage generators to a circuit configured to set and maintain a second voltage equal to the reference voltage, wherein a control word defines which of the plurality of reference voltage generators will have its reference voltage passed by the multiplexer.

12. The SRAM device of claim 1, wherein the circuit configured to set and maintain the second voltage equal to the reference voltage is a low-dropout amplifier.

13. A method of operating a static random access memory (SRAM) device in retention mode, the method comprising: In hold mode, an array of SRAM cells powered between a first voltage and a second voltage is supplied. Detect process variation information regarding the array of SRAM cells, and generate a control word based on the process variation information; A reference voltage is generated that is proportional to the absolute temperature and has an amplitude curve set by the control word; as well as The second voltage is maintained at an equal level to the reference voltage.

14. The method of claim 13, wherein generating the control word comprises the following steps: a) Set the control word as the default control word, wherein the reference voltage is generated in response to the default control word as an amplitude curve in which the array of SRAM cells is not expected to fail in hold mode; b) Increment the control word to the next control word, wherein the reference voltage is generated in response to the next control word as an amplitude curve of the array having the SRAM cells that would fail in hold mode; c) If a fault occurs in the alarm bit unit, maintain the control word described in step b); as well as d) If a fault occurs in the alarm bit unit, return to step b).

15. The method of claim 14, further comprising performing step a) at each startup of the SRAM device.

16. The method of claim 13, wherein detecting the process change information comprises: A ring oscillator is formed on the same die as the array of SRAM cells; Detect the oscillation frequency of the ring oscillator; as well as The process change information is determined based on the oscillation frequency of the ring oscillator.

17. The method of claim 13, wherein generating the reference voltage comprises: Generate a current that is proportional to the absolute temperature and has an amplitude curve set by the control word; as well as The current, which is proportional to the absolute temperature, is supplied to the resistor so that the reference voltage is formed across the resistor.

18. The method of claim 13, wherein generating the reference voltage comprises: Based on the control word, one of a plurality of reference voltages is selected, each reference voltage being proportional to absolute temperature and having a different amplitude curve from the others; as well as The selected reference voltage is transmitted as the reference voltage.

19. A memory device, comprising: An array of memory cells is powered between a first voltage and a second voltage; A reference voltage generator is configured to generate a reference voltage proportional to absolute temperature in response to a control word; The circuit is configured to set and maintain the second voltage equal to the reference voltage; as well as A control circuit device is configured to generate the control word; The control circuit device includes: At least one alarm bit unit is configured to fail at a voltage higher than that of the array of memory units, wherein the failure includes an undesirable change in the state of the data being held. A fault detector is configured to detect unintended changes in the state of the held data in the at least one alarm bit unit, and to generate an output of the fault detector based on the unintended changes; and The controller is configured to generate the control word based on the output of the fault detector.

20. The memory device of claim 19, wherein the at least one alarm bit unit comprises a plurality of alarm bit units, each alarm bit unit being configured to fail at a holding voltage above the array of memory cells; and wherein the fault detector is configured to detect an undesired change in the state of the holding data in the plurality of alarm bit units and generate an output of the fault detector based on the undesired change.

21. The memory device of claim 19, wherein the controller of the control circuitry is configured to perform the following steps: a) Set the control word as the default control word; b) Increment the control word to the next control word; c) If the output of the fault detector indicates a fault, the control word sent to the reference voltage generator is maintained at the control word in step b); as well as d) If the output of the fault detector does not indicate a fault in the alarm bit unit, then return to step b).

22. The memory device of claim 19, wherein the second voltage is a virtual ground and the first voltage is a power supply voltage.

23. The memory device of claim 19, wherein the second voltage is a virtual power supply voltage and the first voltage is ground.

24. The memory device of claim 19, wherein the circuit configured to set and maintain the second voltage equal to the reference voltage is a low-dropout amplifier.

25. The memory device of claim 19, wherein the reference voltage generator comprises: A current generator is configured to generate a current with an amplitude curve proportional to absolute temperature based on the control word. as well as A resistor is coupled between the current generator and ground, wherein the reference voltage is formed across the resistor.

26. The memory device of claim 19, wherein the reference voltage generator comprises: Multiple reference voltage generators, each configured to generate a reference voltage proportional to absolute temperature, wherein the reference voltage generated by each of the multiple reference voltage generators has a different amplitude profile from each other; as well as A multiplexer is configured to pass a reference voltage generated by one of the plurality of reference voltage generators to a circuit configured to set and maintain a second voltage equal to the reference voltage, wherein a control word defines which of the plurality of reference voltage generators will have its reference voltage passed by the multiplexer.

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