Memory device including charge pump circuit

Abstract

The memory device includes: a memory cell array comprising a plurality of memory cells; and a voltage generator configured to supply voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current based on the number of pump units that have received an input voltage. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation to generate a stage control signal for controlling the number of pump units to be driven.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0119304, filed on October 5, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some exemplary embodiments of the present invention relate to semiconductor devices, and more specifically, to memory devices including charge pump circuitry. Background Technology

[0004] Recently, there has been an increasing demand for highly integrated and high-capacity non-volatile semiconductor memory devices. Flash memory, primarily used in portable electronic devices, is a representative example of such non-volatile semiconductor memory devices. During the programming operation of a non-volatile memory device, a relatively high voltage is applied. To generate such a relatively high voltage, a voltage generator can be provided in the non-volatile memory device to amplify the input voltage to the non-volatile memory device. The voltage generator may include a charge pump. A charge pump is a direct-to-direct-current (DC) converter used to generate a voltage higher than the input voltage or lower than ground. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide memory devices including charge pump circuitry that can mitigate or prevent the generation of large peak currents and / or reduce the power consumed by the charge pump circuitry.

[0006] According to some exemplary embodiments of the present invention, a memory device includes: a memory cell array comprising a plurality of memory cells; and a voltage generator configured to supply voltage to the memory cell array. The voltage generator may include: a charge pump circuit comprising n pump units and configured to output a pump voltage and a pump current based on the number of pump units among the n pump units that have received an input voltage, where n is a natural number equal to or greater than 2; a switching circuit configured to output the pump voltage; and a stage controller configured to receive an input signal corresponding to the pump current and perform a stage control operation, the stage control operation including generating a stage control signal, the stage control signal being a signal for controlling the number of pump units among the n pump units that have received the input voltage.

[0007] According to some exemplary embodiments of the present invention, a memory device includes: a charge pump circuit comprising a plurality of pump units and configured to output a pump voltage and a pump current based on the number of pump units among the plurality of pump units that have received an input voltage; a switching circuit configured to output the pump voltage and the pump current; and a stage controller configured to receive an input signal corresponding to the pump current from the switching circuit and generate a stage control signal for controlling stages of the charge pump circuit. The memory device may be configured to increase the number of pump units that have received the input voltage as the number of stages of the charge pump circuit increases.

[0008] According to some exemplary embodiments of the present invention, a memory device includes: a charge pump circuit comprising a plurality of pump units and configured to output a pump voltage and a pump current; and a stage controller configured to perform stage control operations controlling the number of pump units to be driven among the plurality of pump units. The stage controller may include: a pump current replication circuit configured to receive an input signal corresponding to the pump current and generate a replication voltage corresponding to the pump current; a pump current detector configured to output a reference signal based on the replication voltage and a reference voltage; and a stage control signal generator configured to generate a stage control signal for controlling a stage of the charge pump circuit based on the reference signal. Attached Figure Description

[0009] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a memory device including a charge pump circuit according to an exemplary embodiment of the present invention;

[0011] Figure 2 This is a block diagram illustrating a voltage generator for a memory device according to an exemplary embodiment of the present invention;

[0012] Figure 3 This is a block diagram illustrating an exemplary embodiment of a charge pump circuit according to a concept of the present invention;

[0013] Figure 4 This is a block diagram illustrating an exemplary embodiment of a pump unit according to a concept of the present invention;

[0014] Figure 5 This is a block diagram illustrating an example embodiment of a level controller according to a concept of the present invention;

[0015] Figure 6 This is a view illustrating the operation of a level controller according to an exemplary embodiment of the concept of the present invention;

[0016] Figure 7This is a circuit diagram illustrating the switching circuit, pump current replication circuit, and pump current detector included in an exemplary embodiment of a voltage generator according to the present invention.

[0017] Figure 8 This is a view illustrating the operation of a level controller according to an exemplary embodiment of the concept of the present invention;

[0018] Figure 9 This is a block diagram illustrating a voltage generator for a memory device according to an exemplary embodiment of the present invention;

[0019] Figure 10 This is a block diagram illustrating an example embodiment of a level controller according to a concept of the present invention;

[0020] Figure 11 This is a view illustrating the operation of a level controller according to an exemplary embodiment of the concept of the present invention;

[0021] Figure 12 This is a block diagram illustrating a voltage generator for a memory device according to an exemplary embodiment of the concept of the present invention; and

[0022] Figure 13 This is a block diagram illustrating an example of applying a memory device employing a charge pump circuit to a solid-state drive (SSD) system according to an exemplary embodiment of the present invention. Detailed Implementation

[0023] Some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0024] It should be understood that although the terms first, second, third, etc., may be used herein to describe various values, elements, components, regions, layers, and / or portions, these values, elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one value, element, component, region, layer, or portion from another value, element, component, region, layer, or portion. Therefore, without departing from the teachings of the exemplary embodiments, the first value, first element, first component, first region, first layer, or first portion discussed below may be referred to as a second value, second element, second component, second region, second layer, or second portion.

[0025] Figure 1 This is a block diagram illustrating a memory device 10 including a charge pump circuit according to an exemplary embodiment of the present invention.

[0026] Memory device 10 may be, for example, a NAND flash memory device. However, exemplary embodiments of the inventive concept are not limited to NAND flash memory devices. For example, memory device 10 may include NOR flash memory devices, resistive random access memory (RRAM) devices, phase-change random access memory (PRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, spin-transfer torque random access memory (STT-RAM) devices, etc. Furthermore, according to some exemplary embodiments, memory device 10 may be implemented with a three-dimensional array structure. For example, memory device 10 may include a vertical NAND flash memory device with a three-dimensional array structure. The inventive concept can be applied to charge-trapped flash memory (CTF) memory devices in which the charge storage layer includes an insulating layer and to flash memory devices in which the charge storage layer is formed by a conductive floating gate.

[0027] refer to Figure 1 The memory device 10 includes a voltage generator 100, a row decoder 200, a memory cell array 300, a page buffer circuit 400, and control logic 500. Although Figure 1 Although not shown, the memory device 10 may also include data input and output circuitry or input and output interfaces. Furthermore, although not shown, the memory device 10 may also include various sub-circuits, such as error correction circuitry for correcting errors in data read from the memory cell array 300.

[0028] Voltage generator 100 can receive an external voltage EVC supplied from an external device (e.g., a memory controller or host). Voltage generator 100 can generate various internal voltages IVC based on the external voltage EVC using a voltage control signal CTRL_vol. These internal voltages IVC are used to perform programming, reading, and erasing operations on the memory cell array 300. For example, voltage generator 100 can generate word line voltages, programming voltages, read voltages, pass voltages, erase verification voltages, or programming verification voltages. Additionally, voltage generator 100 can also generate serial select line voltages and ground select line voltages based on the voltage control signal CTRL_vol. Furthermore, voltage generator 100 can also generate bit line voltages based on the voltage control signal CTRL_vol.

[0029] Voltage generator 100 may include charge pump circuit 110 and stage controller 130. Charge pump circuit 110 may receive an external voltage EVC supplied from an external device and may generate a pump voltage based on the external voltage EVC. Charge pump circuit 110 may include a first pump unit through an nth pump unit, each pump unit receiving the external voltage EVC. Depending on the stage of charge pump circuit 110, the number of pump units receiving the external voltage EVC in the first through nth pump units may vary. For example, in a first stage, one pump unit may receive the external voltage EVC, and in a second stage, two pump units may receive the external voltage EVC. In other words, the term "stage" or "stage of charge pump circuit" may refer to the number of pump units from the first through nth pump units that will be driven.

[0030] The stage controller 130 can control the stages of the charge pump circuit 110 based on the magnitude of the pump current generated by the charge pump circuit 110. Figure 1 The diagram shows a stage controller 130 included within a voltage generator 100. However, the memory device 10 according to the present invention is not limited thereto. For example, the stage controller 130 may be included within control logic 500.

[0031] The voltage generator 100 of the memory device 10, according to some exemplary embodiments of the present invention, may include a charge pump circuit 110 and a stage controller 130. Therefore, the generation of large peak currents during operation can be prevented by controlling the stages of the charge pump circuit 110. Furthermore, the voltage generator 100 of the memory device 10 can control the stages of the charge pump circuit 110 by sensing the pump current output from the charge pump circuit 110. Therefore, power consumption can be reduced and / or operating speed can be increased during operation.

[0032] The row decoder 200 can select one of the memory blocks BLK1 to BLKz in response to the row address X-ADDR. The row decoder 200 can select one of the word lines WL of the selected memory block, and can also select one of a plurality of string select lines SSL. Furthermore, the row decoder 200 receives an internal voltage IVC from the voltage generator 100 and can send voltages for performing memory operations to the word lines WL of the selected memory block. For example, during an erase operation, the row decoder 200 can send erase voltage and verification voltage to the selected word lines, and can send pass voltage to the unselected word lines.

[0033] The memory cell array 300 may include multiple memory cells. For example, the multiple memory cells included in the memory cell array 300 may be non-volatile memory cells that retain stored data even if power is interrupted. The memory cell array 300 may be connected to the serial select line SSL, word line WL, ground select line GSL, and bit line BL. For example, the memory cell array 300 may be connected to the line decoder 200 via the serial select line SSL, word line WL, and ground select line GSL, and may also be connected to the page buffer circuit 400 via the bit line BL.

[0034] The memory cell array 300 includes multiple memory blocks BLK1 to BLKz. Each of the multiple memory blocks BLK1 to BLKz can have a planar structure or a three-dimensional structure. The memory cell array 300 can have at least one of the following: a single-layer cell block including a single-layer cell (SLC), a multi-layer cell block including a multi-layer cell (MLC), a three-layer cell block including a three-layer cell (TLC), and a four-layer cell block including a four-layer cell (QLC). For example, some of the memory blocks BLK1 to BLKz can be single-layer cell blocks, while other memory blocks can be multi-layer cell blocks, three-layer cell blocks, or four-layer cell blocks.

[0035] Page buffer circuit 400 can send and receive data DATA from outside the memory device 10. Page buffer circuit 400 can select some of the bit lines BL in response to column address Y-ADDR. Page buffer circuit 400 can operate as a write driver or a read amplifier.

[0036] Control logic 500 can output various control signals, such as voltage control signal CTRL_vol, row address X-ADDR, and column address Y-ADDR, to program, read, or erase data DATA stored in memory cell array 300 based on command CMD, address ADDR, and control signal CTRL. For example, control logic 500 can receive command CMD, address ADDR, and control signal CTRL from a memory controller external to memory device 10. Therefore, control logic 500 can fully control various operations within memory device 10.

[0037] Figure 2 This is a block diagram illustrating a voltage generator for a memory device according to an exemplary embodiment of the present invention.

[0038] refer to Figure 2 The voltage generator 100 may include a charge pump circuit 110, a switching circuit 120, and a stage controller 130. The charge pump circuit 110 may include multiple pump units 111.

[0039] An input voltage V_in and an input current I_in can be supplied to the charge pump circuit 110 from an external source. At this time, the input voltage V_in can be... Figure 1 The external voltage EVC. The charge pump circuit 110 can output a pump voltage V_pump by increasing the input voltage V_in. At this time, the charge pump circuit 110 can generate a pump current I_pump to output the pump voltage V_pump.

[0040] In the charge pump circuit 110, the operating stage can be changed according to the received stage control signal SCS. An input voltage V_in can be applied to each of the plurality of pump units 111. Depending on the stage of the charge pump circuit 110, the number of pump units with the input voltage V_in applied to them can be changed. That is, depending on the stage of the charge pump circuit 110, the number of pump units operating in the plurality of pump units 111 can be changed. For example, in the first stage, one pump unit operates, while in the second stage, two pump units can operate.

[0041] Switching circuit 120 can output the pump voltage V_pump from charge pump circuit 110 to the outside as an output voltage V_out. For example, switching circuit 120 can output the pump voltage V_pump from control logic (e.g., Figure 1 The 500) receives control signals (e.g., Figure 1 The CTRL_vol) can be used to output the pump voltage V_pump as the output voltage V_out. At this time, the switching circuit 120 can generate an output current I_out to output the output voltage V_out.

[0042] When the memory device initiates one of the programming, reading, or erasing operations, an output voltage V_out and an output current I_out can be output to the outside of the voltage generator 100 to charge the cells included in the memory cell array 300. For example, when the charging operation of the charge pump circuit 110 is completed, the charged memory cell can be represented as a capacitor. Therefore, the charge pump circuit 110 reaches a steady state, the output voltage V_out can reach the target voltage, and thus the output current I_out can decrease and stabilize to a certain value.

[0043] Stage controller 130 can receive a signal SIP corresponding to the pump current I_pump from switching circuit 120. Stage controller 130 can obtain information about the magnitude of the pump current I_pump from the signal SIP. Stage controller 130 can control the stages of charge pump circuit 110 based on the information about the magnitude of the pump current I_pump. Stage controller 130 can output a stage control signal SCS to charge pump circuit 110 based on the information about the magnitude of the pump current I_pump. References will be made below. Figure 5 Describe the configuration of level controller 130.

[0044] Figure 3 This is a block diagram illustrating an example embodiment of a charge pump circuit 110 according to a concept of the present invention.

[0045] refer to Figure 2 and Figure 3 The charge pump circuit 110 may include first pump units 111_1 to nth pump units 111_n, and first voltage switches 112_1 to nth voltage switches 112_n. Here, n is a natural number equal to or greater than 3. The first pump units 111_1 to nth pump units 111_n can be connected consecutively. Figure 4 The internal configuration of each of the first pump unit 111_1 to the nth pump unit 111_n is described in the text.

[0046] The first voltage switch 112_1 to the nth voltage switch 112_n can be selectively switched on / off. Therefore, the input voltage V_in can be applied to each pump unit according to the switching operation of the first voltage switch 112_1 to the nth voltage switch 112_n. The corresponding switching signals SCSC1 to SCSCn can be applied to the first voltage switch 112_1 to the nth voltage switch 112_n respectively, and thus the on / off operation of the first voltage switch 112_1 to the nth voltage switch 112_n can be controlled. At this time, the switching signals SCSC1 to SCSCn provided to the first voltage switch 112_1 to the nth voltage switch 112_n respectively can be changed according to the stage control signal SCS received from the stage controller 130.

[0047] In an example embodiment, the stage control signal SCS can be formed by n-bit codes SCSC1 to SCSCn, and these bits can respectively correspond to different voltage switches among the first voltage switch 112_1 to the nth voltage switch 112_n. For example, in the stage control signal SCS, the first code SCSC1 can be provided to the first voltage switch 112_1, the second code SCSC2 can be provided to the second voltage switch 112_2, and the nth code SCSCn can be provided to the nth voltage switch 112_n.

[0048] In the example embodiment, the stage control signal SCS is not formed by an n-bit code, but may include an upgrade signal for increasing the number of stages in the charge pump circuit 110 and a downgrade signal for decreasing or reducing the number of stages in the charge pump circuit 110. The charge pump circuit 110 may increase the number of operating pump units upon receiving the upgrade signal and decrease the number of operating pump units upon receiving the downgrade signal.

[0049] In the charge pump circuit 110, the operating stage can be changed according to the received stage control signal SCS. Depending on the stage of the charge pump circuit 110, the number of pump units to which the input voltage V_in is applied in the first pump unit 111_1 to the nth pump unit 111_n can be changed. For example, in the first stage, the input voltage V_in is applied to the first pump unit 111_1, thus driving one pump unit. In the second stage, the input voltage V_in is applied to the first pump unit 111_1 and the second pump unit 111_2, thus driving two pump units. In the nth stage, the input voltage V_in is applied to the first pump unit 111_1 to the nth pump unit 111_n, thus driving n pump units.

[0050] As the number of driving pump units increases, the charge pump circuit 110 can generate a relatively high voltage as the target level while simultaneously outputting a large pump current I_pump. Therefore, as the number of driving pump units increases, the time spent on the pump voltage V_pump to reach the target level (e.g., settling time) can be reduced.

[0051] On the other hand, as the number of drive pump units increases, the power consumed by the charge pump circuit 110 can increase. Furthermore, as the number of drive pump units increases, the peak value of the input current I_in input to the charge pump circuit 110 can increase. Therefore, the operation of the components supplying power to the memory device can become unstable, and the input voltage V_in supplied to the memory device can become unstable.

[0052] In some exemplary embodiments of the memory device according to the present invention, the number of pump units driven in the first pump unit 111_1 to the nth pump unit 111_n included in the charge pump circuit 110 can be controlled according to the stage control signal SCS. Therefore, the operating speed can be increased by reducing power consumption and / or setup time or preventing excessive increase in power consumption and / or setup time.

[0053] Figure 4 This is a block diagram illustrating an example embodiment of a pump unit according to a concept of the present invention. Figure 4 This illustrates the case where the input voltage V_in is provided to the first pump unit 111_1. Figure 3 The first pump unit 111_1. Figure 4The pump unit shown is merely an example. Pump units can be configured with... Figure 4 This is one implementation of a variety of different forms shown. Figure 4 In, it is shown Figure 3 The first pump unit 111_1. The same configuration can be applied to... Figure 3 The second pump unit 111_2 to the nth pump unit 111_n.

[0054] refer to Figure 4 The first pump unit 111_1 may include multiple transistors Q0 to Q4 and multiple capacitors C0 to C4. The multiple transistors Q0 to Q4 may include n-type metal-oxide-semiconductor (NMOS) transistors. The drain terminals and gate terminals of transistors Q0 to Q4 are connected to each other and can operate as diodes. Figure 4 The diagram shows a first pump unit 111_1 comprising five transistors Q0 to Q4 and five capacitors C0 to C4. However, the pump unit conceived according to the present invention is not limited thereto. The number of transistors and capacitors can be varied.

[0055] The first clock signal CLK1 or the second clock signal CLK2 can be input through the first capacitor C1 to the fourth capacitor C4, excluding the output capacitor C0 connected to the output terminal. In the example embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be complementary.

[0056] During the first half-cycle, the first clock signal CLK1 is low and the second clock signal CLK2 can be high, and the first capacitor C1 can be charged by the input voltage V_in. During the second half-cycle, the first clock signal CLK1 is high and the second clock signal CLK2 can be low, and the voltage of the first capacitor C1 can be increased (or boosted) by the first clock signal CLK1 to twice the input voltage V_in. Furthermore, the first transistor Q1 is off and the second transistor Q2 is on, so the voltage of the second capacitor C2 can be increased to twice the input voltage V_in.

[0057] In the second half of the cycle, when the first clock signal CLK1 is again set to low and the second clock signal CLK2 is set to high, the voltage of the second capacitor C2 is increased by the second clock signal CLK2 to three times the input voltage V_in, and the third capacitor C3 can be charged by the voltage of the second capacitor C2. Through this operation, the first pump voltage V_pump1 can be generated by amplifying the input voltage V_in. That is, when the number of transistors included in the first pump unit 111_1 is i, the first pump voltage V_pump1 can be amplified up to i times the input voltage V_in.

[0058] Figure 5 This is a block diagram illustrating a level controller 130 according to an exemplary embodiment of the present invention.

[0059] refer to Figure 2 and 5 The stage controller 130 may include a pump current replication circuit 131, a pump current detector 132, and a stage control signal generator 133.

[0060] The pump current replication circuit 131 can receive a signal SIP corresponding to the pump current I_pump from the switching circuit 120. The pump current replication circuit 131 can generate a replication voltage VR based on the signal SIP corresponding to the pump current I_pump, the magnitude of which corresponds to the magnitude of the pump current I_pump. In an example embodiment, the pump current replication circuit 131 may include a current mirror circuit and a current-to-voltage conversion circuit. For example, the current-to-voltage conversion circuit of the pump current replication circuit 131 may include a variable resistor R, and the magnitude of the replication voltage VR may be proportional to the magnitude of the variable resistor R.

[0061] Pump current detector 132 can receive the replicated voltage VR output from pump current replication circuit 131. Pump current detector 132 can generate a reference signal CS based on replicated voltage VR and reference voltage Vref. For example, pump current detector 132 can compare replicated voltage VR with reference voltage Vref and generate reference signal CS based on the comparison result. In this case, reference signal CS can be referred to as comparison signal. In an example embodiment, pump current detector 132 can be implemented by analog-to-digital converter (ADC). In this case, reference voltage Vref can be provided externally or can be generated in pump current detector 132.

[0062] For example, the pump current detector 132 can output a first-level (e.g., high-level) reference signal CS when the replication voltage VR is greater than the reference voltage Vref, and can output a second-level (e.g., low-level) reference signal CS when the replication voltage VR is less than or equal to the reference voltage Vref. The operation of the pump current detector 132 according to the present invention is not limited thereto. It can output a low-level reference signal CS when the replication voltage VR is greater than the reference voltage Vref, and can output a high-level reference signal CS when the replication voltage VR is less than or equal to the reference voltage Vref.

[0063] In an example embodiment, the pump current detector 132 can generate a reference signal CS based on a replicated voltage VR and multiple reference voltages (e.g., Vref1 and Vref2). For example, the pump current detector 132 can compare the replicated voltage VR with multiple reference voltages (e.g., Vref1 and Vref2) and generate the reference signal CS based on the comparison result. In this case, the reference signal CS can be referred to as a comparison signal.

[0064] The stage control signal generator 133 can receive a reference signal CS from the pump current detector 132 and can output a stage control signal SCS. In this case, the operation of the stage control signal generator 133, which outputs the stage control signal SCS, can be changed according to the operation period. The control operation of the stage controller 130 can be divided into operations in a first time period P1 and operations in a second time period P2 based on a pre-specified first reference time tp1 (see...). Figure 6 In an example embodiment, the charge pump circuit 110 performs a charging operation on the memory cell during a first time period, and can complete the charging operation during a second time period.

[0065] In an example embodiment, after the operation of the memory device begins, during a first period of charging the memory cells, when the reference signal CS transitions from a first level (e.g., high level) to a second level (e.g., low level), the stage control signal generator 133 can output a stage control signal SCS that increases the stage. On the other hand, after the first period (e.g., during...) Figure 6 In the second time period after tp1, when the reference signal CS changes from the second level to the first level, the stage control signal generator 133 can output the stage control signal SCS that reduces the number of stages.

[0066] In an example embodiment, the stage control signal generator 133 can receive information about a first reference time tp1 from an external source, which is the start time of the second time period. For example, data corresponding to the first reference time tp1 can be stored in the stage control signal generator 133, and based on the pre-stored data about the first reference time tp1, the operations of the first time period and the operations of the second time period can be performed separately. In an example embodiment, the stage control signal generator 133 can detect the first reference time tp1 as the start time of the second time period. For example, the stage control signal generator 133 can detect the first reference time tp1 as the start time of the second time period by detecting the charge pump circuit (e.g., Figure 3 The charge pump circuit 110 reaches the maximum stage (e.g., the nth stage) at the time point to obtain the first reference time tp1. The operation of the stage control signal generator 133 according to the present invention is not limited to this.

[0067] According to the foregoing example embodiments, the memory device can change the number of stages in the charge pump circuit based on the magnitude of the pump current I_pump output from the charge pump circuit. Therefore, the memory device can increase the pump current I_pump by sensing that the magnitude of I_pump is insufficient and increasing the number of stages. Furthermore, the memory device can control the number of stages (e.g., the maximum number of stages) after checking the magnitude of the pump current I_pump so that it does not operate at an undesirably high stage from the start of the operation where the charge pump circuit generates the pump voltage V_pump. Therefore, power consumption can be reduced. The memory device can further reduce power consumption by reducing the number of stages in the charge pump circuit (e.g., the maximum number of stages) during a second time period.

[0068] Figure 6 This is a view illustrating the operation of a level controller according to an exemplary embodiment of the concept of the present invention. Figure 6 This is a view showing the stage variation according to the magnitude of the pump current, and includes a graph showing the pump current variation over time. The charge pump circuit in the comparative example operates at stage (K+2) without stage variation. Figure 6 The operation of the level controller shown is merely an example, and the operation of the level controller conceived according to the present invention is not limited thereto.

[0069] refer to Figure 2 , Figure 5 and Figure 6 When the charge pump circuit 110 of the exemplary embodiment of the present invention begins to operate, the charge pump circuit 110 can operate at a predetermined K level. At this time, K can be any number, which is a natural number equal to or greater than 1.

[0070] The stage controller 130 can control the stages of the charge pump circuit 110. The operation of the stage controller 130 can be divided into operations in a first time period P1 and operations in a second time period P2 based on a first reference time tp1. The charge pump circuit 110 can perform the operation of charging the memory cells in the first time period P1 and can complete the charging operation in the second time period P2.

[0071] Data corresponding to the first reference time tp1 can be pre-stored in the stage controller 130. In some example embodiments, the stage controller 130 can detect the first reference time tp1. The stage controller 130 can output a stage control signal SCS based on the first reference time tp1. In example embodiments, the stage control signal SCS may include an upgrade signal SCS_UP and a downgrade signal SCS_DOWN, and the stage controller 130 can output the upgrade signal SCS_UP in a first time period P1 and the downgrade signal SCS_DOWN in a second time period P2.

[0072] When the charge pump circuit 110 starts operating, the pump current I_pump can increase to the magnitude of the peak current I_peak. In the charge pump circuit 110 according to the exemplary embodiment, K pump units can operate, and in the charge pump circuit according to the comparative example, (K+2) pump units can operate. Therefore, the magnitude of the peak current I_peak of the charge pump circuit 110 according to the exemplary embodiment can be less than the magnitude of the peak current Ic_peak of the charge pump circuit according to the comparative example. Therefore, according to the exemplary embodiment, damage to devices external to the memory device due to undesirable high peak currents generated in the memory device according to the comparative example can be prevented, thereby stably providing input voltage to the memory device.

[0073] After the pump current I_pump reaches the peak current I_peak, the pump current I_pump gradually decreases and can reach the reference current at a first time t1. At the first time t1, the pump current replication circuit 131 can generate a replication voltage VR corresponding to the pump current I_pump based on the signal SIP corresponding to the pump current I_pump. At this time, the replication voltage VR can be equal to the reference voltage Vref. Because the replication voltage VR gradually decreases and reaches the reference voltage Vref, the pump current detector 132 can output a reference signal CS that transitions from a high level to a low level. The stage control signal generator 133 can receive the reference signal CS that transitions from a high level to a low level and can output an upgrade signal SCS_UP for adding a stage. The charge pump circuit 110 can receive the upgrade signal SCS_UP and can operate at the (K+1)th stage. As the stage of the charge pump circuit 110 increases, the pump current I_pump can increase again to a certain magnitude.

[0074] The magnitude of the pump current I_pump can be reduced again, reaching the magnitude of the reference current at a second time t2. The pump current replication circuit 131 can generate a replication voltage VR corresponding to the magnitude of the pump current I_pump based on the signal SIP corresponding to the pump current I_pump. At the second time t2, the magnitude of the replication voltage VR can be equal to the magnitude of the reference voltage Vref. Because the replication voltage VR gradually decreases and reaches the reference voltage Vref, the pump current detector 132 can output a reference signal CS that transitions from a high level to a low level. The stage control signal generator 133 can receive the reference signal CS and output an upgrade signal SCS_UP for increasing the stage. The charge pump circuit 110 can receive the upgrade signal SCS_UP and can operate at the (K+2)th stage. As the stages of the charge pump circuit 110 increase, the magnitude of the pump current I_pump can be increased again to a certain value. Because the charge pump circuit 110 performs a charging operation in the first time period P1, the stage controller 130 can control the magnitude of the pump current I_pump to be equal to or greater than the magnitude of the reference current, and can reduce the settling time spent on the pump voltage V_pump reaching the target voltage.

[0075] At time t3 in the second time period P2, the pump current I_pump decreases again and can reach the reference current. The pump current replication circuit 131 can generate a replication voltage VR based on the signal SIP corresponding to the pump current I_pump, the magnitude of which corresponds to the pump current I_pump. At time t3, the replication voltage VR can be equal to the reference voltage Vref. Because the replication voltage VR gradually decreases and reaches the reference voltage Vref, the pump current detector 132 can output a reference signal CS that transitions from low to high. The stage control signal generator 133 can receive the reference signal CS and output a degradation signal SCS_DOWN for reducing the stage. The charge pump circuit 110 can receive the degradation signal SCS_DOWN and can operate at stage (K+1). Because the charging operation of the charge pump circuit 110 is completed in the second time period, the number of pump units driving the charging operation can be reduced, thereby reducing power consumption.

[0076] Figure 7 This is a circuit diagram illustrating a voltage generator including a switching circuit, a pump current replication circuit, and a pump current detector in an exemplary embodiment according to the present invention. Figure 7 The circuit diagram is the same as Figure 6 The example configuration corresponds to the operation of the intermediate controller. Therefore, the voltage generator conceived according to the present invention is not limited to this, and various circuit configurations can be used.

[0077] refer to Figure 5 and Figure 7 The switching circuit 120 may include multiple transistors. For example, the switching circuit 120 may include M transistors. In this case, M can be a natural number equal to or greater than 2.

[0078] The pump current replication circuit 131 may include a current mirror circuit 131_1 and a current-to-voltage conversion circuit 131_2. The current mirror circuit 131_1 can receive a signal SIP corresponding to the pump current I_pump, reduce the pump current I_pump to 1 / M, and replicate the reduced pump current I_pump to 1 / M. The current-to-voltage conversion circuit 131_2 can convert the replicated current 1 / M·I_pump into a replicated voltage VR.

[0079] The current mirror circuit 131_1 can be connected to both ends of the switching circuit 120 and can receive the voltage between the two ends of the switching circuit 120 as a signal SIP corresponding to the pump current I_pump. In an example embodiment, the current mirror circuit 131_1 may include two transistors and an operational amplifier. The configuration of the current mirror circuit is not limited thereto. The current mirror circuit 131_1 may have one of various circuit configurations that reduce the pump current I_pump to 1 / M and can output a current 1 / M·I_pump.

[0080] In the example embodiment, the current-to-voltage conversion circuit 131_2 can be implemented by a variable resistor R connected to ground. The value of the variable resistor R can be determined according to control logic (e.g., Figure 1 The control logic 500 can be changed. For example, the value of the variable resistor R can be controlled to compensate for the offset of the current mirror circuit 131_1. In some example embodiments, such as... Figure 10 As shown, the value of the variable resistor R can be controlled to detect the memory cell array (e.g., Figure 1 The memory cell array 300 includes defective memory cells.

[0081] In an example embodiment, the pump current detector 132 may be implemented using an ADC. For example, the pump current detector 132 may include two comparators COMP1 and COMP2 and an SR latch.

[0082] The replication voltage VR and the first reference voltage Vref1 can be input to the first comparator COMP1, and the replication voltage VR and the second reference voltage Vref2 can be input to the second comparator COMP2. At this time, one of the first reference voltage Vref1 and the second reference voltage Vref2 can be compared with... Figure 5 The reference voltage Vref is greater than the offset, and the other of the first reference voltage Vref1 and the second reference voltage Vref2 can be greater than the offset. Figure 5The offset is smaller than the reference voltage Vref. For example, the first reference voltage Vref1 may be larger than the reference voltage Vref by the offset, and the second reference voltage Vref2 may be smaller than the reference voltage Vref by the offset.

[0083] The first comparator COMP1 can output a high-level signal when the replication voltage VR is greater than the first reference voltage Vref1, and a low-level signal when the replication voltage VR is less than the first reference voltage Vref1. The second comparator COMP2 can output a low-level signal when the replication voltage VR is greater than the second reference voltage Vref2, and a high-level signal when the replication voltage VR is less than the second reference voltage Vref2.

[0084] The SR latch can receive signals from the first comparator COMP1 and the second comparator COMP2, and can output a reference signal CS. For example, when the SR latch receives a low-level signal from the first comparator COMP1 and a high-level signal from the second comparator COMP2, that is, when the replication voltage VR is less than the second reference voltage Vref2, the SR latch can output a low-level reference signal CS. When the SR latch receives a high-level signal from the first comparator COMP1 and a low-level signal from the second comparator COMP2, that is, when the replication voltage VR is greater than the first reference voltage Vref1, the SR latch can output a high-level reference signal CS. When the SR latch receives a low-level signal from the first comparator COMP1 and a low-level signal from the second comparator COMP2, that is, when the replication voltage VR is less than the first reference voltage Vref1 and greater than the second reference voltage Vref2, the SR latch can output a reference signal CS with the same level as the previously output reference signal CS.

[0085] Therefore, the pump current detector 132 can output a low-level reference signal CS when the replication voltage VR is less than the second reference voltage Vref2, output a high-level reference signal CS when the replication voltage VR is greater than the first reference voltage Vref1, and output a reference signal CS with the same level as the previously output reference signal CS when the replication voltage VR has a value between the first reference voltage Vref1 and the second reference voltage Vref2. In the example embodiment, when the reference signal CS changes from high to low, the stage control signal generator 133 can output a stage control signal SCS.

[0086] Figure 7The pump current detector 132 shown includes two comparators, COMP1 and COMP2, and therefore may not sense changes in a certain offset relative to the reference voltage Vref. The pump current detector 132 according to the example embodiment may include a comparator. The replication voltage VR and the reference voltage Vref can be input to this comparator. Therefore, when the replication voltage VR is greater than the reference voltage Vref, the reference signal CS may be high, and when the replication voltage VR is less than the reference voltage Vref, the reference signal CS may be low.

[0087] Figure 8 This is a view illustrating the operation of a level controller according to an exemplary embodiment of the concept of the present invention.

[0088] refer to Figure 5 and Figure 8 The pump current detector 132 can receive the replicated voltage VR as an analog signal and can generate a reference signal CS based on the replicated voltage VR and multiple reference voltages Vref1 and Vref2. Figure 8 The diagram shows two reference voltages. However, the pump current detector of an exemplary embodiment of the invention can compare the replicated voltage VR with three or more reference voltages.

[0089] For example, the pump current detector 132 can receive the replication voltage VR and output a 2-bit reference signal CS. When the replication voltage VR is greater than the first reference voltage Vref1, the pump current detector 132 can output a reference signal CS of 11. When the replication voltage VR is less than the second reference voltage Vref2, the pump current detector 132 can output a reference signal CS of 01. When the replication voltage VR has a value between the first reference voltage Vref1 and the second reference voltage Vref2, the pump current detector 132 can output a reference signal CS of 10.

[0090] During the first time period before the first reference time tp1, when the reference signal CS of 11 is received, the stage control signal generator 133 can generate the stage control signal SCS, and thus the charge pump circuit (e.g., Figure 2 The charge pump circuit 110 can operate at the first stage. During the first time period, when a reference signal CS of 10 is received, the stage control signal generator 133 can generate a stage control signal SCS, and therefore the charge pump circuit 110 can operate at the second stage. Furthermore, during the first time period, when a reference signal CS of 01 is received, the stage control signal generator 133 can generate a stage control signal SCS, and therefore the charge pump circuit 110 can operate at the third stage. That is, the stage corresponding to the magnitude of the replication voltage VR in the first time period can be predetermined.

[0091] According to an exemplary embodiment of the present invention, the stage controller 130 can, based on the magnitude of the replica voltage VR corresponding to the pump current, except... Figure 7 and Figure 8 One of the various methods besides the configuration shown is used to control the level.

[0092] Figure 9 This is a block diagram illustrating a voltage generator 100a of a memory device according to an exemplary embodiment of the present invention. Figure 9 In the middle, it will no longer be repeated with Figure 2 The component has the same description as the component.

[0093] refer to Figure 9 The voltage generator 100a may include a charge pump circuit 110, a switching circuit 120, and a stage controller 130a. The charge pump circuit 110 may include multiple pump units 111 (e.g., 111_1 to 111_n). The number of driving pump units may vary depending on the stage.

[0094] The stage controller 130a can terminate stage control operations in response to a stage controller control signal CSC received from an external source. In an example embodiment, when an operation on a memory cell (e.g., one of a programming, reading, and erasing operation) is completed, the stage controller 130a can receive the stage controller control signal CSC and terminate stage control operations on the charge pump circuit, thereby reducing power consumption.

[0095] In the example embodiment, in response to a level controller control signal CSC received from an external source, level controller 130a can terminate level control operation and perform an error detection operation regarding one of the memory cell array and voltage generator. The level control operation of level controller 130a can be coupled with… Figure 2 The level control operation of level controller 130 is the same. In the example embodiment, when an operation is performed on a memory cell, the level controller control signal CSC can be received, and level controller 130a can perform an error detection operation. The level controller control signal CSC can be included in... Figure 1 The voltage control signal CTRL_vol is used. The stage controller 130a can receive the signal SIP corresponding to the pump current I_pump from the switching circuit 120. The stage controller 130a can obtain information about the magnitude of the pump current I_pump based on the signal SIP corresponding to the pump current I_pump.

[0096] The stage controller 130a can determine that an error has occurred when the pump current I_pump is greater than the reference current. For example, when a faulty memory cell is included in a memory cell performing one of the programming, reading, or erasing operations, the pump current I_pump may be greater than the reference current, and the stage controller 130a can determine that an error has occurred. Furthermore, for example, when a defective transistor included in the charge pump circuit 110 or the switching circuit 120 generates a loss current, the pump current I_pump may be greater than the reference current, and the stage controller 130a can determine that an error has occurred.

[0097] When an error is detected, the stage controller 130a can output the error detection signal EDS to the control logic (e.g., Figure 1 The control logic 500 (in the example embodiment) can receive an error detection signal EDS, determine that a working memory cell includes a faulty memory cell, and process the memory block including the faulty memory cell as a bad block. Figure 10 The configuration of the level controller 130a is described in the middle.

[0098] Figure 10 This is a block diagram illustrating an example embodiment of a level controller according to a concept of the present invention. Figure 11 This is a view illustrating the operation of a level controller according to an exemplary embodiment of the concept of the present invention. Figure 10 This is a view showing the intermediate controller performing error detection operations in the third time period P3. Figure 11 This is a graph showing the pump current over time when programming a normal memory cell is performed, and it is also shown in contrast to the graph showing the pump current over time when the control stage is adjusted according to the magnitude of the pump current. Figure 6 The curves are the same. In Figure 11 The example described below illustrates the scenario where a memory device performs a programming operation. However, the same description can be applied when performing a read or erase operation.

[0099] refer to Figures 9 to 11 The stage controller 130a may include a pump current replication circuit 131a, a pump current detector 132a, and a stage control signal generator 133a. When a programming operation is performed on the memory cell, at the second reference time tp2, the stage controller 130a may receive a stage controller control signal CSC. In response to the stage controller control signal CSC, the stage controller 130a may perform an error detection operation in a third time period P3 after the second reference time tp2.

[0100] When no error is detected, the pump current I_pump in the third time period P3 can be smaller than the pump current I_pump in another time period, and can be stable. For example, when the programmed memory cells do not include faulty memory cells, the pump current I_pump can be reduced and can be stable. On the other hand, when the programmed memory cells include faulty memory cells, leakage current can occur, and therefore the pump current I_pump can be larger than in the case where no error is detected. Figure 11 The diagram only shows the case including a faulty memory cell. However, the inventive concept is not limited to this. For example, when a defective transistor is included in the switching circuit, a loss current is generated, and therefore the magnitude of the pump current I_pump can be greater than in the case where no error is detected. The pump current replication circuit 131a can receive a signal SIP corresponding to the pump current I_pump from the switching circuit 120. The pump current replication circuit 131a can generate a replication voltage VR_f based on the signal SIP corresponding to the pump current I_pump, the magnitude of which corresponds to the magnitude of the pump current I_pump.

[0101] In an example embodiment, the pump current replication circuit 131a may include a current mirror circuit and a current-to-voltage conversion circuit, and the current-to-voltage conversion circuit may be implemented by a variable resistor R_f connected to ground. After a stage control operation, when an error detection operation begins, the value of the variable resistor R_f in the pump current replication circuit 131a may be increased. That is, in response to the stage controller control signal CSC, the value of the variable resistor R_f included in the pump current replication circuit 131a may be increased.

[0102] The pump current I_pump during the stage controller 130a's error detection operation (e.g., in the third time period P3) can be smaller than the pump current I_pump during the stage controller 130a's stage control operation (e.g., in the first time period P1 and the second time period P2). Therefore, when the stage controller 130a performs the error detection operation, the variable resistor of the pump current replication circuit 131a can be increased, and thus the pump current detector 132a can easily detect the replicated voltage VR_f.

[0103] Pump current detector 132a can receive the replication voltage VR_f output from pump current replication circuit 131a. Pump current detector 132a can generate a reference signal CS_f based on replication voltage VR_f and reference voltage Vref_f. For example, pump current detector 132a can compare replication voltage VR_f with reference voltage Vref_f and generate reference signal CS_f based on the comparison result. Because the pump current I_pump when stage controller 130a performs error detection operation (e.g., in the third period P3) is less than the pump current I_pump when stage controller 130a performs stage control operation (e.g., in the first period P1 and the second period P2), the reference voltage Vref_f during error detection operation can be lower than the reference voltage during stage control operation. Therefore, replication voltage VR_f can be easily detected. At this time, the value of reference voltage Vref_f can be a voltage value corresponding to the maximum value of pump current I_pump after normal memory cell is programmed. Reference voltage Vref_f can be provided externally or generated in pump current detector 132a.

[0104] For example, the pump current detector 132a can output a high-level reference signal CS_f when the replication voltage VR_f is higher than the reference voltage Vref_f, and can output a low-level reference signal CS_f when the replication voltage VR_f is equal to or lower than the reference voltage Vref_f. The operation of the pump current detector 132a according to the present invention is not limited to this. When the replication voltage VR_f is higher than the reference voltage Vref_f, a low-level reference signal CS_f can be output, and when the replication voltage VR_f is equal to or lower than the reference voltage Vref_f, a high-level reference signal CS_f can be output.

[0105] The stage control signal generator 133a can receive a reference signal CS_f from the pump current detector 132a and can output an error detection signal EDS. For example, when the replication voltage VR_f is higher than the reference voltage Vref_f, the stage control signal generator 133a can receive a high-level reference signal CS_f and can output the error detection signal EDS to the control logic (e.g., Figure 1 (Control logic 500).

[0106] exist Figure 10In the present invention, when the stage controller 130a performs an error detection operation, the variable resistor R_f included in the pump current replication circuit 131a increases, and the reference voltage Vref_f in the pump current detector 132a decreases. However, the inventive concept is not limited thereto. In some example embodiments, when the stage controller 130a performs an error detection operation, the variable resistor R_f included in the pump current replication circuit 131a decreases, and the reference voltage Vref_f in the pump current detector 132a may increase.

[0107] Figure 12 This is a block diagram illustrating a voltage generator 100b of a memory device according to an exemplary embodiment of the present invention. Figure 12 In the middle, it will no longer be repeated with Figure 2 The component has the same description as the component.

[0108] refer to Figure 12 The voltage generator 100b may include a charge pump circuit 110b, a switching circuit 120, a stage controller 130b, and a pump clock generator 140b. The charge pump circuit 110b may include multiple pump units 111. The inventive concept is not limited to... Figure 12 The stage controller 130b and the pump clock generator 140b can be components of the memory device and are located outside the voltage generator 100b.

[0109] The stage controller 130b can receive a signal SIP corresponding to the pump current I_pump from the switching circuit 120. The stage controller 130b can obtain information about the magnitude of the pump current I_pump from the signal SIP corresponding to the pump current I_pump.

[0110] The stage controller 130b can control the stages of the charge pump circuit 110b based on information about the magnitude of the pump current I_pump. The stage controller 130b can output a stage control signal SCS to the charge pump circuit 110b based on the magnitude of the pump current I_pump. Furthermore, the stage controller 130b can control the frequency of the pump clock signal PCLK provided to the charge pump circuit 110b based on the magnitude of the pump current I_pump. The stage controller 130b can output a clock control signal CCLK to the pump clock generator 140b based on the magnitude of the pump current I_pump. In an example embodiment, the stage control signal generator (not shown) included in the stage controller 130b can output the clock control signal CCLK to the pump clock generator 140b based on the magnitude of the pump current I_pump.

[0111] Pump clock generator 140b can generate a pump clock signal PCLK and can provide the pump clock signal PCLK to charge pump circuit 110b. For example, the pump clock signal PCLK may include... Figure 4 The first clock signal CLK1 and the second clock signal CLK2.

[0112] In an example embodiment, the pump clock generator 140b may be an oscillator. The pump clock generator 140b may receive a clock control signal CCLK from the stage controller 130b and generate a pump clock signal PCLK frequency based on the clock control signal CCLK. For example, the pump clock generator 140b may generate a pump clock signal PCLK with a frequency that increases to an integer multiple or decreases to an integer fraction relative to the fundamental frequency, based on the clock control signal CCLK.

[0113] As the frequency of the pump clock signal PCLK increases, the charge pump circuit 110b can generate a high voltage at the target level while outputting a large pump current I_pump. Therefore, as the number of driving pump units increases, the settling time spent for the pump voltage V_pump to reach the target level can be reduced. On the other hand, as the frequency of the pump clock signal PCLK increases, the power consumption of the charge pump circuit 110b can increase.

[0114] According to an example embodiment, the memory device can control the stages of the charge pump circuit 110b and the pump clock signal PCLK provided to the charge pump circuit 110b by sensing the pump current I_pump. Therefore, power consumption or setup time can be reduced, or excessive increases in power consumption or setup time can be prevented. Consequently, operating speed can be increased.

[0115] Figure 13 This is a block diagram illustrating an example of applying a memory device employing a charge pump circuit to a solid-state drive (SSD) system 1000 according to an exemplary embodiment of the present invention.

[0116] refer to Figure 13 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can send signals to and receive signals from the host 1100 via a signal connector SIG, and can receive power via a power connector PWR. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. At this time, references can be used... Figures 1 to 12The above example embodiments are used to implement the SSD 1200. Each of the memory devices 1230, 1240, and 1250 may include a charge pump circuit 1232 and a stage controller for controlling the stage of the charge pump circuit 1232. Therefore, when performing operations (e.g., one of programming, reading, and erasing operations), the SSD system 1000 can reduce power consumption and / or increase operating speed depending on the magnitude of the pump current.

[0117] While the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A memory device comprising: A memory cell array, which includes multiple memory cells; and A voltage generator is configured to supply voltage to the memory cell array. The voltage generator includes, A charge pump circuit comprising n pump units and configured to output pump voltage and pump current based on the number of pump units among the n pump units that have received an input voltage, where n is a natural number equal to or greater than 2. A switching circuit, configured to output the pump voltage, and A stage controller is configured to receive an input signal corresponding to the pump current and perform stage control operations, the stage control operations including generating a stage control signal, which is a signal for controlling the number of pump units out of the n pump units that have received the input voltage. The level controller includes: A pump current replication circuit is configured to receive the input signal corresponding to the pump current and generate a replication voltage corresponding to the pump current. A pump current detector, configured to output a reference signal based on the replicated voltage and the reference voltage; and A stage control signal generator is configured to generate the stage control signal based on the reference signal.

2. The memory device according to claim 1, in, The charge pump circuit further includes n voltage switches configured to selectively apply the input voltage to one or more corresponding pump units among the n pump units, and The n voltage switches are configured to be turned on in response to the stage control signal.

3. The memory device according to claim 1, wherein, The pump current replication circuit includes a variable resistor connected to the ground power supply.

4. The memory device according to claim 1, wherein, The pump current detector is configured to output the reference signal based on the replicated voltage, the first reference voltage, and the second reference voltage having a level lower than the first reference voltage.

5. The memory device according to claim 4, wherein, The pump current detector is configured as follows: When the level of the replication voltage is higher than the level of the first reference voltage, the reference signal of the first level is output. When the level of the replication voltage is lower than the level of the second reference voltage, the reference signal at the second level is output. When the level of the replication voltage is between the level of the first reference voltage and the level of the second reference voltage, the reference signal of the third level is output, which is the same level as the previously output reference signal.

6. The memory device according to claim 1, wherein, The stage control signals include upgrade signals for increasing the number of pump units that have received the input voltage and downgrade signals for decreasing the number of pump units that have received the input voltage.

7. The memory device according to claim 1, further comprising: A pump clock generator is configured to provide a pump clock signal to the charge pump circuit. The stage controller is further configured to generate a clock control signal for controlling the pump clock generator based on the input signal corresponding to the pump current.

8. The memory device according to claim 7, wherein, The pump clock generator is also configured to change the frequency of the pump clock signal according to the clock control signal.

9. The memory device according to claim 1, wherein, The level controller is also configured to terminate the level control operation when a level controller control signal is received from outside the level controller.

10. The memory device according to claim 1, wherein, The stage controller is also configured to, when receiving a stage controller control signal from outside the stage controller, perform an operation to detect an error generated in one of the memory cell array and the voltage generator based on the input signal corresponding to the pump current.

11. The memory device according to claim 10, wherein, When the programming operation for the memory cell is completed, the level controller control signal is input to the level controller.

12. A memory device comprising: A charge pump circuit includes multiple pump units and is configured to output pump voltage and pump current based on the number of pump units among the multiple pump units that have received an input voltage. A switching circuit configured to output the pump voltage and the pump current; and A stage controller is configured to receive an input signal corresponding to the pump current from the switching circuit, generate a stage control signal for controlling a stage of the charge pump circuit, and output the stage control signal to the charge pump circuit based on information about the magnitude of the pump current. The memory device is configured to increase the number of pump units that have received the input voltage as the number of stages in the charge pump circuit increases. The level controller includes: A pump current replication circuit is configured to receive the input signal corresponding to the pump current and generate a replication voltage corresponding to the pump current. A pump current detector, configured to output a reference signal based on the replicated voltage and the reference voltage; and A stage control signal generator is configured to generate the stage control signal based on the reference signal.

13. The memory device according to claim 12, in, The charge pump circuit also includes a voltage switch configured to selectively apply the input voltage to one or more of the plurality of pump units, respectively. The voltage switch is configured to be turned on in response to the stage control signal.

14. A memory device comprising: A charge pump circuit comprising multiple pump units and configured to output pump voltage and pump current; and A level controller is configured to perform level control operations that control the number of pump units to be driven among the plurality of pump units. The level controller includes, A pump current replication circuit is configured to receive an input signal corresponding to the pump current and generate a replication voltage corresponding to the pump current. A pump current detector, configured to output a reference signal based on the replicated voltage and the reference voltage, and A stage control signal generator is configured to generate stage control signals for controlling the charge pump circuit based on the reference signal.

15. The memory device of claim 14, further comprising: A pump clock generator is configured to provide pump clock signals with different frequencies to the charge pump circuit. The stage control signal generator is further configured to receive the input signal corresponding to the pump current and generate a clock control signal for controlling the pump clock generator.

16. The memory device according to claim 15, in, The stage control signals include upgrade signals for increasing the stage of the charge pump circuit and downgrade signals for decreasing the stage of the charge pump circuit. The level control signal generator is configured to generate the upgrade signal in a first time period and the downgrade signal in a second time period based on the reference signal.

17. The memory device according to claim 14, wherein, The stage controller is configured to terminate the stage control operation when a stage controller control signal is received from outside the stage controller, and to perform an error detection operation for detecting faulty memory cells based on the input signal corresponding to the pump current.

18. The memory device according to claim 17, wherein, The stage control signal generator is also configured to output an error detection signal based on the reference signal.

19. The memory device according to claim 17, in, The pump current replication circuit includes a variable resistor connected to ground power, and Wherein, the first value of the variable resistor when performing the error detection operation is greater than the second value of the variable resistor when performing the stage control operation.

20. The memory device according to claim 17, wherein, The first level of the reference voltage when performing the error detection operation is lower than the second level of the reference voltage when performing the level control operation.

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