Semiconductor device

Abstract

A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction; a first gate contact and a dummy gate contact spaced apart from each other in the first horizontal direction and in contact with a top surface of the first gate electrode; a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to an upper surface of the substrate; and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage from the voltage generator via the first interconnect line and the first gate contact. The dummy gate contact receives the first voltage via the first gate electrode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor. BACKGROUND

[0002] Due to its small size, multi-functionality, and / or low cost characteristics, a semiconductor device is considered an important element in the electronic industry. A semiconductor device is classified as a semiconductor memory device for storing data, a semiconductor logic device for processing data, and a hybrid semiconductor device including both a memory element and a logic element. As the electronic industry develops, there is a growing demand for semiconductor devices having improved characteristics. For example, there is a growing demand for semiconductor devices having high reliability, high performance, and / or multi-functionality. To meet such demand, the complexity and / or integration density of semiconductor devices is increasing. SUMMARY

[0003] An embodiment of the present inventive concept provides a semiconductor device having improved performance or reliability characteristics.

[0004] According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction with respect to an upper surface of the substrate; a first gate contact and a dummy gate contact spaced apart from each other in the first horizontal direction and in contact with a top surface of the first gate electrode; a first interconnection line extending in a second horizontal direction different from the first horizontal direction with respect to the upper surface of the substrate and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate; and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnection line and the first gate contact. The dummy gate contact receives the first voltage via the first gate electrode.

[0005] According to an exemplary embodiment of the present inventive concept, a semiconductor device includes: a plurality of gate electrodes on a substrate, each of the plurality of gate electrodes extending in a first horizontal direction with respect to an upper surface of the substrate and the plurality of gate electrodes being spaced apart from each other in a second horizontal direction with respect to the upper surface of the substrate, the second horizontal direction being different from the first horizontal direction; a plurality of gate contacts, each of the plurality of gate contacts being disposed on and electrically connected with a corresponding one of the plurality of gate electrodes; a plurality of interconnection lines, each of the plurality of interconnection lines extending in the second horizontal direction and overlapping at least one of the plurality of gate contacts in a vertical direction with respect to the upper surface of the substrate, the plurality of interconnection lines being spaced apart from each other in the first horizontal direction; a voltage generator configured to generate a first voltage and apply the first voltage to the plurality of gate electrodes via the plurality of gate contacts and the plurality of interconnection lines; and a dummy gate contact disposed on a corresponding one of the plurality of gate electrodes and spaced apart from a gate contact of the plurality of gate contacts disposed on the corresponding one of the plurality of gate electrodes in the first horizontal direction. The first voltage is applied to the dummy gate contact through the corresponding one of the plurality of gate electrodes.

[0006] According to an exemplary embodiment of the present inventive concept, a semiconductor device includes: a substrate including a first active region and a second active region spaced apart from each other in a first horizontal direction with respect to an upper surface of the substrate; a plurality of active fins protruding from the substrate in a vertical direction with respect to the upper surface of the substrate and extending in a second horizontal direction crossing the first horizontal direction with respect to the upper surface; a first gate electrode, a second gate electrode, and a third gate electrode crossing the plurality of active fins in the first horizontal direction, being parallel to each other in the second horizontal direction, and being a linear pattern; a first gate contact disposed on the second gate electrode and overlapping a region between the first active region and the second active region in the vertical direction; a first dummy gate contact overlapping the second gate electrode in the vertical direction and spaced apart from the first gate contact in the first horizontal direction, the first dummy gate contact overlapping one of the first active region and the second active region in the vertical direction or being adjacent to one of the first active region and the second active region in the first horizontal direction, at least two or at least three of the plurality of active fins being disposed in each of the first active region and the second active region; a first interconnection line extending in the second horizontal direction and overlapping the first gate contact in the vertical direction; and a voltage generator configured to generate a first voltage and apply the first voltage to the second gate electrode through the first gate contact and the first interconnection line. The first voltage is applied to the first dummy gate contact through the second gate electrode. BRIEF DESCRIPTION OF DRAWINGS

[0007] The example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. The following is set forth to depict the exemplary embodiments described herein and is not intended to limit the scope of what can be claimed.

[0008] Figure 1 is a block diagram illustrating a computer system configured to perform a semiconductor design process according to an embodiment of the present inventive concept.

[0009] Figure 2 is a flowchart of a method of designing and manufacturing a semiconductor device according to an embodiment of the present inventive concept.

[0010] Figure 3A , Figure 3B and Figure 3C are layouts each illustrating a semiconductor device according to an embodiment of the present inventive concept.

[0011] Figure 4A , Figure 4B and Figure 4C are cross-sectional views taken along lines I-I' and II-II' of Figure 3A , Figure 3B and Figure 3C respectively.

[0012] Figure 5 is a layout illustrating a semiconductor device according to an embodiment of the present inventive concept.

[0013] Figure 6 is a cross-sectional view illustrating a vertical cross-section taken along lines I-I' and III-III' of Figure 5 .

[0014] Figure 7 is a layout of a semiconductor device according to an embodiment of the present inventive concept.

[0015] Figure 8 is a cross-sectional view taken along lines IV-IV' and V-V' of Figure 7 .

[0016] Figure 9 is a layout of a semiconductor device according to an embodiment of the present inventive concept.

[0017] Figure 10 is a cross-sectional view taken along line VI-VI' of Figure 9 .

[0018] Figure 11 is a layout of a semiconductor device according to an embodiment of the present inventive concept.

[0019] Figures 12A-12C is a layout illustrating a portion (e.g., a standard cell) of a semiconductor device according to an embodiment of the present inventive concept.

[0020] Figure 13A , Figure 13B andFigure 13C They are respectively along Figure 12B Cross-sectional views taken from lines VII-VII', VIII-VIII', and IX-IX'.

[0021] Figure 14A , Figure 14B and Figure 14C They are respectively along Figure 12B Cross-sectional views taken from lines VII-VII', VIII-VIII', and IX-IX'.

[0022] Figure 15A and Figure 15B This is a layout diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0023] Figure 16 This is a layout diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0024] Figure 17 This is a layout diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0025] Figure 18 This is a layout diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0026] Figure 19 This is a layout diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0027] Figure 20 This is a layout diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0028] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments. For example, the relative thickness and location of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0029] Figure 1 This is a block diagram illustrating a computer system configured to perform a semiconductor design process according to an embodiment of the concept of the present invention.

[0030] Reference Figure 1The computer system can include a central processing unit (CPU) 100, a working memory 30, an input / output device 50, and an auxiliary storage device 70. In an embodiment, the computer system can be provided in the form of a custom system configured to perform a layout design process according to the inventive concept. Further, the computer system can be configured to execute various design and checking simulation programs.

[0031] The CPU 100 can be configured to execute various software programs, such as an application program, an operating system, and a device driver, which are executed on the computer system. The CPU 100 can execute an operating system loaded on the working memory 30. Further, the CPU 100 can execute various application programs based on the operating system. For example, the CPU 100 can execute a layout design tool 32, a placement and routing tool 34, and / or an optical proximity correction (OPC) tool 36 loaded on the working memory 30.

[0032] The operating system or the application program can be loaded on the working memory 30. For example, when the computer system starts a booting operation, an image of the operating system (not shown) stored in the auxiliary storage device 70 can be loaded on the working memory 30 according to a predetermined booting sequence. In the computer system, the entire input / output operation can be managed by the operating system. Similarly, some application programs selected by a user or provided for a basic service can be loaded on the working memory 30.

[0033] A place and route tool 32 for a place and route process can be loaded on the working memory 30 from the secondary storage device 70. A place and route tool 34 for placing designed standard cells and routing the placed standard cells can be loaded on the working memory 30 from the secondary storage device 70. An OPC tool 36 for performing an OPC process on designed place data can be loaded on the working memory 30 from the secondary storage device 70. Using available design tools, including electronic design automation (EDA) and computer-aided design (CAD) tools, different logic functions can be integrated into an integrated circuit (IC). A standard cell includes a plurality of transistors for implementing a logic function. The logic function can include Boolean functions (e.g., AND, OR, and NOT), memory functions (e.g., flip-flops, latches, and buffers), and digital combinatorial functions (e.g., multiplexers and demultiplexers). Each standard cell has a predetermined geometry (width and height). EDA and CAD design tools include a library (commonly referred to as a standard cell library) that stores standard cell definitions for these logic functions. During semiconductor device design, a design tool selects one or more standard cells from the cell library based on a logic design and process parameters (i.e., dimensions and widths of the standard cells) and places the standard cells in rows and columns. Upon completion of the placement, the semiconductor device design is simulated, verified, and then transferred to a chip (i.e., formed in silicon).

[0034] The place and route tool 32 can be configured to change biasing data for some place patterns. For example, the place and route tool 32 can be configured to allow a particular place pattern to have a shape and position that is different from that given by the design rules. In addition, the place and route tool 32 can be configured to perform a design rule check (DRC) operation under the direction of the changed biasing data. The working memory 30 can be at least one of a volatile memory device (e.g., a static or dynamic random access memory (SRAM or DRAM) device) and a non-volatile memory device (e.g., a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a NOR flash device).

[0035] The input and output device 50 can be configured to control input and output data of a user through a user interface device. For example, the input and output device 50 can include a keyboard and / or a monitor for receiving relevant information from a designer. Through the use of the input and output device 50, the designer can receive information about a region or a data path of a semiconductor device that needs to have an adjusted operational characteristic. The input and output device 50 can also be used to display a status or a result of a process performed by the OPC tool 36.

[0036] Auxiliary storage device 70 can be provided as a storage medium for a computer system. Auxiliary storage device 70 can be used to store images of applications, operating systems, and various types of data. Auxiliary storage device 70 can be or may include at least one of memory cards (e.g., MMC, eMMC, SD, MicroSD, etc.), hard disk drives (HDDs), and solid-state drives (SSDs). Auxiliary storage device 70 may include NAND flash memory devices with large storage capacities. In one embodiment, auxiliary storage device 70 may include next-generation non-volatile memory devices (e.g., PRAM, MRAM, ReRAM, and FRAM devices) and / or NOR flash memory devices.

[0037] The system interconnect 90 can be further provided as a system bus for an internal network of a computer system. The CPU 100, working memory 30, input / output devices 50, and auxiliary storage devices 70 can be electrically connected to each other via the system interconnect 90 to exchange data between them. However, the structure of the system interconnect 90 is not limited to this example, and in one embodiment, additional data exchange elements can be provided to improve efficiency in the data processing process.

[0038] Figure 2 This is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to an embodiment of the concept of the present invention.

[0039] Reference Figure 2 You can use about Figure 1 The described computer system performs a high-level design process for semiconductor integrated circuits (in S10). For example, in the high-level design process, the integrated circuit, which is the target of the design process, can be described using a high-level computer language. In one embodiment, C language can be an example of a high-level computer language. The circuit designed through the high-level design process can be described more specifically through register-transfer-level (RTL) encoding or simulation. Furthermore, the code generated by RTL encoding can be converted into a netlist, and the results can be combined to describe the overall semiconductor device. The combined schematic circuit can be verified using simulation tools, and in some cases, adjustment steps can be further performed taking into account the results of the verification steps.

[0040] A layout design process can be performed to implement a logically-prepared form of a semiconductor integrated circuit on a silicon substrate (in S20). For example, during the layout design process, a schematic circuit or corresponding netlist prepared in the advanced design process can be referenced.

[0041] A cell library for use in a place-and-route process can contain information regarding the operation, speed, and power consumption of standard cells. Most place-and-route tools can be configured to define a cell library that is used to represent a gate-level circuit in the form of a layout. Here, the layout can be prepared to define the geometric features (e.g., shape, position, or size) of a pattern that is used to form transistors and interconnect lines that will be integrated on a silicon substrate. For example, forming an inverter circuit on a silicon substrate can include laying out a pattern in at least one or more layers of a layout to implement the constituent elements (e.g., PMOS, NMOS, N-WELL, gate electrodes, and interconnect lines thereon) of the inverter circuit. Then, a search operation can be performed to select the most suitable inverter layout from among the inverter layouts that have been stored in the cell library.

[0042] A step of placing various standard cells stored in the cell library and establishing a routing structure (in S30) can be performed. For example, the standard cells can be placed to form a two-dimensional arrangement. Then, a routing pattern can be placed on the placed standard cells. The routing step can be performed to connect the placed standard cells to each other in a manner that has been previously designed. The step of placing and routing the standard cells can be performed automatically by the place-and-route tool 34.

[0043] After the routing step, a verification step can be performed on the layout to check whether there are portions that violate given design rules. In an embodiment, the verification step can include evaluating verification items such as design rule checking (DRC), electrical rule checking (ERC), and layout versus circuit (LVS). Here, the DRC can be performed to evaluate whether the layout satisfies given design rules, the ERC can be performed to evaluate whether there are electrical open problems in the layout, and the LVS can be performed to evaluate whether the layout is prepared to be consistent with a gate-level netlist.

[0044] An OPC step (in S40) can be performed. Generally, when performing a photolithography process on a silicon wafer using a photomask that is fabricated based on the designed layout, optical proximity effects can occur. The OPC step can be performed to correct for optical proximity or distortion problems in the photolithography process. For example, in the OPC step, the layout can be modified to reduce shape differences between the designed pattern and the actually formed pattern that can be caused by optical proximity effects or during an exposure step of the photolithography process. As a result of the OPC step, the designed shape and position of the layout pattern can be slightly changed or shifted.

[0045] A photomask can be generated based on the layout that is modified by the OPC step (in S50). Generally, the photomask can be fabricated by patterning a chromium layer formed on a glass substrate in such a way to delineate the layout pattern.

[0046] The manufactured photomask can be used to manufacture semiconductor devices (in S60). During the manufacturing process, various exposure and etching steps can be performed or repeated to sequentially form patterns defined in the layout design process on the silicon substrate.

[0047] Figure 3A , Figure 3B and Figure 3C These are layout diagrams, each illustrating a semiconductor device according to an embodiment of the concept of the present invention. Figure 4A , Figure 4B and Figure 4C They are respectively along Figure 3A , Figure 3B and Figure 3C The cross-sectional views taken from lines I-I' and II-II'.

[0048] Reference Figure 3A and Figure 4A Semiconductor device 10a can be provided on substrate 1. Figure 3A The layout can correspond to a portion of the layout of a standard cell. In this embodiment, the semiconductor device 10a can be a single transistor. The substrate 1 can be a group IV element semiconductor substrate (e.g., a silicon, germanium, or silicon-germanium substrate) or a compound semiconductor substrate. As an example, the substrate 1 can be a silicon wafer. A device isolation layer 3 can be disposed in the substrate 1 to define an active region AR. The active region AR of the substrate 1 can be doped with n-type or p-type impurities. The active region AR can be a PMOSFET region or an NMOSFET region.

[0049] The gate electrode GE can be configured to intersect with the active region AR. The gate electrode GE can be a linear structure extending in the first direction D1. The gate electrode GE can be formed of or include a conductive material. For example, the gate electrode GE can be formed of at least one of doped polysilicon, metal nitride, metal silicide, and metal-containing materials, or include at least one of doped polysilicon, metal nitride, metal silicide, and metal-containing materials. The gate insulating layer Gox can be interposed between the gate electrode GE and the substrate 1. The gate insulating layer Gox can include a silicon oxide layer and / or a high-k dielectric layer with a dielectric constant higher than that of the silicon oxide layer. The high-k dielectric layer can include a metal oxide (e.g., aluminum oxide or hafnium oxide). The gate electrode GE can be covered by a gate cap pattern GP. The gate cap pattern GP can be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxide nitride, or include at least one of, for example, silicon oxide, silicon nitride, and silicon oxide nitride, and can have a single-layer or multi-layer structure.

[0050] Source / drain regions (SD) 5 can be provided in portions of the substrate 1 on opposite sides of the gate electrode GE. The source / drain regions 5 can be doped to have a conductivity type different from that of the substrate 1. For example, in the case where the active region AR is a PMOSFET region, the substrate 1 can be doped with n-type impurities and the source / drain regions 5 can be doped with p-type impurities. In the case where the active region AR is an NMOSFET region, the substrate 1 can be doped with p-type impurities and the source / drain regions 5 can be doped with n-type impurities. Gate spacers GS can be disposed on two opposite side surfaces of the gate electrode GE. The gate spacers GS can be formed of, or include, at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride, and can have a single-layer or multi-layer structure.

[0051] The gate electrode GE, the gate cap pattern GP, the gate spacers GS, the substrate 1, and the device isolation layer 3 can be covered with a first interlayer insulating layer IL1. The first interlayer insulating layer IL1 can be formed of, or include, at least one of, for example, silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, and a porous material, and can have a single-layer or multi-layer structure.

[0052] The gate contact CB and the dummy gate contact DCB can be provided to penetrate the first interlayer insulating layer IL1 and the gate cap pattern GP and to contact the gate electrode GE. The gate contact CB and the dummy gate contact DCB can be spaced apart from each other in the first direction D1. The dummy gate contact DCB can overlap the active region AR. The gate contact CB can overlap the device isolation layer 3. In a top view, the gate contact CB can be horizontally spaced apart from the active region AR. The dummy gate contact DCB can have the same size and height as the gate contact CB. A top surface of the dummy gate contact DCB can be located at the same height as a top surface of the gate contact CB. A bottom surface of the dummy gate contact DCB can be located at the same height as a bottom surface of the gate contact CB. The term "contact" as used herein refers to a direct connection (i.e., touching), unless the context otherwise indicates. As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function and exists in a device only as a pattern.

[0053] A second interlayer insulating layer IL2 can be provided on the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 can be formed of or include at least one of, for example, silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, and a porous material, and can have a single layer or a multi-layer structure. The first line (e.g., interconnection line) M1 and the gate via VB can be provided in the second interlayer insulating layer IL2. The gate via VB can electrically connect the first line M1 to the gate contact CB. The gate via VB and the first line M1 can not be provided on the dummy gate contact DCB. A voltage can be applied to the gate electrode GE through the gate contact CB. The dummy gate contact DCB can not be used to apply a voltage to an element. For example, a voltage generator VG can generate a voltage and apply the voltage to the gate electrode GE through the gate contact CB, and the voltage can be applied to the dummy gate contact DCB via the gate electrode GE. The gate contact CB can be configured to transmit a voltage to the gate electrode GE. The dummy gate contact DCB can not be used to transmit any voltage to the gate electrode GE. An electrical connection between the voltage generator VG and the first line M1 can be made using an interconnection line located at the same level as the first line M1 or at a higher level than the first line M1. For example, such a connection can be formed by a functional block including a row decoder. For simplicity of the drawing, an electrical connection between the voltage generator VG and the first line M1 and the functional block can be omitted. In addition, it is noted that, in Figures 3A-3C and some other drawings, the gate via VB is shown to have a size larger than that of the gate contact CB and the width of the first line M1 to distinguish them from each other, and their sizes are not limited thereto. In certain embodiments, the gate via VB can be omitted, and the gate contact CB can be directly connected to the first line M1.

[0054] In certain embodiments, as shown in Figure 3B and Figure 4B The semiconductor device 10b can further include a dummy gate via DVB provided on the dummy gate contact DCB. The dummy gate via DVB can not be used to apply a voltage to an element. The gate contact CB and the gate via VB can be configured to transmit a voltage to the gate electrode GE. The dummy gate contact DCB and the dummy gate via DVB can not be used to transmit any voltage to the gate electrode GE.

[0055] In certain embodiments, as shown in Figure 3C and Figure 4CAs shown, the semiconductor device 10c can also include a dummy gate via DVB and a dummy line DM1 disposed on the dummy gate contact DCB. The dummy line DM1 can not be used to apply a voltage to an element. The gate contact CB, the gate via VB, and the first line M1 can be configured to transmit a voltage to the gate electrode GE. The dummy gate contact DCB, the dummy gate via DVB, and the dummy line DM1 can not be used to transmit any voltage to the gate electrode GE. In some embodiments, the first line M1 can be connected to an auxiliary line (which will be referred to as an auxiliary line 1) and the same voltage can be applied to the first line M1 and the auxiliary line 1 from the voltage generator VG. Figure 17 The same voltage can be applied to the first line M1 and the auxiliary line 1 from the voltage generator VG.

[0056] In Figures 3A-3C and Figures 4A-4C , the semiconductor devices 10a, 10b, and 10c are shown as planar transistors, but the inventive concept is not limited to this example or particular implementation. For example, a semiconductor device according to an embodiment of the inventive concept can be a FinFET, a multi-bridge-channel field effect transistor (MBCFET), a vertical field effect transistor (VFET), or a negative capacitance field effect transistor (NCFET).

[0057] Each of the semiconductor devices 10a, 10b, and 10c can include a dummy gate contact DCB. The dummy gate contact DCB overlapping the active region AR can cause a change in the characteristics of the semiconductor devices 10a, 10b, and 10c. For example, the dummy gate contact DCB can weakly apply an electrical / mechanical stress to the channel region. In the case where the semiconductor devices 10a, 10b, and 10c are PMOSFETs, such a stress can cause the mobility of holes in the channel region to increase, and thus, the operating speed of the semiconductor device can increase. Conversely, in the case where the semiconductor devices 10a, 10b, and 10c are NMOSFETs, due to the stress, the mobility of electrons in the channel region can decrease, but the threshold voltage of the NMOSFET increases and its leakage current decreases. As the semiconductor devices 10a, 10b, and 10c are being scaled down, the length of the channel region under the gate electrode GE can become increasingly small. Thus, the presence of the dummy gate contact DCB can greatly affect the characteristics of the semiconductor devices 10a, 10b, and 10c. According to an embodiment of the inventive concept, in step S20 or S30 of Figure 2 , the dummy gate contact DCB can be laid out at a suitable location to improve the performance of the device. A photomask can be fabricated based on the layout described above, and then can be used to manufacture the semiconductor devices 10a, 10b, and 10c.

[0058] Figure 5 is a layout showing a semiconductor device according to an embodiment of the inventive concept. Figure 6 is a layout showing a semiconductor device according to an embodiment of the inventive concept.Figure 5 a cross-sectional view of a vertical cross-section taken by lines I-I' and III-III'.

[0059] Referring to Figure 5 and Figure 6 , the semiconductor device 10d can include a first transistor TR1 and a second transistor TR2 disposed on the substrate 1 and spaced apart from each other. The first transistor TR1 can be substantially the same as the transistor described with reference to FIGS. 3 and 4. The second transistor TR2 can not include the dummy gate contact DCB. In certain embodiments, the first transistor TR1 can include a first gate electrode GE1 crossing the first active region AR1. A first gate insulating layer Gox1 can be interposed between the first gate electrode GE1 and the substrate 1. A first gate cap pattern GP1 can be disposed on the first gate electrode GE1. The dummy gate contact DCB can overlap the first active region AR1. For example, the dummy gate contact DCB can overlap a channel region of the first active region AR1 between source / drain regions, leaving the channel region between the source / drain regions.

[0060] The second transistor TR2 can include a second gate electrode GE2 crossing the second active region AR2. A second gate insulating layer Gox2 can be interposed between the second gate electrode GE2 and the substrate 1. A second gate cap pattern GP2 can be disposed on the second gate electrode GE2. The dummy gate contact as described above can not overlap the second active region AR2. For the second transistor TR2, which is a transistor having a type different from that of the first transistor TR1 (e.g., the second transistor TR2 of an NMOSFET and the first transistor TR1 of a PMOSFET, or vice versa), the second gate electrode GE2 can be formed of or include a conductive material different from the first gate electrode GE1. The second gate insulating layer Gox2 can be formed of or include an insulating material or a high-k dielectric material different from the first gate insulating layer Gox1. The second gate cap pattern GP2 and the first gate cap pattern GP1 can be formed of or include the same insulating material or different insulating materials from each other.

[0061] Although not shown, first source / drain regions can be provided in the substrate 1 on opposite sides of the first gate electrode GE1, and second source / drain regions can be provided in the substrate 1 on opposite sides of the second gate electrode GE2. For the second transistor TR2, which is a transistor of a different type from that of the first transistor TR1 (e.g., a second transistor TR2 of an NMOSFET and a first transistor TR1 of a PMOSFET, or vice versa), the first source / drain regions and the second source / drain regions can differ from each other in the kind or concentration of dopant therein.

[0062] The first transistor TR1 and the second transistor TR2 can be covered with a first interlayer insulating layer IL1. Each of the first gate contact CB1 and the dummy gate contact DCB can be provided to penetrate the first interlayer insulating layer IL1 and the first gate cap pattern GP1 and to contact the first gate electrode GE1. The dummy gate contact DCB can overlap the first active region AR1, and the first gate contact CB1 can be spaced apart from the first active region AR1. In some embodiments, the first gate contact CB1 can be vertically spaced apart from the first active region AR1. The second gate contact CB2 can be provided to penetrate the first interlayer insulating layer IL1 and the second gate cap pattern GP2 and to contact the second gate electrode GE2.

[0063] The first interlayer insulating layer IL1 can be covered with a second interlayer insulating layer IL2. The first gate via VB1 and the first line M1 can be provided in the second interlayer insulating layer IL2 and can be electrically connected to the first gate contact CB1. The second gate via VB2 and the second line M2 can be provided in the second interlayer insulating layer IL2 and can be electrically connected to the second gate contact CB2. Except for the above-described differences, the semiconductor device 10d according to the present embodiment can have substantially the same features as those described with reference to the semiconductor device 10a. Figure 3A and Figure 4A described with reference to the semiconductor device 10a.

[0064] Figure 7 is a layout of a semiconductor device according to an embodiment of the inventive concept. Figure 8 is a cross-sectional view taken along lines IV-IV' and V-V' of Figure 7

[0065] In the semiconductor device 10e according to the present embodiment, a device isolation layer 3 can be provided on the substrate 1 to define the second active region AR2 to the sixth active region AR6 spaced apart from each other, as shown in Figure 7 and Figure 8 described with reference to the semiconductor device 10a.​Figure 5 and Figure 6 The second transistor TR2 is described. The second transistor TR2 can be configured to have a structure similar to that in the foregoing embodiments, and thus a repetitive description thereof will be omitted.

[0066] The third active region AR3 and the fourth active region AR4 can be spaced apart from each other in the first direction D1. The third gate electrode GE3 can be disposed to cross the third active region AR3, and the fourth gate electrode GE4 can be disposed to cross the fourth active region AR4. Each of the third gate electrode GE3 and the fourth gate electrode GE4 can be a linear pattern extending in the first direction D1. The third gate electrode GE3 and the fourth gate electrode GE4 can be located on a single straight line extending in the first direction D1. The third gate electrode GE3 and the fourth gate electrode GE4 can be spaced apart from each other by a gate separation pattern IP. In some embodiments, the conductive line can be separated into the third gate electrode GE3 and the fourth gate electrode GE4 by the gate separation pattern IP.

[0067] A third gate insulating layer Gox3 can be interposed between the third gate electrode GE3 and the substrate 1. A fourth gate insulating layer Gox4 can be interposed between the fourth gate electrode GE4 and the substrate 1. The third gate electrode GE3 and the fourth gate electrode GE4 can be formed of the same material and can have the same structure. The third gate insulating layer Gox3 and the fourth gate insulating layer Gox4 can be formed of the same material and can have the same structure. A third gate cap pattern GP3 can be disposed on the third gate electrode GE3, and a fourth gate cap pattern GP4 can be disposed on the fourth gate electrode GE4. The third gate cap pattern GP3 and the fourth gate cap pattern GP4 can be formed of the same material and can have the same structure.

[0068] The gate separation pattern IP can be formed of or include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate separation pattern IP can be interposed between the third gate cap pattern GP3 and the fourth gate cap pattern GP4, between the third gate electrode GE3 and the fourth gate electrode GE4, and between the third gate insulating layer Gox3 and the fourth gate insulating layer Gox4, and can be in contact with the device isolation layer 3.

[0069] The fifth active region AR5 and the sixth active region AR6 can be spaced apart from each other in the first direction D1. The fifth active region AR5 and the sixth active region AR6 of the substrate 1 can be doped with impurities whose conductive types are different from each other, respectively. A fifth gate electrode GE5 can be disposed to cross the fifth active region AR5 and the sixth active region AR6. A fifth gate insulating layer Gox5 can be interposed between the fifth gate electrode GE5 and the substrate 1. A fifth gate cap pattern GP5 can be disposed on the fifth gate electrode GE5.

[0070] The second to fifth gate electrodes GE2 to GE5 and the substrate 1 can be sequentially covered with the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The third line M3 and the third gate via VB3 provided in the second interlayer insulating layer IL2 can be electrically connected to the third gate electrode GE3 through the third gate contact CB3 formed to penetrate the first interlayer insulating layer IL1 and the third gate cap pattern GP3. The fourth line M4 and the fourth gate via VB4 provided in the second interlayer insulating layer IL2 can be electrically connected to the fifth gate electrode GE5 through the fourth gate contact CB4 formed to penetrate the first interlayer insulating layer IL1 and the fifth gate cap pattern GP5.

[0071] The first dummy gate contact DCB1 can be provided to penetrate the first interlayer insulating layer IL1 and the fourth gate cap pattern GP4 and to contact the fourth gate electrode GE4. The second dummy gate contact DCB2 can be provided to penetrate the first interlayer insulating layer IL1 and the fifth gate cap pattern GP5 and to contact the fifth gate electrode GE5. The first dummy contact DCB1 and the second dummy contact DCB2 can not be used to apply a voltage to an element. Gate contacts and interconnection lines can be electrically connected to the fourth gate electrode GE4 to apply a voltage thereto, but they are not shown for simplicity of the drawing.

[0072] Figure 9 is a layout of a semiconductor device according to an embodiment of the inventive concept. Figure 10 is a cross-sectional view taken along the line VI-VI' of Figure 9

[0073] Referring to Figure 9 and Figure 10 The semiconductor device 10f according to the present embodiment can include a first standard cell ST1 and a second standard cell ST2 disposed on the substrate 1 to be adjacent to each other in the first direction D1. The first standard cell ST1 can include a first NMOS region NR1 and a first PMOS region PR1 spaced apart from each other by the device isolation layer 3. The second standard cell ST2 can include a second NMOS region NR2 and a second PMOS region PR2 spaced apart from each other by the device isolation layer 3. The first NMOS region NR1 can be adjacent to the second NMOS region NR2. The first NMOS region NR1 and the second NMOS region NR2 can be disposed between the first PMOS region PR1 and the second PMOS region PR2. The first standard cell ST1 and the second standard cell ST2 can include or share a gate electrode GE disposed to cross all of the regions (NR1, PR1, NR2, and PR2).

[0074] ​A first power line MP1 can be disposed adjacent to the first PMOS region PR1 of the first standard cell ST1. A second power line MP2 can be provided between the first standard cell ST1 and the second standard cell ST2. A third power line MP3 can be disposed adjacent to the second PMOS region PR2 of the second standard cell ST2. A first voltage can be applied to the first power line MP1 and the third power line MP3. A second voltage different from the first voltage can be applied to the second power line MP2. One of the first voltage and the second voltage can be a power supply voltage (Vdd) and the other can be a ground voltage (Vss).

[0075] A first line M1 can be disposed between the first PMOS region PR1 and the first NMOS region NR1. The first line M1 can be electrically connected to the gate electrode GE through the gate via VB and the gate contact CB. A dummy gate contact DCB can be disposed between the second PMOS region PR2 and the second NMOS region NR2 to contact the gate electrode GE. The dummy gate contact DCB can be closer to the second NMOS region NR2 than to the second PMOS region PR2. In an embodiment, in a top view, the dummy gate contact DCB can overlap a boundary between the second NMOS region NR2 and a device isolation layer 3 adjacent thereto. In certain embodiments, unlike in Figure 9

[0076] Figure 11 is a layout of a semiconductor device according to an embodiment of the inventive concept.

[0077] Reference is made to Figure 11 ​, the semiconductor device 10g can include first to fourth standard cells ST1 to ST4 arranged on the substrate 1 to form a single column in the first direction D1. Each of the first to fourth standard cells ST1 to ST4 can include an NMOS region NR and a PMOS region PR. The arrangement of the NMOS region NR and the PMOS region PR of the first standard cell ST1 can be symmetrical to the arrangement of the NMOS region NR and the PMOS region PR of the second standard cell ST2. The arrangement of the NMOS region NR and the PMOS region PR of the third standard cell ST3 can be symmetrical to the arrangement of the NMOS region NR and the PMOS region PR of the second standard cell ST2. The arrangement of the NMOS region NR and the PMOS region PR of the fourth standard cell ST4 can be symmetrical to the arrangement of the NMOS region NR and the PMOS region PR of the third standard cell ST3. A first power line MP1 can be disposed adjacent to the PMOS region PR of the first standard cell ST1. A second power line MP2 can be disposed between the first standard cell ST1 and the second standard cell ST2. A third power line MP3 can be disposed between the second standard cell ST2 and the third standard cell ST3. A fourth power line MP4 can be disposed between the third standard cell ST3 and the fourth standard cell ST4. A fifth power line MP5 can be disposed adjacent to the PMOS region PR of the fourth standard cell ST4. A first voltage can be applied to the first power line MP1, the third power line MP3, and the fifth power line MP5. A second voltage can be applied to the second power line MP2 and the fourth power line MP4. One of the first voltage and the second voltage can be a power supply voltage (Vdd), and the other can be a ground voltage (Vss).

[0078] A first line M1 can be disposed between the PMOS region PR and the NMOS region NR of the first standard cell ST1. The first line M1 can be electrically connected to the gate electrode GE through a gate via VB and a gate contact CB. A first dummy gate contact DCB1 can contact the gate electrode GE between the PMOS region PR and the NMOS region NR of the second standard cell ST2. A second dummy gate contact DCB2 can contact the gate electrode GE between the PMOS region PR and the NMOS region NR of the third standard cell ST3. A third dummy gate contact DCB3 can contact the gate electrode GE between the PMOS region PR and the NMOS region NR of the fourth standard cell ST4. Figure 11An example in which three dummy gate contacts (DCB1, DCB2, and DCB3) are provided is shown, but in an embodiment, the semiconductor device 10g can be configured to have one or two dummy gate contacts. In an embodiment, at least one of the dummy gate contacts (DCB1, DCB2, and DCB3) can be adjacent to or overlap the PMOS region PR or the NMOS region NR of at least one of the first to fourth standard cells ST1 to ST4.

[0079] Figures 12A-12C is a layout showing a semiconductor device according to an embodiment of the present inventive concept. For example, Figures 12A-12C is a layout showing a standard cell according to an embodiment of the present inventive concept.

[0080] Referring to Figure 12A , the semiconductor device 10h can include first to fifth gate electrodes GE1 to GE5 disposed on the substrate 1 and spaced apart from each other. Each of the first to fifth gate electrodes GE1 to GE5 can be a linear pattern extending in a length direction (e.g., the first direction D1), and the first to fifth gate electrodes GE1 to GE5 can be spaced apart from each other in a second direction D2 different from the first direction D1. First to third insulating spacer patterns IS1 to IS3 spaced apart from each other can be disposed on the substrate 1. Each of the first to third insulating spacer patterns IS1 to IS3 can be a linear pattern extending in a length direction (e.g., the first direction D1), and the first to third insulating spacer patterns IS1 to IS3 can be spaced apart from each other in the second direction D2. The first insulating spacer pattern IS1 can be spaced apart from the second gate electrode GE2 with the first gate electrode GE1 interposed therebetween. The second insulating spacer pattern IS2 can be disposed between the fourth gate electrode GE4 and the fifth gate electrode GE5. The third insulating spacer pattern IS3 can be spaced apart from the second insulating spacer pattern IS2 with the fifth gate electrode GE5 interposed therebetween.

[0081] In an embodiment, the distance between the first gate electrode GE1 and the second gate electrode GE2, the distance between the second gate electrode GE2 and the third gate electrode GE3, the distance between the third gate electrode GE3 and the fourth gate electrode GE4, the distance between the first insulating spacer pattern IS1 and the first gate electrode GE1, the distance between the second insulating spacer pattern IS2 and the fourth gate electrode GE4, the distance between the second insulating spacer pattern IS2 and the fifth gate electrode GE5, and the distance between the third insulating spacer pattern IS3 and the fifth gate electrode GE5 can be the same as each other.

[0082] The source / drain contacts CA can be provided between the first insulating isolation pattern IS1 and the first gate electrode GE1, between the first gate electrode GE1 to the fifth gate electrode GE5, and between the third insulating isolation pattern IS3 and the fifth gate electrode GE5. The source / drain contacts CA can have a bar shape elongated in the first direction D1. The first power line MP1 and the second power line MP2 can be spaced apart from each other and can be provided to cross end portions of the first gate electrode GE1 to the fifth gate electrode GE5. The first line M1 to the sixth line M6 can be provided between the first power line MP1 and the second power line MP2. Some of the source / drain contacts CA can be electrically connected to the lines (MP1, MP2 and M2, M5, M6) through the source / drain vias VA.

[0083] Each of the first gate electrode GE1 to the fifth gate electrode GE5 can be electrically connected to a corresponding line (i.e., a corresponding interconnection line) through a gate contact CB and a gate via VB. For example, the first gate electrode GE1 can be electrically connected to the first line M1 through the gate contact CB and the gate via VB overlapping the first gate electrode GE1. The third gate electrode GE3 can be electrically connected to the first line M1 through the gate contact CB and the gate via VB overlapping the third gate electrode GE3. The second gate electrode GE2 can be electrically connected to the third line M3 through the gate contact CB and the gate via VB overlapping the second gate electrode GE2. The fourth gate electrode GE4 can be electrically connected to the fourth line M4 through the gate contact CB and the gate via VB overlapping the fourth gate electrode GE4. The fifth gate electrode GE5 can be electrically connected to the second line M2 through the gate contact CB and the gate via VB overlapping the fifth gate electrode GE5.

[0084] Referring to Figures 3A-11 The dummy gate contact DCB described can be laid out to improve performance and reliability of the semiconductor device 10h having Figure 12A the layout of the standard cell shown. For example, the dummy gate contact DCB can be laid out in the layout design step S20 or in the step S30 of laying out and wiring the standard cell. Figure 2

[0085] The dummy gate contact DCB can be laid out on at least one of the first gate electrode GE1 to the fifth gate electrode GE5 in the PMOS region PR to improve speed and performance of the transistor. For example, the dummy gate contact DCB can be provided on the PMOS region PR of the semiconductor device 10h shown in Figure 12A For example, as shown in the semiconductor device 10i according to the present embodiment, the dummy gate contact DCB can be provided on the second gate electrode GE2 and the fourth gate electrode GE4, respectively, in the PMOS region PR. The dummy gate contact DCB can overlap the first line M1 but can not be electrically connected to the first line M1. Figure 12B For example, as shown in the semiconductor device 10i according to the present embodiment, the dummy gate contact DCB can be provided on the second gate electrode GE2 and the fourth gate electrode GE4, respectively, in the PMOS region PR. The dummy gate contact DCB can overlap the first line M1 but can not be electrically connected to the first line M1.​

[0086] exist Figure 12C In this context, the dummy gate contact DCB can be disposed on at least one of the first gate electrode GE1 to the fifth gate electrode GE5 in the NMOS region NR and / or near the boundary of the NMOS region NR to reduce or suppress [the gate's behavior]. Figure 12A The leakage current of the semiconductor device 10h is reduced, thereby improving the reliability of the semiconductor device 10h, although it may reduce the speed of the transistors in the NMOS region NR. For example, in the semiconductor device 10j according to this embodiment, such as Figure 12C As shown, the dummy gate contact DCB can be positioned in the NMOS region NR and / or near the boundary of the NMOS region NR, respectively positioned on the first gate electrode GE1, the third gate electrode GE3, the fourth gate electrode GE4, and the fifth gate electrode GE5. The dummy gate contact DCB may not overlap with the first line M1 to the sixth line M6.

[0087] At least one of the first line M1 to the sixth line M6 can be a pin connection line. The pin connection line can be used to receive signals from outside the standard cell. In one embodiment, the pin connection line can be used to output signals to outside the standard cell.

[0088] Photomasks can be used Figures 12A-12C The standard cell layout is used to fabricate and can be used to manufacture semiconductor devices. The following will describe the use of... Figure 12B The layout of the standard cells shown is an example of a semiconductor device fabricated on a substrate.

[0089] Figure 13A , Figure 13B and Figure 13C They are respectively along Figure 12B Cross-sectional views taken from lines VII-VII', VIII-VIII', and IX-IX'. Figure 13A , Figure 13B and Figure 13C The semiconductor device 10i can correspond to an example of FinFET.

[0090] Reference Figure 12B , Figure 13A , Figure 13B and Figure 13C The substrate 1 may include a PMOS region PR and an NMOS region NR. The PMOS region PR and the NMOS region NR may be defined by a second trench TC2, which is formed in the upper part of the substrate 1. The second trench TC2 may be located between the PMOS region PR and the NMOS region NR. The PMOS region PR and the NMOS region NR may be spaced apart from each other in a first direction D1, such that the second trench TC2 is interposed between them.

[0091] A plurality of active fins AF can be provided in each of the PMOS region PR and the NMOS region NR. The active fins AF can extend in the second direction D2 to be parallel to each other. The active fins AF can be vertically protruding portions of the substrate 1. The first trench TC1 can define the active fins AF. In certain embodiments, the first trench TC1 can surround a lower portion of each active fin AF. The first trench TC1 can be shallower than the second trench TC2. For example, a bottom surface of the first trench TC1 can be higher than a bottom surface of the second trench TC2.

[0092] The device isolation layer 3 can fill the first trench TR1 and the second trench TR2. The device isolation layer 3 can include a silicon oxide layer. An upper portion of the active fin AF can vertically protrude above the device isolation layer 3. The device isolation layer 3 can not cover a side surface of the upper portion of the active fin AF. The device isolation layer 3 can cover a side surface of a lower portion of the active fin AF. The first to fifth gate electrodes GE1 to GE5 can be disposed to cross the active fin AF. A gate insulating layer Gox can be interposed between the first to fifth gate electrodes GE1 to GE5 and the active fin AF.

[0093] Each active fin AF on the PMOS region PR can include a first top surface TS1 and a first side surface SW1. Each of the first to fifth gate electrodes GE1 to GE5 can cover the first top surface TS1 and the first side surface SW1. A first channel region CH1 can be provided in an upper portion of the active fin AF. The first channel region CH1 can correspond to the upper portion of the active fin AF that respectively overlaps the first to fifth gate electrodes GE1 to GE5 in the PMOS region PR. A first source / drain pattern SD1 can be provided on the active fin AF. In certain embodiments, the first source / drain pattern SD1 can be located on opposite sides of each of the first to fifth gate electrodes GE1 to GE5 in the PMOS region PR. The first source / drain pattern SD1 can be formed of or include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of a semiconductor material constituting the substrate 1. The first source / drain pattern SD1 can exert a compressive stress on the first channel region CH1. The first source / drain pattern SD1 can be doped with a p-type impurity (e.g., boron).

[0094] Each active fin AF in the NMOS region NR may include a second top surface TS2 and a second side surface SW2. Each of the first gate electrodes GE1 to the fifth gate electrodes GE5 may be provided to cover the second top surface TS2 and the second side surface SW2. A second channel region CH2 may be disposed in the upper portion of the active fin AF. The second channel region CH2 may correspond to the upper portion of the active fin AF that overlaps with the first gate electrodes GE1 to the fifth gate electrodes GE5 in the NMOS region NR, respectively. A second source / drain pattern SD2 may be provided on a portion of the active fin AF. In some embodiments, the second source / drain pattern SD2 may be located on opposite sides of each of the first gate electrodes GE1 to the fifth gate electrodes GE5 in the NMOS region NR. The second source / drain pattern SD2 may be a semiconductor epitaxial pattern. As an example, the second source / drain pattern SD2 may be formed of the same semiconductor material (e.g., Si) as the substrate 1, or may include the same semiconductor material (e.g., Si) as the substrate 1. The second source / drain pattern SD2 may be doped with an n-type impurity (e.g., phosphorus or arsenic).

[0095] like Figure 13A As shown, each of the first insulating isolation pattern IS1 and the second insulating isolation pattern IS2 can be provided to penetrate the first interlayer insulating layer IL1 and the active fin AF, and can extend into the substrate 1. The first insulating isolation pattern IS1 and the second insulating isolation pattern IS2 can be formed of at least one of silicon oxide, silicon nitride, and silicon nitride, or include at least one of silicon oxide, silicon nitride, and silicon nitride.

[0096] like Figure 13B As shown, the gate contact CB can be provided to penetrate the first interlayer insulating layer IL1 and the gate cap pattern GP and contact the second gate electrode GE2. The gate contact CB can be disposed between the PMOS region PR and the NMOS region NR and can overlap with the device isolation layer 3. The gate contact CB can be electrically connected to the third line M3 through the gate path VB. The dummy gate contact DCB can be provided to penetrate the first interlayer insulating layer IL1 and the gate cap pattern GP and contact the second gate electrode GE2. The dummy gate contact DCB can overlap with at least one of the active fins AF in the PMOS region PR. For the simplicity of the figures, it is assumed that the PMOS region has three active fins AF, and one of the three active fins AF overlaps with the dummy gate contact DCB. In one embodiment, the PMOS region may include more than three active fins AF or fewer than three active fins AF. In one embodiment, the dummy gate contact DCB can overlap with two or more active fins AF. In one embodiment, the dummy gate contact DCB can be configured to overlap with a portion of an active fin AF in the PMOS region PR.

[0097] likeFigure 13C As shown, the first source / drain patterns SD1 can contact each other. The second source / drain patterns SD2 can also contact each other. The first source / drain patterns SD1 can be electrically connected to the second line M2 through the source / drain contacts CA and the source / drain vias VA. The second source / drain patterns SD2 can be electrically connected to the fifth line M5 through the source / drain contacts CA and the source / drain vias VA.

[0098] Figure 14A Figure 14B Figure 14C are cross-sectional views taken along lines VII-VII', VIII-VIII', and IX-IX' of Figure 12B Figure 14A Figure 14B Figure 14C The semiconductor device 10i of

[0099] Referring to Figure 14A Figure 14B Figure 14C The semiconductor device 10i can include a single active fin AF in each of the PMOS region PR and the NMOS region NR. In the PMOS region PR, a plurality of first channel patterns CP1 can be stacked in series on the active fin AF. The plurality of first channel patterns CP1 can be spaced apart from each other. In the NMOS region NR, a plurality of second channel patterns CP2 can be stacked in series on the active fin AF. The plurality of second channel patterns CP2 can be spaced apart from each other. The second gate electrode GE2 can extend into regions between the plurality of first channel patterns CP1 and regions between the plurality of second channel patterns CP2. Except for the above differences, the semiconductor device 10i according to the present embodiment can have substantially the same features as described with reference to Figures 13A-13C The semiconductor device 10i can include a single active fin AF in each of the PMOS region PR and the NMOS region NR. In the PMOS region PR, a plurality of first channel patterns CP1 can be stacked in series on the active fin AF. The plurality of first channel patterns CP1 can be spaced apart from each other. In the NMOS region NR, a plurality of second channel patterns CP2 can be stacked in series on the active fin AF. The plurality of second channel patterns CP2 can be spaced apart from each other. The second gate electrode GE2 can extend into regions between the plurality of first channel patterns CP1 and regions between the plurality of second channel patterns CP2. Except for the above differences, the semiconductor device 10i according to the present embodiment can have substantially the same features as described with reference to Figure 14B The semiconductor device 10i can include a single active fin AF in each of the PMOS region PR and the NMOS region NR. In the PMOS region PR, a plurality of first channel patterns CP1 can be stacked in series on the active fin AF. The plurality of first channel patterns CP1 can be spaced apart from each other. In the NMOS region NR, a plurality of second channel patterns CP2 can be stacked in series on the active fin AF. The plurality of second channel patterns CP2 can be spaced apart from each other. The second gate electrode GE2 can extend into regions between the plurality of first channel patterns CP1 and regions between the plurality of second channel patterns CP2. Except for the above differences, the semiconductor device 10i according to the present embodiment can have substantially the same features as described with reference to

[0100] Figure 15A Figure 15B are layout diagrams illustrating a semiconductor device according to an embodiment of the present inventive concept.

[0101] Referring to Figure 15A ​​​​​​​​In the semiconductor device 10k, the substrate 1 can include PMOS regions PR and NMOS regions NR that are spaced apart from each other. Each pair of the PMOS regions PR and the NMOS regions NR that are adjacent to each other can be disposed symmetrically to each other. The gate electrodes GE can be disposed to cross the PMOS regions PR and the NMOS regions NR. Although not shown, the gate separation pattern IP described with reference to Figure 7 and Figure 8 The gate separation pattern IP can be interposed between two gate electrodes GE that are adjacent to each other in the first direction Dl. The two gate electrodes GE can be spaced apart from each other in the first direction Dl with the gate separation pattern IP therebetween. The insulating isolation pattern IS can be sparsely distributed on the substrate 1 to be interposed between the gate electrodes GE. For ease of illustration, the interconnection lines, the source / drain contacts, and the source / drain vias are omitted in Figure 15A The gate contact CB can be disposed at an appropriate position on the gate electrode GE. The gate contact CB can be used to apply a voltage to the gate electrode GE.

[0102] However, as shown in the specific region P1, the gate contact CB can be disposed near an end portion of the gate electrode GE that extends through the specific region P1 in the first direction Dl. The gate contact CB can not be disposed in the specific region P1. As shown in Figure 15B The dummy gate contact DCB can be disposed in the specific region P1 to improve performance and reliability of some transistors in the specific region P1. The dummy gate contact DCB can be in contact with the gate electrode GE of some transistors in the specific region P1.

[0103] Referring to Figure 15B In the semiconductor device 101, the dummy gate contact DCB can be disposed in the specific region P1 and on the gate electrode GE. The dummy gate contact DCB can not be used to apply a voltage to an element. Each dummy gate contact DCB can be disposed adjacent to the PMOS region PR or the NMOS region NR. In a plan view, each dummy gate contact DCB can be in contact with a boundary of the PMOS region PR or the NMOS region NR. In an embodiment, in a plan view, each dummy gate contact DCB can partially overlap the PMOS region PR or the NMOS region NR.

[0104] Figure 16 is a layout showing a semiconductor device according to an embodiment of the present inventive concept.

[0105] Referring to Figure 16, the semiconductor device 10m according to the present embodiment can include a first standard cell ST1 and a second standard cell ST2 disposed on the substrate 1 adjacent to each other in the first direction D1. Each of the first standard cell ST1 and the second standard cell ST2 can include a pair of a PMOS region PR and an NMOS region NR. A gate electrode GE can be disposed to cross the PMOS region PR and the NMOS region NR. A first power line MP1 can be disposed adjacent to the first standard cell ST1. A second power line MP2 can be provided between the first standard cell ST1 and the second standard cell ST2. A third power line MP3 can be disposed adjacent to the second standard cell ST2. The first power line MP1 to the third power line MP3 can be substantially the same as or similar to the first power line MP1 to the third power line MP3 described with reference to Figure 9 Some of the source / drain contacts CA can be electrically connected to the first power line MP1 or the third power line MP3 through the source / drain vias VA.

[0106] A gate contact CB can be disposed on at least some of the gate electrodes GE and can be electrically connected to the first line M1 through a gate via VB. A dummy gate contact DCB can be disposed on at least some of the gate electrodes GE. In the present embodiment, the dummy gate contact DCB can be located between the PMOS region PR and the NMOS region NR. The dummy gate contact DCB can be connected to a dummy line DM1 through a dummy gate via DVB. The dummy line DM1 can not be electrically connected to other lines other than the gate electrodes GE. Except for these differences, the semiconductor device 10m according to the present embodiment can have features substantially the same as or similar to those in the previous embodiments.

[0107] Figure 17 is a layout showing a semiconductor device according to an embodiment of the present inventive concept. Figure 17 may be a layout of a single standard cell.

[0108] Referring to Figure 17The semiconductor device 10n can include a substrate 1. A PMOS region PR and an NMOS region NR can be provided in the substrate 1. Insulating isolation patterns IS can be provided on the substrate 1 to be spaced apart from each other. First to fifth gate electrodes GE1 to GE5 can be provided between the insulating isolation patterns IS to be spaced apart from each other in a second direction D2. Source / drain contacts CA can be provided between the left insulating isolation pattern IS and the first gate electrode GE1, between the first to fifth gate electrodes GE1 to GE5, and between the fifth gate electrode GE5 and the right insulating isolation pattern IS. A first power line MP1 can be provided on end portions of the first to fifth gate electrodes GE1 to GE5. A second power line MP2 can be provided on other end portions of the first to fifth gate electrodes GE1 to GE5. First to fourth lines M1 to M4 can be provided between the first power line MP1 and the second power line MP2 to be spaced apart from each other in a first direction D1. An auxiliary line AM1 can be provided between the fourth line M4 and the second power line MP2.

[0109] In the PMOS region PR, gate contacts CB can be provided on the second to fifth gate electrodes GE2 to GE5, respectively. The gate contacts CB can be electrically connected to the first line M1 through gate vias VB. The first line M1 can be electrically connected to the source / drain contact CA adjacent to one side of the first gate electrode GE1 through a source / drain via VA. A plurality of auxiliary gate contacts ACB can be provided in the NMOS region NR and on the second to fifth gate electrodes GE2 to GE5, respectively. The auxiliary gate contacts ACB can be electrically connected to the auxiliary line (i.e., auxiliary interconnection line) AM1 through auxiliary gate vias AVB. The auxiliary line AM1 can be electrically connected to the first line M1 and can be applied with the same electrical signal as in the first line M1. For example, a voltage generator VG can generate a first voltage and apply the first voltage to the first line M1 and the auxiliary line AM1. The electrical connection between the voltage generator VG, the first line M1, and the auxiliary line AM1 can be made using an interconnection line located at the same level as the first line M1 or at a higher level. For simplicity of the drawing, such electrical connections between the voltage generator VG, the first line M1, and the auxiliary line AM1 can be omitted.

[0110] Figure 18 is a layout showing a semiconductor device according to an embodiment of the inventive concept.

[0111] Referring to Figure 18semiconductor device 10o according to the present embodiment can include a substrate 1 in which a PMOS region PR and an NMOS region NR are provided. Two active fins AF can be disposed in each of the PMOS region PR and the NMOS region NR. The two active fins AF disposed between the PMOS region PR and the NMOS region NR can also be dummy fins in some embodiments. The active fins AF can be spaced apart from each other in a first direction and can extend in a second direction D2. First to fifth gate electrodes GE1-GE5 can extend in the first direction D1 to cross the active fins AF. The first to fifth gate electrodes GE1-GE5 can be spaced apart from each other by the same distance in the second direction D2. Each of the first to fifth gate electrodes GE1-GE5 can have a first width W1 when measured in the second direction D2.

[0112] One of the gate contacts (CB1-CB3) and one of the dummy gate contacts (DCB1-DCB3) can be disposed on each of the second to fourth gate electrodes GE2-GE4. Each of the gate contacts (CB1-CB3) can have a second width W2 when measured in the second direction D2. Each of the dummy gate contacts (DCB1-DCB3) can have a third width W3 when measured in the second direction D2. The second width W2 can be equal to the third width W3. The second width W2 can be greater than the first width W1 of each of the first to fifth gate electrodes GE1-GE5. In an embodiment, the second width W2 can be about 3 to 5 times the first width W1. For example, the first width W1 can be about 4 nm, and the second width W2 can be about 16 nm. Terms such as“about” or“approximately” can reflect a quantity, dimension, orientation, or placement that varies only in a minor relative way and / or in a way that does not significantly change the operation, function, or structure of certain elements. For example, a range from“about 0.1 to about 1” can encompass ranges from, such as, 0% to 5% deviation around 0.1 and 0% to 5% deviation around 1, especially if such deviations maintain the same effect as the range listed.

[0113] Each active fin AF can have a fourth width W4 when measured in the first direction D1. Each of the gate contacts (CB1-CB3) can have a fifth width W5 when measured in the first direction D1. Each of the dummy gate contacts (DCB1-DCB3) can have a sixth width W6 when measured in the first direction D1. The fifth width W5 can be equal to the sixth width W6. The fifth width W5 can be greater than the fourth width W4. In an embodiment, the fifth width W5 can be about 1.5 to 2.5 times the fourth width W4. For example, the fourth width W4 can be about 8 nm, and the fifth width W5 can be about 16 nm.

[0114] The gate contacts (CB1-CB3) can overlap portions of the active fins AF. The dummy gate contacts (DCB1-DCB3) can overlap portions of the active fins AF. The first gate contact CB1 can be disposed on the PMOS region PR and on the second gate electrode GE2. The second gate contact CB2 can be disposed between the PMOS region PR and the NMOS region NR and on the third gate electrode GE3. The third gate contact CB3 can be disposed adjacent to a boundary of the PMOS region PR and on the fourth gate electrode GE4. The second dummy gate contact DCB2 can be disposed on the PMOS region PR and on the third gate electrode GE3.

[0115] The first gate contact CB1, the second gate contact CB2, and the second dummy gate contact DCB2 can be disposed to have centers located at vertices of a triangle (hereinafter, a first triangle TG1), respectively. In an embodiment, the first triangle TG1 can be a right triangle. The first triangle TG1 can have a first angle Θ1 at the center of the first gate contact CB1. In an embodiment, the first angle Θ1 can be an angle between about 30° and about 50°.

[0116] The third gate contact CB3, the second gate contact CB2, and the second dummy gate contact DCB2 can be disposed to have centers located at vertices of a triangle (hereinafter, a second triangle TG2), respectively. In an embodiment, the second triangle TG2 can be an isosceles triangle. The second triangle TG2 can have a second angle Θ2 at the center of the third gate contact CB3. The second angle Θ2 can be an angle between about 30° and about 50°.

[0117] Figure 19 is a layout illustrating a semiconductor device according to an embodiment of the present inventive concept.

[0118] Referring to Figure 19 , the semiconductor device 10p according to the present embodiment can include a substrate 1 in which a PMOS region PR and an NMOS region NR are provided. Three active fins AF can be disposed in each of the PMOS region PR and the NMOS region NR. One active fin AF can be disposed between the PMOS region PR and the NMOS region NR. Gate electrodes GE can be disposed to cross the active fins AF. Gate contacts CB and dummy gate contacts DCB can be disposed on the gate electrodes GE. Each dummy gate contact DCB can be disposed between the active fins AF or can overlap at least a portion of the active fins AF. Except for the above differences, the semiconductor device 10p according to the present embodiment can have substantially the same features as those described with reference to Figure 18 .

[0119] Figure 20 is a layout showing a semiconductor device according to an embodiment of the inventive concept.

[0120] Referring to Figure 20 , the semiconductor device 10q according to the present embodiment can include a substrate 1 in which a PMOS region PR and an NMOS region NR are provided. Two active fins AF can be disposed in each of the PMOS region PR and the NMOS region NR. The two active fins AF can be disposed between the PMOS region and the NMOS region NR adjacent to each other in a first direction. A gate electrode GE can be disposed to cross the active fins AF. A gate contact CB and a dummy gate contact DCB can be disposed on the gate electrode GE. Each dummy gate contact DCB can be disposed between the two active fins AF or can overlap at least a portion of the active fins AF. A width of the active fins AF measured in the first direction D1 can be about 5 nm. Each dummy gate contact DCB can be adjacent to a boundary of the NMOS region NR or the PMOS region PR. Except for the above differences, the semiconductor device 10q according to the present embodiment can have substantially the same features as those described with reference to Figure 18 .

[0121] According to embodiments of the inventive concept, a semiconductor device can include a dummy gate contact that improves a signal speed or performance of the semiconductor device. Further, the dummy gate contact can be used to suppress a leakage current, which makes it possible to improve a reliability of the semiconductor device.

[0122] While embodiments of the inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that changes in form and details can be made therein without departing from the spirit and scope of the claims.

[0123] This application claims priority from Korean Patent Application Nos. 10-2019-0094008, 10-2019-0097258, and 10-2020-0007423, filed on August 1, 2019, August 9, 2019, and January 20, 2020, respectively, with the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

Claims

1. A semiconductor device, comprising: A first gate electrode is disposed on a substrate and extends in a first horizontal direction about the upper surface of the substrate; The first gate contact and the dummy gate contact are spaced apart from each other in the first horizontal direction and are in contact with the top surface of the first gate electrode; The first interconnect extends in a second horizontal direction different from the first horizontal direction with respect to the upper surface of the substrate, and contacts and overlaps the first gate in a vertical direction with respect to the upper surface of the substrate. A device isolation layer is disposed in the substrate to define an active region; and A voltage generator is configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect and the first gate contact. The dummy gate contact receives the first voltage through the first gate electrode, and The dummy gate contact overlaps with the active region in the vertical direction or is adjacent to the active region in the first horizontal direction.

2. The semiconductor device according to claim 1, further comprising: A gate path is disposed on the first gate contact and inserted in the vertical direction between the first interconnect and the first gate electrode.

3. The semiconductor device according to claim 1, further comprising: A dummy gate path is provided on the dummy gate contact; and The dummy interconnects are configured on the dummy gate path. The dummy interconnect extends in the second horizontal direction. The dummy interconnects are horizontally spaced from the first interconnects in the first horizontal direction, and The dummy gate contact overlaps with the dummy interconnect in the vertical direction.

4. The semiconductor device according to claim 3, The dummy interconnect extends in the second horizontal direction and is spaced apart from the first interconnect in the first horizontal direction, and The first voltage is applied to the dummy interconnect via the first gate electrode, the dummy gate contact, and the dummy gate path.

5. The semiconductor device according to claim 1, further comprising: The active fin protrudes from the substrate in the vertical direction and has a top surface that is higher than the top surface of the device isolation layer. The dummy gate path overlaps with the active fin in the vertical direction.

6. The semiconductor device according to claim 5, further comprising: Multiple channel patterns are sequentially stacked on the active fin in the vertical direction. The first gate electrode is configured to surround each of the plurality of channel patterns.

7. The semiconductor device according to claim 2, further comprising: Interlayer insulation layer, The first interconnect and the gate path are disposed in the interlayer insulating layer. The gate path is in contact with the bottom surface of the first interconnect and the top surface of the first gate contact. The interlayer insulating layer contacts the top surface of the dummy gate contact, and The top surface of the first gate contact and the top surface of the dummy gate contact are located at the same height from the upper surface of the substrate in the vertical direction.

8. The semiconductor device according to claim 7, further comprising: A second gate electrode is disposed on the substrate and extends in the first horizontal direction. The second gate electrode is spaced apart from the first gate electrode in the second horizontal direction that intersects the first horizontal direction; The second gate contact is disposed on the second gate electrode; The third gate electrode is spaced apart from the second gate electrode in the first horizontal direction; as well as A gate separator pattern is inserted between the end of the second gate electrode and the end of the third gate electrode.

9. The semiconductor device according to claim 1, The device isolation layer defines a first active region and a second active region spaced apart from each other in the first horizontal direction within the substrate. The first gate electrode is configured to span across the first active region and the second active region. The first gate contact overlaps with the portion of the device isolation layer between the first active region and the second active region in the vertical direction, and The dummy gate contact overlaps with one of the first active region and the second active region in the vertical direction, or is adjacent to one of the first active region and the second active region in the first horizontal direction.

10. A semiconductor device, comprising: Multiple gate electrodes on the substrate Each of the plurality of gate electrodes extends in a first horizontal direction about the upper surface of the substrate, and the plurality of gate electrodes are spaced apart from each other in a second horizontal direction about the upper surface of the substrate, the second horizontal direction being different from the first horizontal direction; Multiple gate contacts, Each of the plurality of gate contacts is disposed on and electrically connected to a corresponding one of the plurality of gate electrodes; Multiple interconnecting lines Each of the plurality of interconnects extends in the second horizontal direction and overlaps with at least one of the plurality of gate contacts in a vertical direction relative to the upper surface of the substrate. The plurality of interconnect lines are spaced apart from each other in the first horizontal direction; A voltage generator configured to generate a first voltage and apply the first voltage to the plurality of gate electrodes via the plurality of gate contacts and the plurality of interconnects; A device isolation layer is disposed in the substrate to define a first active region and a second active region spaced apart from each other in the first horizontal direction; as well as A dummy gate contact is disposed on a corresponding gate electrode among the plurality of gate electrodes, and is spaced apart in the first horizontal direction from the gate contacts disposed on the corresponding gate electrode among the plurality of gate contacts. The first voltage is applied to the dummy gate contact through the corresponding gate electrode, and The dummy gate contact overlaps with one of the first active region and the second active region in the vertical direction, or is adjacent to one of the first active region and the second active region in the first horizontal direction.

11. The semiconductor device of claim 10, further comprising: Multiple gate paths are respectively disposed on the multiple gate contacts. Each of the plurality of gate paths is inserted in the vertical direction between a corresponding gate contact among the plurality of gate contacts and a corresponding interconnect among the plurality of interconnects.

12. The semiconductor device according to claim 10, further comprising: A dummy gate path is provided on the dummy gate contact.

13. The semiconductor device according to claim 12, further comprising: The dummy interconnects are configured on the dummy gate path. The dummy gate path is inserted between the dummy interconnect and the dummy gate contact in the vertical direction, and The first voltage from the voltage generator is applied to the dummy interconnect via the dummy gate contact and the dummy gate path.

14. The semiconductor device according to claim 10, The plurality of gate electrodes are configured to span across the first active region and the second active region. At least one of the plurality of gate contacts is disposed between the first active region and the second active region and on the device isolation layer, and The dummy gate contact overlaps with one of the first active region and the second active region in the vertical direction, or is disposed adjacent to one of the first active region and the second active region in the first horizontal direction.

15. A semiconductor device, comprising: The substrate includes a first active region and a second active region spaced apart from each other in a first horizontal direction about the upper surface of the substrate; Multiple active fins protrude from the substrate in a vertical direction with respect to the upper surface of the substrate and extend in a second horizontal direction with respect to the upper surface that intersects the first horizontal direction; The first gate electrode, the second gate electrode, and the third gate electrode intersect the plurality of active fins in the first horizontal direction, are parallel to each other in the second horizontal direction, and form a linear pattern. A first gate contact is disposed on the second gate electrode and overlaps with the region between the first active region and the second active region in the vertical direction; The first dummy gate contact overlaps with the second gate electrode in the vertical direction and is spaced apart from the first gate contact in the first horizontal direction. The first dummy gate contact overlaps with one of the first active region and the second active region in the vertical direction, or is adjacent to one of the first active region and the second active region in the first horizontal direction. Wherein at least two or at least three of the plurality of active fins are disposed in each of the first active region and the second active region; A first interconnect extends in the second horizontal direction and contacts and overlaps with the first gate in the vertical direction; as well as A voltage generator is configured to generate a first voltage and apply the first voltage to the second gate electrode via the first gate contact and the first interconnect. The first voltage is applied to the first dummy gate contact through the second gate electrode.

16. The semiconductor device according to claim 15, Each of the first dummy gate contact and the first gate contact overlaps with a corresponding one of the plurality of active fins in the vertical direction, or overlaps with the region between two adjacent active fins in the plurality of active fins in the vertical direction.

17. The semiconductor device of claim 15, further comprising: A second gate contact is disposed on the first gate electrode and in the first active region; and The second dummy gate contact is disposed on the first gate electrode and in the second active region. The first voltage is applied to the first gate electrode through the second gate contact and to the second dummy gate contact through the first gate electrode.

18. The semiconductor device of claim 17, further comprising: The third gate contact is adjacent to the boundary of the first active region in the first horizontal direction and overlaps with the third gate electrode in the vertical direction; and The third dummy gate contact is adjacent to the boundary of the second active region in the first horizontal direction and overlaps with the third gate electrode in the vertical direction. The first voltage is applied to the third gate electrode through the third gate contact and to the third dummy gate contact through the third gate electrode.

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