A method of manufacturing an integrated circuit

Abstract

The application discloses a preparation method of an integrated circuit and relates to the technical field of integrated circuits; the method comprises the following steps: pretreating an N-type monocrystalline silicon substrate; depositing a SiO2-Si3N4-SiO2 transition layer containing CeO2; implanting phosphorus ions with low and high energy to form an active region; depositing a TiN barrier layer and a TiMoV barrier layer containing nano Cr on the surface of the active region in sequence; electroplating a CuMnFe interconnection layer containing Y; annealing; and preparing a passivation structure of a composite passivation inner layer. The preparation method can solve the problems that the existing integrated circuit has a high failure rate during low-temperature starting, the interconnection layer is prone to failure under temperature variation and vibration, and the integrated circuit is prone to electric leakage caused by oil penetration when the integrated circuit is applied to an engine compartment of a vehicle; and finally, the integrated circuit that meets the requirements of high and low temperature cycles of -35 DEG C to 120 DEG C, 10-2000Hz wide frequency vibration and resistance to oil pollution of the engine compartment of the vehicle is prepared, so that the long-term reliable operation of an electronic module is ensured.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for fabricating integrated circuits suitable for automotive engine compartments. Background Technology

[0002] Electronic modules in the automotive engine compartment (such as ignition control modules and sensor signal processing modules) need to operate in a complex and harsh environment for extended periods. In terms of temperature, during a cold start in winter, the compartment temperature can rapidly drop below -35°C, while after the engine resumes normal operation, the temperature rises again to 120°C or even higher, creating frequent high-low temperature cycles between -35°C and 120°C. In terms of vibration, the engine generates wide-frequency vibrations of 10-2000Hz with 10g acceleration during operation, which continuously affect the interlayer structure of integrated circuits. Furthermore, engine oil vapor is generated in the compartment, which easily mixes with dust to form sticky oil stains that directly contact the surface of integrated circuits.

[0003] However, current design standards for commercial integrated circuits are mainly designed for general consumer electronics or industrial applications (commercial-grade temperature range is typically 0℃~70℃), and their application in automotive engine compartments presents the following problems:

[0004] Firstly, the threshold voltage of traditional silicon-based MOSFETs increases significantly in low-temperature environments, resulting in insufficient start-up voltage for electronic modules. This leads to a higher failure rate during cold starts in winter and, in severe cases, prevents the engine from starting normally.

[0005] Secondly, conventional integrated circuits mostly use aluminum-silicon alloys as interconnects, whose coefficient of thermal expansion differs significantly from that of the silicon substrate. Under the combined effects of high and low temperature cycling and broadband vibration, the interconnects may peel or break due to continuous stress concentration, and the mean time between failures (MTBF) of electronic modules is far lower than the standards required by the automotive electronics industry.

[0006] Third, traditional integrated circuits use silicon dioxide as a passivation layer, which has poor barrier properties against organic oil stains. When oil vapor mixed with dust in the engine compartment, it can easily penetrate into the passivation layer, causing a significant increase in leakage current in the circuit, leading to malfunctions or even failure of electronic modules.

[0007] Therefore, it is extremely important to develop a method for fabricating application-specific integrated circuits that can adapt to the harsh environment of automotive engine compartments. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for fabricating integrated circuits to solve problems such as high failure rate of low-temperature start-up, easy failure of interconnect layers under temperature and vibration, and leakage caused by oil contamination when existing integrated circuits are applied to automobile engine compartments.

[0009] The technical objective of this invention is achieved through the following technical solution:

[0010] An integrated circuit fabrication method includes the following steps:

[0011] S1. Substrate pretreatment: Select an N-type single crystal silicon substrate and perform alkaline cleaning and oxygen-nitrogen mixed atmosphere plasma activation treatment on its functional surfaces in sequence;

[0012] S2. Transition layer preparation: A 30-40 nm thick SiO2-Si3N4-SiO2 three-layer composite transition layer is deposited on the functional surface of the substrate;

[0013] The intermediate Si3N4 layer is doped with 0.8-1.2wt% CeO2, 0.3-0.5wt% 5-10nm nano-Ti powder, and 0.1-0.2wt% 3-5nm LiAlO2 nanoparticles;

[0014] S3. Formation of active region: A source region is provided on the surface of the transition layer, and phosphorus ions are implanted sequentially using low energy of 30-40keV and high energy of 80-100keV;

[0015] S4. Barrier layer preparation: A 4-6 nm thick TiN barrier layer is deposited only on the surface of the active region;

[0016] S5. Barrier layer preparation: A 15-20 nm thick TiMoV barrier layer is deposited only on the surface of the TiN barrier layer, wherein the TiMoV barrier layer is doped with 0.2-0.4 wt% 8-12 nm nano-Cr powder and 0.05-0.1 wt% 2-4 nm Y2O3 nanoparticles;

[0017] S6. Interconnect layer preparation: A 250-300 nm thick CuMnFe interconnect layer is deposited only on the surface of the TiMoV barrier layer using an electroplating process. 0.01-0.03 wt% rare earth Y and 0.02-0.04 wt% ZnSO4 are added to the electroplating solution.

[0018] S7. Synchronous annealing: The structure prepared above is subjected to three-stage annealing, with the first stage temperature being 250-300℃, the second stage temperature being 820-850℃, and the third stage temperature being 400-450℃;

[0019] The aforementioned TiN diffusion barrier layer, TiMoV barrier layer, and CuMnFe interconnect layer together form a step on the surface of the active region;

[0020] S8. Passivation layer preparation:

[0021] S81. A 10-15 nm thick Si3N4 passivation layer is deposited at the edge of the step sidewall;

[0022] S82. A 100-120 nm thick AlN-Si3N4 composite passivation inner layer is deposited on the surface of the interconnect layer and the exposed transition layer; the composite passivation inner layer contains 0.5-0.8 wt% 50-80 nm nano-SiO2 powder and 0.1-0.2 wt% AlN@MgO core-shell particles;

[0023] S83. Coat the surface of the composite passivation inner layer with an 80-100nm thick fluorocarbon resin-PI blend passivation outer layer; incorporate 8-12wt% 40-60nm AlN nanoparticles into the blend passivation outer layer;

[0024] S84. Multiple heat dissipation through-holes are formed on the blended passivation outer layer;

[0025] The integrated circuit is a dedicated integrated circuit for automotive engine compartments.

[0026] As one possible implementation method of this application, in step S1, the volume ratio of the two gases in the oxygen-nitrogen mixed atmosphere is 1:3, the plasma activation RF power is 80-100W, and the activation time is 30-60s. In this scheme, by limiting the relevant parameters, the functional surface of the substrate can be activated more fully, the surface impurity residue can be reduced, the adhesion between the subsequent transition layer and the substrate can be enhanced, and the stability of the underlying structure of the integrated circuit can be improved.

[0027] As some possible implementations of this application, in step S2, the deposition process of the transition layer is LPCVD, the deposition temperature is 680-720℃, the silicon source is TEOS, the ammonia flow rate is 40-60 sccm, and the vacuum degree is 2-4 Torr.

[0028] As one possible implementation of this application, in step S2, the gaps between the two SiO2 layers and the Si3N4 layer are subjected to oxygen atmosphere plasma interface treatment; the power of the oxygen atmosphere plasma interface treatment is 40-60W, and the treatment time is 1-2 minutes. In this scheme, oxygen plasma treatment is performed on the gaps between the two SiO2 and Si3N4 layers to avoid voids caused by weak interfacial bonding inside the transition layer, prevent oil vapor from penetrating from the inside of the transition layer, enhance the overall structural strength of the transition layer, reduce the risk of interlayer cracking during high and low temperature cycling, resist interlayer separation caused by vibration, and improve the synergistic effect of oil stain resistance and vibration resistance.

[0029] As one possible implementation of this application, in step S3, the low-energy implanted phosphorus ion concentration is 1×10⁻⁶. 19 ~2×10 19 cm-3 Dosage 4×10 14 ~6×10 14 cm -2 The high-energy injected phosphorus ion concentration was 4 × 10⁻⁶. 18 ~6×10 18 cm -3 Dosage 1×10 14 ~3×10 14 cm -2 The substrate temperature during implantation is 150-200℃. Furthermore, a beam feedback compensation system is configured during implantation, ensuring beam current fluctuations of ≤±2%. This solution precisely controls the doping depth and concentration uniformity of the active region by limiting the phosphorus ion implantation concentration, dose, substrate temperature, and beam stability, reducing lattice defects and ensuring stable carrier migration. The beam feedback compensation system avoids performance inhomogeneity in the active region caused by beam current fluctuations during implantation, ensuring stable threshold voltage of the MOS transistor in the low-temperature environment of the engine nacelle and reducing startup failures.

[0030] As one possible implementation of this application, in step S5, the TiMoV barrier layer is deposited by magnetron sputtering at a sputtering temperature of 200-220°C and a vacuum degree of ≤5×10⁻⁶. -5 Pa, sputtering power 180-220W.

[0031] As some possible implementations of this application, in step S7, the holding times for the three-stage annealing are: 5-8s for the first stage, 8-10s for the second stage, and 3-5s for the third stage. In this solution, by limiting the annealing time, the three-dimensional bonding network of the transition layer, the interface bonding of the barrier layer and the interconnect layer, and the grain refinement of the interconnect layer can be fully achieved, avoiding insufficient interlayer bonding or unstable interconnect layer performance caused by insufficient annealing, and ensuring long-term reliable operation of the integrated circuit under the combined temperature change and vibration environment of the engine compartment.

[0032] As one possible implementation of this application, in step S82, the deposition process of the AlN-Si3N4 composite passivation inner layer is PECVD, the deposition temperature is 350-380℃, the aluminum source is TMA, and the ammonia flow rate is 50-70 sccm. In this scheme, by limiting the relevant parameters, it is possible to ensure that the components of the composite passivation inner layer are evenly dispersed, improve the inner layer's resistance to oil penetration and thermal conductivity, and avoid the inner layer from becoming structurally loose due to improper process parameters under high-temperature oil conditions, which could lead to oil penetration or poor heat dissipation.

[0033] As some possible implementations of this application, in step S82, the AlN to Si3N4 thickness ratio of the AlN-Si3N4 composite passivation inner layer is 3:1; the TMA flow control accuracy is ≤±2sccm, the reaction pressure is 2.8-3.2 Torr, and the RF power during the AlN deposition stage is gradually increased from 190-210W to 240-260W (RF power gradient adjustment can avoid internal stress in the inner layer during deposition and reduce the risk of inner layer cracking during vibration). In this scheme, by limiting the parameters, the stress absorption and oil barrier effects of the elastic network can be further enhanced.

[0034] As one possible implementation of this application, in step S8, filling the heat dissipation through hole with silver-copper-epoxy composite slurry can improve the heat conduction efficiency of the through hole, quickly dissipate the heat generated by the integrated circuit in the high temperature environment of the engine compartment, and avoid performance degradation caused by excessive local temperature rise.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] 1. The method for fabricating a dedicated integrated circuit for automotive engine compartments provided by this invention, through the synergistic design of a transition layer → active region → barrier layer → blocking layer → interconnect layer → passivation layer, fabricates a dedicated integrated circuit that meets the requirements of high and low temperature cycling (-35℃~120℃), wide-frequency vibration (10-2000Hz), and resistance to engine oil contamination in automotive engine compartments. This method specifically addresses three major issues in engine compartments: high and low temperature cycling, wide-frequency vibration, and engine oil contamination. The details are as follows:

[0037] Regarding the high and low temperature cycling problem:

[0038] ① Transition Layer-Active Region Synergy: In the intermediate Si3N4 layer of the transition layer, CeO2 and LiAlO2 are bonded through Ce-O-Al bridge bonds. During the subsequent high-temperature (820-850℃) second stage of the three-stage annealing process, the CeO2 and LiAlO2 in the intermediate Si3N4 layer are further bonded through Ce-O-Al bridge bonds, forming a three-dimensional bond network with nano-Ti powder. This bond network can absorb the thermal stress generated by high and low temperature cycles through the elastic deformation of chemical bonds, preventing lattice defects in the active region due to thermal stress impact. Simultaneously, the bond network stabilizes the carrier transport environment in the active region, reducing the obstruction of carrier migration at low temperatures, preventing abnormal increases in the threshold voltage of MOS transistors, and solving the problem of poor low-temperature startup reliability in traditional integrated circuits.

[0039] ② Barrier Layer-Interconnect Layer Synergy: The alloying properties of Mo and V in the TiMoV barrier layer, combined with the solid solution formed by nano-Cr powder, can enhance the structural stability of the barrier layer and suppress the diffusion of Cu atoms into the active region at high temperatures; and the Y₂O₃… 3+It can form metallic bonds with rare earth Y in the interconnect layer, strengthening the interfacial bonding between the barrier layer and the interconnect layer and reducing thermal stress caused by the difference in their coefficients of thermal expansion. In addition, the solid solution formed by Mn in the CuMnFe interconnect layer and ZnSO4 in the electroplating solution can refine the interconnect layer grains, reduce the fluctuation of its coefficient of thermal expansion, and further reduce the risk of interlayer delamination caused by temperature changes.

[0040] Regarding vibration issues:

[0041] ① Synergistic effect of transition layer-barrier layer-blocking layer: The three-dimensional bond network of the transition layer has good stress dispersion ability, which can uniformly transfer the local stress generated by the 10-2000Hz broadband vibration to the entire transition layer, avoiding stress concentration; the TiN barrier layer and the transition layer LiAlO2 form a tight interface bond through physical adsorption and ion diffusion, which can enhance the interlayer bonding strength of the active region surface and prevent the barrier layer from falling off due to vibration; the Y2O3 in the TiMoV blocking layer 3+ With the N of the TiN layer 3— Ionic bonds are formed through electrostatic interactions, which further enhances the vibration resistance of the barrier layer and the interfacial layer, and reduces interlayer delamination caused by vibration.

[0042] ② Interconnect layer-passivation layer synergy: The CuMnFe interconnect layer is synergistically modified with rare earth Y and ZnSO4, and the refined grains enhance its plastic deformation capacity, which can alleviate stress concentration during vibration through its own deformation; the elastic network formed by the MgO shell of AlN@MgO core-shell particles and nano-SiO2 powder in the composite passivation inner layer can absorb vibration energy and reduce the risk of cracking of the passivation layer due to vibration; the Si3N4 passivation layer deposited on the stepped sidewall can fill the interlayer gaps, enhance the integrity of the sidewall structure, avoid sidewall damage caused by vibration, and ensure the stability of the overall structure under long-term vibration environment.

[0043] Regarding the oil temperature issue:

[0044] ① Synergistic effect of composite passivation inner and outer layers: The composite passivation inner layer has an AlN-Si3N4 composite structure. The MgO shell of the AlN@MgO core-shell particles has good chemical inertness, which can block the penetration of oil vapor and dust mixed with oil stains; the AlN component can improve the thermal conductivity of the inner layer and avoid local temperature rise caused by oil stains. The fluorocarbon resin-PI blend system of the blended passivation outer layer has low surface energy, which can reduce oil stain adhesion, and the incorporated AlN nanoparticles can enhance the density of the outer layer structure, further blocking the oil stain penetration path and avoiding the problem of increased leakage current caused by oil stain penetration in traditional silicon dioxide passivation layers.

[0045] ② Full-structure oil-resistant auxiliary: The dense structure of the TiN barrier layer can block oil from entering from the edge of the active area; the stable structure formed by the Mo-Cr solid solution and Y2O3 in the TiMoV barrier layer can prevent oil from corroding the barrier layer and avoid its barrier performance failure; the three-layer structure of SiO2-Si3N4-SiO2 in the transition layer also has a certain barrier effect on oil, which, together with the passivation layer, forms a multi-layer oil protection system to ensure the long-term stable operation of integrated circuits in the oil vapor environment.

[0046] 2. Unlike existing technologies that anneal each layer individually, this invention employs a single temperature gradient annealing process after all functional layers have been deposited. This avoids interlayer interface oxidation and thermal stress accumulation caused by multiple annealing processes, simultaneously enhancing the performance of each layer and cross-layer bonding, thus meeting the vibration and temperature change resistance requirements of automotive engine compartments. Specifically, in the first low-temperature stage (250-300℃), the transition layer nano-Ti powder absorbs the lattice stress remaining from ion implantation in the active region, while the Li in LiAlO2... + The initial activation energy is obtained to prepare for subsequent high-temperature diffusion and avoid stress concentration caused by the instantaneous and violent diffusion of ions during subsequent high-temperature treatment; under the second high temperature (820-850℃), the transition layer CeO2 and LiAlO2 fully react to construct a stable three-dimensional bond network, and the activated Li in LiAlO2... + Ionic bonds are formed by diffusion into the TiN barrier layer, Mo-V in the barrier layer forms a solid solution with Cr powder, Y2O3 forms metallic bonds with rare earth Y in the interconnect layer, and Mn and ZnSO4 in the interconnect layer form a solid solution to refine the grains, simultaneously enhancing the performance of each layer and cross-layer bonding. In the third stage, at a medium temperature (400-450℃), the bonding structure of each layer is stabilized and solidified. Slow cooling reduces the difference in thermal expansion between the substrate and the functional layers to avoid cracking, while ensuring the surface smoothness of the interconnect layer, laying the foundation for subsequent passivation layer deposition. This process not only reduces the number of annealing times but also avoids the problems of interlayer oxidation and thermal stress accumulation that may be caused by multiple annealing, effectively improving the integrated circuit's resistance to vibration, temperature changes, and Cu diffusion, ensuring its long-term reliable operation in the harsh environment of an automotive engine compartment. Detailed Implementation

[0047] Example 1

[0048] S1. Substrate Pretreatment: Select an N-type single-crystal silicon substrate (12 inches in diameter, 725 μm thick) with a resistivity of 2-5 Ω·cm. Clean the functional surfaces with a 4 wt% potassium hydroxide solution (65°C, 12 min), then activate them with plasma in an oxygen-nitrogen mixed atmosphere (oxygen:nitrogen = 1:3, volume ratio) (RF power 90 W, processing time 60 s). Deposit a 50 nm SiO2 insulating layer on the back side using PECVD process, with an insulation resistance ≥ 1 × 10⁻⁶.14 Ω・cm.

[0049] S2. Transition Layer Preparation: A 35nm thick SiO2-Si3N4-SiO2 three-layer composite transition layer was deposited on the functional surface of the substrate using LPCVD process, with a thickness ratio of 1:2:1 (7nm SiO2 layer near the functional surface, 14nm Si3N4 layer, and 14nm SiO2 layer away from the functional surface). The deposition temperature was 700℃, the silicon source was TEOS, the ammonia flow rate was 50sccm, and the vacuum degree was 3Torr. The middle Si3N4 layer was doped with 1.0wt% CeO2, 0.4wt% 8nm nano-Ti powder, and 0.15wt% 4nm LiAlO2 nanoparticles. The gaps between the two SiO2 and Si3N4 deposition layers were treated with oxygen atmosphere plasma (50W power, 55s time).

[0050] S3. Active region formation: A 500μm × 500μm active region is delineated on the surface of the transition layer, and then sequentially applied with a low energy of 35keV (phosphine ion concentration 1.5 × 10⁻⁶). 19 cm -3 Dosage 5×10 14 cm -2 ), 90keV high energy (phosphine ion concentration 5×10), 18 cm -3 Dosage 2×10 14 cm -2 Phosphorus ions are implanted; the substrate temperature during implantation is 180℃; a beam current feedback compensation system is also configured during implantation, with beam current fluctuation ≤±2% per hour; the active region doping depth is 120nm, and the flatness deviation with the transition layer surface is ≤±3nm.

[0051] S4. Barrier layer fabrication: A 5nm thick TiN barrier layer was deposited only on the surface of the active region using the ALD process, with a pulse period of TiCl4:NH3=1:2 (50ms / pulse) and a substrate temperature of 250℃.

[0052] S5. Barrier Layer Preparation: An 18 nm thick TiMoV barrier layer was deposited solely on the TiN barrier layer surface using magnetron sputtering. The layer contained 4% Mo (atomic fraction) and 1.5% V (atomic fraction), along with 0.3 wt% 10 nm Cr nanoparticles and 0.08 wt% 3 nm Y₂O₃ nanoparticles. The sputtering temperature was 210 °C, and the vacuum degree was 3 × 10⁻⁶. -5 Pa, sputtering power 200W.

[0053] S6. Interconnect Layer Preparation: A 280 nm thick Cu-0.2Mn-0.1Fe interconnect layer (i.e., Mn mass percentage 0.2%, Fe mass percentage 0.1%, and the remaining 99.7% Cu) was deposited only on the TiMoV barrier layer surface using an electroplating process. This was achieved through a single, simultaneous deposition process using a mixed electroplating method, with 0.05 wt% ethylenediaminetetraacetic acid (EDTA) added to the electroplating solution as a complexing agent (EDTA reacts with Cu). 2+ Mn 2+ Fe 2+ The coordination molar ratios were 1:1, the electroplating solution temperature was 55℃, the current density was 2.5A / dm², the pulse current duty cycle was 50%, and 0.02wt% rare earth Y and 0.03wt% ZnSO4 were added to the electroplating solution; the thickness of the interconnect layer corner (the 90° bend extending from the edge of the active region to the chip peripheral pad) was 364nm (30% thicker than the 280nm of the straight region).

[0054] S7. Synchronous annealing: The structure prepared above is subjected to three-stage annealing: the first stage is held at 280℃ for 6s, the second stage is held at 830℃ for 9s, and the third stage is held at 420℃ for 4s. The annealing atmosphere is nitrogen + 3% hydrogen (volume fraction, total flow rate 500-600 sccm).

[0055] S8. Passivation layer preparation:

[0056] S81. A 12 nm thick Si3N4 passivation layer is deposited on the edge of the sidewall of the step (TiN diffusion barrier layer, TiMoV barrier layer, and CuMnFe interconnect layer are formed together on the surface of the active region to form the step);

[0057] S82. A 110 nm thick AlN-Si3N4 composite passivation inner layer was deposited on the surface of the interconnect layer and the exposed transition layer using PECVD process. The AlN to Si3N4 thickness ratio was 3:1, the deposition temperature was 360℃, the aluminum source was TMA, the ammonia flow rate was 60 sccm, the TMA flow control accuracy was ±1.5 sccm, the reaction pressure was 3.0 Torr, and the RF power was gradually increased from 200W to 250W during the AlN deposition stage.

[0058] The composite passivation inner layer contains 0.6 wt% 60 nm nano-SiO2 powder and 0.15 wt% AlN@MgO core-shell particles (core 25 nm, shell 8 nm). The mass ratio of doping in the AlN layer to the Si3N4 layer is 7:3. During doping, the nano-SiO2 powder and AlN@MgO core-shell particles are first mixed and then added to the corresponding precursors.

[0059] The preparation method of AlN@MgO core-shell particles is as follows:

[0060] A 0.1 mol / L aluminum nitrate solution and a 0.1 mol / L urea solution were mixed at a volume ratio of 1:2 and stirred in an 80°C water bath for 3 hours to generate an aluminum hydroxide precursor. The precursor was then placed in a tube furnace and calcined at 1200°C for 4 hours under a nitrogen atmosphere. After cooling, it was ground to obtain 25 nm AlN nanoparticles. The AlN nanoparticles were then dispersed in deionized water at a concentration of 10 g / L, and 0.01 wt% silane coupling agent (KH550) was added. The mixture was ultrasonically treated at 300 W for 30 minutes. Finally, a 0.02 mol / L magnesium nitrate solution (AlN and Mg) was added. 2+ The mixture was prepared with ammonia water at a molar ratio of 1:0.3, and the pH was adjusted to 9.0. The mixture was stirred at 60°C for 1 hour. The mixture was then transferred to a hydrothermal reactor and hydrothermally reacted at 180°C for 6 hours. After cooling, the mixture was centrifuged. The product was calcined at 500°C for 3 hours in air to obtain AlN@MgO core-shell particles.

[0061] S83. A 90nm thick fluorocarbon resin-PI blended passivation outer layer is coated on the surface of the composite passivation inner layer, wherein the mass ratio of fluorocarbon resin and PI is 3:7, and 10wt% 50nm AlN nanoparticles are also incorporated into the blended passivation outer layer.

[0062] S84. Multiple heat dissipation through holes are opened above the non-active region of the blended passivation outer layer (no through holes above the active region). The through holes are 10 μm in diameter, 50 μm apart, and arranged in a matrix. The through holes are filled with silver-copper-epoxy composite slurry (75 wt% silver, 15 wt% copper, and 10 wt% epoxy).

[0063] Example 2

[0064] Compared to Example 1, the following adjustments are made; all other aspects are the same as in Example 1.

[0065] S1. Potassium hydroxide solution concentration 5%, cleaning temperature 68℃, treatment time 10min; plasma activation power 85W, time 42s; back side SiO2 insulating layer thickness 48nm.

[0066] S2. The total thickness of the transition layer is 32nm (8nm for the SiO2 layer near the functional surface, 16nm for the Si3N4 layer, and 8nm for the SiO2 layer away from the functional surface), the deposition temperature is 690℃, and the ammonia flow rate is 45sccm; the Si3N4 layer is doped with 0.9wt% CeO2, 0.35wt% 7nm nano-Ti powder, and 0.12wt% 3.5nm LiAlO2 nanoparticles.

[0067] S3. Low-energy injection voltage 32keV, phosphorus ion concentration 1.2×10⁻⁶ 19 cm -3 Dosage: 4.5 × 10 14 cm -2 High-energy injection voltage 85keV, phosphorus ion concentration 4.5×10⁻⁶ 18 cm -3 Dosage 1.5 × 10 14 cm -2 Substrate temperature 170℃.

[0068] S6. Interconnect layer thickness 260nm, electroplating bath temperature 52℃, current density 2.2A / dm²; corner thickness 290nm (11.5% increase).

[0069] S8. The composite passivation inner layer is 105nm thick (AlN layer 78.75nm, Si3N4 layer 26.25nm), and the heat dissipation via diameter is 9μm with a spacing of 45μm.

[0070] Comparative Example 1

[0071] Compared to Example 1, CeO2 is removed from the S2 transition layer.

[0072] The remaining steps and parameters are the same as in Example 1.

[0073] Comparative Example 2

[0074] Compared to Example 1, Y2O3 nanoparticles are removed from the S5 barrier layer.

[0075] The remaining steps and parameters are the same as in Example 1.

[0076] Comparative Example 3

[0077] Compared to Example 1, the S82 composite passivation inner layer removes AlN@MgO core-shell particles.

[0078] The remaining steps and parameters are the same as in Example 1.

[0079] Comparative Example 4

[0080] Compared to Example 1, the S4 barrier layer is removed, and a TiMoV barrier layer is directly deposited on the surface of the active region.

[0081] The remaining steps and parameters are the same as in Example 1.

[0082] Comparative Example 5

[0083] Compared to Example 1, the three-stage simultaneous annealing is changed to three-stage layered annealing, as detailed below:

[0084] After deposition of the S2 transition layer: annealing at 250℃ for 5 seconds;

[0085] After deposition of the S6 interconnect layer: annealing at 820℃ for 8 seconds;

[0086] Before S7 passivation layer deposition: annealing at 400℃ for 3 seconds;

[0087] The remaining steps and parameters are the same as in Example 1.

[0088] Comparative Example 6

[0089] Compared to Example 1, the interconnect layer is replaced with a conventional Al-1% Si alloy (i.e., the mass fraction of Si is 1%), and the transition layer is replaced with a single SiO2 layer.

[0090] The remaining steps and parameters are the same as in Example 1.

[0091] Comparative Example 7

[0092] Compared to Example 1, the passivation outer layer is replaced with a 90nm conventional SiO2 layer.

[0093] The remaining steps and parameters are the same as in Example 1.

[0094] Comparative Example 8

[0095] Compared to Example 1, LiAlO2 is removed from the transition layer in S2.

[0096] The remaining steps and parameters are the same as in Example 1.

[0097] Experimental Example

[0098] The integrated circuits prepared in Examples 1, 2, and Comparative Examples 1-8 were subjected to relevant performance tests. The test conditions simulated the actual working conditions of an automobile engine compartment. The test results are shown in Table 1.

[0099] The specific test experiments are as follows:

[0100] (1) Low temperature start reliability test: The sample was placed in a -35℃ low temperature chamber for 24 hours to simulate the cold start environment in winter. Then the threshold voltage drift rate of the MOS tube was measured. The test was repeated 50 times, and the failure rate of the electronic module was counted each time it started.

[0101] Wherein, threshold voltage drift rate = (threshold voltage at low temperature - threshold voltage at room temperature) / threshold voltage at room temperature × 100%;

[0102] (2) Temperature-vibration synergistic failure test: The sample was first subjected to high and low temperature cycling from -35℃ to 120℃ (1000 cycles, heating / cooling rate 5℃ / min), and then subjected to wideband vibration of 10-2000Hz (10g acceleration, 10 7 (After each cycle), the interconnect layer fracture rate and interlayer peeling rate are detected, and the mean time between failures (MTBF) of the electronic module is calculated.

[0103] Wherein, the interconnect layer breakage rate = number of broken interconnect segments / total number of interconnect segments × 100%;

[0104] (3) Oil penetration resistance test: The sample was immersed in 120℃ engine oil (simulating the high temperature engine oil environment in the engine compartment) for 1000h. During this period, the change rate of leakage current of the circuit was measured every 200h. After the test, the penetration depth of oil in the passivation layer was detected.

[0105] Wherein, the leakage current change rate = (leakage current after immersion - leakage current before immersion) / leakage current before immersion × 100%.

[0106] Table 1 Test Results:

[0107]

[0108] As shown in Table 1, Examples 1-2 strictly followed the entire fabrication process provided by this invention, which included substrate pretreatment, transition layer preparation, active region formation, barrier layer preparation, blocking layer preparation, interconnect layer preparation, simultaneous annealing, and passivation layer preparation. The final integrated circuit exhibited a low-temperature start-up failure rate ≤0%, a MOS transistor threshold voltage drift rate ≤1.02%, an interconnect layer breakage rate ≤0.0004%, an interlayer peeling rate ≤0.0004%, an MTBF ≥35479 hours, a leakage current change rate ≤1.2% after oil immersion, and an oil penetration depth ≤1.9 nm. This meets the stringent requirements of automotive engine compartments for low-temperature start-up reliability, temperature-induced vibration stability, and resistance to oil penetration in integrated circuits.

[0109] In Comparative Example 1, the absence of CeO2 prevents the formation of Ce-O-Al bridge bonds with LiAlO2, thus compromising the integrity of the three-dimensional bond network constructed by the nano-Ti powder. This structural defect reduces the stability of the carrier transport channels in the active region, hinders carrier migration at low temperatures, and weakens the stress buffering effect of the transition layer on the substrate and the active region, ultimately leading to performance degradation.

[0110] In Comparative Example 2, removing the Y2O3 nanoparticles resulted in the loss of Y2O3. 3+The barrier layer forms metallic bonds with rare earth Y atoms in the interconnect layer. The interfacial bonding between the barrier layer and the interconnect layer is significantly weakened. At the same time, due to the lack of buffering effect of Y2O3 on interfacial stress, micro-cracks are easily generated at the interface under temperature change and vibration conditions. This not only reduces the barrier ability against Cu ions, but also destroys the interlayer synergy, leading to the overall performance degradation.

[0111] In Comparative Example 3, without the addition of AlN@MgO core-shell particles, the synergistic effect of the thermal conductivity of the AlN core and the anti-permeability of the MgO shell was lost. The density and elastic modulus of the passivated inner layer decreased, and oil stains could easily penetrate through the interlayer pores. At the same time, thermal stress could not be effectively dispersed, which aggravated the risk of leakage and structural damage.

[0112] In Comparative Example 4, TiN acts as a dense ion barrier and interface bonding layer. Its absence leads to easy diffusion of phosphorus ions from the active region into the barrier layer, while the interfacial bonding force between the barrier layer and the active region is significantly reduced. Under high temperature and vibration environments, voids easily form at the interface, becoming weak links for oil penetration and carrier transport.

[0113] In Comparative Example 5, changing the three-stage synchronous annealing to three-stage layered annealing disrupts the continuity of the process and the thermal synergy effect. The low-temperature annealing after the deposition of the transition layer cannot fully eliminate the stress within the layer, and the high-temperature annealing after the deposition of the interconnect layer easily leads to thermal damage at the interface between the transition layer and the active region. Furthermore, the medium-temperature annealing before passivation will cause secondary stress accumulation between the interconnect layer and the barrier layer. The superposition of multiple stresses reduces the interlayer bonding performance.

[0114] In Comparative Example 6, the single SiO2 layer lacks the bonding reinforcement of doped components and cannot form a stable carrier transport environment; the thermal expansion coefficient of Al-1% Si alloy differs greatly from that of the surrounding layer, and it is prone to generating large thermal stress during temperature change. At the same time, its resistance to electrochemical corrosion is weaker than that of Cu-Mn-Fe alloy. These two defects lead to the deterioration of overall performance.

[0115] In Comparative Example 7, replacing the fluorocarbon resin-PI blend passivation outer layer with a conventional SiO2 layer resulted in the loss of the oleophobic properties of the blend system and the reinforcing effect of the nano-AlN particles. The conventional SiO2 layer has a relatively loose structure and lacks oleophobic groups, allowing machine oil to easily penetrate and react with the internal layers, damaging the insulation performance. Furthermore, its poor resistance to vibration and impact makes it prone to cracking under stress, further exacerbating performance failure.

[0116] In Comparative Example 8, the absence of LiAlO2 prevents CeO2 from forming stable Ce-O-Al bridge bonds. The three-dimensional bond network constructed by nano-Ti powder loses key connection nodes, becoming loose and fragmented. It cannot absorb the thermal stress generated by high and low temperature cycles through the elastic deformation of the bond network, nor can it stabilize the carrier transport environment in the active region. This leads to a sharp drift in the threshold voltage of the MOSFET at low temperatures, resulting in a significant increase in the startup failure rate. In addition, the incomplete three-dimensional bond network significantly weakens the stress buffering effect of the transition layer on the substrate and the active region. The local stress generated by temperature-induced vibration is directly transmitted to the interconnect layer and the barrier layer, causing an increase in the interconnect layer fracture rate and interlayer peeling rate. At the same time, the loose bond network of the transition layer reduces the structural density, making it easier for oil and dirt to penetrate from the pores of the transition layer, further aggravating the risk of circuit leakage.

Claims

1. A method for fabricating an integrated circuit, characterized in that, Includes the following steps: S1. Substrate pretreatment: Select an N-type single crystal silicon substrate and perform alkaline cleaning and oxygen-nitrogen mixed atmosphere plasma activation treatment on its functional surfaces in sequence; S2. Transition layer preparation: A 30-40 nm thick SiO2-Si3N4-SiO2 three-layer composite transition layer is deposited on the functional surface of the substrate; The middle Si3N4 layer is doped with CeO2, nano-Ti powder, and LiAlO2 nanoparticles; S3. Formation of active region: A source region is provided on the surface of the transition layer, and phosphorus ions are implanted sequentially using low energy of 30-40keV and high energy of 80-100keV; S4. Barrier layer preparation: A 4-6 nm thick TiN barrier layer is deposited only on the surface of the active region; S5. Barrier layer preparation: A 15-20 nm thick TiMoV barrier layer is deposited only on the surface of the TiN barrier layer, wherein nano-Cr powder and Y2O3 nanoparticles are incorporated into the TiMoV barrier layer; S6. Interconnect layer preparation: A 250-300 nm thick CuMnFe interconnect layer is deposited only on the surface of the TiMoV barrier layer using an electroplating process, with rare earth Y and ZnSO4 added to the electroplating solution; S7. Synchronous annealing: The structure prepared above is subjected to three-stage annealing, with the first stage temperature being 250-300℃, the second stage temperature being 820-850℃, and the third stage temperature being 400-450℃; The aforementioned TiN diffusion barrier layer, TiMoV barrier layer, and CuMnFe interconnect layer together form a step on the surface of the active region; S8. Passivation layer preparation: S81. A 10-15 nm thick Si3N4 passivation layer is deposited at the edge of the step sidewall; S82. A 100-120 nm thick AlN-Si3N4 composite passivation inner layer is deposited on the surface of the interconnect layer and the exposed transition layer; nano-SiO2 powder and AlN@MgO core-shell particles are added to the composite passivation inner layer; S83. Coat the surface of the composite passivation inner layer with an 80-100 nm thick fluorocarbon resin-PI blend passivation outer layer; incorporate AlN nanoparticles into the blend passivation outer layer; S84. Multiple heat dissipation through-holes are formed on the blended passivation outer layer; The integrated circuit is a dedicated integrated circuit for automotive engine compartments.

2. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S1, the oxygen-nitrogen mixed atmosphere has a volume ratio of 1:3 and the plasma activation radio frequency power is 80-100W.

3. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S2, the deposition process of the transition layer is LPCVD, the deposition temperature is 680-720℃, the silicon source is TEOS, the ammonia flow rate is 40-60 sccm, and the vacuum degree is 2-4 Torr.

4. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S2, the gaps between the two SiO2 layers and the Si3N4 layer are treated with oxygen atmosphere plasma interface.

5. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S3, the low-energy injected phosphorus ion concentration is 1×10⁻⁶. 19 ~2×10 19 cm -3 Dosage 4×10 14 ~6×10 14 cm -2 The high-energy injected phosphorus ion concentration was 4 × 10⁻⁶. 18 ~6×10 18 cm -3 Dosage 1×10 14 ~3×10 14 cm -2 The substrate temperature during implantation is 150-200℃.

6. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S5, the TiMoV barrier layer is deposited by magnetron sputtering at a sputtering temperature of 200-220℃ and a vacuum degree of ≤5×10⁻⁶. -5 Pa, sputtering power 180-220W.

7. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S7, the holding times for the three-stage annealing are: 5-8s for the first stage, 8-10s for the second stage, and 3-5s for the third stage.

8. The method for fabricating an integrated circuit according to claim 1, characterized in that, In step S82, the deposition process of the AlN-Si3N4 composite passivation inner layer is PECVD, the deposition temperature is 350-380℃, the aluminum source is TMA, and the ammonia flow rate is 50-70 sccm.

9. A method for fabricating an integrated circuit according to claim 8, characterized in that, In step S82, the thickness ratio of AlN to Si3N4 in the AlN-Si3N4 composite passivation inner layer is 3:

1.

10. A method for fabricating an integrated circuit according to claim 1, characterized in that, In step S8, the heat dissipation through holes are filled with silver-copper-epoxy composite slurry.

Images