Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes a complementary metal oxide semiconductor (CMOS) wafer having a display region having a plurality of cell regions and a boundary region; a light emitting element layer on the CMOS wafer and having a plurality of light emitting diodes and a planarization layer covering the plurality of light emitting diodes; an auxiliary electrode connected to the plurality of light emitting diodes; and a common electrode on the planarization layer and connected to the auxiliary electrode. The planarization layer includes a trench overlapping the boundary region, and a portion of the trench is recessed in a direction from an upper surface of the planarization layer toward the CMOS wafer, and the auxiliary electrode is provided in the trench and has an inverted trapezoidal shape in a cross section.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0106493, filed on August 9, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure herein relate to display devices and electronic devices, and for example, to display devices including complementary metal-oxide-semiconductor (CMOS) wafers and light-emitting diodes, and to electronic devices including display devices. Background Technology

[0004] Electronic devices that provide images to users (such as smartphones, laptops, car navigation systems, and smart TVs) include display devices that display images. Augmented reality devices, virtual reality devices, and video projection devices can include microdisplay devices. Microdisplay devices can include CMOS wafers and light-emitting diodes on the CMOS wafers to display images with high brightness while being driven at low power. Summary of the Invention

[0005] Embodiments of this disclosure provide a display device in which light loss and defects are reduced.

[0006] Embodiments of this disclosure provide a display device, comprising: a complementary metal-oxide-semiconductor (CMOS) wafer including a display area and a non-display area, the display area having a plurality of cell regions and having a grid shape and providing boundary regions between the plurality of cell regions, the non-display area being adjacent to the display area; a light-emitting element layer on the CMOS wafer, including a plurality of light-emitting diodes overlapping the plurality of cell regions and a planarization layer covering the plurality of light-emitting diodes; an auxiliary electrode connected to the plurality of light-emitting diodes; and a common electrode connected to the auxiliary electrode and on the planarization layer, wherein the planarization layer includes trenches overlapping the boundary regions, and portions of the trenches are recessed in a direction from the upper surface of the planarization layer toward the CMOS wafer, and the auxiliary electrode is provided in the trenches and has an inverted trapezoidal shape in cross-section.

[0007] In an embodiment, the auxiliary electrode may include an upper portion adjacent to the upper surface of the planarization layer, a lower portion opposite to the upper portion, and a side portion connecting the upper and lower portions, and the angle between the side portion and the virtual line extending from the lower portion may be approximately 60 degrees to approximately 89 degrees.

[0008] In an embodiment, the width of the upper portion may be from approximately 0.5 μm to approximately 1.0 μm, and the width of the lower portion may be from approximately 0.3 μm to approximately 0.7 μm.

[0009] In an embodiment, the thickness from top to bottom can be from about 0.5 μm to about 1.7 μm.

[0010] In this embodiment, the upper surface may be uneven.

[0011] In one embodiment, the upper part may have a concave shape in the direction from the upper part to the lower part.

[0012] In an embodiment, the display device may further include a barrier pattern provided in the trench and covering the lower and side portions, and the barrier pattern may be conductive (e.g., electrically conductive).

[0013] In an embodiment, each of the plurality of light-emitting diodes may include: a first electrode structure on a CMOS wafer and connected to a transistor included in the CMOS wafer; a light-emitting layer on the first electrode structure; and a second electrode structure on the light-emitting layer.

[0014] In an embodiment, at least one of the first electrode structure and the light-emitting layer may have a trapezoidal shape in cross-section, and the second electrode structure may cover at least a portion of the upper surface and / or side surface of the light-emitting layer.

[0015] In an embodiment, the first electrode structure may include: a metal layer; a reflective layer on the metal layer; a first barrier layer between the metal layer and the reflective layer; a first transparent conductive oxide layer on the reflective layer; and a second barrier layer between the reflective layer and the first transparent conductive oxide layer.

[0016] In the embodiments, the metal layer may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), and / or may include an alloy of two of the metals selected from gold, copper, silver, tin, titanium, zirconium, and tantalum.

[0017] In one embodiment, the auxiliary electrode may be located between adjacent first electrode structures in cross-section.

[0018] In an embodiment, the first barrier layer and the second barrier layer may each include a barrier metal nitride layer.

[0019] In an embodiment, the first electrode structure may further include a third barrier layer under the metal layer, and the third barrier layer may include titanium nitride and / or tantalum nitride.

[0020] In an embodiment, the second electrode structure may include a transparent conductive oxide layer.

[0021] In an embodiment, a CMOS wafer may include: a silicon substrate defining a source region or a drain region therein; a gate on the silicon substrate; a first insulating layer on the silicon substrate and covering the gate; a first contact electrode connected to the source region or drain region through a first contact hole defined in the first insulating layer; a second insulating layer on the first insulating layer and covering the first contact electrode; and a second contact electrode connected to the first electrode structure and connected to the first contact electrode through a second contact hole through the second insulating layer.

[0022] In an embodiment, the display device may further include a side insulating layer and a side reflective layer, wherein the side insulating layer covers a light-emitting diode, and the side reflective layer covers the side insulating layer that overlaps with the light-emitting diode and is spaced apart from each other on the side insulating layer.

[0023] In one embodiment, the common electrode can contact the light-emitting diode through a contact hole, which overlaps with the light-emitting diode and penetrates the planarization layer, the side reflective layer, and the side insulating layer.

[0024] In an embodiment, the display device may further include a passivation layer on a common electrode, and the passivation layer may include organic and / or inorganic materials.

[0025] In this embodiment, the planarization layer may include an inorganic material.

[0026] According to one or more embodiments, the electronic device may include a display device, wherein the electronic device may be selected from flat panel displays, curved displays, computer monitors, medical monitors, televisions, billboards, indoor lights, outdoor lights, signal lights, head-up displays, fully transparent displays, partially transparent displays, flexible displays (e.g., rollable displays, foldable displays, stretchable displays), laser printers, telephones (e.g., mobile phones, tablet phones), tablet computers, personal digital assistants (PDAs), wearable devices, laptop computers, digital cameras, portable video cameras, viewfinders, microdisplays, three-dimensional (3D) displays, virtual reality displays, augmented reality displays, vehicles, video walls comprising multiple displays spliced ​​together, theater screens, stadium screens, light therapy devices, and signs. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the subject matter of this disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings:

[0028] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure;

[0029] Figure 2 As an example illustration Figure 1 The figure shows a cross-sectional view of the display device.

[0030] Figure 3A A plan view of the common electrode provided in the display area and non-display area of ​​the display device according to an embodiment of the present disclosure;

[0031] Figure 3B This is a plan view illustrating the arrangement of the voltage transmission electrode, auxiliary electrode, and common electrode according to an embodiment of the present disclosure;

[0032] Figure 4A It is a diagram. Figure 3A A magnified plan view of a portion of the display area;

[0033] Figure 4B It is along Figure 4A A cross-sectional view taken from line I-I';

[0034] Figure 4C yes Figure 4B Enlarged cross-sectional view of the auxiliary electrode section;

[0035] Figure 5A and Figure 5B It is a diagram. Figure 4B Detailed cross-sectional view of the first electrode structure in the diagram;

[0036] Figure 6 It is a diagram. Figure 4B Detailed cross-sectional view of the light-emitting diode in the image;

[0037] Figure 7A It is a diagram. Figure 3A A magnified plan view of a portion of the non-display area in the image;

[0038] Figure 7B It is along Figure 7A A cross-sectional view taken from line II-II';

[0039] Figure 8A It is a diagram and Figure 4B A cross-sectional view of the region corresponding to the area in the diagram;

[0040] Figure 8B This is a cross-sectional view of a portion of the auxiliary electrode according to an embodiment of the present disclosure;

[0041] Figure 8C This is a cross-sectional view illustrating a portion of the auxiliary electrode according to an embodiment of the present disclosure; and

[0042] Figures 9A to 9E This is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. Detailed Implementation

[0043] In this specification, it will be understood that when an element (or region, layer, or portion, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element may be directly on / connected to / coupled to the other element, or an intermediary element may be between the element and the other element.

[0044] The same reference numerals or symbols always indicate the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of elements may be exaggerated for the effective description of the technical content. The term "and / or" includes all or one combination that can be defined by the relevant elements.

[0045] Although the terms first, and / or second, etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0046] In addition, terms such as "below," "on the lower side of," "above," or "on the upper side of" can be used to describe the relationships between the elements illustrated in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0047] It will be understood that, when used in this specification, the terms “comprising” or “including” specify the presence of the stated features, integers, steps, operations, elements, components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly stated herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense.

[0049] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0051] refer to Figure 1The display device DD according to embodiments of the present disclosure may have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, embodiments of the present disclosure are not limited thereto, and the display device DD may have various suitable shapes such as circles or other polygonal shapes. Hereinafter, the direction intersecting substantially perpendicularly to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. In this specification, the phrase "when viewed in a plane" is defined as being viewed in the third direction DR3.

[0052] The upper surface of the display device DD can be defined as a display surface DS, and can have a plane defined by a first direction DR1 and a second direction DR2. An image generated in the display device DD can be provided to the user through the display surface DS.

[0053] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA displays an image, and the non-display area NDA does not display an image. The non-display area NDA may surround the display area DA. However, embodiments of this disclosure are not limited thereto, and the non-display area NDA may not be provided on one side of the display area DA.

[0054] Multiple pixels (PXs) can be provided in the display area DA. Pixels (PXs) can be provided in a matrix. Each pixel (PX) can include pixel circuitry and a light-emitting diode (LED). All pixels (PXs) can generate light of the same color. In embodiments of this disclosure, pixels (PXs) can include multiple groups that generate light of different colors.

[0055] Figure 2 As an example illustration Figure 1 The figure shows a cross-sectional view of the display device.

[0056] refer to Figure 2 The display device DD may include a circuit element layer 10 and a light-emitting element layer 20. However, the embodiments of this disclosure are not limited thereto, and another functional layer, such as a lens layer, on the light-emitting element layer 20 may be added to the display device DD according to the embodiments of this disclosure.

[0057] Circuit element layer 10 may include pixel circuitry. Pixel circuitry can control the operation of light-emitting diodes in light-emitting element layer 20, which will be further described herein. Pixel circuitry may include at least one transistor. Circuit element layer 10 may include a CMOS wafer. The CMOS wafer may include complementary interconnected n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (NMOS) and p-channel MOSFETs (PMOS). Multiple pixel regions are regularly provided on the CMOS wafer, and pixel circuitry is provided in each pixel region.

[0058] The light-emitting element layer 20 may include light-emitting diodes electrically connected to the pixel circuitry. A type (or class of) compound semiconductor light-emitting diode is an electrically driven light-emitting diode containing gallium (Ga), phosphorus (P), and arsenic (As) as the main semiconductor materials. When a forward current is applied to the pn junction structure, electrons and holes can recombine at the junction surface to generate light of a set or specific wavelength corresponding to the band gap.

[0059] According to an embodiment, the lens layer may be on the light-emitting element layer 20 and may include a lens. The lens may be provided to correspond to the light-emitting diode. The lens focuses the light emitted from the light-emitting diode. The light focused by the lens may be transmitted through a light guide unit.

[0060] Figure 3A A plan view of a common electrode provided in the display area and non-display area of ​​a display device according to an embodiment of the present disclosure. Figure 3B This is a plan view illustrating the arrangement of the voltage transmission electrode, auxiliary electrode, and common electrode according to an embodiment of the present disclosure.

[0061] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may surround the display area DA. The display area DA and non-display area NDA of the display device DD can be similarly applied to a reference. Figure 2 The circuit element layer 10 described is, for example, a CMOS wafer. Hereinafter, circuit element layer 10 will be described as CMOS wafer 10 and referred to by the same reference numerals.

[0062] The majority of the common electrode CME can be provided in the display area DA, and the edge portion of the common electrode CME can be provided in the non-display area NDA. The common electrode CME can transmit the power supply voltage applied from the outside to the entire display area DA.

[0063] In this specification, the portion of the non-display area NDA that overlaps with the edge of the common electrode CME can be defined as the first non-display area NDA1, and the other portion of the non-display area NDA besides the first non-display area NDA1 can be defined as the second non-display area NDA2. Therefore, the second non-display area NDA2 can be a region where the common electrode CME is not provided.

[0064] A dummy LED, which will be further described herein, may be provided in the first non-display area NDA1. The dummy LED may have the same stacked structure as the LEDs in the display area DA, but because the dummy LED is not electrically connected to the common electrode CME, it may not be driven (or may not emit light). The structural features of the dummy LED will be further described herein.

[0065] When light-emitting diodes (LEDs) are formed in a defined or specific region using the same process, the outer region may have different process conditions than the inner region. For example, the thickness of the deposited metal layer may be smaller, and / or the etch rate of the deposited metal layer may be different. Therefore, defective LEDs may be formed in the outer region, and considering this, instead of using good LEDs, dummy LEDs are used for LEDs formed in the outer region. When the process conditions and process efficiency are consistent regardless of the region, the dummy LEDs can be omitted, and therefore the first non-display region NDA1 can be omitted in the embodiments of this disclosure.

[0066] It can be used on CMOS wafer 10 (see Figure 2 Multiple driving circuits are provided in the second non-display area NDA2. For example, a scan driver may be provided in the left and right regions of the second non-display area NDA2, respectively, and the display area DA is located between the left and right regions of the second non-display area NDA2. A data driver may be provided in a portion of the second non-display area NDA2 below the display area DA. In an embodiment, analog circuitry, such as power supply circuitry, may be provided in a portion of the second non-display area NDA2. The aforementioned scan driver, data driver, and analog circuitry may be embedded in a CMOS wafer. For example, the scan driver, data driver, and analog circuitry may include transistors formed using the same methods as pixel circuitry.

[0067] A pad area PDA with multiple pad electrodes PD can be provided on one side of the second non-display area NDA2. The pad area PDA may correspond to a portion of the second non-display area NDA2. A circuit board may be connected to the pad area PDA. Figure 3A Only four pad electrodes (PDs) are illustrated, receiving the power supply voltage applied to the common electrode (CME), but more pad electrodes (PDs) can be provided in the pad area PDA. The pad electrode PDs can receive data image signals and / or control signals from the outside and provide these signals to the data driver.

[0068] Voltage transfer electrodes (VTEs) can be provided in the second non-display area NDA2. The illustration shows four voltage transfer electrodes (VTEs) corresponding to the four pad electrodes (PDs). The voltage transfer electrodes (VTEs) can extend from the common electrode (CME) toward the pad area PDA. The voltage transfer electrodes (VTEs) and the common electrode (CME) can be formed using the same process and can have the same stacked structure and a monolithic shape. The voltage transfer electrodes (VTEs) and the common electrode (CME) can correspond to different portions of an electrode formed using the same process.

[0069] Figure 3BThis is a plan view illustrating the arrangement of the voltage transfer electrode VTE, auxiliary electrode SE, and common electrode CME according to an embodiment of the present disclosure.

[0070] The auxiliary electrode SE can overlap with each of the common electrode CME and the voltage transfer electrode VTE. The auxiliary electrode SE can be on the third-party DR3 below the common electrode CME and the voltage transfer electrode VTE.

[0071] The auxiliary electrode SE may include a plurality of first auxiliary electrodes SE1 extending in a first direction DR1 and a plurality of second auxiliary electrodes SE2 extending in a second direction DR2. The first auxiliary electrodes SE1 may be provided in the second direction DR2, and the second auxiliary electrodes SE2 may be provided in the first direction DR1.

[0072] The unit region UA ​​can overlap within the region defined by the two first auxiliary electrodes SE1 that are most adjacent to each other along the second direction DR2 in the first auxiliary electrode SE1 and the two second auxiliary electrodes SE2 that are most adjacent to each other along the first direction DR1 in the second auxiliary electrode SE1.

[0073] It is possible Figure 3A The display area DA provides the cell area UA. Figure 3B A representative illustration of a cell region UA ​​is shown. At least one light-emitting diode can be provided in the cell region UA, and this will be described in further detail herein.

[0074] A portion of the auxiliary electrode SE can overlap with the common electrode CME, and this overlapping portion can be fully connected to the common electrode CME, thereby reducing the voltage drop in the common electrode CME. Another portion of the auxiliary electrode SE can overlap with the voltage transfer electrode VTE, and this overlapping portion can be fully connected to the voltage transfer electrode VTE, thereby reducing the pad electrode PD (see [link to relevant documentation]). Figure 3A The resistance (e.g., resistance) of the voltage transfer path between the auxiliary electrode SE and the common electrode CME. The auxiliary electrode SE can be formed by the same process regardless of the region and can have an integral shape.

[0075] Figure 4A It is a diagram. Figure 3A A magnified plan view of a portion of the display area. Figure 4B It is along Figure 4A The cross-sectional view taken from line I-I'. Figure 4C yes Figure 4B Enlarged cross-sectional view of the auxiliary electrode section.

[0076] refer to Figure 4AThe auxiliary electrode SE may include a first auxiliary electrode SE1 and a second auxiliary electrode SE2 that intersect each other. The auxiliary electrode SE may be provided in a trench TR. The trench TR may include a first trench TC1 and a second trench TC2. A planarization layer 140 (see below), which will be further described herein, can be recessed in a direction from the upper surface toward the lower surface. Figure 4B The part is used to form the trench TR.

[0077] The first auxiliary electrode SE1 can be provided in the first trench TC1, and the second auxiliary electrode SE2 can be provided in the second trench TC2.

[0078] The display area DA may include multiple cell areas UA and a boundary area BA having a grid shape and located between the cell areas UA. Each of the multiple cell areas UA may be an internal region defined by two first trenches TC1 adjacent to each other along the second direction DR2 in the first trench TC1 and two second trenches TC2 adjacent to each other along the first direction DR1 in the second trench TC1. The boundary area BA may be the region in which the first trenches TC1 and the second trenches TC2 are provided. For example, the boundary area BA may correspond to the shape of the first auxiliary electrode SE1 and the second auxiliary electrode SE2.

[0079] In this embodiment, the boundary region BA is defined as the region in which the first trench TC1 and the second trench TC2 are provided, but embodiments of this disclosure are not limited thereto. The plurality of cell regions UA can be defined as... Figure 4A These cell regions are narrow. In an embodiment, the width of the boundary region BA can be further increased, and for example, the boundary region BA can be defined to have a width greater than that of the first auxiliary electrode SE1 and the second auxiliary electrode SE2.

[0080] Figure 4A The diagram shows a light-emitting diode (LED) and an opening CNT (also referred to as a contact hole CNT) in the cell area UA. Figure 4B The common electrode CME and Figure 4B The light-emitting diodes (LEDs) in the structure are connected via an opening (CNT).

[0081] refer to Figure 4B The display device DD may include a CMOS wafer 10 and a light-emitting element layer 20. According to an embodiment, the display device DD may include a lens layer on the light-emitting element layer 20 and include a lens overlapping a light-emitting diode (LED).

[0082] The CMOS wafer 10 includes a silicon substrate 101. A plurality of source or drain regions 111 are defined in the silicon substrate 101. Each source or drain region 111 may be a region doped with a dopant. Depending on the signal flow, the source or drain regions 111 may serve as the source or drain of a transistor. A pair of source or drain regions 111 may define a transistor together with a gate 121, which will be further described herein.

[0083] A shallow trench isolation (STI) region 115 can be further defined in the silicon substrate 101. The STI region 115 can prevent or reduce leakage current by isolating transistors. The STI region 115 can be provided differently depending on the pixel circuit design.

[0084] Gate 121 is on silicon substrate 101. Gate 121 may contain metal. Each gate 121 is provided corresponding to a pair of source regions or drain regions 111. First insulating layer 123 is on silicon substrate 101. First insulating layer 123 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or an aluminum oxide layer. The first insulating layer 123 is illustrated as a single layer, but the first insulating layer 123 is not limited to a single layer.

[0085] The CMOS wafer 10 may include a first contact electrode 125. The first contact electrode 125 may be connected to a source region or a drain region 111 via a first contact hole CH1 defined in a first insulating layer 123. The upper surface of the first contact electrode 125 and the upper surface of the first insulating layer 123 may define the same plane (or flat surface). The first contact electrode 125 may be formed by a damascene process. The first contact electrode 125 may contain a metal such as copper and / or tungsten.

[0086] The second insulating layer 130 may be on the first insulating layer 123. A second contact hole CH2 exposing the first contact electrode 125 may be defined within the second insulating layer 130. The second insulating layer 130 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or an aluminum oxide layer. The second insulating layer 130 is illustrated as a single layer, but it is not limited to a single layer.

[0087] A second contact electrode 135 may be provided within a second contact hole CH2. The upper surface of the second contact electrode 135 and the upper surface of the second insulating layer 130 may define the same plane (or flat surface). The second contact electrode 135 may include a metal structure 135-1 and a barrier layer 135-2, the metal structure 135-1 being provided inside the second contact hole CH2, and the barrier layer 135-2 being between the side surface of the metal structure 135-1 and the inner surface of the second contact hole CH2, and between the lower surface of the metal structure 135-1 and the upper surface of the first contact electrode 125 exposed through the second contact hole CH2.

[0088] The metal structure 135-1 may contain metals such as copper and / or tungsten. The barrier layer 135-2 is also conductive (e.g., electrically conductive). The barrier layer 135-2 may increase the adhesion between the second insulating layer 130 and the first contact electrode 125, and may prevent or reduce the diffusion of metal atoms from the metal structure 135-1 into the second insulating layer 130.

[0089] Barrier layer 135-2 may include a barrier metal layer and a barrier metal nitride layer. The barrier metal nitride layer may be provided in proportion to the barrier metal layer adjacent to the second insulating layer 130. The barrier metal layer increases adhesion, and the barrier metal nitride layer prevents or reduces the diffusion of atoms of the metal structure 135-1. The barrier metal may include titanium and / or tantalum. Barrier layer 135-2 may include a titanium nitride layer and a titanium layer, or it may include a tantalum nitride layer and a tantalum layer.

[0090] In embodiments of this disclosure, the second contact electrode 135 may include a tungsten structure, a titanium layer surrounding the side and bottom surfaces of the tungsten structure, and a titanium nitride layer surrounding the titanium layer. In embodiments of this disclosure, the second contact electrode 135 may include a copper structure, a tantalum layer surrounding the side and bottom surfaces of the copper structure, and a tantalum nitride layer surrounding the tantalum layer.

[0091] According to an embodiment, the upper surface of the second contact electrode 135 may be concave. The first electrode structure ES1, which will be further described herein, can contact the concave upper surface of the second contact electrode 135. The shape of the concave upper surface of the second contact electrode 135 can be formed by a damascene process. During the chemical mechanical polishing (CMP) of the damascene process, the second contact electrode 135 may be polished more than the second insulating layer 130, which may result in a recess in the second contact electrode 135.

[0092] The light-emitting diode (LED) can be located on the second insulating layer 130. According to the embodiments, the LEDs can generate light of the same color. However, the embodiments of this disclosure are not limited thereto, and one of the four LEDs can generate red light, another of the four LEDs can generate green light, and yet another of the four LEDs can generate blue light. The remaining one of the four LEDs can generate one of red, green, blue, and white light.

[0093] A light-emitting diode (LED) according to an embodiment may include a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode. In this embodiment, the first electrode is described as a first electrode structure ES1, and the second electrode is described as a second electrode structure ES2. In this embodiment, the light-emitting layer includes a semiconductor junction structure SJS.

[0094] According to this embodiment, a light-emitting diode (LED) may include a first electrode structure ES1, a semiconductor junction structure SJS on the first electrode structure ES1, and a second electrode structure ES2 on the semiconductor junction structure SJS.

[0095] The first electrode structure ES1 may contact the second contact electrode 135 and may have a larger diameter than the semiconductor junction structure SJS. The second electrode structure ES2 may cover at least a portion of the upper surface and / or side surface of the semiconductor junction structure SJS. However, embodiments of this disclosure are not limited thereto, and the second electrode structure ES2 may be on the upper surface of the semiconductor junction structure SJS, and in embodiments, the second electrode structure ES2 may have the same diameter as the semiconductor junction structure SJS. This disclosure is not limited to any one embodiment.

[0096] like Figure 4A As illustrated in the diagram, when the light-emitting diode (LED) has a circular shape, the first electrode structure ES1 can also have a circular shape. However, the shape of the first electrode structure ES1 is not limited to this. The first electrode structure ES1 can have an elliptical shape, or it can have a polygonal shape such as a square or an octagon.

[0097] In this embodiment, the first electrode structure ES1 is described as an anode (or anode structure), and the second electrode structure ES2 is described as a cathode (or cathode structure). However, the first electrode structure ES1 and the second electrode structure ES2 are not limited thereto. In embodiments of this disclosure, the first electrode structure ES1 may be a cathode, and the second electrode structure ES2 may be an anode. The stacking structure of the semiconductor junction structure SJS may be appropriately varied depending on whether the first electrode structure ES1 is an anode or a cathode.

[0098] The light-emitting element layer 20 may include a side insulating layer SI on the side surface of the first electrode structure ES1, the side surface of the second electrode structure ES2, and the upper surface of the second electrode structure ES2. The side insulating layer SI may expose a portion EU of the upper surface of the second electrode structure ES2 and may cover the remaining portion of the second electrode structure ES2 and the side surface of the first electrode structure ES1.

[0099] The side insulating layer SI prevents or reduces contact between the light-emitting diode (LED) and the side reflective layer SRL, which will be further described herein. The side insulating layer SI may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, and / or a titanium oxide layer. According to embodiments, the side insulating layer SI may be provided as a single layer. However, embodiments of this disclosure are not limited thereto, and the side insulating layer SI may have a single-layer structure of the aforementioned layers or a multilayer structure of any layer selected from the aforementioned layers.

[0100] The side reflective layer SRL can be on the side insulating layer SI. Multiple side reflective layers SRL can be provided, and each of the multiple side reflective layers SRL can cover the portion of the side insulating layer SI that overlaps with the light-emitting diode (LED). The side reflective layers SRL can be spaced apart from each other on the side insulating layer SI. The side reflective layers SRL can be separated from each other and spaced apart in the boundary region BA. However, embodiments of this disclosure are not limited thereto, and the side reflective layers SRL can have a monolithic shape. For example, the side reflective layers SRL can be... Figure 4A The display area DA has a unified shape.

[0101] Side reflective layers (SRLs) can increase luminous efficiency by reflecting light generated by light-emitting diodes (LEDs), thereby enabling the emission of light generated by LEDs. SRLs can include gold (Au), copper (Cu), silver (Ag), titanium (Ti), and / or aluminum (Al).

[0102] According to this embodiment, the first contact hole CNT-1 of the portion EU exposing the upper surface of the second electrode structure ES2 can be defined in the side insulating layer SI and the side reflective layer SRL.

[0103] The planarization layer 140 is located on the second insulating layer 130. The planarization layer 140 may overlap with multiple cell regions UA and boundary regions BA, and may cover light-emitting diodes (LEDs). The planarization layer 140 may include inorganic materials.

[0104] A second contact hole CNT-2, overlapping with the first contact hole CNT-1, may be defined in the planarization layer 140. The planarization layer 140 may not be on the second electrode structure ES2 within the display area DA. The first contact hole CNT-1 and the second contact hole CNT-2 may overlap each other to define a contact hole CNT, and the contact hole CNT may expose a portion EU of the upper surface of the second electrode structure ES2.

[0105] According to this disclosure, the planarization layer 140 can fill areas where no light-emitting diode (LED) is provided. For example, in the portion overlapping with the boundary region BA, the planarization layer 140 can contact the side insulating layer SI exposed between the side reflective layers SRL.

[0106] As described above, since at least one of the first electrode structure ES1 and the semiconductor junction structure SJS has a trapezoidal shape in cross-section, the area between adjacent light-emitting diodes (LEDs) can be formed in a shape similar to an inverted trapezoid.

[0107] Therefore, in the planarization layer 140 covering the light-emitting diodes (LEDs), the upper surface of the planarization layer 140, which fills the area between adjacent LEDs, can be recessed to form a second trench TC2 with an inverted trapezoidal shape. The above description can also be generally applied to [other applications] included in the reference [reference]. Figure 4A The first trench TC1 in the described trench TR.

[0108] According to this disclosure, the cross-sectional shape of the auxiliary electrode SE provided in the trench TR can be generated by the shape of the trench TR in the region between adjacent light-emitting diodes (LEDs) formed in the planarization layer 140.

[0109] The common electrode CME is located on the planarization layer 140. The common electrode CME may overlap with the cell region UA ​​and the boundary region BA. The common electrode CME may include a transparent conductive material to emit light generated from the light-emitting diode (LED). The common electrode CME may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and / or indium gallium zinc oxide (IGZO).

[0110] The common electrode CME is connected to the second electrode structure ES2 of the light-emitting diode (LED) through the contact hole CNT. The power supply voltage applied through the common electrode CME can be transmitted to the LED. Figure 4B The illustration shows the common electrode CME connected to two light-emitting diodes (LEDs). One of the two LEDs can be defined as a first LED, and the other of the two LEDs can be defined as a second LED.

[0111] The common electrode CME contacts a portion EU of the upper surface of the second auxiliary electrode SE2, which is exposed by the contact hole CNT. For example... Figure 4A As shown in the figure, the upper surface of the second auxiliary electrode SE2 can contact the common electrode CME along the length direction of the second trench TC2, and thus the common electrode CME and the second auxiliary electrode SE2 can ensure a suitable or sufficient contact area between the common electrode CME and the second auxiliary electrode SE2.

[0112] Passivation layer 150 is on the common electrode CME. Passivation layer 150 protects the common electrode CME. Passivation layer 150 can be combined with... Figure 3A and Figure 3B The display area DA and the non-display area NDA overlap, and can be protected. Figure 3A and Figure 3B The voltage transfer electrode VTE is located in the middle. The passivation layer 150 may include organic and / or inorganic materials.

[0113] According to an embodiment, the lens may be on the passivation layer 150. The lens focuses light emitted from the light-emitting diode (LED). The lens may include an organic material and may have a hemispherical shape. The diameter of the lens may be approximately 1 micrometer or less.

[0114] Figure 4C The figure shows an enlarged cross-sectional view of the second auxiliary electrode SE2 in the second trench TC2. A similar description of the second auxiliary electrode SE2 can be applied to the reference. Figure 4A The first auxiliary electrode SE1 is described.

[0115] refer to Figure 4C According to an embodiment, the second auxiliary electrode SE2 may include an upper portion SU, a lower portion SB opposite to the upper portion SU, and a side portion SS connecting the upper portion SU and the lower portion SB in cross-section. The upper portion SU may be adjacent to the upper surface 140-U of the planarization layer 140. According to this embodiment, the upper surface 140-U of the planarization layer 140 and the upper surface of the upper portion SU may define the same plane.

[0116] According to this embodiment, the second auxiliary electrode SE2 can have an inverted trapezoidal shape in cross-section. The shape of the internal space of the second trench TC2 can correspond in cross-section to the shape of the second auxiliary electrode SE2.

[0117] The thickness TH from the upper SU to the lower SB of the second auxiliary electrode SE2 (e.g., the thickness of the second auxiliary electrode SE2 on the third-direction DR3) can be from about 0.5 μm to about 1.7 μm.

[0118] The first width WD1 of the lower SB in the first direction DR1 can be approximately 0.3 μm to approximately 0.7 μm.

[0119] The second width WD2 of the upper SU in the first direction DR1 can be approximately 0.5 μm to approximately 1.0 μm.

[0120] According to an embodiment, the angle θ between the side SS and the virtual line extending from the lower SB can be approximately 60 degrees to approximately 89 degrees.

[0121] According to this disclosure, the first auxiliary electrode SE1 and the second auxiliary electrode SE2 included in the auxiliary electrode SE can overlap with the common electrode CME, and the first auxiliary electrode SE1 and the second auxiliary electrode SE2 overlapping with the common electrode CME can fully contact the common electrode CME, thereby reducing the voltage drop that occurs in the common electrode CME. Therefore, a display device DD with improved quality can be provided.

[0122] In an embodiment, another portion of the auxiliary electrode SE may be connected to the voltage transfer electrode VTE (see...). Figure 3A) overlaps with and is associated with the voltage transfer electrode VTE (see Figure 3A The overlapping portion can be fully connected to the voltage transfer electrode VTE (see...). Figure 3A This reduces the pad electrode PD (see...). Figure 3A The resistance (e.g., resistance) of the voltage transfer path between the common electrode CME and the common electrode CME.

[0123] Figure 5A and Figure 5B It is a diagram. Figure 4B A detailed cross-sectional view of the first electrode structure. Figure 6 It is a diagram. Figure 4B Detailed cross-sectional view of the light-emitting diode in the image.

[0124] refer to Figure 5A The first electrode structure ES1 may include at least a metal layer ML, a reflective layer RL on the metal layer ML, and a transparent conductive oxide layer (hereinafter referred to as the first transparent conductive oxide layer TCO) on the reflective layer RL. The metal layer ML, the reflective layer RL, and the first transparent conductive oxide layer TCO may be stacked continuously, or additional functional layers may be further disposed between the metal layer ML, the reflective layer RL, and the first transparent conductive oxide layer TCO.

[0125] The metal layer ML corresponds to the adhesive layer used to bond the CMOS wafer and the semiconductor substrate during the manufacturing of the display device. For example, the metal layer ML may be a layer formed by bonding the metal layer of the CMOS wafer and the metal layer of the semiconductor substrate.

[0126] The metal layer ML may include at least one metal layer. The at least one metal layer may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), and / or may include an alloy of two of these metals.

[0127] In this embodiment, as an example, a metal layer ML is illustrated to have a three-layer structure including a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3. The second metal layer ML2 may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), but may include metals different from the first metal layer ML1 and the third metal layer ML3. The first metal layer ML1 and the third metal layer ML3 may each include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta). In embodiments of this disclosure, the metal layer ML may include two consecutive metal layers from the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3.

[0128] The reflective layer RL can reflect light generated from the semiconductor junction structure SJS towards the semiconductor junction structure SJS. The reflective layer RL may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), and / or aluminum (Al).

[0129] The first transparent conductive oxide layer (TCO) injects holes into the semiconductor junction structure SJS. Due to its high work function, the first transparent conductive oxide layer (TCO) may be advantageous or beneficial for hole injection and can transmit light reflected from the reflective layer RL. The first transparent conductive oxide layer (TCO) includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO).

[0130] In this embodiment, the first electrode structure ES1 is described as an anode and has the aforementioned structure. However, when the first electrode structure ES1 is a cathode, the structure of the first electrode structure ES1 can be changed. The electron injection functional layer and the reflective layer can be integrated into a single metal layer. For example, the metal layer serves as both the electron injection layer and the reflective layer. Therefore, the cathode structure can include two metal layers that are distinct from each other.

[0131] The first electrode structure ES1 can have a thickness of approximately 500 nm or less. As the thickness of the first electrode structure ES1 increases, process errors occur due to the thickness. For example, the etching rate can be appropriately varied according to the thickness. When the first electrode structure ES1 is thicker, it is formed with a more inclined side surface. The first electrode structure ES1 can have a thickness of, for example, approximately 500 nm or less, such that it is formed with a vertical side surface.

[0132] refer to Figure 5A The first electrode structure ES1 may include a first barrier layer BRL1 between the metal layer ML and the reflective layer RL, a second barrier layer BRL2 between the reflective layer RL and the first transparent conductive oxide layer TCO, and a third barrier layer BRL3 under the metal layer ML. Each of the first barrier layer BRL1 to the third barrier layer BRL3 may include a barrier metal layer and a barrier metal nitride layer. The barrier metal layer improves the adhesion between adjacent layers, and the barrier metal nitride layer prevents or reduces atomic diffusion into adjacent layers.

[0133] In this embodiment, the first barrier layer BRL1 may include a barrier metal nitride layer BMLN containing titanium nitride, and titanium-containing barrier metal layers BML on and below the barrier metal nitride layer BMLN, respectively. For example, the titanium nitride-containing layer can block or reduce the migration of metal atoms from the metal layer ML to the reflective layer RL, and can prevent or reduce the occurrence of electromigration in the reflective layer RL.

[0134] In this embodiment, the second barrier layer BRL2 may include a barrier metal nitride layer BMLN containing titanium nitride. For example, the titanium nitride-containing layer can block or reduce atomic migration between the first transparent conductive oxide layer TCO and the reflective layer RL, and can prevent or reduce the formation of voids in the first transparent conductive oxide layer TCO and / or prevent or reduce the oxidation of the reflective layer RL.

[0135] In this embodiment, the third barrier layer BRL3 may include a barrier metal nitride layer BMLN containing titanium nitride, and titanium-containing barrier metal layers BML respectively on and below the barrier metal nitride layer BMLN. The titanium nitride-containing layer can prevent or reduce the interaction between the metal layer ML and the barrier metal layer BMLN. Figure 4B Electromigration occurs between the second contact electrodes 135.

[0136] Figure 5B As an example illustration, the stacking structure ratio Figure 5A The first electrode structure ES1 has a simpler stacked structure. The metal layer ML may include a single metal layer. The first barrier layer BRL10 may include a barrier metal nitride layer BMLN and a barrier metal layer BML on top of the barrier metal nitride layer BMLN. The third barrier layer BRL30 may include a barrier metal nitride layer BMLN and a barrier metal layer BML below the barrier metal nitride layer BMLN. The barrier metal nitride layer BMLN of the first barrier layer BRL10 may be in contact with the upper surface of the metal layer ML, and the barrier metal nitride layer BMLN of the third barrier layer BRL30 may be in contact with the lower surface of the metal layer ML.

[0137] Figure 5B The stacking structure in the middle can be made by making Figure 5A In a stacked structure, layers or certain layers are formed using the same material. For example, when... Figure 5A When the metal layer ML in the first barrier layer BRL1 and the barrier metal layer BML of the third barrier layer BRL3 include titanium (Ti), the metal layer ML and the barrier metal layer BML of the first barrier layer BRL1 and the third barrier layer BRL3 adjacent to the metal layer ML can constitute a single metal layer.

[0138] refer to Figure 6 The light-emitting diode (LED) is described in more detail. Figure 6 In the diagram, the first electrode structure ES1 is schematically illustrated as a single layer, and the semiconductor junction structure SJS is illustrated in more detail. As an example, the first electrode structure ES1 is illustrated to have a disk shape, but the shape of the first electrode structure ES1 is not limited to this. In this embodiment, the light-emitting diode (LED) can have a cylindrical shape, but is not limited to this.

[0139] The semiconductor junction structure SJS may include an active layer ACT, a p-type semiconductor layer SP on one side of the active layer ACT, and an n-type semiconductor layer SN on the other side of the active layer ACT. In this embodiment, since the first electrode structure ES1, which serves as the anode, is under the active layer ACT, the p-type semiconductor layer SP is also under the active layer ACT.

[0140] The active layer ACT can be formed as a single quantum well structure or a multi-quantum well structure. In response to an electrical signal applied through the p-type semiconductor layer SP and the n-type semiconductor layer SN, light can be emitted through the recombination of electron-hole pairs. The active layer ACT can emit light with wavelengths from approximately 400 nm to approximately 900 nm and can be used in a dual heterostructure configuration.

[0141] In embodiments of this disclosure, the active layer ACT may have a structure in which semiconductor materials with high energy band gaps and semiconductor materials with low energy band gaps are alternately stacked, or may include group III to group V semiconductor materials selected according to the wavelength range of the emitted light.

[0142] The p-type semiconductor layer SP can comprise at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and can be doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), and / or barium (Ba). For example, the p-type semiconductor layer SP can be p-GaN doped with magnesium (Mg). However, the materials constituting the p-type semiconductor layer SP are not limited to these, and various suitable materials can also be used to constitute the p-type semiconductor layer SP.

[0143] The n-type semiconductor layer SN may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a second conductivity type dopant such as silicon (Si), germanium (Ge), and / or tin (SN). However, the materials constituting the n-type semiconductor layer SN are not limited to these, and various suitable materials may be used to constitute the n-type semiconductor layer SN.

[0144] In embodiments, the light-emitting diode (LED) may further include a cladding layer. The cladding layer may be on the upper and / or lower side of the active layer ACT. The cladding layer may include an AlGaN layer and / or an InAlGaN layer. The LED may also include a tensile strain barrier reducing (TSBR) layer on the upper and / or lower side of the active layer ACT. The TSBR layer may be a strain-relieving layer that acts as a buffer between semiconductor layers with different lattice structures to reduce differences in lattice constants. The TSBR layer may consist of a p-type semiconductor layer such as p-GaInP, p-AlInP, and / or p-AlGaInP, but embodiments of this disclosure are not limited thereto.

[0145] In this embodiment, the second electrode structure ES2 may include a transparent conductive oxide layer (hereinafter referred to as the second transparent conductive oxide layer). The second transparent conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and / or indium gallium zinc oxide (IGZO). The second transparent conductive oxide layer may correspond to a protective layer during the manufacturing process of a light-emitting diode (LED) and may inject electrons into the semiconductor junction structure SJS. A detailed description of the second transparent conductive oxide layer used as a protective layer will be provided herein with reference to the manufacturing method.

[0146] The second electrode structure ES2 may further include an electrode metal layer between the second transparent conductive oxide layer and the semiconductor junction structure SJS. The electrode metal layer may include a metal with a work function lower than that of the second transparent conductive oxide layer. The electrode metal layer can improve the electron injection performance of the second electrode structure ES2. The electrode metal layer may include aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), nickel (Ni), copper (Cu), their oxides, and / or alloys thereof.

[0147] Figure 7A It is a diagram. Figure 3A A magnified plan view of a portion of the non-display area in the image. Figure 7B It is along Figure 7A The cross-sectional view taken from line II-II'.

[0148] refer to Figure 7A Within the first non-display area NDA1, a first auxiliary electrode SE1 is provided in the first trench TC1, and a second auxiliary electrode SE2 is provided in the second trench TC2. The first auxiliary electrode SE1... Figure 4A The first auxiliary electrode SE1 extends from the middle, and the second auxiliary electrode SE2 extends from the middle. Figure 4A The second auxiliary electrode SE2 extends in the middle.

[0149] The first non-display area NDA1 may include a cell area UA and a boundary area BA between the cell areas UA. A dummy light-emitting diode DED can be provided in the cell area UA of the first non-display area NDA1.

[0150] Figure 7B The dummy LED (DED) shown in the diagram can have the same characteristics as... Figure 4B The LEDs shown in the diagram have essentially the same stacked structure. This is because the dummy LED (DED) and LED are formed using the same process. The second electrode structure ES2 of the dummy LED (DED) is not exposed to the outside and is not connected to the common electrode CME. This is because the contact hole CNT (see...) Figure 4B The dummy light-emitting diode (DED) is not formed in the side insulating layer SI, the side reflective layer SRL, and the planarization layer 140. Therefore, the dummy light-emitting diode (DED) cannot be driven or emit light.

[0151] Figure 8A It is a diagram and Figure 4B A cross-sectional view of the region corresponding to the area in the diagram. Figure 8B This is a cross-sectional view of a portion of the auxiliary electrode according to an embodiment of the present disclosure. Figure 8C This is a cross-sectional view illustrating a portion of the auxiliary electrode according to an embodiment of the present disclosure. (See reference...) Figures 1 to 4C Components that are identical or similar to those described will be referred to by the same or similar reference numerals or symbols, and will not be described again here.

[0152] refer to Figure 8A The display device DD-A according to an embodiment may include a circuit element layer 10 and a light-emitting element layer 20. The light-emitting element layer 20 may include light-emitting diodes (LEDs) and a planarization layer 140 on the circuit element layer 10.

[0153] refer to Figure 4A The trench TR described can be confined within the planarization layer 140. Figure 8A The second trench TC2 is illustrated as an example. The display device DD-A may include an auxiliary electrode SE-A ​​provided inside the second trench TC2.

[0154] According to this embodiment, a barrier pattern SB may also be provided inside the second trench TC2. The barrier pattern SB may be provided in the second trench TC2 and may cover the lower and side portions of the auxiliary electrode SE-A.

[0155] Like the auxiliary electrode SE-A, the barrier pattern SB is conductive (e.g., electrically conductive). The barrier pattern SB can increase the adhesion of the auxiliary electrode SE-A ​​to the planarization layer 140 and can prevent or reduce the diffusion of metal atoms of the auxiliary electrode SE-A ​​into the planarization layer 140.

[0156] The barrier pattern SB may include a barrier metal layer and a barrier metal nitride layer. The barrier metal nitride layer may be provided in proportion to the barrier metal layer close to the planarization layer 140. The barrier metal layer may include titanium and / or tantalum. The barrier metal nitride layer may include a titanium nitride layer and / or a tantalum nitride layer.

[0157] The common electrode CME can be on the planarization layer 140, and the passivation layer 150 can be on the common electrode CME.

[0158] Figure 8B and Figure 8C Illustration Figure 8A An enlarged view of a portion of the area providing the auxiliary electrode. (Compared to reference...) Figure 8A Components that are identical or similar to those described will be referred to by the same or similar reference numerals or symbols, and will not be described again here.

[0159] refer to Figure 8B The auxiliary electrode SE-B included in the display device DD-B can be provided in a second trench TC2 defined in the planarization layer 140. The auxiliary electrode SE-B may include an upper portion SU adjacent to the upper surface of the planarization layer 140, a lower portion SB opposite to the upper portion SU, and a side portion SS connecting the upper portion SU and the lower portion SB.

[0160] According to this embodiment, the upper SU can have an uneven surface. Because the auxiliary electrode SE-B is formed by chemical mechanical polishing (CMP) using an inlay process, the surface of the upper SU can be formed to be uneven during the polishing process of the auxiliary electrode SE-B.

[0161] The common electrode CME can be located on the auxiliary electrode SE-B. The common electrode CME can contact the uneven upper SU. According to this embodiment, because the surface of the upper SU has an uneven shape, the contact area between the common electrode CME and the auxiliary electrode SE-B can be increased.

[0162] refer to Figure 8C The auxiliary electrode SE-C included in the display device DD-C can be provided in a second trench TC2 defined in the planarization layer 140. The auxiliary electrode SE-C may include an upper portion SU adjacent to the upper surface of the planarization layer 140, a lower portion SB opposite to the upper portion SU, and a side portion SS connecting the upper portion SU and the lower portion SB.

[0163] According to this embodiment, the upper SU can have a concave shape in the direction from the upper SU toward the lower SB. Because the auxiliary electrode SE-C is formed by chemical mechanical polishing (CMP) of the inlay process, the surface of the upper SU can be formed to be concave in the direction from the upper SU toward the lower SB during the polishing process of the auxiliary electrode SE-C.

[0164] The common electrode CME can be on the auxiliary electrode SE-C. The common electrode CME can contact the concave upper part SU. According to this embodiment, because the upper part SU has a concave shape, the contact area between the common electrode CME and the auxiliary electrode SE-C can be increased.

[0165] Figures 9A to 9E This is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. (See reference...) Figures 1 to 7B Components that are identical or similar to those described will be referred to by the same or similar reference numerals or symbols, and will not be described again here.

[0166] refer to Figure 9A The method of manufacturing a display device according to this embodiment may include providing a CMOS wafer. The CMOS wafer can be provided by forming a silicon substrate 101, a first insulating layer 123, and a second insulating layer 130.

[0167] A source or drain region 111 and a shallow trench isolation (STI) region 115 may be formed in a silicon substrate 101. A gate 121 may be formed on the silicon substrate 101. A first contact hole CH1 may be formed in a first insulating layer 123, and a first contact electrode 125 may be formed inside the first contact hole CH1 and connected to the source or drain region 111 through the first contact hole CH1.

[0168] A second contact hole CH2 may be formed in the second insulating layer 130. The second contact hole CH2 may expose the first contact electrode 125. A second contact electrode 135 may be formed in the second contact hole CH2. The second contact electrode 135 may include a metal structure 135-1 and a barrier layer 135-2, the metal structure 135-1 being provided inside the second contact hole CH2, and the barrier layer 135-2 being between the side surface of the metal structure 135-1 and the inner surface of the second contact hole CH2, and between the lower surface of the metal structure 135-1 and the upper surface of the first contact electrode 125 exposed through the second contact hole CH2.

[0169] The method may then include the step of forming a light-emitting diode (LED) by forming a conductive layer (e.g., an electrical conductive layer) on the second insulating layer 130 and patterning the conductive layer.

[0170] Each light-emitting diode (LED) may include a first electrode structure ES1 connected to a second contact electrode 135, a semiconductor junction structure SJS formed on the first electrode structure ES1, and a second electrode structure ES2 formed on the semiconductor junction structure SJS.

[0171] Subsequently, a side insulating layer SI can be formed to cover the light-emitting diode (LED). The side insulating layer SI may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, and / or a titanium oxide layer.

[0172] Next, side reflective layers SRL can be formed on the side insulating layers SI, spaced apart from each other and overlapping with the corresponding light-emitting diodes (LEDs). Each side reflective layer SRL can cover the portion of the side insulating layer SI that overlaps with the LED. The side reflective layers SRL can include gold (Au), copper (Cu), silver (Ag), titanium (Ti), and / or aluminum (Al).

[0173] Subsequently, a first contact hole CNT-1 can be formed through the side insulating layer SI and the side reflective layer SRL. The first contact hole CNT-1 can expose the upper surface of the second electrode structure ES2 of the light-emitting diode (LED) formed in the display area DA.

[0174] Then, refer to Figure 9B A method for manufacturing a display device according to an embodiment may include forming a planarization layer 140. The planarization layer 140 may be formed in the display area DA and the non-display area NDA to cover the light-emitting diode (LED).

[0175] According to this disclosure, at least either the first electrode structure ES1 or the semiconductor junction structure SJS included in each of the light-emitting diodes (LEDs) may have a trapezoidal shape in cross-section. Therefore, the upper surface of the planarization layer 140, which fills the space between adjacent LEDs along the first direction DR1, may be recessed to have an inverted trapezoidal shape. The recessed portion of the upper surface of the planarization layer 140 may be defined as a trench TR. The trench TR may be formed in the region between adjacent LEDs.

[0176] Subsequently, refer to Figure 9C The method of manufacturing a display device according to an embodiment may include forming an auxiliary electrode SE. First, the auxiliary electrode SE may be formed in the display area DA and the non-display area NDA.

[0177] Subsequently, the method may include polishing the auxiliary electrode SE using a mosaic process. Polishing of the auxiliary electrode SE can be performed using chemical mechanical polishing (CMP) of a mosaic process. CMP can polish the auxiliary electrode SE by applying pressure to a rotary polisher RH. In embodiments, a slurry SL (a polishing slurry, or class of polishing slurries) may be applied to prevent or reduce damage to the auxiliary electrode SE.

[0178] Afterwards, refer to Figure 9D When the auxiliary electrode SE is polished by chemical mechanical polishing (CMP), the upper surface 140-U of the planarization layer 140 and a surface of the upper portion SU of the auxiliary electrode SE can define the same plane. In fact, the surface of the upper portion SU of the auxiliary electrode SE can be uneven due to chemical mechanical polishing (CMP), or the upper portion SU can have a concave shape in the thickness direction.

[0179] The method may then include forming a second contact hole CNT-2 in the planarization layer 140. The second contact hole CNT-2 may overlap with the first contact hole CNT-1 and expose a portion of the upper surface of the second electrode structure ES2.

[0180] The method may then include forming a common electrode CME on the planarization layer 140. The common electrode CME may make contact with a portion of the upper surface of the second electrode structure ES2 through a contact hole CNT defined in the display area DA.

[0181] According to embodiments of this disclosure, the light-emitting diode (LED) formed in the non-display area (NDA) can be defined as a dummy LED (DED). The second electrode structure ES2 included in the dummy LED (DED) may not be connected to the common electrode CME, and therefore the dummy LED cannot be driven or emit light.

[0182] refer to Figure 9E A method for manufacturing a display device according to an embodiment may include forming a passivation layer 150 on a common electrode CME. The passivation layer 150 may include organic and / or inorganic materials.

[0183] According to one or more embodiments, the electronic device may include a display device, wherein the electronic device may be selected from flat panel displays, curved displays, computer monitors, medical monitors, televisions, billboards, indoor lights, outdoor lights, signal lights, head-up displays, fully transparent displays, partially transparent displays, flexible displays (e.g., rollable displays, foldable displays, stretchable displays), laser printers, telephones (e.g., mobile phones, tablet phones), tablet computers, personal digital assistants (PDAs), wearable devices, laptop computers, digital cameras, portable video cameras, viewfinders, microdisplays, 3D displays, virtual reality displays, augmented reality displays, vehicles, video walls comprising multiple displays spliced ​​together, theater screens, stadium screens, light therapy devices, and signs.

[0184] The display device according to embodiments of the present disclosure may include an auxiliary electrode connected to a common electrode, thereby reducing the voltage drop that occurs in the common electrode.

[0185] The embodiments have been described above with reference to them, but those skilled in the art or those of ordinary skill in the art will understand that various suitable modifications and changes can be made to the subject matter of this disclosure without departing from the spirit and scope of the disclosure as described in the appended claims and their equivalents.

[0186] Therefore, the technical scope of this disclosure is not limited to the specific description in the specification, but should be determined by the appended claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: A complementary metal-oxide-semiconductor wafer includes a display area and a non-display area, the display area having a plurality of cell regions and a grid shape and providing boundary regions between the plurality of cell regions, the non-display area being adjacent to the display area; A light-emitting element layer is provided on the complementary metal-oxide-semiconductor wafer, and the light-emitting element layer includes a plurality of light-emitting diodes overlapping the plurality of unit regions and a planarization layer covering the plurality of light-emitting diodes; Auxiliary electrodes are connected to the plurality of light-emitting diodes; and A common electrode, connected to the auxiliary electrode and located on the planarization layer, The planarization layer includes trenches overlapping the boundary region, and portions of the trenches are recessed in a direction from the upper surface of the planarization layer toward the complementary metal-oxide-semiconductor wafer. The auxiliary electrode is provided in the trench and has an inverted trapezoidal shape in cross-section.

2. The display device according to claim 1, wherein, The auxiliary electrode includes an upper portion adjacent to the upper surface of the planarization layer, a lower portion opposite to the upper portion, and a side portion connecting the upper portion and the lower portion. The angle between the side portion and the virtual line extending from the bottom portion is 60 to 89 degrees.

3. The display device according to claim 2, wherein, The width of the upper part is 0.5 μm to 1.0 μm, and The width of the lower part is 0.3 μm to 0.7 μm.

4. The display device according to claim 2, wherein, The thickness from the upper part to the lower part is 0.5 μm to 1.7 μm.

5. The display device according to claim 2, wherein, The upper surface is not flat.

6. The display device according to claim 2, wherein, The upper part has a concave shape in the direction from the upper part toward the lower part.

7. The display device according to claim 2, wherein, The display device also includes a barrier pattern provided in the groove and covering the lower portion and the sides. The barrier pattern is conductive.

8. The display device according to claim 1, wherein, Each of the plurality of light-emitting diodes includes: A first electrode structure is located on the complementary metal-oxide-semiconductor wafer and connected to a transistor included in the complementary metal-oxide-semiconductor wafer; A light-emitting layer is formed on the first electrode structure; and The second electrode structure is located on the light-emitting layer.

9. The display device according to claim 8, wherein, At least one of the first electrode structure and the light-emitting layer has a trapezoidal shape in cross-section, and the second electrode structure covers at least a portion of the upper surface and / or side surface of the light-emitting layer.

10. The display device according to claim 8, wherein, The first electrode structure includes: Metal layer; A reflective layer is placed on the metal layer. A first barrier layer is located between the metal layer and the reflective layer; A first transparent conductive oxide layer is placed on the reflective layer; and A second barrier layer is located between the reflective layer and the first transparent conductive oxide layer.

11. The display device according to claim 10, wherein, The metal layer includes any one of gold, copper, silver, tin, titanium, zirconium, and tantalum, and / or an alloy of two of the metals selected from gold, copper, silver, tin, titanium, zirconium, and tantalum.

12. The display device according to claim 10, wherein, In cross-section, the auxiliary electrode is located between adjacent first electrode structures.

13. The display device according to claim 10, wherein, The first barrier layer and the second barrier layer each include a barrier metal nitride layer.

14. The display device according to claim 10, wherein, The first electrode structure further includes a third barrier layer beneath the metal layer, and The third barrier layer comprises titanium nitride and / or tantalum nitride.

15. The display device according to claim 8, wherein, The second electrode structure includes a transparent conductive oxide layer.

16. The display device according to claim 8, wherein, The complementary metal-oxide-semiconductor wafer includes: A silicon substrate, in which a source region or a drain region is defined; Gate, on the silicon substrate; A first insulating layer is formed on the silicon substrate and covers the gate. The first contact electrode is connected to the source region or the drain region through a first contact hole defined in the first insulating layer; A second insulating layer is formed on the first insulating layer and covers the first contact electrode; and The second contact electrode is connected to the first electrode structure and is connected to the first contact electrode through a second contact hole passing through the second insulating layer.

17. The display device according to claim 1, wherein, The display device further includes a side insulating layer and a side reflective layer, the side insulating layer covering the light-emitting diode, and the side reflective layer covering the side insulating layer that overlaps with the light-emitting diode and being spaced apart from each other on the side insulating layer.

18. The display device according to claim 17, wherein, The common electrode contacts the light-emitting diode through a contact hole, which overlaps with the light-emitting diode and penetrates the planarization layer, the side reflective layer, and the side insulating layer.

19. The display device according to claim 18, wherein, The display device further includes a passivation layer on the common electrode. The passivation layer comprises organic and / or inorganic materials.

20. An electronic device comprising the display device of claim 1, wherein, The electronic device is selected from the following: flat panel display, curved display, computer monitor, medical monitor, television set, billboard, indoor light, outdoor light, signal light, head-up display, fully transparent display, partially transparent display, flexible display, rollable display, foldable display, stretchable display, laser printer, telephone, mobile phone, tablet computer, tablet phone, personal digital assistant, wearable device, laptop computer, digital camera, portable camcorder, viewfinder, miniature display, 3D display, virtual reality display, augmented reality display, vehicle, video wall including multiple displays spliced ​​together, theater screen, stadium screen, light therapy device, and signboard.

Images