Sensing device

Abstract

To provide a sensing device capable of detecting photons with high accuracy regardless of the illuminance of the environment. The sensing device is provided with: a photodetector; a first resistor connected between the photodetector and a first reference potential; the second resistor is connected between a photoelectric detector and the first resistor; a first transistor of a first conductivity type, a gate of which is connected to the first resistor and the second resistor via a first signal line interposed between the first resistor and the second resistor; a second transistor of the first conductivity type having a first terminal connected to a first reference potential, a second terminal connected to a first terminal of the first transistor, and a gate connected to a second signal line; the first end of the third transistor is connected to the second end of the first transistor, and the second end of the third transistor is connected to a second reference potential; and a first inverter bridged between a third signal line and a fourth signal line, the third signal line being interposed between the first transistor and a third transistor (24).

Description

[0001] The present application is a divisional application of the Chinese national phase application for international application No. PCT / JP2020 / 039647, filed on October 22, 2020, with the title of “Sensing device and ranging apparatus”, the entering national phase date of which is April 26, 2022, the application number of which is 202080075067.5, and the title of which is “Sensing device and ranging apparatus”. TECHNICAL FIELD

[0002] The present disclosure relates to a sensing device and a ranging apparatus. BACKGROUND

[0003] In a plurality of fields including vehicle-mounted and mobile devices, there are increasing applications that use a sensing device to measure a distance to an object based on a time of flight (ToF), which is a time taken by emitted light from a light source, reflected by the object, before reaching a detector. An avalanche photodiode (APD) is a well-known light-receiving element for a sensing device. A voltage equal to or higher than a breakdown voltage is applied across terminals of the APD in a Geiger mode. Then, a single photon entering the photodiode causes an avalanche phenomenon. The APD multiplying a single photon by the avalanche phenomenon is called a single photon avalanche diode (SPAD).

[0004] With the SPAD, reducing a voltage across the terminals to the breakdown voltage can prevent the avalanche phenomenon. Reducing the terminal-terminal voltage to prevent the avalanche phenomenon is called quenching. Recharging the voltage across the terminals of the SPAD to a bias voltage equal to or higher than the breakdown voltage allows detecting photons again.

[0005] LIST OF CITATIONS

[0006] PATENT LITERATURE

[0007] JP 2019-007877A

[0008] NON-PATENT LITERATURE

[0009] Non-Patent Literature 1: Matteo Perenzoni et al., “A 64×64-Pixels Digital Silicon Photomultiplier Direct TOF Sensor With 100-MPhotons / s / pixel Background Rejection and Imaging / Altimeter Mode With 0.14% Precision Up To 6 km for Spacecraft Navigation and Landing”, JSSC 2017

[0010] Non-Patent Literature 2: Cristiano Niclass et al., “A 0.18 µm CMOS SoC for a 100 m-Range 10fps 200×96-Pixel Time-of-Flight Depth Sensor,” ISSCC 2013 SUMMARY

[0011] PROBLEMS TO BE SOLVED BY THE INVENTION

[0012] In a high-illuminance environment, for example, there can be a case where a sensing device cannot be recharged or the recharging time is extended. In such a case, the accuracy of detecting photons decreases. In order to measure a distance with high accuracy, a sensing device and a distance measuring device that support a wide dynamic range are required.

[0013] Therefore, the present disclosure provides a sensing device and a distance measuring device capable of detecting photons with high accuracy regardless of the environmental illuminance.

[0014] According to one embodiment of the present disclosure, a sensing device can be provided, which is provided with: a photodetector; a first resistor connected between the photodetector and a first reference potential; a second resistor connected between the photodetector and the first resistor; a first transistor of a first conductivity type, whose gate is connected to the first resistor and the second resistor via a first signal line interposed between the first resistor and the second resistor; a second transistor of the first conductivity type, whose first end is connected to the first reference potential, whose second end is connected to a first end of the first transistor, and whose gate is connected to a second signal line; a third transistor of a second conductivity type, whose first end is connected to a second end of the first transistor, and whose second end is connected to a second reference potential; and a first inverter connected between a third signal line and a fourth signal line, the third signal line being interposed between the first transistor and the third transistor (24).

[0015] According to one embodiment of the present disclosure, a sensing device can be provided, which includes: a photodetector; a load element connected between the photodetector and a first reference potential; a first transistor of a first conductivity type configured to be turned on in accordance with a voltage of a first signal line interposed between the photodetector and the load element; a second transistor of the first conductivity type configured to be turned on between the first reference potential and the first transistor in accordance with a current of the first transistor or a voltage of a second signal line; a third transistor of a second conductivity type configured to be turned on between the first transistor and a second reference potential in accordance with the voltage of the second signal line; and a first inverter connected between a third signal line and a fourth signal line, the third signal line being interposed between the first transistor and the third transistor.

[0016] The sensing device can further include a pulse generator configured to output a pulse to the second signal line according to a voltage of the fourth signal line.

[0017] The pulse generator can be configured such that, when a voltage level on the fourth signal line changes, the pulse generator outputs a pulse to the second signal line after a time delay.

[0018] The sensing device can further include a first resistor connected between the load element and the photodetector, and a fourth transistor of the first conductivity type connected in series to the first resistor.

[0019] The sensing device can further include a second inverter connected to the second signal line. The load element can be a fifth transistor of the first conductivity type. The fifth transistor can be configured to turn on according to an output voltage from the second inverter.

[0020] The sensing device can further include a sixth transistor of the second conductivity type configured to turn on between a second reference potential and the second signal line according to a voltage of the second signal line, wherein the load element is a fifth transistor of the first conductivity type configured to turn on according to a voltage of the second signal line.

[0021] The pulse generator can include a first delay device, a second delay device connected in series to the first delay device, an AND circuit connected to a downstream side of the second delay device, and a third inverter connected between the first delay device and the AND circuit, the first delay device being connected to the fourth signal line, the downstream side of the AND circuit being connected to the second signal line.

[0022] The pulse generator can include an inverter chain.

[0023] The pulse generator can include a flip-flop having a D terminal connected to the fourth signal line, and a fourth inverter connected to a Q terminal of the flip-flop, an output side of the fourth inverter being connected to the second signal line.

[0024] The pulse generator can include a two-stage amplification circuit with a source electrode grounded, a first current source connected to a first stage of the two-stage amplification circuit, a second current source connected to a second stage of the two-stage amplification circuit, a capacitor connected between the first stage and the second stage of the two-stage amplification circuit, and a fifth inverter connected to the first stage of the two-stage amplification circuit, an input terminal of the two-stage amplification circuit being connected to the fourth signal line, an output terminal of the fifth inverter being connected to the second signal line.

[0025] The photodetector can be mounted on a first substrate that electrically connects other elements mounted thereon to a second substrate via a Cu-Cu connection.

[0026] The photodetector can include an avalanche photodiode.

[0027] According to another embodiment of the present disclosure, a distance measuring apparatus having a plurality of sensing devices can be provided, the distance measuring apparatus including a light source, a logic circuit configured to output a result of an OR operation of output voltages from the plurality of sensing devices, and a measurement circuit configured to measure a distance to an object based on a timing of emitting light from the light source and a signal output from the logic circuit.

[0028] The distance measuring apparatus can further include a control circuit connected to a second signal line of the plurality of sensing devices, wherein the control circuit is configured to output a pulse to the second signal line based on a signal input to the measurement circuit from a fourth signal line of at least any one of the sensing devices.

[0029] According to a further embodiment of the present disclosure, a sensing device can be provided, the sensing device including a photodetector, a load element connected between the photodetector and a first reference potential, a seventh transistor of a second conductivity type configured to turn on between the photodetector and a sixth signal line according to a voltage of a fifth signal line, an eighth transistor of a first conductivity type configured to turn on between the first reference potential and the seventh transistor according to the voltage of the fifth signal line, a ninth transistor of the first conductivity type configured to turn on between the first reference potential and a seventh signal line according to a voltage of the sixth signal line, a tenth transistor of the second conductivity type configured to turn on between the seventh signal line and a second reference potential according to a voltage of an eighth signal line, and a sixth inverter connected between the seventh signal line and a ninth signal line, wherein the fifth signal line is connected to the ninth signal line.

[0030] The sensing device can further include a pulse generator configured to output a pulse to an eighth signal line according to the voltage of the ninth signal line.

[0031] The sensing device can further include a first resistor connected between the load element and the photodetector, and a fourth transistor of the first conductivity type connected in series to the first resistor.

[0032] The sensing device can further include an eleventh transistor configured to turn on between the first reference potential and the ninth transistor according to a voltage applied to a first control electrode.

[0033] The sensing device can further include a twelfth transistor configured to turn on between the seventh signal line and the tenth transistor according to a voltage applied to a second control electrode.

[0034] According to another embodiment of this disclosure, a sensing device is provided, comprising: a photodetector; a load element connected between the photodetector and a first reference potential; a seventh transistor of a second conductivity type configured to conduct between the photodetector and a sixth signal line according to a voltage of a fifth signal line; an eighth transistor of a first conductivity type configured to conduct between the first reference potential and the seventh transistor according to a voltage of the fifth signal line; a ninth transistor of a first conductivity type configured to conduct between the first reference potential and the seventh signal line according to a voltage of the sixth signal line; and a tenth transistor of a second conductivity type. The tenth transistor is configured to conduct between the seventh signal line and the second reference potential according to the voltage of the eighth signal line; a sixth inverter connected to the seventh signal line; a seventh inverter connected between the sixth inverter and the ninth signal line; a third delay device connected to the ninth signal line; a NOR circuit configured to output the result of a NOR operation on the output voltage of the third delay device and the voltage of the tenth signal line to the eighth signal line; and a NAND circuit configured to output the result of a NAND operation on the voltage of the ninth signal line and the voltage of the eighth signal line to the fifth signal line. Attached Figure Description

[0035] Figure 1 This is a schematic block diagram depicting an exemplary sensing device according to the present disclosure.

[0036] Figure 2 This is a schematic diagram depicting an example of measuring distance using a sensing device.

[0037] Figure 3 This is a detailed circuit diagram of an exemplary sensing device according to the present disclosure.

[0038] Figure 4 These are a set of graphs illustrating exemplary voltage signals and photon counts using a sensing device according to this disclosure.

[0039] Figure 5 This is a block diagram illustrating an exemplary sensing device with reversed polarity.

[0040] Figure 6 This is a block diagram illustrating an exemplary sensing device in which some components are omitted.

[0041] Figure 7 yes Figure 3 Detailed circuit diagram of the sensing device in the image.

[0042] Figure 8 It describes the use of Figure 3A set of graphs showing the exemplary voltage signal and photon count of the sensing device in the image.

[0043] Figure 9 It is a description of Figure 3 A set of graphs showing exemplary pulses from a sensing device.

[0044] Figure 10 It is a set of graphs describing an exemplary pulse of a sensing device according to this disclosure.

[0045] Figure 11 This is a circuit diagram depicting an exemplary sensing device in the first variation.

[0046] Figure 12 This is a circuit diagram depicting an exemplary sensing device in the second variation.

[0047] Figure 13 This is a circuit diagram depicting an exemplary sensing device in the third variant.

[0048] Figure 14 This is a circuit diagram depicting an exemplary sensing device in the fourth variant.

[0049] Figure 15 This is a circuit diagram depicting an exemplary sensing device in the fifth variant.

[0050] Figure 16 This is a circuit diagram depicting an exemplary pulse generator that includes a delay device.

[0051] Figure 17 It describes including Figure 16 A graph of an exemplary signal waveform of the sensing device of the pulse generator in the image.

[0052] Figure 18 This is a circuit diagram depicting an exemplary pulse generator including an inverter chain.

[0053] Figure 19 This is a circuit diagram depicting an exemplary pulse generator including a trigger.

[0054] Figure 20 It describes including Figure 19 A graph of an exemplary signal waveform of the sensing device of the pulse generator in the image.

[0055] Figure 21 This is a circuit diagram illustrating an exemplary pulse generator including a source-grounded amplifier.

[0056] Figure 22 This is a circuit diagram depicting an exemplary sensing device in the sixth variation.

[0057] Figure 23This is a graph depicting an exemplary signal waveform of the sensing device in the sixth variation.

[0058] Figure 24 This is a circuit diagram depicting an exemplary sensing device in the seventh variation.

[0059] Figure 25 This is a circuit diagram showing an exemplary sensing device in the eighth variation.

[0060] Figure 26 This is a circuit diagram showing an exemplary sensing device in the ninth variation.

[0061] Figure 27 This is a circuit diagram showing an exemplary sensing device in the ninth variation.

[0062] Figure 28 This is a perspective view showing an example of how to install a sensing device using a Cu-Cu connection.

[0063] Figure 29 This is a circuit diagram illustrating an exemplary circuit that supports dToF-based distance measurement.

[0064] Figure 30 This is a schematic diagram depicting an exemplary circuit including a counter and a TDC.

[0065] Figure 31 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0066] Figure 32 This diagram illustrates an example of the installation location of the vehicle's external information detection unit and imaging unit. Detailed Implementation

[0067] Some preferred embodiments of this disclosure are described in detail below with reference to the accompanying drawings. It should be noted that throughout the following description and drawings, the same reference numerals denote the same or corresponding constituent elements having substantially similar functions, and where such elements are redundant, explanations of these elements will be omitted.

[0068] Figure 1 The block diagram schematically illustrates an exemplary sensing device according to the present invention. Figure 1 The sensing device 1 includes a detector 5, a quenching unit 6, and a detection unit 9. The detection unit 9 has a switching unit 2, an initialization unit 3, and an amplification unit 4 as its constituent elements. For example, a photodetector such as a photodiode can be used as the detector 5. In the following description, it is assumed that a single-photon avalanche diode (SPAD) is used as an exemplary detector 5. Alternatively, a sensor that detects other physical information can be used as the detector 5. A ranging device 90 that combines the sensing device 1 with the measurement circuit 7 can be installed.

[0069] Figure 2 This is a schematic diagram depicting an example of measuring distance using a sensing device. Figure 2 This illustrates a scenario where the distance to an object 80 is measured using a light source 91 and a ranging device 90. The light source 91 emits light em towards the object 80. The ranging device 90 detects the reflected light rl from the light em of the object 80 using a sensing device 1. Although the object 80 is... Figure 2 The term refers to vehicles, but there are no restrictions on the type of object. See below for further details. Figure 1 and Figure 2 A description of a sensing device according to this disclosure is provided.

[0070] Photons entering detector 5 cause an avalanche phenomenon, changing the voltage of signal line Vi1. In the quenching unit 6, a voltage drop due to the current occurs, causing the voltage between the terminals of detector 5 to drop to the breakdown voltage, thereby stopping the avalanche phenomenon. Switching unit 2 switches between detection operation and reset operation. The detection operation involves detecting the photon response signal, and the reset operation resets its internal state. Initialization unit 3 changes the voltage level in detector unit 9 during the reset operation, enabling detector unit 9 to detect photons again.

[0071] When detector 5 reacts to a photon during detection operation, detector 9 outputs a corresponding pulse via signal line Vout. Measurement circuit 7 is connected downstream of detector 9 (sensing device 1) via buffer Buuf. Buffer Buuf is also referred to as a sampler circuit that digitizes the signal output from detector 9. Figure 1 As shown, multiple sensing devices and multiple buffers (Buf) can be connected to the measurement circuit 7.

[0072] Measurement circuit 7 includes, for example, a TDC (Time-to-Digital Converter) and a histogram generator. Based on information related to the emission time t0 input from the signal line TIM, the TDC measures the time elapsed from the emission time t0 to the photon incident time t1. The elapsed time corresponds to the time of flight (ToF), during which the light emitted from the light source 91 is reflected by the object 80 before reaching the detector 5. The histogram generator accumulates the results of multiple measurements of the time of flight to generate a histogram. Performing multiple measurements of the time of flight allows for differentiation between background light (ambient light) and reflected light rl emitted from the light source. When generating the histogram, calculations can be performed to average the multiple measurements of the time of flight. Obtaining the peak value in the histogram allows for the calculation of the distance between the sensing device 1 and the object 80. For example, if "c" represents the speed of light, the distance between the sensing device 1 and the object 80 can be calculated using the formula L=c / 2(t1-t0). Furthermore, the above is only an example of the processing of measurement circuit 7. Measurement circuit 7 can alternatively perform different processing.

[0073] For example, the measurement circuit 7 can be installed using hardware circuitry such as an FPGA (Field Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit). Alternatively, the functionality of the measurement circuit 7 can be implemented by a CPU (Central Processing Unit) and a program executed by it. The measurement circuit 7 may include memory or storage to hold the program and the data necessary for its execution.

[0074] Figure 3 The circuit diagram shows an exemplary circuit corresponding to sensing device 1. Figure 3 The circuit 100 includes a photodiode PD, a pulse generator 8, transistors 10, 11, 12, 13, and 14, and an inverter 30. Transistors 10, 11, and 13 are P-MOS transistors. Transistors 12 and 14 are N-MOS transistors. The photodiode PD is an example of the detector 5 described above. Transistor 10 corresponds to the quenching section 6 described above. Additionally, transistor 10 corresponds to the load element of the photodiode PD. Transistor 10 can be replaced by a resistor as the load element. The downstream portion of the signal line Vi1 in circuit 100 corresponds to the detection section 9 described above.

[0075] First, the structure of circuit 100 will be explained.

[0076] The sources of transistors 10, 11, and 13 are connected to the power supply potential Vdd. On the other hand, the drain of transistor 10 is connected to the cathode of photodiode PD. Furthermore, the cathode of photodiode PD is connected to the source of transistor 12 via signal line Vi1. A voltage Van is applied to the anode of photodiode PD. The value of voltage Vn can be determined by applying a reverse voltage equal to or higher than the breakdown voltage between the cathode and anode of photodiode PD (i.e., between the terminals). The drain of transistor 12 is connected to the drain of transistor 11 and the gate of transistor 13. Signal line Vi2 connects the node between the drains of transistors 11 and 12 to the gate of transistor 13.

[0077] The drain of transistor 13 is connected to the input terminal of inverter 30 and the drain of transistor 14 via signal line Vi3. Signal line Vout is connected to the output terminal of inverter 30. Additionally, the output terminal of inverter 30 is also connected to the input terminal of pulse generator 8. The output terminal of inverter 30 is further connected to the gates of transistors 11 and 12 via signal line FB. On the other hand, the gate of transistor 14 is connected to the output terminal of pulse generator 8 via signal line INI. The source of transistor 14 is connected to ground potential. For example, the reference potential of circuit 100, the reference potential of the signal line, or the ground voltage can be used as the ground potential. However, the type of potential used as the ground potential is not important. Note that in circuit 100, the parasitic capacitance Cp between signal line Vi3 and the ground potential is represented. The sources of transistors 10, 11, and 13 can all be connected to a common power supply potential Vdd. Moreover, the source of at least one of transistors 10, 11, and 13 can be connected to different power supply potentials.

[0078] Figure 4 An exemplary voltage signal and photon count are depicted with respect to sensing device 1. Figure 4 Curve 61 in Figure 61 shows the voltage waveform on signal line Vi1 in circuit 100. The line th in curve 61 represents the threshold voltage of inverter 30. Curve 62 depicts the voltage waveform on signal line Vi2 in circuit 100. Curve 63 depicts the voltage waveform on signal line Vout in circuit 100. On the other hand, curve 64 depicts an exemplary photon count in circuit 100 with respect to measurement circuit 7. Figure 17 , Figure 20 and Figure 23 Exemplary voltage waveforms on signal lines Vi1, Vi2, and Vi3 are also depicted.

[0079] Next, we will explain how circuit 100 works.

[0080] When the photodiode PD reacts with a photon, causing an increase in current between the cathode and anode of the photodiode, the voltage drop of signal line Vi1 (curve 61) matches the voltage drop between the source and drain of transistor 10. As a result, the voltage of signal line Vi2, connected to signal line Vi1 via transistor 12, changes from high to low (curve 62). When a low voltage is applied to the gate of transistor 13, the state between the source and drain of transistor 13 is turned on. The voltage of signal line Vi3 is made high by the power supply potential Vdd. When a high signal is received from signal Vi3, inverter 30 outputs a low signal. In circuit 100, when a photon is detected, signal line Vout outputs a low-level (negative polarity) pulse. Furthermore, given a low-level pulse, downstream measurement circuit 7 can perform the aforementioned distance measurement process.

[0081] At this time, a low voltage is applied to the gates of transistors 11 and 12. The state between the source and drain of transistor 11 is turned on. Furthermore, the state between the drain and source of transistor 12 is turned off. As a result, signal line Vi2 is electrically disconnected from signal line Vi1, and the voltage is brought high by the power supply potential Vdd. By applying a high voltage to the gate of transistor 13, the state between the source and drain of transistor 13 is turned off.

[0082] When the output voltage of inverter 30 goes low, pulse generator 8 outputs a high-level (positive) pulse to signal line INI after a predetermined time delay. This applies a high-level voltage to the gate of transistor 14, turning on the drain-source interface of transistor 14. This initializes signal line Vi3 to a low voltage. As the voltage on signal line Vi3 goes low, the output voltage of inverter 30 goes high. This ends the low-level pulse on signal line Vout.

[0083] The duration of the low-level pulse output from signal line Vout can be changed by adjusting the time delay from when the low-level pulse from inverter 30 is input to pulse generator 8 to when pulse generator 8 generates a high-level pulse. When the output voltage of inverter 30 becomes high, a high voltage is applied to the gates of transistors 11 and 12. This cuts off the state between the source and drain of transistor 11. Conversely, it turns on the state between the drain and source of transistor 12. Because conduction is established between signal lines Vi1 and Vi2, photons can be detected again.

[0084] The voltage within circuit 100 is reset when a pulse is output after each reaction with a photon. Therefore, photons can be detected even in high-illuminance environments represented by Lh1 in curves 61 to 64. When circuit 100 is used, the photon count record with measurement circuit 7 shows an absolute monotonic increase consistent with the illuminance level (curve 64).

[0085] Figure 5 The block diagram illustrates an exemplary sensing device with reversed polarity. Figure 5 In the sensing device 1A, the quenching unit 6A and the detector 5A are connected in the reverse order of their counterparts in the sensing device 1. That is, the sensing device according to this disclosure can use polarity and Figure 3 Circuit 100 is a circuit with opposite polarity. To reverse the polarity, the N-MOS transistor in circuit 100 only needs to be replaced by a P-MOS transistor, and the P-MOS transistor in circuit 100 is replaced by an N-MOS transistor. In the case where detector 5A is a photodiode such as an avalanche diode (APD), a positive bias voltage is applied to the cathode of the photodiode. Not only circuit 100, but also several circuits described below can be configured with opposite polarity.

[0086] The sensing device according to this disclosure may include a photodetector, a load element, a seventh transistor of a second conductivity type, an eighth transistor of a first conductivity type, a ninth transistor of a first conductivity type, a tenth transistor of a second conductivity type, and a sixth inverter. The load element is connected between the photodetector and a first reference potential. The seventh transistor conducts the state between the photodetector and the sixth signal line according to the voltage of the fifth signal line. The eighth transistor conducts the state between the first reference potential and the seventh transistor according to the voltage of the fifth signal line. The ninth transistor conducts the state between the first reference potential and the seventh signal line according to the voltage of the sixth signal line. The tenth transistor conducts the state between the seventh signal line and the second reference potential according to the voltage of the eighth signal line. The sixth inverter is connected between the seventh signal line and the ninth signal line. Furthermore, the fifth signal line is connected to the ninth signal line.

[0087] For example, a P-MOS transistor can be used as the first conductivity type transistor, and an N-MOS transistor can be used as the second conductivity type transistor. In this case, the power supply potential can be used as the first reference potential, and the ground potential can be used as the second reference potential. Alternatively, an N-MOS transistor can be used as the first conductivity type transistor, and a P-MOS transistor can be used as the second conductivity type transistor. In this case, the ground potential can be used as the first reference potential, and the power supply potential can be used as the second reference potential.

[0088] Figure 3 Transistor 10 is an example of a load element. It should be noted that a load element can be a passive component such as a resistor. Transistor 12 is an example of a seventh transistor. Signal line FB is an example of a fifth signal line. Figure 3 Signal line Vi2 is an example of the sixth signal line. Transistor 11 is an example of the eighth transistor. Transistor 13 is an example of the ninth transistor. Figure 3 Signal line Vi3 is an example of the seventh signal line. Transistor 14 is an example of the tenth transistor. Figure 3 The signal line INI in the example is the eighth signal line. Figure 3 Inverter 30 in the diagram is an example of the sixth inverter. Figure 3 The signal line Vout in the example is the ninth signal line. For example, an avalanche photodiode can be used as a photodetector.

[0089] Furthermore, the sensing device according to this disclosure may further include a pulse generator configured to output pulses to an eighth signal line based on the voltage of the ninth signal line.

[0090] Figure 6 An exemplary sensing device is shown, in which some components are omitted. Figure 3The sensing device 1B includes a detector 5, a quenching unit 6, and a detection unit 9B. For example... Figure 1 As shown, the measurement circuit 7 is connected to the downstream side of the sensing device 1B via a buffer Buf.

[0091] Figure 7 The circuit diagram describes the circuit corresponding to sensing device 1B. Figure 7 Circuit 50 includes a photodiode PD, transistors 10, 18, and 19, and an inverter 30. Transistors 10 and 18 are P-MOS transistors. Transistor 19 is an N-MOS transistor. The source of transistor 10 is connected to the power supply potential Vdd. Additionally, the drain of transistor 10 is connected to the cathode of the photodiode PD. A voltage Van is applied to the anode of the photodiode. The value of voltage Van can be determined by applying a reverse voltage equal to or higher than the breakdown voltage between the cathode and anode of the photodiode PD (i.e., between the terminals).

[0092] Additionally, the gate of transistor 18 is connected via signal line Vil to a node between the drain of transistor 10 and the cathode of photodiode PD. The source of transistor 18 is connected to the power supply potential Vdd. The drain of transistor 18 is connected to the input terminal of inverter 30 via signal line Vi4. Furthermore, the drain of transistor 18 is also connected to the drain of transistor 19. The output terminal of inverter 30 is connected to signal line Vout. The source of transistor 19 is connected to ground potential. In circuit 50, photodiode PD corresponds to detector 5, and transistor 10 corresponds to quenching section 6. Furthermore, transistors 18 and 19, as well as inverter 30, correspond to detector section 9B.

[0093] When the photodiode PD reacts with a photon, the current between the cathode and anode of the photodiode PD increases. As a result, the voltage at the cathode of the photodiode PD drops, matching the voltage drop between the source and drain of transistor 10. Consequently, the voltage on signal line Vil becomes low, applying a low voltage to the gate of transistor 18. This turns on the state between the source and drain of transistor 18. The voltage on signal line Vi4 becomes high through the power supply potential Vdd. When a high voltage input is received, inverter 30 outputs a low voltage. When detecting a photon, circuit 50 therefore outputs a low (negative) pulse.

[0094] When the voltage between the cathode and anode drops to the breakdown voltage, the avalanche current stops. This suppresses the voltage drop between the source and drain of transistor 10, causing the voltage on signal line Vi1 to go high. When a high voltage is applied to the gate of transistor 18, the state between the source and drain of transistor 18 is cut off. When an external control circuit applies a high voltage Vbn to the gate of transistor 19, the state between the drain and source of transistor 19 is turned on. As a result, signal line Vi4 is disconnected from the power supply potential Vdd and connected to ground. When the voltage on signal line Vi4 goes low, inverter 30 outputs a high voltage. Therefore, circuit 50 stops outputting low pulses.

[0095] Figure 8 An exemplary voltage waveform and photon count using sensing device 1B are depicted. Figure 8 Curve 65 depicts an exemplary voltage waveform on signal line Vi1 in circuit 50. Curve 66 depicts an exemplary voltage waveform on signal line Vout in circuit 50. Curve 67 indicates an exemplary photon count of measurement circuit 7 in circuit 50. Because the switching unit 2 and initialization unit 3 are omitted in sensing device 1B, the above-described reset operation is not performed. When sensing device 1B is used in a high-illuminance environment, there is a possibility that detector 5 may react with photons again before the quenching unit 6 reduces the voltage between the terminals of detector 5 to the breakdown voltage. In this case, the voltage of signal line Vi1 continues to decrease (Lh2 in curve 65), making it impossible to generate pulses (Lh2 in curve 66). As a result, as shown by Lh2 in curve 67, the photon count does not increase monotonically, making it difficult to detect photons correctly. In addition, for comparison, line Lr in curves 65 to 67 represents a graph corresponding to the time during which sensing device 1B operates normally.

[0096] Figure 9 The graph in the figure shows an exemplary pulse of sensing device 1B. Figure 9 Curve 68 in the diagram depicts an exemplary voltage waveform on signal line Vi1 in circuit 50. Curve 68 indicates that the characteristic changes caused by the process can result in two types of sensing devices: one with a short recharge time and the other with a long recharge time. The width of the pulse output to signal line Vi1 is proportional to the recharge time. As a result, when the voltage waveform on signal line Vi1 changes as shown by curve 69, the width of the pulse output to signal line Vout also changes. To prevent missed photons, it is preferable that both the dead time and the recharge time are as short as possible. However, if the width of the pulse output to signal line Vout is too narrow, the downstream measurement circuit 7 becomes difficult to detect photons.

[0097] at the same time, Figure 10 The graph in the figure illustrates an exemplary pulse with a sensing device (circuit 100) according to the present disclosure.Figure 10 Graph 70 in the diagram depicts an exemplary voltage waveform on signal line Vi1 in circuit 100. Also in graph 70, the voltage changes over the recharge time depending on the sensing device. However, circuit 100 detects the falling edge of the voltage signal on signal line Vi1 and outputs a pulse of a specific time width (Td) to signal line Vout. Therefore, regardless of the change in the recharge time of the sensing device, a pulse of a specific width can be output to downstream measurement circuit 7. Circuit 100 can be constructed in a manner that allows adjustment of the pulse width Td. This allows the pulse width and pulse output timing to be controlled in a manner that adjusts measurement circuit 7. Because circuit 100 resets its internal voltage each time a pulse is output, circuit 100 can quickly return to a state ready to detect the next photon.

[0098] Figure 11 The circuit diagram illustrates an exemplary sensing device in the first variation. Figure 11 Circuit 101 corresponds to circuit 100 supplemented with resistor R1. Resistor R1 is connected in series to photodiode PD. By adding resistor R1, the voltage between the terminals of photodiode PD during photon reaction is reduced, limiting the current flowing through photodiode PD. The resistance value of resistor R1 is set such that quenching occurs when the parasitic capacitance of the cathode of photodiode PD discharges. In circuit 101, the voltage amplitude from the start of photon reaction to the execution of quenching is reduced. As a result, the power consumption of the circuit can be reduced. The other structures of circuit 101 are the same as those of circuit 100. Furthermore, the basic operation of circuit 101 is the same as that of circuit 100.

[0099] Figure 12 The circuit diagram illustrates an exemplary sensing device in the second variation. Figure 12 Circuit 102 corresponds to circuit 100 supplemented with resistor R1 and transistor 15. Resistor R1 and transistor 15 are connected in series to photodiode PD. Transistor 15 is a P-MOS transistor. A negative voltage Vclp, used to make the voltage Vgs between the gate and source of transistor 15 equal to or higher than a threshold, is applied to the gate of transistor 15. Before a photon enters photodiode PD, the state between the source and drain of transistor 15 remains on. However, when photodiode PD reacts with a photon and the voltage of signal line Vi1 decreases, the voltage Vgs between the gate and source of transistor 15 decreases. As a result, the resistance between the source and drain of transistor 15 increases. Therefore, this allows the voltage amplitude on signal line Vi to be limited and power consumption to be reduced. It should be noted that, although not shown, circuit 102 can be configured without resistor R1. The remaining configuration of circuit 102 is similar to that of circuit 100. Furthermore, the basic operation of circuit 102 is similar to that of circuit 100.

[0100] That is, the sensing device according to this disclosure may further include: a first resistor connected between the load element and the photodetector; and a fourth transistor of a first conductivity type connected in series with the first resistor. Figure 12 Resistor R1 is an example of the first resistor. Furthermore, transistor 15 is an example of the fourth transistor.

[0101] Figure 13 The circuit diagram depicts an exemplary sensing device in the third variant. Figure 13 Circuit 103 corresponds to circuit 102, which omits the pulse generator 8. The signal line INIT in circuit 103 is connected to, for example, an external control circuit 150. The external control circuit 150 generates a reset pulse instead of the pulse generator 8. With the configuration of circuit 103, it is not necessary to prepare a pulse generator for each pixel (i.e., photodiode). Therefore, multiple pixels can share the control circuit 150. The control circuit 150 does not need to provide pulses to every pixel connected to it. When at least one of the pixels connected to the measurement circuit 7 (i.e., a sensing device) detects a photon, the control circuit 150 outputs a pulse to the signal line INIT of the photon-detecting pixel. When the control circuit 150 is shared by multiple pixels (i.e., the initialization unit is shared by multiple detection units), the overall circuit can be miniaturized. For example, compared to circuit 102, circuit 103 reduces the area of ​​the pulse-generating circuit block by three-quarters. The remaining configuration of circuit 103 is similar to that of circuit 102. Except for the control circuit 150 generating the reset pulse, the operation of circuit 103 is similar to that of circuit 100 described above.

[0102] Figure 14 The circuit diagram depicts an exemplary sensing device in the fourth variant. Figure 14 Circuit 104 corresponds to circuit 102 supplemented with transistor 16. The source of transistor 16 is connected to the power supply potential Vdd. On the other hand, the drain of transistor 16 is connected to the source of transistor 13. Transistor 16 is a P-MOS transistor. In circuit 102, for example, when the timing of the reset pulse input to signal line INI by pulse generator 8 or external control circuit coincides with the timing of the voltage of signal line Vi2 going low, there is a possibility that current may flow between the power supply potential Vdd and the ground potential. In circuit 104, the voltage Vbp2 applied to the gate of transistor 16 can be controlled to prevent the occurrence of current flow. This can reduce the power consumption of the circuit. The remaining configuration of circuit 104 is similar to that of circuit 102. Moreover, the basic operation of circuit 104 is similar to that of circuit 100 described above.

[0103] The sensing device according to this disclosure may further include an eleventh transistor, which conducts a state between a first reference potential and a ninth transistor according to a voltage applied to a first control electrode. Figure 14 Transistor 13 in the diagram is an example of the ninth transistor. Figure 14 Transistor 16 in the diagram is an example of an eleventh transistor. The gate of transistor 16 is an example of a first control electrode.

[0104] Figure 15 The circuit diagram depicts an exemplary sensing device in the fifth variant. Figure 15 Circuit 105 corresponds to circuit 102 supplemented with transistor 17. The drain of transistor 17 is connected to signal line Vi3. On the other hand, the source of transistor 17 is connected to the drain of transistor 14. Transistor 17 is an N-MOS transistor. In circuit 105, the voltage Vbn2 applied to the gate of transistor 17 can be controlled to prevent overcurrent and reduce power consumption. The remaining configuration of circuit 105 is similar to that of circuit 102. Furthermore, the basic operation of circuit 105 is similar to that of circuit 100 described above.

[0105] The sensing device according to this disclosure may further include a twelfth transistor, which conducts a state between the seventh signal line and the tenth transistor according to a voltage applied to the second control electrode. Figure 15 The signal line Vi3 in the example is the seventh signal line. Figure 15 Transistor 14 in the diagram is an example of the tenth transistor. Figure 15 Transistor 17 is an example of the twelfth transistor. The gate of transistor 17 is an example of the second control electrode.

[0106] The specific structure of pulse generator 8 will be described below.

[0107] Figure 16 The circuit diagram depicts the first instance of a pulse generator. Figure 16 The pulse generator 8A includes delay devices D1 and D2, an inverter 31, and an AND circuit P1. Delay devices D1 and D2, and the AND circuit P1 are connected in series between signal line Vout and signal line INI. Signal line Vd1 connects delay devices D1 and D2. Furthermore, signal line Vd2 connects delay device D2 to one input terminal of the AND circuit P1. Inverter 31 connects signal line Vd1 to the other input terminal of the AND circuit P1.

[0108] Figure 17An exemplary circuit voltage waveform is described using a pulse generator 8A. A signal delayed by delay devices D1 and D2 is input from signal line Vd2 to the input terminal of the AND circuit P1. Conversely, a signal delayed by delay device D1 and inverted by inverter 31 is input to the other input terminal of the AND circuit P1. The AND circuit P1 outputs a signal corresponding to the logical product (AND) of the signals input from the two input terminals to signal line INI. See also... Figure 17 The voltage waveform shows that, given a low-level pulse on signal line Vout, a high-level pulse with a predetermined width is output from signal line INI after a time delay.

[0109] Figure 18 The circuit diagram illustrates a second instance of the pulse generator. Figure 18 The pulse generator 8B includes an inverter chain 300. In the inverter chain 300, five inverters are connected in series between signal line Vout and signal line INI. Alternatively, the inverter chain may include a different number of inverters. An even number of inverters may be provided for circuit use, depending on the polarity of the reset pulse. As another alternative, an odd number of inverters may be provided.

[0110] Figure 19 The circuit diagram illustrates the third instance of a pulse generator. Figure 19 The pulse generator 8C includes a flip-flop F1 and an inverter 31. Flip-flop F1 is a D flip-flop. Signal line Vout is connected to the D terminal of flip-flop F1. Signal line CK is connected to the clock terminal of flip-flop F1. Inverter 32 is connected between the Q terminal of flip-flop F1 and signal line INI.

[0111] Figure 20 An exemplary circuit voltage waveform is described using a pulse generator 8C. (Reference) Figure 20 It is revealed that the clock signal supplied to signal line CK can be controlled to adjust the time delay from the time of the low-level pulse input to signal line Vout to the time of the high-level signal output to signal line INI. For example, increasing the inter-pulse interval of the clock signal can increase the time delay. Conversely, shortening the inter-pulse interval of the clock signal can reduce the time delay. That is, by using pulse generator 8C, the time delay can be easily controlled by an externally supplied clock signal.

[0112] Figure 21 The circuit diagram describes the fourth example of a pulse generator. Figure 21 The pulse generator 8D includes transistors 40, 41, 42, and 43, an inverter 33, and a capacitor C1. Transistors 40 and 41 are P-MOS transistors. Transistors 42 and 43 are N-MOS transistors.

[0113] First, the connections between the components of pulse generator 8D are explained. The sources of transistors 40 and 41 are both connected to the power supply potential Vdd. The gates of transistors 40 and 41 are both connected to terminal Vbp. Furthermore, the drain of transistor 40 is connected to the drain of transistor 41 via signal line s1. The drain of transistor 41 is connected to the drain of transistor 43 via signal line s2. Inverter 33 is connected between signal line S1 and signal line INI. That is, the output terminal of pulse generator 8D is connected to signal line INI. Capacitor C1 is connected between signal lines s1 and s2. Furthermore, the gate of transistor 43 is connected to signal line s1. Signal line Pout is connected to the gate of transistor 42. That is, the input terminal of pulse generator 8D is connected to signal line Pout. For example, signal line Pout is connected to the output terminal of inverter 30. The sources of transistors 42 and 43 are both connected to ground potential.

[0114] The operation of pulse generator 8D will now be explained. Transistors 40 and 41 operate as current sources under the control of the voltage applied to terminal Vbp. Therefore, the current sources cause current to flow through signal lines s1 and s2, thereby charging capacitor C1 corresponding to the feedback capacitor. Transistors 42 and 43 constitute a two-stage amplifier circuit with its source grounded. If the amplification factor of the two-stage amplifier circuit is A, the result is equal to (1+A) times the electrostatic capacitance of capacitor C1 caused by the mirror effect. As a result, even if a capacitor with a small electrostatic capacitance is used as capacitor C1, a large time delay can be obtained. Using pulse generator 8D can reduce the area where capacitor C1 is mounted. Furthermore, by controlling the voltage applied to terminal Vbq, the delay time from the input of a low-level pulse to signal line Vout to the output of a high signal to signal line INI can be adjusted. For example, the control circuit 150 described above can control the voltage applied to terminal Vbp.

[0115] The sensing device according to this disclosure may have an output stage integrated with a pulse generator. Figure 22 In the circuit described below, the pulse generator is integrated with the output stage of the sensing device.

[0116] Figure 22 An exemplary sensing device in the sixth variant is depicted. (With) Figure 12 Compared to circuit 102 in the middle, Figure 22 The circuit 106 described above has a different configuration between signal line Vi3 and signal line Vout. The differences between circuit 106 and circuit 102 described above will be explained in detail below.

[0117] In circuit 106, pulse generator 8E is connected between signal line Vi3 and signal line Vout. Pulse generator 8E includes inverters 34 and 35, delay device D3, NAND circuit NP, and NOR circuit NS. Inverters 34 and 35 are connected in series between signal line Vi3 and signal line Vout. Furthermore, delay device D3 is connected between signal line Vout and one input terminal of NAND circuit NP. Terminal DET_EN is connected to another input terminal of NAND circuit NP. The output terminal of NAND circuit NP is connected to the gate of transistor 14 and one input terminal of NOR circuit NS. Note that the other input terminal of NOR circuit NS is connected to signal line Vout. The output terminal of NOR circuit NS is connected to the gates of transistors 11 and 12 via signal line FB.

[0118] Next, the operation of circuit 106 will be explained. It should be noted that... Figure 23 The graph in the figure depicts an exemplary voltage waveform of circuit 106. Figure 23 The graphs in the diagram show exemplary voltage waveforms on signal lines Vi1, Vi2, Vi3, Vout, terminal DET_EN, and signal line INI.

[0119] When the photodiode PD reacts with a photon, the current between the cathode and anode increases, thereby reducing the voltage of signal line Vi1. Consequently, the voltage of signal line Vi2, connected to signal line Vi1 via transistor 12, changes from high to low. When a low voltage is applied to the gate of transistor 13, the state between the source and drain of transistor 13 is turned on. As a result, the voltage of signal line Vi3 becomes high through the power supply potential Vdd. Then, inverter 35 outputs a high signal to signal line Vout. This allows circuit 106 to output a high-level (positive polarity) pulse from signal line Vout to downstream measurement circuit 7 when a photon is detected, such as... Figure 23 As shown. It should be noted that this disclosure does not limit the polarity of the pulses output from the sensing device of this disclosure to the downstream measurement circuit.

[0120] A high signal is input from signal line Vout to one input terminal of the NOR circuit NS. Next, the NOR circuit NS outputs a low voltage, causing the voltage on signal line FB to go low. As a result, a low voltage is applied to the gates of transistors 11 and 12. The source and drain of transistor 11 are turned on. On the other hand, the drain and source of transistor 12 are turned off. Signal line Vi2 is electrically disconnected from signal line Vi1, and the voltage is brought high by the power supply potential Vdd.

[0121] When the voltage on signal line Vout goes high, the voltage at one input terminal of the NAND circuit NP also goes high after a delay. As a result, the NAND circuit NP outputs a high voltage unless a high voltage is applied to terminal DET_EN. This high voltage is applied to the gate of transistor 14, thus turning on the state between the drain and source. As a result, signal line Vi3 is reset to ground potential to carry a low voltage. At this time, inverter 35 outputs a low voltage to signal line Vout.

[0122] As a result, the voltage at one input terminal of the NOR circuit NS becomes low. Furthermore, when a low voltage is applied to terminal DET_EN, the voltage at the other input terminal of the NOR circuit NS also becomes low after a delay. Because both input terminals of the NOR circuit NS have low voltages, the NOR circuit NS outputs a high voltage. By making the voltage of signal line FB high, a high voltage is applied to the gates of transistors 11 and 12. Therefore, this cuts off the state between the source and drain of transistor 11. Moreover, the state between the drain and source of transistor 12 is turned on. Because electrical conduction is established between signal lines Vi1 and Vi2, photons can now be detected.

[0123] In circuit 106, when the signal passes twice through the loop formed by inverters 34 and 35, delay device D3, NAND circuit NP, and transistor 14, the circuit reset operation is completed after photon detection. That is, delay device D3 provides a time delay corresponding to two delay devices as a single delay device. The pulse generator 8E with circuit 106 installed does not need to use multiple delay devices, such as... Figure 16 The pulse generator 8A in the example. This allows for a reduction in circuit mounting area.

[0124] The sensing device according to this disclosure may include a photodetector, a seventh transistor of a second conductivity type, an eighth transistor of a first conductivity type, a ninth transistor of a first conductivity type, a tenth transistor of a second conductivity type, a sixth inverter, a seventh inverter, a third delay device, a NOR circuit, and a NAND circuit. The photodetector is connected between the photodetector and a first reference potential. The seventh transistor conducts the state between the photodetector and the sixth signal line according to the voltage of the fifth signal line. The eighth transistor conducts the state between the first reference potential and the seventh transistor according to the voltage of the fifth signal line. The ninth transistor conducts the state between the first reference potential and the seventh signal line according to the voltage of the sixth signal line. The tenth transistor conducts the state between the seventh signal line and the second reference potential according to the voltage of the eighth signal line. The sixth inverter is connected to the seventh signal line. The seventh inverter is connected between the sixth inverter and the ninth signal line. The third delay device is connected to the ninth signal line. The NOR circuit is configured to output the result of a NOR operation on the voltage from the third delay device and the voltage of the tenth signal line to the eighth signal line. The NAND circuit is configured to output the NAND operation result of the voltage of the ninth signal line and the voltage of the eighth signal line to the fifth signal line.

[0125] For example, a P-MOS transistor can be used as a transistor of a first conductivity type, and an N-MOS transistor can be used as a transistor of a second conductivity type. In this case, the power supply potential can be used as a first reference potential, and the ground potential can be used as a second reference potential. Alternatively, an N-MOS transistor can be used as a transistor of a first conductivity type, and a P-MOS transistor can also be used as a transistor of a second conductivity type. In this case, the ground potential can be used as a first reference potential, and the power supply potential can be used as a second reference potential.

[0126] Figure 22 Transistor 12 in the diagram is an example of the seventh transistor. Figure 22 The signal line FB in the example is the fifth signal line. Figure 22 Signal line Vi2 is an example of the sixth signal line. Transistor 11 is an example of the eighth transistor. Transistor 13 is an example of the ninth transistor. Figure 22 Signal line Vi3 is an example of the seventh signal line. Transistor 14 is an example of the tenth transistor. Figure 22 Signal line INI is an example of the eighth signal line. Inverter 34 is an example of the sixth inverter. Inverter 35 is an example of the seventh inverter. Figure 22 The signal line Vout in the example is the ninth signal line.

[0127] Figure 24 The circuit diagram depicts an exemplary sensing device in the seventh variant. Figure 24Circuit 107 has a reduced number of transistors. Circuit 107 includes a photodiode PD, a resistor R1, transistors 10, 15, 21, 23 and 24, an inverter 36, and a pulse generator 8F. The pulse generator D3 has a delay device D3 and a NAND circuit NP as its constituent elements. Transistors 10, 15, 21 and 23 are P-MOS transistors. On the other hand, transistor 24 is an N-MOS transistor. Transistor 10 corresponds to the load element of the photodiode PD. Transistor 10 can be replaced by a resistor as the load element.

[0128] First, the structure of circuit 107 will be explained. The sources of transistors 10 and 21 are connected to the power supply potential Vdd. The drain of transistor 10 is connected to the gate of transistor 23 via signal line Vi1. Additionally, the drain of transistor 10 is also connected to the source of transistor 15. Resistor R1 is connected between the drain of transistor 15 and the cathode of photodiode PD. Voltage Van is applied to the anode of photodiode PD. The value of voltage Vn can be determined by applying a reverse voltage equal to or higher than the breakdown voltage between the cathode and anode of photodiode PD (i.e., between the terminals).

[0129] The source of transistor 23 is connected to the drain of transistor 21. Conversely, the drain of transistor 23 is connected to inverter 36 via signal line Vi3. Furthermore, the drain of transistor 23 is also connected to the drain of transistor 24. The source of transistor 24 is connected to ground. The gate of transistor 24 is connected to the output terminal of NAND circuit NP and the gate of transistor 21. The output terminal of inverter 36 is connected to signal line Vout. Delay device D3 is connected between signal line Vout and one input terminal of NAND circuit NP. The other input terminal of NAND circuit NP is connected to terminal xRST.

[0130] Next, the operation of circuit 107 will be explained. When the photodiode PD reacts with a photon, the current between the cathode and anode increases, thereby reducing the voltage between the source and drain of transistor 10. Consequently, the voltage on signal line Vi1 (i.e., the signal line between photodiode PD and transistor 10) becomes low. As a result, a low voltage is applied to the gate of transistor 23, turning on the state between the source and drain of transistor 23. This, in turn, increases the current flowing between the source and drain of transistor 21. Therefore, the voltage between the gate and source of transistor 21 increases according to the Id-Vgs characteristic.

[0131] That is, approximately simultaneously with the state between the source and drain of transistor 23 being turned on, the state between the gate and source of transistor 21 is also turned on. Because both transistors 21 and 23 are turned on, the voltage of signal line Vi3 becomes high through the power supply potential Vdd. Upon receiving a high voltage input, inverter 36 outputs a low voltage to signal line Vout. Thus, when a photon is detected, circuit 107 outputs a low-level (negative polarity) pulse from signal line Vout to downstream measurement circuit 7. It should be noted that this disclosure does not limit the polarity of the pulse output from the sensing device of this disclosure.

[0132] When the voltage on signal line Vout goes low, the voltage at one input terminal of the NAND circuit NP also goes low after a delay. Therefore, the NAND circuit NP outputs a high voltage to signal line INI. This high voltage is applied to the gate of transistor 24, thus turning on the state between the drain and source of transistor 24. Furthermore, the state between the drain and source of transistor 21 is also turned off, preventing current from flowing from the power supply to ground. Therefore, the voltage on signal line Vi3 (i.e., the signal line between transistors 23 and 34) is initialized to low by ground potential. When the voltage on signal line Vi3 goes low, inverter 36 outputs a high voltage to signal line Vout. This causes circuit 108 to stop outputting low-level pulses.

[0133] It is important to note that Figure 24 The configuration of pulse generator 8F in the above circuit diagram is merely an example. Different configurations of pulse generators can be used alternatively. For example, pulse generator 8F can be configured in each of the circuit diagrams described above (…). Figure 16 , Figure 18 , Figure 19 , Figure 21 and Figure 22 The pulse generator depicted in [the diagram] can be replaced. Alternatively, the pulse generator 8F can be omitted, and the external control circuit 150 can be connected to the signal line INI. In this case, the external control circuit can generate a high-level pulse in response to the output signal from one or more sensing devices. Note that in circuit 107, at least one of transistor 15 or resistor R1 can be omitted.

[0134] Figure 25 The circuit diagram depicts an exemplary sensing device in the eighth variant. Figure 25Circuit 108 corresponds to circuit 107, which omits transistor 15, resistor R1, and pulse generator 8F. The signal line INIT in circuit 108 is connected, for example, to an external control circuit 150. The external control circuit 150 generates a reset pulse instead of the pulse generator 8. With the configuration of circuit 108, it is not necessary to prepare a pulse generator for each pixel (photodiode), thus allowing multiple pixels to share the control circuit 150. The control circuit 150 does not need to provide pulses to each of the connected pixels. For example, when a photon is detected by at least one of the pixels (sensing devices) connected to the measurement circuit 7, the control circuit 150 outputs a pulse to the signal line INIT of the photon-detecting pixel. When multiple pixels share the control circuit 150 (i.e., when multiple detection units share an initialization unit), the overall circuit can be miniaturized. The remaining configuration of circuit 108 is similar to that of circuit 107. The basic operation of circuit 108 is similar to that of circuit 107 described above, except that a reset pulse is generated by the control circuit 150.

[0135] The sensing device according to this disclosure may include a photodetector, a load element, a first transistor of a first conductivity type, a second transistor of a first conductivity type, a third transistor of a second conductivity type, and a first inverter. The load element is connected between the photodetector and a first reference potential. The first transistor conducts according to the voltage of a first signal line between the photodetector and the load element. The second transistor conducts according to the current of the first transistor or the voltage of the second signal line, indicating the state between the first reference potential and the first transistor. The third transistor conducts according to the voltage of the second signal line, indicating the state between the first transistor and the second reference potential. The first inverter is connected between a third signal line (between the first and third transistors) and a fourth signal line.

[0136] For example, a P-MOS transistor can be used as a transistor of a first conductivity type, and an N-MOS transistor can be used as a transistor of a second conductivity type. In this case, the power supply potential can be used as a first reference voltage, and the ground potential can be used as a second reference potential. Alternatively, an N-MOS transistor can be used as a transistor of the first conductivity type, and a P-MOS transistor can also be used as a transistor of the second conductivity type. In this case, the ground potential can be used as the first reference potential, and the power supply potential can be used as the second reference potential.

[0137] Figure 24 and Figure 25 Transistor 10 is an example of a load element. It should be noted that passive components such as resistors can be used as load elements. Transistor 23 is an example of a first transistor. Transistor 21 is an example of a second transistor. Transistor 24 is an example of a third transistor. Figure 24 and Figure 25Signal line INI is an example of the second signal line. Furthermore, signal line Vi3 is an example of the third signal line. Signal line Vout is an example of the fourth signal line. For example, an avalanche photodiode can be used as a photodetector.

[0138] Furthermore, the sensing device according to this disclosure may further include a pulse generator configured to output pulses to the second signal line based on the voltage of the fourth signal line. Alternatively, the pulse generator may be configured to output pulses to the second signal line after a time delay in response to a change in the voltage level on the fourth signal line. The sensing device may further include: a first resistor connected between the load element and the photodetector; and a fourth transistor of a first conductivity type connected in series with the first resistor. Figure 24 Transistor 15 is an example of the fourth transistor. Furthermore, resistor R1 is an example of the first resistor.

[0139] In addition, such as in Figure 16 In one example, the pulse generator may include a first delay device, a second delay device connected in series with the first delay device, an AND circuit connected to the downstream side of the second delay device, and a third inverter connected between the first delay device and the AND circuit. Figure 16 Delay device D1 is an example of a first delay device. Delay device D2 is an example of a second delay device. Inverter 31 is an example of a third inverter. In this case, the first delay device can be connected to the fourth signal line, and the downstream side of the AND circuit can be connected to the second signal line. Here, Figure 24 and Figure 25 The signal line Vout in the example is an example of the fourth signal line. Furthermore, the signal line INI is an example of the second signal line. Additionally, as in... Figure 18 In the example, the pulse generator may include an inverter chain.

[0140] Moreover, such as Figure 19 In one example, the pulse generator may include a flip-flop and a fourth inverter connected to the Q terminal of the flip-flop. In this case, the D terminal of the flip-flop may be connected to a fourth signal line, and the output of the fourth inverter may be connected to a second signal line.

[0141] In addition, such as in Figure 21 In the example, the pulse generator may include a two-stage amplifier circuit with its source grounded, a first current source, a second current source, a capacitor, and a fifth inverter. Here, the first current source is connected to the first stage of the two-stage amplifier circuit. The second current source is connected to the second stage of the two-stage amplifier circuit. The capacitor provides the connection between the first and second stages of the two-stage amplifier circuit. The fifth inverter is connected to the first stage of the two-stage amplifier circuit. Figure 21Transistors 42 and 43 form an example of a two-stage amplifier circuit with its source grounded. Transistor 40 is an example of a first current source. Transistor 41 is an example of a second current source. In this case, the input terminals of the two-stage amplifier circuit can be connected to the fourth signal line, and the output terminal of the fifth inverter can be connected to the second signal line.

[0142] Figure 26 The circuit diagram depicts an exemplary sensing device in the ninth variant. Figure 26 Circuit 109 corresponds to circuit 107 without transistor 15 and resistor R1, but supplemented with inverter 37. The input terminal of inverter 37 is connected to the output terminal of NAND circuit NP via signal line INI. Additionally, the gate of transistor 10 is connected to the output terminal of inverter 37 in place of terminal Vbq. The remaining configuration of circuit 109 is similar to that of circuit 107.

[0143] In circuit 109, similar to circuit 107, the photodiode PD reacts with photons, resulting in a low voltage on signal line Vi1, a high voltage on signal line Vi3, and a low voltage on signal line Vout (a low-level pulse is output to signal line Vout). At this time, the NAND circuit NP outputs a high voltage to signal line INI. In this situation, inverter 37 applies a low voltage to the gate of transistor 10 to output a low voltage. This turns the source and drain of transistor 10 on. As a result, the potential of signal line Vi1 and the cathode of photodiode PD become high through the power supply potential Vdd. Consequently, the voltage between the terminals of photodiode PD drops to the breakdown voltage, stopping the avalanche phenomenon (i.e., quenching photodiode PD).

[0144] Furthermore, when the voltage of signal line INI is high, a high voltage is applied to the gates of transistors 21 and 24. This cuts off the drain-source connection of transistor 21 and turns the drain-source connection of transistor 24 on. As a result, the voltage of signal line Vi3 is initialized low by ground potential. When the voltage of signal line Vi3 becomes low, inverter 36 outputs a high voltage to signal line Vout. This causes the voltage at one input terminal of the NAND circuit NP to become high after a delay of delay device D3. Furthermore, when a high voltage is applied to terminal xRST, the NAND circuit NP outputs a low voltage to signal line INI. At this time, after inversion by inverter 37, a high voltage is applied to the gate of transistor 10. Because the state between the source and drain of transistor 10 is cut off, signal line Vi1 is disconnected from the power supply potential Vdd. Since the voltage between the terminals of photodiode PD becomes equal to or higher than the breakdown voltage, circuit 100 is ready to detect photons again.

[0145] Similar to circuit 109, pulse-driven active quenching can be performed using transistor 10. Circuit 109 allows for high-speed quenching within a short time. Furthermore, since the resistor or current source transistor is not connected in series with the photodiode PD in circuit 109, the photodiode PD can respond at high speed. Alternatively, as with circuit 107 described above, transistor 10 can also be used as a current source for passive quenching. Furthermore, output quenching circuits or high-Z quenching circuits can be used in combination. The sensing device according to the invention can employ any type of quenching method. Alternatively, it can be configured to adjust the high and low voltage levels output from inverter 37 according to the characteristics of the photodiode PD. For example, the high voltage level can be set to Vbq, and the low voltage level can be set to 0V.

[0146] The sensing device according to this disclosure may further include a second inverter connected to a second signal line. In this case, the load element is a fifth transistor of a first conductivity type, which is turned on according to the output voltage from the second inverter. Figure 26 Signal line INI is an example of a second signal line. Inverter 37 is an example of a second inverter. Transistor 10 is an example of a fifth transistor.

[0147] Figure 27 The circuit diagram depicts an exemplary sensing device in the tenth variant. Figure 27 Circuit 110 in the diagram corresponds to circuit 109 supplemented with transistor 25. It should be noted that, for simplicity, in... Figure 27 Inverter 37 is omitted. Transistor 25 is an N-MOS transistor. The gate of transistor 10 is connected to the output terminal of the NAND circuit NP via signal line INI. The gate of transistor 25 is also connected to the output terminal of the NAND circuit NP via signal line INI. Furthermore, the drain of transistor 25 is connected to signal line Vi1. The source of transistor 25 is connected to ground. The remaining configuration of circuit 110 is similar to that of circuit 109.

[0148] In circuit 110, similar to circuits 107 and 109, the photodiode PD reacts with photons, resulting in a low voltage on signal line Vil, a high voltage on signal line Vi3, and a low voltage on signal line Vout (a low-level pulse is output to signal line Vout). At this time, the NAND circuit NP outputs a high voltage to signal line INI. As a result, a high voltage is applied to the gate of transistor 25, thereby turning on the state between the drain and source of transistor 25. Therefore, the cathode of the photodiode PD is connected to ground potential, which prevents avalanche phenomena. As described above, circuit 110 is a circuit that performs active quenching.

[0149] Furthermore, in circuit 110, conduction occurs between the drain and source of transistor 24, causing the voltage of signal line Vi3 to go low and the voltage of signal line Vout to go high. When a high voltage is applied to terminal xRST, after the delay of delay device D3, the voltage of one input terminal of NAND circuit NP goes high, causing NAND circuit NP to output a low voltage to signal line INI. Since a low voltage is applied to the gate of transistor 10, conduction occurs between the source and drain of transistor 10. As a result, the potential of the cathode of photodiode PD is raised by the power supply potential Vdd. Furthermore, because the inter-terminal voltage of photodiode PD becomes equal to or higher than the breakdown voltage, circuit 110 is once again ready to detect photons.

[0150] In circuit 110, when a signal corresponding to a photon is output from signal line Vout, the cathode of photodiode PD is connected to ground potential. This allows for high-speed quenching. Since transistor 10 is also pulse-driven, the cathode voltage of photodiode PD rises much faster than when using a current-source transistor.

[0151] The sensing device according to this disclosure may further include a sixth transistor of a second conductivity type, which conducts a state between a second reference potential and the second signal line according to the voltage of the second signal line. In this case, the load element is a fifth transistor of a first conductivity type that is turned on according to the voltage of the second signal line. Figure 27 Signal line INI is an example of the second signal line. Ground potential is an example of the second reference potential. Transistor 25 is an example of the sixth transistor. Furthermore, transistor 10 is an example of the fifth transistor.

[0152] Figure 28 The perspective view shows an example of how to install a sensing device using a Cu-Cu connection. Figure 28 Substrates 51 and 52 are shown; for example, substrates 51 and 52 are silicon substrates. It should be noted that the materials of substrates 51 and 52 are not limited. A plurality of pixels 510 are formed on substrate 51. Each pixel 510 contains a photodiode PD (e.g., a SPAD). The surface of the photodiode PD in pixel 510 is at least partially open, allowing the photodiode PD to react with incident photons. On substrate 52, a circuit block 520 is formed corresponding to each pixel 510. The circuit block 520 includes, for example, components corresponding to... Figure 1 The circuitry of the detection unit 9 or 9A (e.g., circuits 100 to 110 discussed above). The pixel 510 on the substrate 51 and the circuit block 520 on the substrate 52 are electrically connected to each other via Cu-Cu connections (copper-to-copper connections). Using Cu-Cu connections allows for miniaturization of the sensing device and reduces production costs.

[0153] In pixel 510, only a photodiode PD can be formed. This maximizes the area of ​​the photodiode PD. Alternatively, other components besides the photodiode PD can be formed in pixel 510. For example, a resistor R1 or a transistor 15 can be formed in pixel 510. In this case, the area of ​​circuit block 520 can be reduced or the functions implemented by circuit block 520 can be increased. Furthermore, since the signal amplitude on the Cu-Cu connection is limited, power consumption can be reduced. The allocation of components to pixel 510 and circuit block 520 can be adjusted according to the required application. It should be noted that although... Figure 28 This example illustrates mounting the sensing device using a Cu-Cu connection, but this method is merely one instance. Another example is mounting the sensing device using through-silicon vias (TSVs), etc. In other words, there are no limitations on the mounting method for the sensing device. Although... Figure 28 The examples in the text have a two-layer substrate structure, but there is no limit to the number of substrates that can be configured.

[0154] In the sensing device according to the present disclosure, a first substrate on which a photodetector is mounted can be electrically connected via a Cu-Cu connection to a second substrate on which other components are mounted.

[0155] Figure 29 The circuit diagram illustrates an exemplary circuit supporting dToF-based distance measurement. Figure 29 In this circuit, multiple circuits 109 are connected to the downstream measurement circuit 7 via circuit TR1. Circuit TR1 performs an OR operation on the output signals from the multiple circuits 109 (i.e., the voltage signals from the signal line Vout). This allows the measurement circuit 7 to count the number of output pulses. Based on the time correlation between the pulses, the measurement circuit 7 can determine whether the reflected light rl of the light em emitted from the light source 91 is detected. If it is determined that the reflected light rl should be detected, the distance from the sensing device to the object 80 can be calculated based on the time of flight as described above.

[0156] Figure 30 An exemplary circuit including a counter and a TDC is schematically shown. Figure 30 An example of the above-described measurement circuit 7 is shown. Figure 30Circuit 200 includes circuit block 54, multiple buffers 55, circuit TR2, AND circuit P2, trigger circuit 56, logic circuit P3, flip-flop F2, and multiple flip-flops 57. Circuit block 54 corresponds to multiple sensing devices (e.g., circuits 100 to 110 discussed above). Multiple buffers 55 digitize signals output from individual sensing devices. Circuit TR2 is a circuit in which OR circuits are connected in a tree structure, and circuit TR2 performs an OR operation on the signals output from multiple buffers 55. AND circuit P2 performs an AND operation on the signal input from signal line CTR1 and the output signal from circuit TR2, and inputs the result of the AND operation to trigger circuit 56. Alternatively, circuit TR2 can be a circuit that performs an EXOR operation instead of an OR operation. This allows for the counting of simultaneously detected photons at two timings (i.e., at the falling and rising edges of the signal waveform).

[0157] The trigger circuit 56 is configured to output a trigger signal to the TDC 58 when a pulse with a time correlation exceeding a threshold is detected within a specified period. It should be noted that digital control signals are supplied to signal lines CTR1, CTR2, and CTR3. The TDC 58 provides information about the measured time difference TDC_cnt to downstream circuitry. Multiple triggers 57 are interconnected. These triggers 57 supply downstream circuitry with a "count" of the number of photons detected within a predetermined time period. It should be noted that circuit 200 is merely an example of a measurement circuit. Measurement circuits with different configurations can be connected to a sensing device.

[0158] like Figure 1 , Figure 2 , Figure 13 , Figure 25 , Figure 29 as well as Figure 30 As shown, the ranging device according to this disclosure may include a light source, multiple sensing devices, logic circuitry, and a measuring circuit. The logic circuitry is configured to output the result of an OR operation on the output voltages from the multiple sensing devices. The measuring circuitry is configured to measure the distance to an object based on the timing of light emitted from the light source and the signal output from the logic circuitry. Here, Figure 29 The circuit TR1 and Figure 30 The circuits TR2 in the diagram are all examples of logic circuits. In measurement circuit 7 and... Figure 20 In circuit 200, the components downstream of circuit TR2 constitute an example of a measurement circuit.

[0159] In addition, such as Figure 25As shown, the ranging device according to this disclosure may include control circuitry connected to a second signal line of a plurality of sensing devices. The control circuitry is configured to output pulses to the second signal line based on signals input to the measuring circuitry from a fourth signal line of at least any one of the sensing devices.

[0160] In the sensing device and ranging apparatus according to this disclosure, the voltage in the circuit is reset after the photodiode PD reacts with a photon each time a pulse is generated. This allows for the detection of subsequent photons within a short time period. Therefore, the sensing device and ranging apparatus according to this disclosure allow for the detection of photons with monotonically increasing characteristics, even in high-illuminance environments. The sensing device and ranging apparatus according to this disclosure support a wide dynamic range of brightness. This allows for high-precision measurement of the distance to an object regardless of the illumination environment. Furthermore, the sensing device and ranging apparatus according to this disclosure allow for the output of pulses of constant width to downstream circuits, regardless of the length of the recharge time. A configuration that allows adjustment of the time delay for generating the reset pulse and the width of the pulse output to the downstream circuits can also be employed. In this case, the pulse output timing and pulse width can be adjusted in accordance with the measurement circuit in use.

[0161] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology of the present invention can be implemented as a device to be installed on a mobile body, such as any type of automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, and robot.

[0162] Figure 31 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of the present disclosure can be applied.

[0163] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 31 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as examples of the functional structure of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0164] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate braking force for the vehicle.

[0165] The body system control unit 12020 controls the operation of various devices supplied to the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0166] The exterior information detection unit 12030 detects information outside the vehicle, including information from the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives those images. Furthermore, the exterior information detection unit 12030 can also perform processing based on the received images, such as detecting people, vehicles, obstacles, signs, text on the road surface, etc., or detecting their distances.

[0167] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0168] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0169] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to realize functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0170] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about the outside or inside of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive autonomously without relying on the driver's operation.

[0171] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the outside of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam, for example, based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030, to perform cooperative control aimed at preventing glare.

[0172] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 31 In this example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0173] Figure 32 This is a schematic diagram illustrating an example of the mounting position of the imaging unit 12031.

[0174] exist Figure 32 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are imaging units 12031.

[0175] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, installed on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper part of the windshield inside the vehicle. Imaging unit 12101 installed on the front nose inside the vehicle and imaging unit 12105 installed on the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 installed on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 installed on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. The front images acquired by imaging units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0176] Incidentally, Figure 32 Examples of the imaging ranges of imaging units 12101 to 12104 are described. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0177] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0178] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time variation of that distance (relative speed to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead. This nearest three-dimensional object specifically exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset a following distance to stay ahead of the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, cooperative control for autonomous driving can be executed, enabling the vehicle to drive autonomously without relying on driver operation.

[0179] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0180] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon representing the pedestrian is displayed at a desired location.

[0181] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been explained above. The technology of this disclosure can be advantageously applied, for example, to the imaging unit 12031 described above. Specifically, the ranging device 90 (i.e., the circuits 100 to 109 described above) having the aforementioned detection device and the light source 91 can be mounted together in the imaging unit 12031. Applying the technology of this disclosure to the imaging unit 12031 enables accurate distance information to be obtained in environments with a wide dynamic range of brightness, thereby enhancing the functionality and safety of the vehicle 12100.

[0182] This disclosure can preferably be implemented in the following configuration: (1) A sensing device, comprising: Photodetector; A load element, wherein the load element is connected between the photodetector and the first reference potential; A first transistor of a first conductivity type is configured to conduct according to the voltage of a first signal line between the photodetector and the load element; The second transistor of the first conductivity type is configured to conduct between the first reference potential and the first transistor according to the current of the first transistor or the voltage of the second signal line; The third transistor of the second conductivity type is configured to conduct the state between the first transistor and the second reference potential according to the voltage of the second signal line; and A first inverter is connected between a third signal line and a fourth signal line, wherein the third signal line is located between the first transistor and the third transistor. (2)

[0184] The sensing device as described in paragraph (1) above further includes: A pulse generator is configured to output pulses to the second signal line based on the voltage of the fourth signal line. (3)

[0186] The sensing device described in paragraph (2) above, wherein

[0187] The pulse generator is configured such that when the voltage level on the fourth signal line changes, the pulse generator outputs a pulse to the second signal line after a time delay. (4)

[0189] The sensing device as described in any of paragraphs (1) to (3) above further includes: A first resistor is connected between the load element and the photodetector; and The fourth transistor of the first conductivity type is connected in series with the first resistor. (5)

[0191] The sensing device as described in any of paragraphs (1) to (4) above further includes: The second inverter is connected to the second signal line, wherein... The load element is the fifth transistor of the first conductivity type, and The fifth transistor is configured to turn on according to the output voltage from the second inverter. (6)

[0193] The sensing device as described in any of paragraphs (1) to (4) above further includes: The sixth transistor of the second conductivity type is configured to conduct the state between the second reference potential and the second signal line according to the voltage of the second signal line, wherein The load element is a fifth transistor of a first conductivity type configured to conduct according to the voltage of the second signal line. (7)

[0195] The sensing device as described in paragraph (2) or (3) above, wherein

[0196] The pulse generator includes: a first delay device; a second delay device connected in series with the first delay device; an AND circuit connected to the downstream side of the second delay device; and a third inverter connected between the first delay device and the AND circuit. The first delay device is connected to the fourth signal line, and the downstream side of the AND circuit is connected to the second signal line. (8)

[0198] The sensing device as described in paragraph (2) or (3) above, wherein

[0199] The pulse generator includes an inverter chain. (9)

[0201] The sensing device as described in paragraph (2) or (3) above, wherein

[0202] The pulse generator includes a trigger and a fourth inverter connected to the Q terminal of the trigger. The trigger has a D terminal connected to the fourth signal line, and the fourth inverter has an output side connected to the second signal line. (10)

[0204] The sensing device as described in paragraph (2) or (3) above, wherein

[0205] The pulse generator includes: a two-stage amplifier circuit with its source grounded; a first current source connected to the first stage of the two-stage amplifier circuit; a second current source connected to the second stage of the two-stage amplifier circuit; a capacitor connected between the first stage and the second stage of the two-stage amplifier circuit; and a fifth inverter connected to the first stage of the two-stage amplifier circuit. The input terminals of the two-stage amplifier circuit are connected to the fourth signal line, and the output terminal of the fifth inverter is connected to the second signal line. (11)

[0207] The sensing device described in any of paragraphs (1) to (10) above, wherein

[0208] The photodetector is mounted on a first substrate that is electrically connected to a second substrate on which other components are mounted via a Cu-Cu connection. (12)

[0210] The sensing device described in any of paragraphs (1) to (10) above, wherein

[0211] The photodetector includes an avalanche photodiode. (13)

[0213] A ranging device having a plurality of sensing devices as described in any one of paragraphs (1) to (12) above, the ranging device comprising: light source; Logic circuitry, configured to output the result of an OR operation on the output voltages from the plurality of sensing devices; and The measurement circuit is configured to measure the distance to the object based on the timing of light emitted from the light source and the signal output from the logic circuit. (14)

[0215] The ranging device as described in paragraph (13) above further includes: The control circuit is connected to the second signal line of the plurality of sensing devices, wherein The control circuit is configured to output pulses to the second signal line based on signals input to the measurement circuit from the fourth signal line of at least one of the sensing devices. (15)

[0217] A sensing device, comprising: Photodetector; A load element, wherein the load element is connected between the photodetector and the first reference potential; The seventh transistor of the second conductivity type is configured to conduct the state between the photodetector and the sixth signal line according to the voltage of the fifth signal line; The eighth transistor of the first conductivity type is configured to conduct the state between the first reference potential and the seventh transistor according to the voltage of the fifth signal line; The ninth transistor of the first conductivity type is configured to conduct the state between the first reference potential and the seventh signal line according to the voltage of the sixth signal line; The tenth transistor of the second conductivity type is configured to conduct the state between the seventh signal line and the second reference potential according to the voltage of the eighth signal line; and The sixth inverter is connected between the seventh and ninth signal lines, wherein... The fifth signal line is connected to the ninth signal line. (16)

[0219] The sensing device as described in paragraph (15) above further includes: A pulse generator is configured to output pulses to the eighth signal line based on the voltage of the ninth signal line. (17)

[0221] The sensing device as described in paragraph (15) or (16) above further includes: A first resistor is connected between the load element and the photodetector; and The fourth transistor of the first conductivity type is connected in series with the first resistor. (18)

[0223] The sensing device as described in any one of paragraphs (15) to (17) above further includes: The eleventh transistor is configured to conduct the state between the first reference potential and the ninth transistor according to the voltage applied to the first control electrode. (19)

[0225] The sensing device as described in any one of paragraphs (15) to (18) above further includes: The twelfth transistor is configured to conduct the state between the seventh signal line and the tenth transistor according to the voltage applied to the second control electrode. (20)

[0227] A sensing device, comprising: Photodetector; A load element, wherein the load element is connected between the photodetector and the first reference potential; The seventh transistor of the second conductivity type is configured to conduct the state between the photodetector and the sixth signal line according to the voltage of the fifth signal line; The eighth transistor of the first conductivity type is configured to conduct the state between the first reference potential and the seventh transistor according to the voltage of the fifth signal line; The ninth transistor of the first conductivity type is configured to conduct the state between the first reference potential and the seventh signal line according to the voltage of the sixth signal line; The tenth transistor of the second conductivity type is configured to conduct the state between the seventh signal line and the second reference potential according to the voltage of the eighth signal line; The sixth inverter is connected to the seventh signal line; The seventh inverter is connected between the sixth inverter and the ninth signal line; A third delay device is connected to the ninth signal line; A NOR circuit is configured to output the result of a NOR operation on the output voltage from the third delay device and the voltage of the tenth signal line to the eighth signal line; and The NAND circuit is configured to output the result of the NAND operation to the fifth signal line at the voltages of the ninth signal line and the eighth signal line.

[0228] The embodiments disclosed herein are not limited to those discussed above and include various variations that may be conceived by those skilled in the art. Furthermore, the advantageous effects of the invention are not limited to those described above. That is, within the technical concept and scope of this disclosure as defined by the appended claims and their equivalents, the content disclosed above may be variably supplemented, modified, or partially deleted.

[0229] [List of Reference Symbols]

[0230] C1: Capacitor

[0231] D1, D2, D3: Delay devices

[0232] F1, F2: Triggers

[0233] NP: NAND circuit

[0234] NS: NOR circuit

[0235] P1, P2, P3: AND circuit

[0236] PD: Photodiode

[0237] R1: Resistor

[0238] 1, 1A, 1B: Sensing devices

[0239] 2, 2A: Switching Unit

[0240] 3. 3A: Initialization Section

[0241] 4. 4A: Enlarged section

[0242] 5. 5A: Detection Unit

[0243] 6: Quenching section

[0244] 7: Measurement Circuit

[0245] 8, 8A, 8B, 8C, 8D, 8E, 8F: Pulse generator

[0246] 9, 9A, 9B: Detection Unit

[0247] 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 23, 24, 25, 40, 41, 42, 43: Transistors

[0248] 30, 31, 32, 33, 34, 35, 36, 37: Inverters

[0249] 51, 52: Substrate

[0250] 53: Cu-Cu connection

[0251] 54, 520: Circuit blocks

[0252] 55: Buffer

[0253] 56: Trigger circuit

[0254] 57: Multiple triggers

[0255] 58: TDC

[0256] 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71: Curves

[0257] 80: Object

[0258] 90: Distance measuring equipment

[0259] 91: Light source

[0260] TR1, TR2, 50, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 200: Circuit

[0261] 150: Control Circuit

[0262] 300: Inverter Chain

[0263] 510: pixels.

Claims

1. A sensing device, comprising: Photodetector (PD); A first resistor (10) is connected between the photodetector (PD) and the first reference potential (Vdd); A second resistor (R1) is connected between the photodetector (PD) and the first resistor (10); A first transistor (23) of a first conductivity type, the gate of the first transistor (23) is connected to the first resistor (10) and the second resistor (R1) via a first signal line (Vi1) between the first resistor (10) and the second resistor (R1). The second transistor (21) of the first conductivity type is connected to the first reference potential (Vdd), the second terminal of the second transistor (21) is connected to the first terminal of the first transistor (23), and the gate of the second transistor (21) is connected to the second signal line (INI). A third transistor (24) of the second conductivity type, wherein the first terminal of the third transistor (24) is connected to the second terminal of the first transistor (23), and the second terminal of the third transistor (24) is connected to the second reference potential (GND); and The first inverter (36) is connected between the third signal line (Vi3) and the fourth signal line (Vout), wherein the third signal line (Vi3) is located between the first transistor (23) and the third transistor (24).

2. The sensing device according to claim 1, further comprising: A pulse generator (8F) is configured to output pulses to the second signal line (INI) based on the voltage of the fourth signal line (Vout).

3. The sensing device according to claim 2, wherein, The pulse generator (8F) is configured such that when the voltage level on the fourth signal line (Vout) changes, the pulse generator (8F) outputs a pulse to the second signal line (INI) after a time delay.

4. The sensing device according to claim 1, further comprising: The fourth transistor (15) of the first conductivity type is connected in series with the first resistor (10).

5. The sensing device according to claim 4, wherein, The fourth transistor (15) is a P-type transistor.

6. The sensing device according to claim 1, wherein, The photodetector (PD) includes an avalanche photodiode.

7. The sensing device according to claim 1, wherein, The first transistor (23) is configured to be turned on according to the first signal line (Vi1).

8. The sensing device according to claim 1, wherein, The second transistor (21) is configured to be turned on according to the first transistor (23), wherein the second transistor (21) is configured to be turned off according to the voltage of the second signal line (INI).

9. The sensing device according to claim 1, wherein, The third terminal of the third transistor (24) is connected to the gate of the second transistor (21) via the second signal line (INI), wherein the third transistor (24) is configured to be turned on according to the voltage of the second signal line (INI).

Images