Component organization system for achieving CNC numerical control function

Abstract

The invention relates to a component organization system for realizing a CNC numerical control function, which comprises an application layer, an HAL core layer, a hardware driving layer and a physical equipment layer, the application layer, the HAL core layer, the hardware driving layer and the physical equipment layer are connected and installed in sequence and communicate through a standardized interface, the application layer is used for running track planning and G code interpretation, and the HAL core layer is used for carrying out data processing. The HAL core layer is used for signal routing and component management and central coordination, and a plurality of specific hardware interfaces are packaged in the hardware driving layer. By the adoption of the component organization system for achieving the CNC numerical control function, the problem of hardware dependence is solved through a modularized architecture, system performance is guaranteed through a real-time scheduling mechanism, system integration is simplified through a signal routing mechanism, and the system is managed through configuration. And the maintainability is improved. The whole scheme has high flexibility and reliability, and can meet the strict requirements of the industrial control field on real-time performance, certainty and maintainability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of industrial automation, in particular to the field of time control system, and more particularly to a component organization system for realizing CNC numerical control function. BACKGROUND

[0002] Step 1: Hardware initialization configuration Load device driver through static configuration file (such as / etc / modules.conf). The execution condition is system startup, and it depends on specific hardware ID identification. The parameter I / O address is 0x378, the interrupt number is 7, and the DMA channel is 5.

[0003] Step 2: Control logic binding Directly call hardware operation function (such as write_parallel_port()) in application layer. The dependent relationship is that application code and hardware driver are strongly coupled. The parameter pulse frequency is 1 kHz, and the acceleration is 100 mm / s².

[0004] Step 3: Real-time task scheduling Use standard Linux scheduler (CFS) or simple polling mechanism. The execution condition is timer interrupt or busy waiting loop. The parameter sampling period is 10 ms, and the priority is normal process.

[0005] Step 4: Data exchange processing Transfer control data through global variable or shared memory. The dependent relationship is that there is a lack of standardized interface between modules. The parameter buffer size is 4 KB, and the timeout time is 100 ms.

[0006] The function mechanism is described as follows: The purpose of step 1 is to establish the basis of hardware communication and map physical devices to memory space. The purpose of step 2 is to realize the direct conversion of motion control algorithm to hardware. The purpose of step 3 is to provide a basic time slice round robin execution environment. The purpose of step 4 is to realize data sharing between different control modules.

[0007] Defect 1 is the lack of real-time performance. The existing technology adopts the standard scheduler implementation mode of step 3, which leads to uncontrollable response delay, the worst case delay can reach hundreds of milliseconds; poor determinacy, unable to guarantee strict time constraints; obvious jitter, greatly affected by system load, affecting processing precision.

[0008] Defect 2 is the complexity of system integration. The existing technology adopts the direct function call implementation mode of step 2, which leads to high module coupling degree, and the influence range of function modification is difficult to control; debugging is difficult, and problem positioning needs to go deep into multiple module interiors; limited scalability, and new functions need to modify the core architecture.

[0009] The original problem is that the Linux standard scheduler cannot meet the us-level response. The VCORE solution is user space real-time scheduling, deterministic thread scheduling (cycle accuracy ± 5us), supporting multi-priority real-time tasks, avoiding kernel / user state switching overhead.

[0010] The original problem is black box operation, and fault location requires an oscilloscope. The VCORE solution is a built-in visual debugging tool, VCOREscope real-time signal waveform display, and real-time monitoring of component status.

[0011] The original problem is that the new function needs to modify the core architecture, and the VCORE solution is a modular plug-in architecture. SUMMARY

[0012] The purpose of the present application is to overcome the above-mentioned shortcomings of the prior art, and to provide a component organization system for realizing CNC numerical control function with good real-time performance, high flexibility and good reliability.

[0013] In order to achieve the above-mentioned purpose, the component organization system for realizing CNC numerical control function of the present application is as follows: The component organization system for realizing CNC numerical control function, its main feature is that the system includes an application layer, a HAL core layer, a hardware driver layer and a physical device layer, the application layer, the HAL core layer, the hardware driver layer and the physical device layer are connected and installed in turn, and communicate through standardized interface, the application layer is used for running trajectory planning and G code interpretation, the HAL core layer is used for signal routing and component management, central coordination, the hardware driver layer is encapsulated with a plurality of specific hardware interfaces.

[0014] Preferably, the system further comprises a digital input interface, an analog interface and an encoder interface, the digital input interface directly accesses the hardware register through memory mapping, and performs IO operation through configuration of base address and bit mask, the analog interface is used for configuration management of ADC and DAC channel, and the encoder interface is used for acquisition of quadrature encoder counter.

[0015] Preferably, the HAL core layer includes a component manager, a signal router and a real-time scheduler, the component manager is connected with the application layer, the signal router is connected with the component manager, the real-time scheduler is connected with the component manager and the signal router, the component manager is used for realizing life cycle management of all functional components, the signal router is used for realizing data communication between components, and the real-time scheduler is used for guaranteeing the deterministic response of the system.

[0016] Preferably, when the system is started, the component manager parses the configuration file to determine the component loading order according to the dependency relationship; dynamically loads each component into the memory and allocates an independent resource space for each component; the component manager registers the pin and parameter interface provided by the component in the component initialization stage and establishes the static connection relationship between the components; in the running stage, the component manager monitors the health status of each component and automatically performs fault isolation and recovery operation if an abnormality is found.

[0017] Preferably, when the system establishes the signal connection, the signal router verifies the data type compatibility of the source pin and the target pin, creates a signal object and establishes a bidirectional connection relationship; in the data transmission process, the signal router adopts the write-once-copy mechanism; the signal router dynamically modifies the connection relationship of the connection topology graph in the running time.

[0018] Preferably, the system creates multiple real-time threads, configures different execution cycles and priority levels for each thread; the real-time scheduler adopts the priority inheritance algorithm to prevent priority inversion, binds the thread to a specific core through the CPU affinity setting and executes; in the execution control, a timer is used to trigger the periodic task and the component processing function is called in a preset order; the real-time scheduler monitors the task execution time in real time and performs degradation processing on the overdue task.

[0019] The component organization system for realizing the CNC numerical control function adopts the HAL technical scheme, solves the hardware dependency problem through the component architecture, guarantees the system performance through the real-time scheduling mechanism, simplifies the system integration through the signal routing mechanism, improves the maintainability through the configuration management system, has high flexibility and reliability and can meet the strict requirements of the industrial control field on real-time performance, determinacy and maintainability. The HAL technical scheme realizes significant technical breakthroughs in hardware compatibility, real-time performance and system reliability through the innovative software architecture. Compared with the traditional technology, not only the technical indicators are improved by orders of magnitude, but more importantly, the technical threshold is reduced, the digital transformation and upgrading of the entire manufacturing industry are promoted and the open source characteristics bring significant social benefits, providing a solid technical foundation for the development of intelligent manufacturing. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The system configuration bus schematic diagram of the component organization system for realizing the CNC numerical control function of the application is shown. Figure 2 The connection relationship schematic diagram of the component organization system for realizing the CNC numerical control function of the application is shown. DETAILED DESCRIPTION

[0021] In order to more clearly describe the technical content of the application, further description will be made in combination with specific embodiments.

[0022] The component organization system for realizing CNC numerical control function of the present application comprises an application layer, a HAL core layer, a hardware driver layer and a physical device layer, which are connected and installed in sequence and communicate through a standardized interface, the application layer is used for running trajectory planning and G code interpretation, the HAL core layer is used for signal routing and component management and central coordination, and the hardware driver layer is encapsulated with a plurality of specific hardware interfaces.

[0023] As a preferred embodiment of the present application, the system further comprises a digital input interface, an analog interface and an encoder interface, the digital input interface directly accesses hardware registers through memory mapping and performs IO operation by configuring a base address and a bit mask, the analog interface is used for configuring and managing ADC and DAC channels, and the encoder interface is used for collecting quadrature encoder counter.

[0024] As a preferred embodiment of the present application, the HAL core layer comprises a component manager, a signal router and a real-time scheduler, the component manager is connected with the application layer, the signal router is connected with the component manager, and the real-time scheduler is connected with the component manager and the signal router, the component manager is used for realizing life cycle management of all functional components, the signal router is used for realizing data communication between components, and the real-time scheduler is used for guaranteeing deterministic response of the system.

[0025] As a preferred embodiment of the present application, when the system is started, the component manager parses a configuration file, determines component loading sequence according to a dependency relationship, dynamically loads each component into memory, allocates an independent resource space for each component, registers pin and parameter interfaces provided by the component manager in a component initialization stage, establishes a static connection relationship between components, and monitors health status of each component in a running stage, and if an abnormality is found, automatically performs fault isolation and recovery operation.

[0026] As a preferred embodiment of the present application, when the system establishes signal connection, the signal router verifies data type compatibility of source pins and target pins, creates a signal object and establishes a bidirectional connection relationship, adopts a write-once copy mechanism in a data transmission process, and dynamically modifies a connection relationship of a connection topology graph in a running time.

[0027] As a preferred embodiment of the present application, the system creates multiple real-time threads, configures different execution cycles and priority levels for each thread; the real-time scheduler uses a priority inheritance algorithm to prevent priority inversion, binds the thread to a specific core and executes through CPU affinity setting; in execution control, a timer triggers periodic tasks, and the component processing function is called in a predetermined order; the real-time scheduler monitors the task execution time in real time, and performs downgrade processing on the overdue task.

[0028] I. System overall architecture description The VCORE technical solution takes a three-axis numerical control machine tool control system as an example, adopts a layered modular architecture, From top to bottom, it is divided into an application layer, a HAL core layer, a hardware driver layer and a physical device layer. The application layer includes G code interpreter, trajectory planner and human-machine interface control logic components, and runs trajectory planning and G code interpretation and other high-level control logic; the HAL core layer is composed of component manager, signal router and real-time scheduler, realizes hardware-independent signal routing and component management, and undertakes the central coordination function of the system; the hardware driver layer encapsulates specific hardware interfaces such as EtherCAT, parallel port, CAN bus, and encapsulates specific device operations; the bottom layer is the actual physical device layer, including servo motors, encoders, IO modules and other actual hardware. The layers communicate with each other through standardized interfaces, realizing the complete separation of control logic and hardware devices, ensuring the modularity and maintainability of the system.

[0029] II. Hardware interface implementation scheme In terms of hardware connection, VCORE designs a unified hardware interface circuit. The digital input interface directly accesses the hardware register through memory mapping, and the hardware register is accessed by the driver to configure the base address and bit mask to realize fast IO operation. In addition to base address mapping, the digital output interface also includes output polarity configuration function to adapt to the level requirements of different devices. The analog interface is specially designed to manage the configuration of ADC and DAC channels, while the encoder interface is responsible for the accurate acquisition of the quadrature encoder counter. This hardware abstraction design makes the upper layer application not need to care about the specific hardware details, but only need to access the device function through the standardized interface.

[0030] The digital output interface realizes the output polarity configuration function as follows: Suppose there is a digital output interface connected to the GPIO pin of the microcontroller, and the external circuit may include a driver such as a transistor or relay driver.

[0031] Step 1: Define the data structure of output polarity configuration In the driver layer, a configuration structure is defined for each output channel, which contains a field for setting the polarity.

[0032] Step 2: Apply the polarity configuration in the output function When a logic level needs to be output, adjust the actual output level according to the polarity configuration.

[0033] For example, assume there is a digital output channel, and define: Positive Polarity: External device is on when outputting high level.

[0034] Negative Polarity: External device is on when outputting low level.

[0035] In the driver, it can be handled as follows: Actual output level = Desired logic level XOR polarity configuration bit.

[0036] Where the polarity configuration bit can be defined as: 0 for positive polarity (no inversion), 1 for negative polarity (inversion).

[0037] Step 3: Provide a configuration interface Through the HAL layer or application layer interface, users can set the polarity of each output channel.

[0038] Step 4: Hardware connection Sometimes, the hardware design may have fixed polarity, for example, through inverter circuits. In this case, software configuration may need to match the hardware. If the hardware is configurable, for example, through jumpers, then software configuration may need to be synchronized with hardware settings.

[0039] III. Core software module workflow Component manager working process: The component manager is responsible for the life cycle management of all functional components. When the system starts, the component manager first parses the configuration file, determines the component loading order according to the dependency relationship. Then dynamically load each component into memory, allocate independent resource space for each component. The component initialization stage will register the pin and parameter interface it provides, and establish the static connection relationship between components. In the running stage, the component manager monitors the health status of each component, and automatically performs fault isolation and recovery operations when an exception is found.

[0040] Signal router data flow mechanism: Signal router implements data communication between components. When a signal connection is established, the router first verifies the data type compatibility of the source pin and the target pin, then creates a signal object and establishes a bidirectional connection relationship. During data transmission, the copy-on-write mechanism is used to avoid resource contention and ensure real-time performance. The router also maintains a complete connection topology graph, supporting dynamic modification of connection relationships at runtime without affecting the normal operation of other parts of the system.

[0041] Real-time scheduler execution control: The real-time scheduler ensures the deterministic response of the system. First, create multiple real-time threads, each with different execution periods and priority levels. The scheduler uses the priority inheritance algorithm to prevent priority inversion, and binds threads to specific cores for execution through CPU affinity settings. In terms of execution control, a high-precision timer is used to trigger periodic tasks, and component processing functions are called in strict accordance with the preset order. The scheduler also monitors task execution time in real time, and performs degradation processing on overdue tasks to ensure that critical tasks are completed on time.

[0042] Four, configuration management system implementation: VCORE defines a dedicated configuration description language (HDL) for describing system hardware connections and control logic. The configuration parser first performs lexical analysis and syntax analysis on the configuration file to generate an abstract syntax tree. Then perform semantic verification to check component dependency relationships and signal compatibility. In the configuration loading stage, components are initialized in topological order, and finally a complete signal connection network is established. The system supports configuration hot update function, allowing dynamic adjustment of parameters at runtime without restarting the entire system.

[0043] Five, fault tolerance processing mechanism The fault detection system ensures system reliability through multi-level monitoring. Hardware level monitors watchdog state and parity error; through program detection null pointer access and array out-of-bounds exception; performance level tracks task response time and resource usage. When a fault is detected, the system takes different recovery strategies according to the fault level: soft faults are solved by restarting the component; hard faults switch to backup components to continue running; critical faults enter a safe state and perform an emergency shutdown. All fault events are recorded in the log system for subsequent analysis.

[0044] Six, alternative technical solutions In addition to the main text configuration solution, VCORE also supports XML-based configuration formats, providing a more structured configuration management approach. In terms of system architecture, in addition to the single-machine deployment solution, it also supports distributed deployment mode, separating control nodes, IO nodes and monitoring nodes, and communicating through real-time Ethernet. This distributed architecture is particularly suitable for large and complex control systems, and can improve the scalability and reliability of the system.

[0045] In the specific embodiments of the present application, the embodiments are taken as an example of a three-axis numerical control machine tool control system, and the specific implementation of VCORE is described in detail.

[0046] I. Overall system implementation architecture The system adopts a layered architecture design, and is divided into an application control layer, a HAL abstraction layer, a hardware driver layer, and a physical device layer from top to bottom. The application control layer runs high-level control logic such as trajectory planning and G-code interpretation; the HAL abstraction layer implements hardware-independent signal routing and component management; the hardware driver layer encapsulates specific device operations; and the physical device layer includes servo motors, encoders, IO modules, and other actual hardware. The layers communicate through well-defined interfaces, ensuring the modularity and maintainability of the system.

[0047] II. Hardware connection implementation details As shown in Figure 1 In terms of hardware implementation, the system uses EtherCAT industrial Ethernet as the main communication bus. The industrial computer connects the EtherCAT master through PCIE, and the master hangs the LD31E / EX51A, servo driver, and other slave devices. The servo driver is powered by three-phase 220VAC, and is connected to the servo motor through the UVW three-phase interface. The encoder feedback uses differential signal transmission to ensure anti-interference. The LD31E / EX51A module provides 24VDC isolated input and output channels for connecting peripheral devices such as limit switches and emergency stop buttons. All hardware devices are connected through standard industrial connectors for quick plug-in connection.

[0048] III. Software system implementation steps System initialization process: When the system starts, it first executes the hardware detection program, automatically identifies the connected EtherCAT slave devices, and establishes a communication link. Then it loads the HAL runtime environment, and dynamically loads each functional component according to the predefined configuration file. During the component loading process, dependency checks are performed to ensure that components are initialized in the correct order. After completing the component loading, the system establishes a signal connection network, connects the input and output pins of each component according to the control logic. Finally, real-time task threads are created, and periodic scheduling execution is started.

[0049] Real-time control cycle implementation: The system creates three different cycle real-time threads: servo control thread (1 kHz), IO processing thread (500 Hz), and monitoring thread (100 Hz). The servo control thread is responsible for executing the position loop PID algorithm, reading encoder feedback values, calculating control output, and sending it to the servo driver. The IO processing thread scans digital input states, updates output signals, and processes emergency stop and safety interlock logic. The monitoring thread collects system operation data, performs fault detection, and updates human-machine interface displays. Each thread uses a priority scheduling strategy to ensure that critical tasks are executed in a timely manner.

[0050] Four, core functional component implementation Motion control component: The motion control component implements multi-axis coordinated motion functions. The trajectory planner receives path segments generated by the G-code interpreter, performs look-ahead velocity planning, and generates smooth S-curve acceleration and deceleration profiles. The interpolation algorithm calculates the position command for each axis based on the planning results, supporting linear and circular interpolation modes. The position loop PID controller receives the position command output by the interpolator and the actual position feedback from the encoder, calculates the control output, and outputs it to the servo driver. PID parameters can be adjusted online, and adaptive control algorithms are supported.

[0051] Safety monitoring component: The safety monitoring component implements multi-level fault detection and protection functions. The hardware watchdog monitors system operation status and triggers a safety handling process when an anomaly is detected. The limit detection module monitors the status of each axis limit switch in real time to prevent mechanical overtravel. The emergency stop processing circuit uses a redundant design to ensure reliable shutdown in emergency situations. The system also includes temperature monitoring, overcurrent protection, communication timeout detection, and other functions to ensure safe operation of the equipment.

[0052] Five, signal connection network implementation The system implements data exchange between components through the HAL signal connection mechanism. Each functional component declares its input and output pins, and the system dynamically establishes the connection relationship between the pins during operation. The signal connection supports multiple data types, including integer, floating-point, and Boolean types, ensuring type-safe data transmission. The connection network uses a publish-subscribe mode, supporting one-to-many and many-to-one connection methods to meet the needs of complex control logic. All signal connections can be defined through configuration files, and runtime dynamic modification is supported.

[0053] Six, parameter configuration management implementation The system uses text-based configuration files to manage all operating parameters. Configuration files include hardware device parameters, control algorithm parameters, safety threshold parameters, and other settings. Parameters support group management, and different device models can use different parameter configuration files. The system provides online parameter modification functions, and important parameter modifications are automatically verified for validity. All parameter changes are logged, and parameter import / export and version management functions are supported.

[0054] Seven, fault diagnosis and processing implementation The system implements a perfect fault diagnosis mechanism. Real-time monitoring of the running state of each component, detecting hardware abnormalities, communication interruptions, control tolerances, and other fault conditions. Faults are divided into three levels: minor, major, and severe. Different levels take different handling strategies. Minor faults only record logs, major faults perform smooth shutdown, and severe faults trigger an emergency stop immediately. The system also provides detailed fault information records, including fault time, fault code, related parameters, etc., for subsequent analysis and processing.

[0055] Eight, debugging and monitoring interface implementation The system provides a rich debugging and monitoring interface. The Vcorescope tool can display the waveform graph of any signal in real time, support multi-signal simultaneous display and trigger capture function. The vcoremeter command allows online monitoring and modification of signal values, facilitating parameter debugging. The system log records detailed running information, supports filtering by level and keyword search. The remote monitoring interface provides system state query and parameter configuration functions through Web service, supporting cross-platform access.

[0056] Nine, effect verification The control system constructed by the above implementation method has the following characteristics: strong hardware compatibility, supporting multiple brands of servo drives and IO devices; excellent real-time performance, control cycle up to 1ms, jitter less than 5μs; high system reliability, with perfect fault detection and processing mechanism; good maintainability, supporting online debugging and parameter adjustment; strong scalability, new functional components can be easily added. Actual tests show that the system can meet the requirements of high-precision numerical control machining, providing a reliable technical foundation for intelligent manufacturing.

[0057] The implementation provides a complete technical solution from hardware connection to software implementation, and technicians can directly implement the HAL control system based on this description without additional creative labor.

[0058] The hardware adaptation efficiency of the present application is improved. The hardware adaptation time is shortened from 2-4 weeks in the traditional scheme to 2-4 hours, the efficiency is improved by 20-40 times, the number of hardware platforms supported is expanded from a single platform to 100+ I / O devices, and the system downtime caused by hardware replacement is reduced by 95%.

[0059] Through a unified hardware abstraction interface, hardware operations are packaged as standard components. When replacing hardware, only the corresponding hardware driver component needs to be replaced, and the upper layer application does not need to be modified. The component manager automatically handles hardware initialization and resource allocation, achieving "plug and play" hardware compatibility.

[0060] The real-time scheduler of this invention employs user-space real-time thread technology, avoiding frequent switching between kernel mode and user mode. Through CPU affinity settings and priority inheritance algorithms, deterministic execution of critical tasks is ensured. A high-precision timer provides a μs-level time base, significantly improving the accuracy of the control cycle.

[0061] The present invention improves motion control accuracy. The three-axis linkage contour error in actual test data is reduced from ±50μm to ±5μm, the trajectory tracking error under high-speed motion is reduced by 80%, and the surface roughness Ra value is improved by 60%.

[0062] III. System Development and Maintenance Technical Effects This invention improves development efficiency, shortens the development cycle of new features by 50%, increases code reuse rate from 15% to 80%, reduces system debugging time by 75%, and achieves 90% automation in regression testing.

[0063] The component-based architecture highly decouples functional modules, allowing new features to be integrated simply by implementing standard component interfaces. The signal connection mechanism provides visualized data flow monitoring, significantly simplifying the system debugging process. Unified configuration management supports version control and automated deployment.

[0064] The present invention improves system reliability. The mean time between failures (MTBF) is increased from 1,000 hours to 10,000 hours, the fault recovery time is reduced from minutes to seconds, and the system availability is increased from 99.9% to 99.99%.

[0065] A health monitoring mechanism monitors component status in real time, and a fault detection algorithm can identify potential problems early. A tiered fault recovery strategy ensures that the system can quickly switch to a safe state when an anomaly occurs. Component isolation design prevents local faults from spreading to the entire system.

[0066] This invention can directly save costs, reducing hardware procurement costs by 60%, eliminating the need for a dedicated control card, reducing system maintenance costs by 80%, reducing personnel training costs by 70%, and saving equipment upgrade costs by 90%.

[0067] The present invention improves production efficiency, increases equipment utilization from 65% to 85%, reduces product changeover time from 30 minutes to 5 minutes, improves product quality consistency by 40%, and improves energy efficiency by 25%.

[0068] VCORE's technology solution achieves significant technological breakthroughs in hardware compatibility, real-time performance, and system reliability through its innovative software architecture. Compared to traditional technologies, it not only achieves orders-of-magnitude improvements in technical indicators but, more importantly, lowers the technical threshold, promoting the digital transformation and upgrading of the entire manufacturing industry. Its open-source nature also brings significant social benefits, providing a solid technological foundation for the development of intelligent manufacturing.

[0069] This technical solution addresses hardware dependency issues through a modular architecture, ensures system performance through a real-time scheduling mechanism, simplifies system integration through a signal routing mechanism, and improves maintainability through a configuration management system. The entire solution offers high flexibility and reliability, meeting the stringent requirements of industrial control for real-time performance, determinism, and maintainability.

[0070] For the specific implementation scheme of this embodiment, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0071] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0072] It should be noted that in the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means at least two.

[0073] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0074] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution device. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0075] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The corresponding program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0076] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0077] The storage media mentioned above can be read-only memory, disk, or optical disk, etc.

[0078] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] The component organization system for implementing CNC numerical control functions, as described in this invention, solves hardware dependency issues through a modular architecture, ensures system performance through a real-time scheduling mechanism, simplifies system integration through a signal routing mechanism, and improves maintainability through a configuration management system. The entire solution exhibits high flexibility and reliability, meeting the stringent requirements of real-time performance, determinism, and maintainability in the industrial control field. The HAL technology solution, through its innovative software architecture, achieves significant technological breakthroughs in hardware compatibility, real-time performance, and system reliability. Compared to traditional technologies, it not only achieves orders-of-magnitude improvements in technical indicators but, more importantly, lowers the technical threshold, promoting the digital transformation and upgrading of the entire manufacturing industry. Its open-source nature also brings significant social benefits, providing a solid technical foundation for the development of intelligent manufacturing.

[0080] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A component organization system for realizing CNC numerical control functions, characterized in that, The system comprises an application layer, a HAL core layer, a hardware driver layer, and a physical device layer. These layers are sequentially connected and communicate through standardized interfaces. The application layer is used for trajectory planning and G-code interpretation, the HAL core layer is used for signal routing and component management, and central coordination, and the hardware driver layer encapsulates multiple specific hardware interfaces.

2. The component organization system for realizing CNC numerical control function according to claim 1, characterized in that, The system also includes a digital input interface, an analog input interface, and an encoder interface. The digital input interface directly accesses hardware registers through memory mapping and performs I / O operations by configuring the base address and bit mask. The analog input interface is used to configure and manage ADC and DAC channels, and the encoder interface is used to acquire quadrature encoder counters.

3. The component organization system for realizing CNC numerical control function according to claim 1, characterized in that, The HAL core layer includes a component manager, a signal router, and a real-time scheduler. The component manager is connected to the application layer, the signal router is connected to the component manager, and the real-time scheduler is connected to both the component manager and the signal router. The component manager is used to manage the lifecycle of all functional components, the signal router is used to enable data communication between components, and the real-time scheduler is used to ensure deterministic response of the system.

4. The component organization system for realizing CNC numerical control function according to claim 3, characterized in that, When the system starts, the component manager parses the configuration file and determines the component loading order according to the dependencies; it dynamically loads each component into memory and allocates independent resource space for each component; during the component initialization phase, the component manager registers the pins and parameter interfaces it provides and establishes static connection relationships between components. During runtime, the component manager monitors the health status of each component. If any abnormality is detected, it automatically performs fault isolation and recovery operations.

5. The component organization system for realizing CNC numerical control function according to claim 3, characterized in that, When establishing a signal connection, the signal router verifies the data type compatibility of the source and target pins, creates a signal object, and establishes a bidirectional connection. During data transmission, the signal router employs a copy-on-write mechanism. The signal router dynamically modifies the connection relationships in the connection topology during runtime.

6. The component organization system for realizing CNC numerical control function according to claim 3, characterized in that, The system creates multiple real-time threads, each configured with a different execution cycle and priority level. The real-time scheduler uses a priority inheritance algorithm to prevent priority inversion and binds threads to specific cores for execution through CPU affinity settings. In terms of execution control, a timer is used to trigger periodic tasks, and the component processing functions are called in a preset order; The real-time scheduler monitors task execution time in real time and downgrades tasks that time out.

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